JP2005159050A - Semiconductor element and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor element wherein a space between barrier metal layers is small and the height of a solder bump is large, and to provide its manufacturing method. <P>SOLUTION: A semiconductor element is manufactured by a manufacturing method which is provided with a first process wherein lower layer bumps 5a are formed on a plurality of barrier metal layers 3 which are arranged so as to be dotted on a semiconductor substrate 1; a second process wherein a resist layer 6 is formed on a region in which the lower layer bumps 5a do not exist, and the lower layer bumps 5a are surrounded with the resist layer 6; and a third process wherein conductive paste 5" is arranged on surfaces of the lower layer bumps, and upper layer bumps are formed on the lower layer bumps 5a by heating the conductive paste 5". <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a semiconductor element such as a flip-chip IC mounted on a circuit board by face-down bonding.

  Conventionally, an IC is face-down bonded to the upper surface of a circuit board having a circuit pattern, that is, the IC is mounted on the circuit board with the integrated circuit formation surface of the IC facing the circuit board. It has been broken.

  An IC used for such face-down bonding is called a flip-chip type IC, and generally has a terminal connected to a circuit pattern on a circuit board via a conductive material such as solder.

  As such a semiconductor element such as a flip-chip IC, solder bumps are selectively formed on a plurality of barrier metal layers made of nickel or the like deposited on one main surface of a substrate on which an integrated circuit is provided. Structures are known. When mounting such semiconductor elements on a circuit board, put them in a reflow furnace with the semiconductor elements placed on the circuit board so that the solder bumps face the corresponding circuit patterns on the circuit board. The barrier metal layer of the semiconductor element is soldered to the circuit pattern on the circuit board by heat treatment and melting the solder bumps.

The semiconductor element as described above is usually manufactured by the following method. That is,
(1) A substrate 21 having a plurality of barrier metal layers 23 on the upper surface and a printing mask 26 having a plurality of openings 27 corresponding to the barrier metal layer 23 on a one-to-one basis are prepared. Arranged on the substrate 21 so that the opening 27 is located on the barrier metal layer 23 (FIG. 5A),
(2) Subsequently, the solder paste 25 ′ is supplied onto the printing mask 26, and the solder paste 25 ′ is filled in the opening 27 by moving the squeegee 29 against the printing mask 26 in a predetermined direction. (FIG. 5 (b)),
(3) Next, by separating the printing mask 26 from the substrate 21, the solder paste 25 ′ filled in the opening 27 is printed and applied on the barrier metal layer 23 (FIG. 5C).
(4) Finally, the solder paste 25 ′ applied on the barrier metal layer 23 is heated to form spherical solder bumps 25 on the barrier metal layer 23, and the substrate 21 is processed into a predetermined shape, thereby producing a semiconductor element. Is completed (FIG. 5D).

  By the way, the reliability of solder bonding when the semiconductor element described above is mounted on a circuit board largely depends on the height of the solder bump, and it is generally preferable that the height of the solder bump is high. . In order to increase the height of the solder bumps, a large amount of solder paste 25 ′ may be applied on the barrier metal layer 23.

  However, in the above-described conventional method of manufacturing a semiconductor device, when a large amount of solder paste 25 'is applied at once, a part of the solder paste 25' protrudes beyond the barrier metal layer 23, and the adjacent solder paste 25 ' Since there exists a possibility of contacting, there existed a subject that it was difficult to make the space | interval of barrier metal layers small.

  Therefore, as shown in Patent Document 1, by applying the solder paste 25 'in a plurality of times, the solder paste and the protrusion of 25' are reduced by reducing the amount of the solder paste 25 'applied at one time. It has been proposed to reduce the distance between the barrier metal layers 23.

The semiconductor device manufactured by such a method is manufactured through the sequence shown in FIG. 6 when the solder paste 25 'is applied in two steps. That is,
(1) First, solder paste 25 'is applied on the barrier metal layer 23, and this is heated to form a lower bump 25a (FIG. 6A),
(2) Next, the printing mask 26 is disposed on the substrate 21 so that the openings 27 are positioned on the lower layer bumps 25a (FIG. 6B).
(3) Subsequently, the solder paste 25 ′ supplied onto the printing mask 26 is applied onto the lower bump 25a through the opening 27 (FIG. 6C).
(4) Finally, the upper layer bump 25b is formed by heating the solder paste 25 'applied on the lower layer bump 25a, thereby completing the solder bump 25 including the lower layer bump 25a and the upper layer bump 25b (FIG. 6 ( d)).
JP 2002-134538 A

  However, when the solder bump 25 is formed by such a manufacturing method, the lower layer bump 25a is once melted by heat when the solder paste 25 ′ applied for the second time is heated to form the upper layer bump 25b. There is a problem that the lower bump 25a spreads sideways and is crushed, and the height of the lower bump 25a is reduced, and the total height of the solder bump 25 cannot be sufficiently increased.

  The present invention has been devised in view of the above problems, and an object of the present invention is to provide a semiconductor device having a small interval between barrier metal layers and a high solder bump, and a method for manufacturing the same.

  The method of manufacturing a semiconductor device of the present invention includes a first step of forming a lower layer bump on a plurality of barrier metal layers provided to be scattered on a semiconductor substrate, and a resist layer in a region where the lower layer bump does not exist A second step of surrounding the lower bump with the resist layer, and supplying a conductive paste to the lower bump surface, and heating the conductive paste to form an upper bump on the lower bump. And a process.

  In the semiconductor device manufacturing method of the present invention, the resist layer and the lower bump are in contact with each other.

  Furthermore, the method for manufacturing a semiconductor device of the present invention is characterized in that the conductive paste supplied in the third step is also supplied to the surface of the resist layer.

  Furthermore, the method for manufacturing a semiconductor device of the present invention is characterized in that the surface of the lower bump is made flat before the formation of the upper bump.

  Furthermore, in the method for manufacturing a semiconductor element of the present invention, when the resist layer is formed by a screen printing method, a non-opening portion of a printing mask for applying a resist material, which is a constituent material of the resist layer, on the substrate is formed in the lower layer By pressing against the surface of the bump, the surface of the lower-layer bump is flattened.

  In the semiconductor device manufacturing method of the present invention, the thickness of the resist layer is substantially equal to the height of the lower bump.

  On the other hand, the semiconductor element of the present invention is a resist that surrounds a lower portion of a bump in a region where the bump does not exist in a semiconductor element having a bump on a plurality of barrier metal layers provided so as to be scattered on a semiconductor substrate. A layer is formed, and the resist layer and the bump are brought into contact with each other.

  According to the present invention, after forming the lower layer bump, before forming the upper layer bump formed on the lower layer bump, a resist layer surrounding the lower layer bump is formed, and thereafter, the conductive layer is formed on the surface of the lower layer bump. Since the paste is supplied and heated to form the upper layer bump, even if the lower layer bump is melted by the heat applied to the conductive paste when forming the upper layer bump, the molten lower layer bump is placed sideways. It is well suppressed that it spreads and collapses greatly. Therefore, the total height of the bumps constituted by the lower layer bumps and the upper layer bumps can be made sufficiently high, and a semiconductor element with high bonding reliability can be realized.

  In addition, since the conductive paste is supplied in a plurality of times, the amount of supply of the conductive paste is reduced. Therefore, when the interval between the barrier metal layers is reduced, the contact between the conductive pastes on the adjacent barrier metal layers can be satisfactorily prevented.

  Further, according to the present invention, by bringing the resist layer and the lower layer bump into contact with each other, it is possible to further prevent the molten lower layer bump from spreading in the lateral direction when the upper layer bump is formed. A high bump can be formed.

  Furthermore, according to the present invention, by supplying the conductive paste supplied after the formation of the resist layer also to the surface of the resist layer, more conductive paste can be supplied onto the lower bumps, and the total bumps It is possible to further increase the height.

  Furthermore, according to the present invention, since the surface of the lower layer bump is made flat before the formation of the upper layer bump, the height of the lower layer bump before the formation of the upper layer bump can be made uniform. There is an advantage that variation in the overall height can be reduced.

  The flattening of the lower layer bump is performed when the resist layer is formed by a screen printing method, and a printing mask used in the screen printing method is formed in a region where the opening portion is not present in the lower layer bump and a non-opening portion is formed. When the resist material, which is placed on the lower bumps and is applied to the printing mask in this state, is applied to the substrate via the openings, the non-opening portions of the printing mask are formed on the lower bumps. If it is made to press against the surface, the surface of the lower layer bump is flattened by the pressing force of the non-opening, so that the application of the resist material and the flattening of the lower layer bump can be performed simultaneously, It is possible to reduce the trouble of flattening the lower bump.

  According to the present invention, in a semiconductor element having bumps on a plurality of barrier metal layers provided so as to be scattered on a semiconductor substrate, a resist layer surrounding a lower portion of the bump is formed in a region where the bump does not exist. Since the resist layer and the bumps are in contact with each other, when a force is applied to a mounting structure configured by mounting such a semiconductor element on a circuit board, not only the bumps, The force is satisfactorily absorbed by the resist layer disposed around the periphery. Therefore, it is possible to provide a semiconductor element with high connection reliability.

  Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

Description of Semiconductor Device First, the semiconductor device of the present invention will be described in detail with reference to FIGS.

  FIG. 1 is a cross-sectional view according to an embodiment of the semiconductor element of the present invention, and FIG. 2 is a cross-sectional view of a mounting structure configured by mounting the semiconductor element of FIG. 1 on a circuit board. The element generally has a configuration in which circuit wiring 2, barrier metal layer 3, passivation layer 4, bump 5, and the like are provided on semiconductor substrate 1.

  The semiconductor substrate 1 is made of a semiconductor material such as single crystal silicon, and a functional element (not shown) such as a transistor, a circuit wiring 2, a barrier metal layer 3, a passivation layer 4, a bump 5 and a resist layer 6 are formed on the upper surface thereof. It is applied and functions as a supporting base material that supports them.

  Such a semiconductor substrate 1 is obtained by, for example, slicing a single crystal silicon ingot formed by a conventionally known chocolate ski method (pull-up method) or the like to a predetermined thickness, and polishing the surface thereof. Thereafter, an insulating film is formed on the entire surface of the plate body by a conventionally known thermal oxidation method.

  The circuit wiring 2 formed on the semiconductor substrate 1 is deposited to a thickness of 0.5 μm to 1.5 μm with a metal material such as aluminum (Al) or copper (Cu), and functions as a transistor (not shown). It functions as a power supply wiring for supplying power from the outside, electric signals, and the like to the element.

  A plurality of barrier metal layers 3 are scattered on the upper surface of a part of the circuit wiring 2 so as to be arranged linearly along the end of the semiconductor substrate 1.

  The barrier metal layer 3 effectively prevents the aluminum or the like forming the circuit wiring 2 from being eroded with the melting of the bump 5 provided on the barrier metal layer 3 when the semiconductor element is mounted on the circuit board 9. For example, zinc (Zn), nickel (Ni), and gold (Au) are sequentially stacked from the semiconductor substrate 1 side so that the wettability with respect to the material constituting the bump 5 is good. Three-layer structure, zinc (Zn), nickel (Ni) two-layer structure, or palladium (Pd), nickel (Ni), gold (Au) three-layer structure, palladium (Pd), nickel (Ni) Such a two-layer structure is conceivable.

  The circuit wiring 2 is formed in a predetermined pattern on the upper surface of the semiconductor substrate 1 by employing conventionally known sputtering, photolithography technology, and etching technology. When the barrier metal layer 3 has a three-layer structure of zinc (Zn), nickel (Ni), and gold (Au), for example, after forming a passivation layer 4 described later, circuit wiring exposed from the passivation layer 4 By adopting a conventionally known electroless plating method or the like on a part of the upper surface of 2, zinc (Zn), nickel (Ni), and gold (Au) are sequentially laminated from the substrate side to form a cylindrical shape. Is done.

On the other hand, a passivation layer 4 made of an electrically insulating material such as silicon nitride (Si ₃ N ₄ ), silicon oxide (SiO ₂ ), or polyimide is provided in the non-formation region of the barrier metal layer 3 with circuit wiring 2 or a functional element (not shown). It is applied to cover.

  The passivation layer 4 effectively prevents the functional elements and the circuit wiring 2 from being corroded by contact with moisture contained in the atmosphere by blocking the functional elements and the circuit wiring 2 from the atmosphere. It is preferable that a part thereof covers the outer peripheral upper surface of the barrier metal layer 3.

  The passivation layer 4 is formed to a thickness of 0.5 μm to 3.0 μm on the upper surface of the semiconductor substrate 1 by employing a conventionally known sputtering, photolithography technique, etching technique or the like.

  A bump 5 is formed on the upper surface of the barrier metal layer 3 described above.

  The bump 5 is melted by being heated when the semiconductor element is mounted on the circuit board 9, and electrically and mechanically connects the barrier metal layer 3 of the semiconductor element and the circuit pattern 10 on the circuit board 9. For example, a conductive material such as solder in which tin (Sn), silver (Ag), and copper (Cu) are melted and solidified in a ratio of 96.5: 3.0: 0.5 is 20 μm. It is formed to a height of ˜100 μm. Such a bump 5 is manufactured by a manufacturing method described later.

  On the other hand, a resist layer 6 surrounding the lower portion of the bump 5 is deposited on the non-formation region of the bump 5, and the resist layer 6 and the bump 5 are in contact with each other.

  The resist layer 6 is for reducing the load applied to the bump 5 by absorbing the external force applied to the mounting structure when the semiconductor element is mounted on the circuit board 9 to constitute the mounting structure. As a result, the junction reliability of the semiconductor element can be maintained high. Therefore, the resist layer 6 is preferably formed of a material having a Young's modulus larger than that of the bump 5, for example, a solder resist material such as an epoxy resin or a polyimide resin.

Description of Method for Manufacturing Semiconductor Device Next, a method for manufacturing a semiconductor device according to the present invention will be described with reference to FIG. FIGS. 3A to 3F are cross-sectional views of each step for explaining a method for manufacturing a semiconductor element.

  (1) First, the semiconductor substrate 1 having the circuit wiring 2, the barrier metal layer 3, and the passivation layer 4 deposited thereon is prepared, and a conductive paste 5 ′ is applied on the barrier metal layer 3 (FIG. 3A). .

  For the application of the conductive paste 5 ′, for example, a conventionally known screen printing method is employed. That is, a printing mask having an opening corresponding to the barrier metal layer 3 is disposed on the semiconductor substrate 1 and the conductive paste 5 ′ placed on the printing mask is placed through the opening of the printing mask through the barrier metal layer 3. Apply on top.

  As the conductive paste 5 ', a solder paste adjusted to a predetermined viscosity by adding and mixing a flux or the like to a large number of solder particles is preferably used.

  In addition, as a material of the printing mask, metal materials such as aluminum alloy, stainless steel, Ni alloy, Cr alloy, resin materials such as polyimide, polyester, epoxy, polycarbonate, polyethylene, polyethylene terephthalate (PET), polypropylene, or these materials For example, when the printing mask is made of a Ni alloy, it is formed by a conventionally well-known additive method.

  (2) Next, the conductive paste 5 ′ applied on the barrier metal layer 3 is heated at a temperature equal to or higher than the melting point of the conductive paste 5 ′ for 40 seconds to 60 seconds, for example, so that the lower bumps are formed on the barrier metal layer 3. 5a is formed (FIG. 3B).

  The conductive paste 5 ′ is heated, for example, by introducing the semiconductor substrate 1 coated with the conductive paste 5 ′ into a reflow furnace and by heat from a heater provided in the reflow furnace.

  (3) Subsequently, a resist material 6 'constituting the resist layer is applied to a region where the lower bump 5a does not exist (FIG. 3C).

  For the application of the resist material 6 ', for example, a conventionally known screen printing method or dispenser method is employed. In this embodiment, a screen printing method is employed. That is, a printing mask used for screen printing is arranged on the substrate such that the opening is located in a region where the lower bump 5a does not exist and the non-opening is located on the lower bump 5a, and the resist material is used. The resist material is applied onto the semiconductor substrate 1 through the opening by placing it on the printing mask and then moving a pressing means such as a squeegee. In the present embodiment, a thermosetting epoxy resin is used as the resist material 6 '.

  (4) Next, the applied resist material 6 ′ is heated at a temperature of, for example, 50 ° C. to 90 ° C. to cause the resist material 6 ′ to flow, and then is thermally cured at a high temperature of 90 ° C. to 160 ° C. Thereby, a resist layer 6 is formed (FIG. 3D).

  At this time, the fluidized resist material 6 'spreads on the semiconductor substrate 1 and surrounds the lower bump 5a. Further, if the fluidization is large, the resist material 6 'comes into contact with the lower bump 5a as in the present embodiment.

  If the thickness of the resist layer 6 is higher than the height of the lower layer bump 5a, it is necessary to remove the resist layer on the lower layer bump 5a in order to form the upper layer bump 5b on the lower layer bump 5a, and the manufacturing process is complicated. Therefore, it is preferable to set the thickness of the resist layer 6 equal to that of the lower layer bump 5a or lower than that of the lower layer bump 5a.

  The difference between the surface of the resist layer 6 and the surface of the bump 5 is preferably set to 4 μm or less. The reason is that if the step between the resist layer 6 and the bump surface is larger than 4 μm, the printing mask is easily damaged by the pressing force from the squeegee when applying the conductive paste by screen printing in the subsequent process. This is because the problem of shortening the lifetime of the mask is induced.

  (5) Subsequently, a conductive paste 5 ″ is applied on the lower bump (FIG. 3E).

  At this time, as shown in FIG. 3 (e), if the conductive paste 5 ″ is applied not only to the surface of the lower bump 5a but also to the surface of the resist layer 6, more conductive paste 5 ″ is applied to the lower bump. It can be applied on 5a, and the total bump height can be increased.

  For the application of the conductive paste 5 ″, for example, a conventionally known screen printing method is adopted. That is, a printing mask having an opening corresponding to the barrier metal layer 3 is disposed on the semiconductor substrate 1, and A conductive paste 5 ″ placed on the printing mask is applied onto the barrier metal layer 3 through the opening of the printing mask.

  (6) Finally, the upper layer bump is formed by heating the conductive paste 5 ″ applied in step (5) at a temperature equal to or higher than the melting point of the conductive paste 5 ″ for 40 seconds to 60 seconds. A bump 5 is formed with the bump (FIG. 3F).

  At this time, although the lower layer bump 5a is melted by the heat applied to the conductive paste 5 ″ when the upper layer bump is formed, the melted lower layer bump 5a is surrounded by the resist layer 6, and therefore the lower layer bump 5a is placed sideways. Therefore, it is possible to satisfactorily suppress the spread and crushing, so that the height of the entire bump composed of the lower layer bump and the upper layer bump can be made sufficiently high, and a semiconductor element with high bonding reliability can be realized. In addition, in the present embodiment, since the resist layer 6 and the lower layer bump 5a are brought into contact with each other, the spread of the molten lower layer bump 5a in the lateral direction can be further prevented, and It becomes possible to form a bump having a high height.

  Further, according to the manufacturing method of the present invention, since the conductive pastes 5 ′ and 5 ″ are applied in a plurality of times, the application amount of the conductive paste is reduced and the distance between the barrier metal layers is small. However, the contact between the conductive pastes on the adjacent barrier metal layers can be satisfactorily prevented.

  Incidentally, since the conductive paste 5 ″ flows into the lower layer bump 5a when the upper layer bump is formed, the upper layer bump and the lower layer bump may not be clearly distinguished after the bump 5 is formed. Needless to say, is applicable.

  The present invention is not limited to the above-described embodiments, and various modifications and improvements can be made without departing from the scope of the present invention.

  For example, in the step (3) of the above-described embodiment, when the resist material 6 ′ is applied by the screen printing method, the non-opening portion of the print mask 7 is applied to the surface of the lower bump by the pressing means 8 such as a squeegee. When pressed (FIG. 4A), the surface of the lower bump 5a is flattened (FIG. 4B), so that the height of the lower bump 5a before the formation of the upper bump can be made uniform. Therefore, it is possible to reduce the height variation of the entire bump after the upper layer bump is formed. In this case, it is preferable to move the pressing means while keeping the pressing force of the pressing means such as a squeegee against the printing mask 7 substantially constant.

  Further, if the height of the resist layer 6 formed after planarizing the lower bump 5a is substantially equal to the height of the lower bump 5a as shown in FIG. 4C, the difference in height is within 4 μm. Since the lower layer bump 5 and the resist layer 6 can be coplanar, as shown in FIG. 4D, when applying the conductive paste 5 ″ by screen printing to form the upper layer bump, The damage can be further reduced and the workability can be improved.

It is sectional drawing of the semiconductor element which concerns on one Embodiment of this invention. It is sectional drawing of the mounting structure comprised by mounting the semiconductor element of FIG. 1 on a circuit board. (A)-(f) is sectional drawing of each process for demonstrating the manufacturing method of the semiconductor element of FIG. (A)-(d) is sectional drawing for demonstrating other embodiment of the manufacturing method of FIG. (A)-(d) is sectional drawing of each process for demonstrating the manufacturing method of the 1st conventional semiconductor element. (A)-(d) is sectional drawing of each process for demonstrating the manufacturing method of the 2nd conventional semiconductor element.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate 2 ... Circuit wiring 3 ... Barrier metal layer 4 ... Passivation layer 5 ... Bump 5 ', 5 "... Conductive paste 6 ... Resist layer 6' ...・ Resist material 7 ... printing mask 8 ... pressing means (squeegee)
9 ... Circuit board 10 ... Circuit pattern

Claims (7)

A first step of forming a lower bump on a plurality of barrier metal layers provided to be scattered on a semiconductor substrate;
Forming a resist layer in a region where the lower bump does not exist, and surrounding the lower bump with the resist layer;
A third step of supplying a conductive paste to the surface of the lower bump and heating the conductive paste to form an upper bump on the lower bump. The method for manufacturing a semiconductor device according to claim 1, wherein the resist layer and the lower bump are in contact with each other. 3. The method of manufacturing a semiconductor element according to claim 1, wherein the conductive paste supplied to the surface of the lower bump in the third step is also supplied to the surface of the resist layer. 4. The method of manufacturing a semiconductor element according to claim 1, wherein the surface of the lower bump is made flat before the formation of the upper bump. When the resist layer is formed by screen printing, a non-opening portion of a printing mask for applying a resist material that is a constituent material of the resist layer onto the substrate is pressed against the surface of the lower bump, 5. The method of manufacturing a semiconductor device according to claim 4, wherein the surface is flattened. 6. The method of manufacturing a semiconductor element according to claim 1, wherein a thickness of the resist layer is substantially equal to a height of the lower layer bump. In a semiconductor element having bumps on a plurality of barrier metal layers provided so as to be scattered on a semiconductor substrate,
A semiconductor element, wherein a resist layer surrounding a lower portion of a bump is formed in an area where the bump does not exist, and the resist layer and the bump are brought into contact with each other.

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