JP2005157940A - Information processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an information processor capable of improving the accuracy of error information when a problem occurs and of improving the reliability of a device. <P>SOLUTION: This information processor includes a plurality of sensors for detecting a state inside the device, a control controller a1 and a control controller b2 for judging an abnormal state inside the device on the basis of information detected in the plurality of sensors, and duplexed control buses 3 and 4 for transmitting the information detected in the plurality of sensors to the control controller a1 and the control controller b2. Thus, the reliability of the error information is improved and the probability of erroneous judgement is lowered. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an information processing apparatus having an error detection control function for detecting abnormalities in various devices, temperatures, and voltages, and more particularly to a technique for improving the reliability of detected error information.

  Conventionally, in an information processing apparatus, error information such as various devices, temperature, and voltage has been collected using a dedicated bus and control controller for error detection control.

Conventionally, there has been a case where an ECC error occurrence is determined by a plurality of error generation circuits (see, for example, Patent Document 1).
JP-A-6-149601

  However, in the conventional information processing apparatus, the error detection control function is to collect error information on the bus for error detection control, and since the reliability of the information itself is not considered, its accuracy is In some cases, error information is given even to a device that is low and has no problem, or error information is erroneously detected due to noise in the sensor part or bus. Due to this problem, even in an information processing device that is operating normally, excessive warnings and alarms are generated, and the continuous operation itself is stopped by analyzing the problem location, etc., and the continuous operation and reliability of the information processing device are reduced. There was a loss.

  In addition, the one described in the cited document 1 realizes the ECC error occurrence and determination by a plurality of error generation circuits, but is applied to bus multiplexing for improving the reliability of a dedicated bus for error detection control. It wasn't possible. Also, the error occurrence information has not been confirmed with a time difference.

  An object of the present invention is to improve the accuracy of error information when a problem occurs and to improve the reliability of the apparatus by multiplexing buses, sensors and control controllers for detecting error information. Is to provide.

  Another object of the present invention is to provide information processing capable of improving the reliability of error information by avoiding instantaneous erroneous detection by adding a time difference to the control on the bus for detecting the multiplexed error information. Is to provide a device.

  An information processing apparatus according to the present invention is detected by a plurality of sensors that detect a state inside the apparatus, a controller that determines an abnormal state inside the apparatus based on information detected by the plurality of sensors, and a plurality of sensors. And a multiplexed bus for transmitting the information to the controller.

  According to the present invention, the quality of error information can be improved by having a plurality of control controllers, buses and sensors for detecting error information physically.

  In addition, according to the present invention, it is possible to further improve the accuracy of error information and reduce the probability of erroneous determination by providing a temporal difference in control on the multiplexed error information detection bus. it can.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

(Embodiment 1)
First, the configuration of the error detection control unit in the information processing apparatus according to Embodiment 1 of the present invention will be described with reference to FIG. FIG. 1 is a block diagram showing a configuration of an error detection control unit in the information processing apparatus according to Embodiment 1 of the present invention, and shows an example in which a bus is duplicated as an example of multiplexing.

  In FIG. 1, the error detection control unit in the information processing apparatus includes a control controller a1, a control controller b2, a control bus a3 connected to the control controller a1, a control bus b4 connected to the control controller b2, and a plurality of CPUs (CPU1 (13-1) to CPUn (13-n)) and a plurality of FANs (FAN1 (14-1) to FANn (14-n)), etc. Has been.

  The sensors of each device are two pairs of the same sensors and are connected to different control buses. In addition, the control controller a1 and the control controller b2 operate independently and check the status of each device through sensors.

  Each sensor is, for example, a voltage sensor a (5-1 to 5-n), a voltage sensor b (6-1 to 6-n) for detecting the voltage of the CPU1 (13-1) to CPUn (13-n), Temperature sensors a (7-1 to 7-n), temperature sensors b (8-1 to 8-n) for detecting temperatures of CPU1 (13-1) to CPUn (13-n), a plurality of locations in the system Temperature sensors a (9-1 to 9-n) for detecting temperatures, temperature sensors b (10-1 to 10-n), and rotation sensors for detecting rotations of FAN1 (14-1) to FANn (14-n) a (11-1 to 11-n) and rotation sensor b (12-1 to 12-n) are provided. Note that these sensors are not limited to this, and sensors for detecting the status of various devices may be provided.

  Next, the details of the operation will be described by taking the voltage sensor a5 and the voltage sensor b6 of the CPU 1 (13-1) as an example. The same operation is performed for other sensors.

  The CPU1 voltage sensor a5 is connected to and monitored by the control controller a1 through the control bus a3. Similarly, the CPU1 voltage sensor b6 is connected to and monitored by the control controller b2 through the control bus b4. Each controller periodically checks the status of each sensor connected to the control bus to confirm whether it is operating normally.

  When an abnormality occurs in the voltage of the CPU 1 (13-1), the information is detected by the CPU 1 voltage sensor a5 and the CPU 1 voltage sensor b6 and responds to the control controller to which each is connected. The control controller a1 and the control controller b2 check each other's error information through the inter-controller bus 15 and share that an abnormality has occurred in the voltage of the CPU 1 (13-1) when an error has occurred in both. Log to the memory 16, and notify the CPU from the host controller connection bus 17 connected to the host controller that can communicate with the CPU 1 (13-1) and other CPUs. It is also possible for the controller a1 to notify the CPU directly.

  Also, if an error is detected only in the CPU1 voltage sensor a5, it can be seen that no error is detected in the CPU1 voltage sensor b6 during the mutual error check between the controllers, and there is a possibility of erroneous detection due to noise or the like. Judge that there is also.

  Next, an error notification pattern according to the first embodiment will be described with reference to FIG. FIG. 2 is a diagram showing a pattern of error notification by detection of error information of the sensor.

  For example, even if error information is not detected for both sensors in a pair, if an error occurs multiple times in one sensor, there may be a problem with that device. Notify the message.

  In the example shown in 201 of FIG. 2, if an error is detected three or more times with only one of the paired sensors, there may be a problem with the undetectable control bus. Even if an error does not occur, the error is notified.

  In the example shown at 202 in FIG. 2, when an error is detected by both of the paired sensors, the consistency is lost and the possibility of the occurrence of the error is high, so the error is notified.

  In the example shown by 203 in FIG. 2, when an error is detected within two times by only one of the paired sensors, an error is not notified because there is a possibility of erroneous detection.

  This number of errors is implemented by storing how many times an error has occurred in the shared memory 16 based on the data detected by the sensor and checking the number of times.

  In addition to the error notification pattern shown in FIG. 2, by setting a combination of a plurality of other error information, an error detection value optimum for the model can be set, and accuracy can be improved.

  Next, the operation of the controller will be described with reference to FIG. FIG. 3 is a flowchart showing the operation of the controller, and shows an example of the operation of the controller a1.

  In FIG. 3, the total number of sensors connected to the controller a1 is m, and the sensors are sensors 1, a to m, a.

  First, error information is initialized after starting the information processing apparatus in S302. This indicates that the sensor itself and a part of the shared memory 16 that temporarily stores the sensor status are cleared. Error information already logged is continuously saved. The logged error information can be referred to at any time when requested by the CPU 1 (13-1) to CPU n (13-n).

  After initialization of error information in S302, synchronization with the controller b2 is performed in S303, it is determined whether there is a response, and it is confirmed whether the controller b2 is operating correctly. At this time, if there is no response from the controller b2, it is considered that an abnormality has occurred in the controller b2, the error information of the controller b2 is logged in the shared memory 16 in S311, the operation is stopped, and the controller a1 Only continue to monitor errors.

  In this case, in S312, it is confirmed whether an error has occurred in each sensor (sensor 1, a to sensor m, a).

  In S313, it is determined whether an error has occurred. If no error has occurred, the process returns to S312. If an error has occurred, error information is logged in the shared memory 16 in S314.

  In S315, for example, based on an error notification pattern as shown in FIG. 2, it is determined whether the number of errors in the controller a1 exceeds a threshold value. If the threshold value is not exceeded, the process returns to S312. If the threshold value is exceeded, an error is notified to the upper CPU in S316.

  If there is a response from the controller b2 in S303, it is checked in S304 whether an error has occurred in each sensor (sensor 1, a to sensor m, a).

  In S305, it is determined whether an error has occurred. If no error has occurred, the process returns to S303. If an error has occurred, error information is logged in the shared memory 16 in S306.

  In S307, it is determined whether the same error has occurred in the control controller b2. If the same error has not occurred, in S309, for example, information on the controller error logged in the shared memory 16 or the like. The number of errors so far is confirmed, and based on the error notification pattern as shown in FIG. 2, it is determined whether the number of errors in the controller a1 exceeds the threshold value. If the threshold value is exceeded, an error is notified to the upper CPU in S310.

  If the same error has occurred in S307, for example, information on the controller error logged in the shared memory 16 and the number of errors so far are confirmed in S308, as shown in FIG. Based on the error notification pattern, it is determined whether the number of errors in the controller a1 and the controller b2 exceeds a threshold value. If the threshold value is not exceeded, the process returns to S303. If the threshold value is exceeded, S310 is determined. To notify the host CPU of the error.

  The control controller b2 performs the same operation as the control controller a1, but is controlled by, for example, the control controller a1 and the control controller b2 so as not to notify the CPU of an error from both control controllers. If the controller a1 has a higher priority, and the controller a1 and the controller b2 are both operating to notify the CPU of an error, the controller a1 having a higher priority determines the error, Notification of an error to the CPU is also performed only from the control controller a1. Further, when a host controller is connected, the controller can determine an error to be notified to the CPU.

  Next, the detection operation timing of the controller a1 and the controller b2 will be described with reference to FIGS. 4 and 5 are time charts showing the timing of the detection operation of the controller a1 and the controller b2, FIG. 4 shows the operation when an error is detected by both of the paired sensors, and FIG. The operation when an error is detected by one of the sensors is shown.

  First, when an error is detected in both of the paired sensors, as shown in FIG. 4, in S4111 and S421, it is confirmed whether the controller a1 and the controller b2 are operating normally, and synchronization is established. After that, only the controller b2 adds a waiting time before checking the first sensors 1 and b as shown by 431 in FIG.

  In S412 to S413, the errors of the sensors 1, a to m, a connected to the controller a1 are confirmed, and the sensors 1, b to m, b connected to the controller b2 in S422 to S423. Check for errors.

  Then, as a result of the sensor error confirmation, both the controller a1 and the controller b2 confirm the error with the i-th sensor (sensor i, a, sensor i, b), and the error of each sensor is confirmed with S414, S424. Log to the shared memory 16 and exchange error information in S415 and S425.

  Then, in S416, based on the error notification pattern as shown in FIG. 2, it is determined whether the number of errors in the control controller a1 and the control controller b2 exceeds the threshold value, and the error is notified to the host CPU based on the determination result. .

  In S417 and S426, after confirming again that the control controller a1 and the control controller b2 are operating normally and synchronizing, only the control controller b2 has the first sensors 1 and b as shown at 432 in FIG. Before checking, a waiting time is added, the sensor error check is restarted from sensors 1 and a in S418, the sensor error check is restarted from sensors 1 and b in S427, and the same operation is repeated.

  Further, when an error is detected in one of the paired sensors, as shown in FIG. 5, in S511 and S521, it is confirmed whether the controller a1 and the controller b2 are operating normally, and synchronization is established. Thereafter, only the controller b2 adds a waiting time before checking the first sensors 1 and b as indicated by 531 in FIG.

  In S512 to S513, the errors of the sensors 1, a to m, a connected to the controller a1 are confirmed, and the sensors 1, b to sensors m, b connected to the controller b2 in S522 to S523. Check for errors.

  As a result of the sensor error check, only the controller a1 checks the error with the i-th sensor (sensor i, a), logs the sensor error into the shared memory 16 at S514, and stores error information at S515 and S524. Exchange.

  Then, in S516, based on the error notification pattern as shown in FIG. 2, it is determined whether the number of errors in the controller a1 exceeds the threshold value, and an error is notified to the host CPU based on the determination result.

  Then, in S517 and S525, after confirming whether the controller a1 and the controller b2 are operating normally with each other again and synchronizing them, only the controller b2 includes the first sensors 1 and b as shown at 532 in FIG. Before checking, a waiting time is added, the sensor error check is restarted from sensors 1 and a in S518, the sensor error check is restarted from sensors 1 and b in S526, and the same operation is repeated.

  As indicated by 431, 432, 531 and 532 in FIGS. 4 and 5, only the controller b2 checks the first sensor 1 and b before adding the waiting time to the paired sensors. It is possible to always have a time difference in the error status check, and it is possible to solve the problem that the paired sensors simultaneously detect sudden noise.

  In addition, the problem that a pair of sensors simultaneously detect a sudden noise is solved by changing the order in which the sensor status is checked instead of adding waiting time between the controller a1 and the controller b2. It is also possible.

(Embodiment 2)
In the second embodiment of the present invention, the controller, the control bus, and the sensor are tripled in the first embodiment.

  The configuration of the error detection control unit in the information processing apparatus according to the second embodiment of the present invention will be described with reference to FIG. FIG. 6 is a block diagram showing the configuration of the error detection control unit in the information processing apparatus according to Embodiment 2 of the present invention.

  In FIG. 6, the error detection control unit in the information processing apparatus includes a control controller c21, a control bus c26 connected to the control controller c21, and a sensor connected to the control bus c26, and other configurations are shown in FIG. The configuration is the same as that of the first embodiment.

  Each sensor includes, for example, a voltage sensor c22-1 for detecting the voltage of the CPU1 (13-1), a temperature sensor c23-1 for detecting the temperature of the CPU1 (13-1), and a temperature sensor c24 for detecting the temperature in the system. -1 and rotation sensor c25-1 for detecting the rotation of FAN1 (14-1) are provided, and each of the CPUs (CPU1 (13-1) to CPUn (13) is similar to the first embodiment. -N)) and a plurality of FANs (FAN1 (14-1) to FANn (14-n)), etc., are also provided with sensors for detecting the state of each device, the temperature of the System at a plurality of locations, and the like.

  The operation of each control controller in the second embodiment is the operation in S303 shown in FIG. 3, in which the controller b2 and the controller c21 are synchronized, and in the subsequent processing, an error notification pattern as shown in FIG. The operation is the same as that of the first embodiment except that the error is notified based on the error detection state in the controller a1, the controller b2, and the controller c21.

  Also, if there is a control controller that does not respond, the operation of the control controller is stopped and, for example, as in the first embodiment, it is continued with the remaining executable control controllers in a duplex state. Then, perform error monitoring.

  Next, an error notification pattern according to the second embodiment will be described with reference to FIG. FIG. 7 is a diagram showing a pattern of error notification by detection of sensor error information.

  For example, even if error information is not detected in all of the sensors that are duplicated, if an error occurs in two sensors, there may be a problem with the device, so an error message To be notified.

  In the example shown in 211 of FIG. 7, when an error is detected by only one of the three sensors, an error is not notified because there is a possibility of erroneous detection.

  In the example shown at 212 in FIG. 7, when an error is detected by all three sensors, the error is notified because there is a high possibility of occurrence of consistency and the occurrence of an error.

  In the example shown at 213 in FIG. 7, if an error is detected by two of the three sensors that are tripled, the error is inconsistent and the possibility of an error is high, so an error is notified. .

  It should be noted that not only the error notification pattern shown in FIG. 7 but also a triple error notification pattern can be set in more detail. Therefore, by setting a combination of a plurality of error information, the model can be changed. An optimum error detection value can be set, and the accuracy can be improved.

  In the second embodiment, the control controller, the control bus, and the sensors are tripled, so that the possibility of erroneous detection of errors can be further reduced and the reliability can be further increased.

  In the second embodiment, the example of triple is described, but it is also possible to implement multiplexing of triple or more by increasing the number of control controllers and control buses.

(Embodiment 3)
In the third embodiment of the present invention, the duplicated control bus is divided into a control bus to which a CPU-related sensor is connected and a control bus to which a system information-related sensor is connected in the first embodiment. It is.

  The configuration of the error detection control unit in the information processing apparatus according to the third embodiment of the present invention will be described with reference to FIG. FIG. 8 is a block diagram showing the configuration of the error detection control unit in the information processing apparatus according to Embodiment 3 of the present invention.

  In FIG. 8, the error detection control unit in the information processing apparatus includes CPU-related sensors (voltage sensor a5-1 to voltage sensor a5-n, temperature sensor a7-1 to temperature sensor a7) in the control bus a3 and the control buzz b4. -N, voltage sensor b6-1 to voltage sensor b6-n, temperature sensor b8-1 to temperature sensor b8-n) are connected, and control bus c26 connected to the controller c21 and control connected to the controller d31 System information related sensors (temperature sensor a9-1 to temperature sensor a9-n, rotation sensor a11-1 to rotation sensor a11-n, temperature sensor b10-1 to temperature sensor b10-n, rotation sensor b12 are connected to bus d41. -1 to rotation sensor b12-n) are connected, and the other configuration is the same as that of the first embodiment shown in FIG.

  The operation of each controller in the third embodiment is performed except that the controller a1 and the controller b2 detect CPU-related sensor errors, and the controller c21 and the controller d31 detect system information-related sensor errors. These are the same as the duplex operation in the first embodiment.

  As for the error notification pattern, the error notification is determined based on the error notification pattern of the first embodiment shown in FIG.

  In the third embodiment, when many sensors are connected, it is possible to avoid conflicts and improve the response by dividing the control bus.

(Embodiment 4)
In the fourth embodiment of the present invention, the sensor is duplicated in the first embodiment, and the controller and the control bus are duplicated.

  The configuration of the error detection control unit in the information processing apparatus according to Embodiment 4 of the present invention will be described with reference to FIG. FIG. 9 is a block diagram showing the configuration of the error detection control unit in the information processing apparatus according to Embodiment 4 of the present invention.

  In FIG. 9, the error detection control unit in the information processing apparatus includes a control controller c21, a control bus c26 connected to the control controller c21, a control controller d31, and a control bus d41 connected to the control controller d31. The controller d31 detects an error of the same sensor as the sensor detecting the error in the controller a1 and the controller b2, and the other configuration is the same as that of the first embodiment shown in FIG. .

  The operation of each control controller according to the fourth embodiment is the operation in S303 shown in FIG. 3, and is synchronized with the controller b2, the controller c21, and the controller d31, and in the subsequent processing, as shown in FIG. The operation is the same as that of the first embodiment except that the error is notified based on the error detection state in the controller a1, the controller b2, the controller c21, and the controller d31 based on the error notification pattern.

  Further, if there is a controller that does not respond, the operation of the controller is stopped and executed in a duplex or triple state, for example, as in the first or second embodiment. Continue error monitoring on the remaining possible controller.

  Next, an error notification pattern according to the fourth embodiment will be described with reference to FIG. FIG. 10 is a diagram showing a pattern of error notification by detection of error information of the sensor.

  For example, even if error information from the sensor is not detected in all the quadruple buses, if an error occurs in three quadruple buses, the error is detected in the device that detected the error. An error message should be notified because there may be a problem.

  In the example indicated by reference numeral 231 in FIG. 10, when an error is detected on four quadruple buses, an error is notified because consistency is likely and an error may occur.

  In the example indicated by reference numeral 232 in FIG. 10, when an error is detected on three quadruple buses, the error is notified because the consistency is high and the possibility of an error occurrence is high.

  In the example indicated by reference numeral 233 in FIG. 10, when an error is detected within two times by the same sensor of two quadruple buses, an error is not notified because there is a possibility of erroneous detection.

  In the example indicated by reference numeral 234 in FIG. 10, if an error is detected three or more times by the same sensor of two buses that are quadruple, there is a possibility that there is a problem with the control bus that cannot be detected. An error is notified even if no error occurs.

  In the example indicated by 235 in FIG. 10, when an error is detected by different sensors on two quadruplicated buses, the error is notified because the possibility of erroneous detection is low.

  In the example indicated by 236 in FIG. 10, when an error is detected with only one quadruple bus, an error is not notified because there is a possibility of erroneous detection.

  In addition to the error notification pattern shown in FIG. 10, when quadruple, the error notification pattern can be set in more detail, so by setting a combination of multiple error information, An optimum error detection value can be set, and the accuracy can be improved.

  In the fourth embodiment, it is possible to further reduce the possibility of erroneous detection of errors and further increase the reliability by duplicating the control controller and the control bus while the sensors are duplicated. Since the sensors remain duplexed, the cost can be reduced as compared with the case where all the sensors are quadrupled.

  In the fourth embodiment, the control controller is quadruple, but it is also possible to reduce the cost while increasing the reliability by making the control controller only double and only the control bus quadruple.

  In the first to fourth embodiments, the system configuration diagram on the same board has been described as an example. However, it is also possible to carry out error control of an external device by extending the control bus. Logically, as long as the bus is connected, there is no difference in the error detection method between the internal device and the external device.

  In the first to fourth embodiments, a plurality of CPUs (CPU1 (13-1) to CPUn (13-n)) and a plurality of FANs (FAN1 (14-1) to FANn (14-n)) are used. Although the example of detecting each state by each sensor has been described, the state of only one CPU or one FAN may be detected by each sensor.

It is a block diagram which shows the structure of the error detection control part in the information processing apparatus by Embodiment 1 of this invention. It is a figure which shows the pattern of the error notification by the detection of the error information of the sensor by Embodiment 1 of this invention. It is a flowchart which shows operation | movement of the controller in the information processing apparatus by Embodiment 1 of this invention. It is a time chart which shows the timing of the detection operation of the controller a and the controller b in the information processing apparatus by Embodiment 1 of this invention. It is a time chart which shows the timing of the detection operation of the controller a and the controller b in the information processing apparatus by Embodiment 1 of this invention. It is a block diagram which shows the structure of the error detection control part in the information processing apparatus by Embodiment 2 of this invention. It is a figure which shows the pattern of the error notification by the detection of the error information of the sensor by Embodiment 2 of this invention. It is a block diagram which shows the structure of the error detection control part in the information processing apparatus by Embodiment 3 of this invention. It is a block diagram which shows the structure of the error detection control part in the information processing apparatus by Embodiment 4 of this invention. It is a figure which shows the pattern of the error notification by the detection of the error information of the sensor in the information processing apparatus by Embodiment 4 of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Control controller a, 2 ... Control controller b, 3 ... Control bus a, 4 ... Control bus b, 5-1 to 5-n ... Voltage sensor a, 6-1 to 6-n ... Voltage sensor b, 7- 1-7-n ... temperature sensor a, 8-1 to 8-n ... temperature sensor b, 9-1 to 9-n ... temperature sensor a, 10-1 to 10-n ... temperature sensor b, 11-1 11-n: rotation sensor a, 12-1 to 12-n ... rotation sensor b, 13-1 to 13-n ... CPU, 14-1 to 14-n ... FAN, 15 ... inter-controller bus, 16 ... shared memory , 17 ... Host controller connection bus, 21 ... Control controller c, 22-1 ... Voltage sensor c, 23-1 ... Temperature sensor c, 24-1 ... Temperature sensor c, 25-1 ... Rotation sensor c, 26 ... Control Bus c, 31 ... Control controller d, 41 ... Control bus d.

Claims (3)

A plurality of sensors for detecting the internal state of the device;
A controller that determines an abnormal state inside the device based on information detected by the plurality of sensors;
An information processing apparatus comprising: a multiplexed bus that transmits information detected by the plurality of sensors to the control controller. A plurality of sensors each multiplexed to detect the internal state of the device;
A multiplexed controller that determines an abnormal state inside the device based on information detected by the plurality of sensors;
An information processing apparatus comprising: a multiplexed bus that transmits information detected by the plurality of multiplexed sensors to the multiplexed controller. The information processing apparatus according to claim 1 or 2,
An information processing apparatus characterized by adding a time difference to transmission control of each information in the multiplexed bus.

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