JP2005153414A - Recorder and method of controlling the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To efficiently use a memory region and to reduce an amount of data transmitted from a host device. <P>SOLUTION: This serial type recorder performs color recording by using a plurality of colors. A recording buffer 4 for diving a recording region in a scanning direction of a recording head into a plurality of regions and storing image data by a unit of division, is provided to the recorder. The image data by a unit of division which is transmitted from a host device connected thereto and includes information relating to a delimiter of each color data is stored in a reception buffer 2. Respective color data are discriminated from the image data stored in the reception buffer by a data development block 3 and writing address information of the image data by a unit of division is stored in a recording buffer 4 together with the color data. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a recording apparatus and a control method for the recording apparatus, and in particular, in order to perform color recording with a plurality of colors by scanning a carriage mounted with a recording head on a recording medium, a recording area in the scanning direction of the recording head is defined. The present invention relates to a recording apparatus having a recording buffer that divides into a plurality of areas and stores image data of the divided areas, and a control method for the recording apparatus.

  Printers are widely used as recording devices for recording images and information output from computer devices and digital cameras. Various types of recording methods are known for printers, but inkjet methods have recently been used for reasons such as non-contact recording on recording media such as paper, easy colorization, and high quietness. In particular, the configuration is a serial in which a recording head for ejecting ink according to desired recording information is mounted and recording is performed while reciprocating scanning in a direction crossing the feeding direction of a recording medium such as paper. In general, the recording method is widely used because it is inexpensive and easy to downsize.

  Such a printer converts received data into recording data and temporarily stores it in a recording buffer. For example, Japanese Patent Publication No. 63-12290 (Patent Document 1) describes a technique using a ring structure in order to use the recording buffer efficiently. This technique includes an address pointer for storing recording data in a memory area, an address pointer for reading out the data, and a recording data number count register for managing an empty area of the memory area, and a circulation area Attempts have been made to improve the efficiency of memory use.

  When such a ring buffer structure is applied to a full-color recording apparatus, if a ring buffer structure corresponding to the color (ink) used for recording is prepared, the buffer structure is first allocated for each color, so recording should be performed. Even when there is no data, it is necessary to prepare the area, and it becomes difficult to use the memory area efficiently.

Japanese Patent Publication No. 63-12290

  However, in the method described in the above specification, the data transmitted from the host device to the recording apparatus and stored in the recording buffer has various data for forming the image in addition to the image data in the command section. . The command part data includes color data to indicate the block structure, but since this color data is provided for each block, the paper size, paper feed execution, paper feed amount setting, and recording head to be used Compared with setting data such as, the amount of data will be considerably larger.

  When the amount of data other than image data increases, the time required for communication with the host device increases and the throughput of the recording apparatus decreases.

  The present invention has been made in view of the above situation, and an object thereof is to reduce the amount of data transmitted from the host device while efficiently using the memory area.

A recording apparatus according to an aspect of the present invention that achieves the above object is provided with a recording area in a scanning direction of a recording head in order to perform color recording with a plurality of colors by scanning a carriage mounted with the recording head on the recording medium. Is a recording apparatus having a recording buffer for storing image data of the divided area units.
A reception buffer that stores image data in units of divided areas that are transmitted from a connected host device and that includes information indicating a delimiter of each color data;
A data processing unit that generates presence / absence information of each color data based on the information indicating the separation of each color data;
A write control unit for controlling to store the write address information of the image data for each area together with the color data in the recording buffer based on the image data stored in the reception buffer and the presence / absence information of each color data;
A read controller for controlling read address information for reading image data stored in the recording buffer for each color data;
According to the image data read based on the read address information, a recording data generating means for generating the divided area unit recording data;
It has.

According to another aspect of the present invention, there is provided a control method for a recording apparatus, wherein a recording area in a scanning direction of a recording head is formed in order to perform color recording with a plurality of colors by scanning a carriage having a recording head on a recording medium. A control method of a recording apparatus having a recording buffer that divides into a plurality of areas and stores image data of the divided areas.
A receiving step of storing the image data of the divided region units including information indicating a delimiter of each color data transmitted from the connected host device in a reception buffer;
A data processing step of generating presence / absence information of each color data based on the information indicating the separation of each color data;
A write control step for controlling to store the write address information of the image data for each area together with the color data in the recording buffer based on the image data stored in the reception buffer and the presence / absence information of each color data;
A read control process for controlling read address information for reading image data stored in the recording buffer for each color data;
According to the image data read based on the read address information, a recording data generation step for generating recording data for the divided area units;
It has.

  That is, in the present invention, in order to perform color recording with a plurality of colors by scanning a carriage having a recording head on a recording medium, the recording area in the scanning direction of the recording head is divided into a plurality of areas. In a recording apparatus having a recording buffer for storing image data for each area, the divided area-unit image data including information indicating a delimiter for each color data transmitted from the connected host device is stored in the reception buffer. Based on the information indicating the separation of each color data, the presence information of each color data is generated. Based on the image data stored in the reception buffer and the presence information of each color data, write address information of the image data for each area is obtained. It is controlled so that it is stored in the recording buffer together with the color data, and a read address for reading out the image data stored in the recording buffer. Controls scan information for each color data, in accordance with the image data read based on the read address information, generates print data of the divided area units.

  In this way, each color data is identified from the divided area unit image data including information indicating the delimiter of each color data transmitted from the host device, and the write address information of the area unit image data is the color data. The read address information of the image data stored in the record buffer together with the data is controlled for each color data, and the record data in units of areas divided according to the image data read based on the read address information Is generated.

  Therefore, when performing color recording using a plurality of colors in the recording apparatus, the amount of data transmitted from the host device to the recording apparatus is reduced in a configuration that efficiently uses the memory area used as the reception buffer and the recording buffer. Can be reduced.

  The read control unit preferably has a register that holds the presence / absence information of each color data, and holds the presence / absence information of each color data generated by the data processor.

  The writing control unit stores the data of each color in the recording buffer with the same size, or the writing control unit is information indicating a color data delimiter in the color data when the data of a certain color is less than a predetermined size. It is good to add it and store it in the recording buffer.

  The recording buffer is preferably configured as a so-called ring buffer capable of storing image data in a circulating manner between areas set by the head address information and the last address information.

  It is more effective that the number of data that can be stored in the recording buffer is the number of data in the recording area smaller than the recording area for one scan.

  As described above, according to the present invention, in the configuration in which the memory area used as the reception buffer and the recording buffer is efficiently used when the recording apparatus performs color recording using a plurality of colors, the host device The amount of data transmitted from the recording device to the recording device can be reduced.

  Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the drawings. However, the constituent elements described in this embodiment are merely examples, and are not intended to limit the scope of the present invention only to them.

  In the embodiment described below, a recording apparatus using a recording head according to an ink jet method will be described as an example.

  In this specification, “recording” (sometimes referred to as “printing”) is not only for forming significant information such as characters and figures, but also for human beings visually perceived regardless of significance. Regardless of whether or not it has been manifested, it also represents a case where an image, a pattern, a pattern, or the like is widely formed on a recording medium or the medium is processed.

  “Recording medium” refers not only to paper used in general recording apparatuses but also widely to cloth, plastic film, metal plate, glass, ceramics, wood, leather, and the like that can accept ink. Shall.

  Furthermore, “ink” (sometimes referred to as “liquid”) is to be interpreted broadly in the same way as the definition of “recording (printing)” above. It represents a liquid that can be used for forming a pattern or the like, processing a recording medium, or processing an ink (for example, solidification or insolubilization of a colorant in ink applied to the recording medium).

  Furthermore, unless otherwise specified, the “nozzle” is a generic term for an ejection port or a liquid channel communicating with the nozzle and an element that generates energy used for ink ejection, and corresponds to a “recording element”. To do.

[First Embodiment]
<Description of inkjet recording apparatus>
FIG. 18 is an external perspective view showing an outline of the configuration of the inkjet recording apparatus 1 which is a typical embodiment of the present invention.

  As shown in FIG. 18, an ink jet recording apparatus (hereinafter referred to as a recording apparatus) transmits a driving force generated by a carriage motor M1 to a carriage 1902 on which a recording head 1903 that performs recording by discharging ink in accordance with an ink jet system is mounted. 1904, the carriage 1902 is reciprocated in the direction of arrow A, and for example, a recording medium P such as recording paper is fed through a paper feeding mechanism 1905 and conveyed to a recording position. At the recording position, the recording head 1903 is conveyed. Recording is performed by ejecting ink onto the recording medium P.

  In order to maintain the state of the recording head 1903 well, the carriage 1902 is moved to the position of the recovery device 1910, and the discharge recovery processing of the recording head 1903 is performed intermittently.

  In addition to mounting the recording head 1903 on the carriage 1902 of the recording apparatus, an ink cartridge 1906 for storing ink to be supplied to the recording head 1903 is mounted. The ink cartridge 1906 is detachable from the carriage 1902.

  The recording apparatus shown in FIG. 18 can perform color recording. For this reason, the carriage 1902 contains four inks containing magenta (M), cyan (C), yellow (Y), and black (K) inks, respectively. A cartridge is installed. These four ink cartridges are detachable independently.

  The carriage 1902 and the recording head 1903 can achieve and maintain a required electrical connection by properly contacting the joint surfaces of both members. The recording head 1903 selectively discharges and records ink from a plurality of discharge ports by applying energy according to a recording signal. In particular, the recording head 1903 of this embodiment employs an ink jet system that ejects ink using thermal energy, and includes an electrothermal transducer to generate thermal energy, which is applied to the electrothermal transducer. Electric energy is converted into thermal energy, and ink is ejected from the ejection port by utilizing pressure changes caused by bubble growth and contraction caused by film boiling caused by applying the thermal energy to the ink. The electrothermal transducer is provided corresponding to each of the ejection ports, and ink is ejected from the corresponding ejection port by applying a pulse voltage to the corresponding electrothermal transducer in accordance with the recording signal.

  As shown in FIG. 18, the carriage 1902 is connected to a part of the driving belt 1907 of the transmission mechanism 1904 that transmits the driving force of the carriage motor M1, and slides in the direction of arrow A along the guide shaft 1913. It is guided and supported freely. Accordingly, the carriage 1902 reciprocates along the guide shaft 1913 by forward and reverse rotations of the carriage motor M1. A scale 1908 is provided for indicating the absolute position of the carriage 1902 along the direction of movement of the carriage 1902 (arrow A direction). In this embodiment, the scale 1908 uses a transparent PET film with black bars printed at the required pitch, one of which is fixed to the chassis 1909 and the other is supported by a leaf spring (not shown). Yes.

  Further, the recording apparatus is provided with a platen (not shown) facing the discharge port surface where the discharge port (not shown) of the recording head 1903 is formed, and the recording head 1903 is driven by the driving force of the carriage motor M1. Simultaneously with the reciprocating movement of the mounted carriage 1902, recording is performed over the entire width of the recording medium P conveyed on the platen by giving a recording signal to the recording head 1903 and ejecting ink.

  In FIG. 18, reference numeral 1914 denotes a conveyance roller driven by the conveyance motor M2 to convey the recording medium P, 1915 denotes a pinch roller that abuts the recording medium P against the conveyance roller 1914 by a spring (not shown), and 1916 denotes a pinch. A pinch roller holder 1917 that rotatably supports the roller 15 is a conveyance roller gear fixed to one end of the conveyance roller 1914. The conveyance roller 1914 is driven by the rotation of the conveyance motor M2 transmitted to the conveyance roller gear 1917 via an intermediate gear (not shown).

  Further, 1920 is a discharge roller for discharging the recording medium P on which an image is formed by the recording head 1903 to the outside of the recording apparatus, and is driven by the rotation of the transport motor M2 being transmitted. . The discharge roller 1920 abuts against a spur roller (not shown) that presses the recording medium P with a spring (not shown). Reference numeral 1922 denotes a spur holder that rotatably supports the spur roller.

  Further, as shown in FIG. 18, the recording apparatus includes a desired position (for example, a home position) outside the range of reciprocal motion (outside the recording area) for the recording operation of the carriage 1902 on which the recording head 1903 is mounted. The recovery device 1910 for recovering the ejection failure of the recording head 1903 is disposed at a position corresponding to the above.

  The recovery device 1910 includes a capping mechanism 1911 for capping the ejection port surface of the recording head 1903 and a wiping mechanism 1912 for cleaning the ejection port surface of the recording head 1903, and interlocks with the capping of the ejection port surface by the capping mechanism 1911. Ink recovery such as forcibly discharging ink from the discharge port by a suction means (suction pump or the like) in the recovery device, thereby removing ink or bubbles having increased viscosity in the ink flow path of the recording head 1903. Process.

  Further, at the time of non-recording operation or the like, by capping the ejection port surface of the recording head 1903 by the capping mechanism 1911, the recording head 1903 can be protected and ink evaporation and drying can be prevented. On the other hand, the wiping mechanism 1912 is disposed in the vicinity of the capping mechanism 1911 and wipes ink droplets adhering to the discharge port surface of the recording head 1903.

  The capping mechanism 1911 and the wiping mechanism 1912 can keep the ink ejection state of the recording head 1903 normal.

<Control configuration of inkjet recording apparatus>
FIG. 19 is a block diagram showing a control configuration of the recording apparatus shown in FIG.

  As shown in FIG. 19, the controller 600 includes a CPU 601, a ROM 602 storing a program corresponding to a control sequence to be described later, a required table, and other fixed data, control of the carriage motor M1, control of the transport motor M2, and recording. A special purpose integrated circuit (ASIC) 603 that generates a control signal for controlling the head 3, a RAM 604 such as an SRAM or DRAM provided with a development area for image data, a work area for program execution, and the like, a CPU 601, an ASIC 603, A system bus 605 that connects the RAMs 604 to each other to exchange data, an A / D converter 606 that inputs analog signals from a sensor group described below, performs A / D conversion, and supplies digital signals to the CPU 601. Consists of.

  In FIG. 19, reference numeral 610 denotes a computer (or an image reading reader, a digital camera, or the like) serving as a supply source of image data, and is collectively referred to as a host device. Image data, commands, status signals, and the like are transmitted and received between the host apparatus 610 and the recording apparatus 1 via an interface (I / F) 611.

  Further, reference numeral 620 denotes a switch group, which instructs activation of a power switch 621, a print switch 622 for instructing printing start, and a process (recovery process) for maintaining the ink ejection performance of the recording head 3 in a good state. For example, a recovery switch 623 for receiving a command input from the operator. Reference numeral 630 denotes a position sensor 631 such as a photocoupler for detecting the home position h, a temperature sensor 632 provided at an appropriate location of the recording apparatus for detecting the environmental temperature, and the like. It is a sensor group.

  Further, 640 is a carriage motor driver that drives a carriage motor M1 for reciprocating scanning of the carriage 2 in the direction of arrow A, and 642 is a conveyance motor driver that drives a conveyance motor M2 for conveying the recording medium P.

  The ASIC 603 transfers drive data (DATA) of the printing element (ejection heater) to the printing head while directly accessing the storage area of the RAM 602 during printing scanning by the printing head 3.

<Data processing configuration>
FIG. 1 is a functional block diagram relating to data processing in the recording apparatus.

  The correspondence between each block in FIG. 1 and the control configuration in FIG. 19 will be described. The interface controller 1 corresponds to the interface 611, the CPU 9 corresponds to the CPU 601, and the recording head 6 corresponds to the recording head 1903. The reception buffer 2, recording buffer 4, and buffer structure information memory 11 are all areas secured in the RAM 604. Further, the data development block 3, the recording data generation block 5, the reception buffering structure control circuit 7, and the recording buffering structure control circuit 9 are all provided in the ASIC 603. The CR encoder 10 includes a scale 1908 shown in FIG. 18 and a sensor that calculates an absolute position or a relative position in the scanning direction of the carriage from a scale memory provided in the carriage 1902.

  In the figure, the interface controller 1 extracts data and image data necessary for the operation of the recording apparatus from data transferred from a host computer (not shown) connected via an interface signal line S1. The extracted data is stored in the reception buffer 2 via the signal line S2.

  The reception buffer 2 is provided in the RAM 604 of FIG. The structure of data stored in the reception buffer 2 will be described with reference to FIGS. 2 (a) and 2 (b).

  As shown in the data structure of the reception buffer in FIG. 2A, data of “command” (201), “data length” (202), and “setting data” (203) are stored in this order from the left. Subsequently, data of “command” (204), “data length” (205), and “setting data” (206) are stored. This indicates that data transferred in chronological order is stored at consecutive addresses in the reception buffer. The setting data 206 shown here includes, for example, execution of paper feed, paper feed amount setting, and recording head to be used. It is information indicating the number and the like, and recording is possible with the recording apparatus only after all the information determined by the setting data is prepared. Thereafter, the image data (209, 212) to be recorded is stored in the reception buffer 2.

  The image data (209, 212) is data obtained by dividing the data amount required when the recording head records on the recording medium in one scan into blocks in units of smaller data amount. The image data is divided in units of blocks, and sequentially stored as first block data (209), second block data (212),.

  FIG. 2B is a diagram showing in detail the data structure of the image data divided into block units. As shown in FIG. 2B, a plurality of color data (213 to 214) are sequentially compressed as data. Stored. This color data is delimited by “color changing codes” (216, 217, 218).

  For example, assuming four color data of cyan, yellow, magenta, and black, using a print head in which nozzle rows each having 64 vertical nozzles for each color are arranged in two rows in the scanning direction, Since the data for each nozzle row constitutes one color data, the two nozzle rows for four colors, that is, the compressed color data of the first to eighth colors are converted into image data in one block data. Stored. The nozzles in this nozzle row are arranged in the recording medium conveyance direction. For example, the first and second colors are cyan data, the third and fourth colors are magenta data, the fifth and sixth colors are yellow data, and the seventh and eighth colors are black data. Become.

  FIG. 3 shows the data structure of a recording buffer that holds image data. For example, when a maximum length of about 8 inches is recorded in one scan, assuming that one block data has a size capable of recording about 1/8 inch in the scanning direction, a total of 8 blocks of image data can be recorded. An image for one scan is completed. The first block to the eighth block are arranged in the scanning direction of the recording head, and the first color data to the eighth color data are stored in each block data. The length of each color data stored in each block corresponds to the number of nozzles of the recording head.

  Returning to FIG. 1, the description of each control block is continued. Of the data stored in the reception buffer 2, “command”, “data length”, and “setting data” which are setting values for controlling the recording apparatus are read from the interface controller 1 by the CPU 9 via the signal line S 902. Are set in the respective control circuits (7, 8) in the figure (S903, S907). The CPU 9 interprets the read data (data corresponding to 201 to 208 in FIG. 2A), and controls overall recording control of the recording apparatus according to the result. On the other hand, regarding the processing of the image data, the CPU 9 activates the data expansion block 3 to execute the processing.

  As shown in FIG. 2B, the data expansion block 3 (data processing block) is sent from the reception buffer 2 to the three types of “compression TAG”, “data”, and “color change code” as the CPU 9 starts DMA. Data is read out and data development control (data processing) is executed based on these data. In this embodiment, PackBits compression is used as the data compression / decompression method. Therefore, when the compression TAG is 8 bits and is a value from 00h to 7Fh, processing is performed assuming that 1 to 128 non-contiguous data exists in the data area, and compression is performed. When TAG is 8 bits and is a value from FFh to 81h, a process of decompressing the next 1-byte data into 2 to 128 consecutive data is performed. When 80h is read at the compression TAG, it is processed as a color change code. The decompressed data is placed on the signal line S4 and written to the recording buffer 4.

  For example, if the TAG is 02h and the data is 11h and 12h, the actual expanded data is 11h and 12h. If the TAG is FEh and the data is aah, the decompressed data is aah, aah, aah.

  The recording buffer 4 stores the decompressed image data in the data structure shown in FIG. The head data of the first color data of the first block is written to the head address of the recording buffer 4 set by the CPU at the time of command interpretation, and the subsequent data is sequentially written while adding the addresses one by one. The area that can be stored as one color data at the address of the recording buffer is determined by the setting data read by the CPU 9 first, and since data exceeding that value cannot be written, the image data is compressed according to the setting data. Data size restrictions will be added. The data after detecting the color change code is sequentially written from the head address of the second color data set in advance by the CPU in the same manner as the area where one color can be stored before data reception.

  However, the processing is different when the color change codes are continuous. After storing the first color data, for example, in FIG. 2, after detecting the color change code (216), if it is detected that the content of the next data is the color change code (217), the second color data Judge that there is no. In this case, the third color data is written in order from the head address instead of the second color data.

  This writing is repeated from the first color data to the eighth color data in the first block, and when the color change code is detected after the eighth color data has been written, all the data in the first block has been written. The data expansion block 3 ends the data expansion operation, notifies the CPU 9 that the data expansion for one block has been completed by an interrupt (INT3), and waits for the next data expansion from the CPU 9 to start.

  The data development block 3 is provided with a counter for detecting the color change code and performs counting. As a result of determining the presence or absence of data from the first color to the eighth color (information), data presence / absence information (for example, 1) for each color Bit data). The data presence / absence register for holding the data presence / absence information of each color is set. For example, if it is determined that there is no second color data, a value indicating “no data” is set in the data presence / absence register for the second color data. As a result, the first color to the eighth color are sent in order, so that the third color data is stored in the area next to the first color data. A value indicating “data present” is set in the data presence / absence registers of the first color data and the third color data. In this way, information on the presence or absence of data for the first color data to the eighth color data is set in the register. These “data present” and “data absent” information are used for reading each color data from a recording buffer, which will be described later.

  When a plurality of blocks of image data are arranged on the recording buffer 4, the CPU 9 operates the carriage motor M1 to start the recording operation, and the recording head 6 scans the image data to the carriage encoder (CR encoder) 10. Images can be recorded on a recording medium by synchronously transferring and recording. After the recording head 6 scans in the main scanning direction, the conveying means conveys the recording medium in the sub scanning direction. Thus, the scanning of the recording head and the conveyance of the recording medium are repeatedly performed to record an image for one page.

  The recording data generation block 5 reads each block structure of the image data on the recording buffer 4 via the signal line S5 at a timing synchronized with the CR encoder 10 in accordance with a value designated by the CPU 9, and the recording head 6 performs recording. The data is output to the signal line S6 while being converted into a possible data structure. This recording data generation block 5 holds information on the block width (indicating the length of the block) in the recording buffer, which will be described later, and information on the height of each color of the block (referred to as “raster number” of color data). To do.

<Receiving buffer write / read control>
As described above, the interface controller 1 writes data to the reception buffer 2 and the data expansion block 3 reads only image data. The reception buffering structure control circuit controls the write address and read address. 7. The reception buffering structure control circuit 7 manages the start address and the end address of the reception buffer 2, and the write address and read address.

  The reception buffering structure control circuit 7 adds one address each time a write request signal (S701) received from the interface controller 1 is received, and outputs this to the reception buffer 2 as write address information (signal line S702). Then, the reception buffering structure control circuit 7 performs control to return the write address to the head address of the reception buffer 2 when the final address of the reception buffer 2 is reached.

  When the write address reaches (matches) the read address, the reception buffer 2 is filled with data and communicates to the interface controller 1 via the signal line S703 that the next data cannot be written.

  At the same time, the reception buffer 2 notifies the CPU 9 that the data cannot be written by an interrupt signal on the signal line S904. The structure of the reception buffer 2 can be set by the CPU 9 writing to an internal register using the bus of the signal line S903.

  When the CPU 9 reads the data in the reception buffer 2 directly through the data read register in the reception buffering structure control circuit 7, the data expansion block 3 sends the data read request signal line S705 to the read address. When the request is made, the read address is added one by one via the signal line S706 and outputted to the reception buffer 2.

  The reception buffering structure control circuit 7 performs control to return the read address to the head address of the reception buffer 2 when the read address reaches the final address. When the read address reaches (matches) the write address, data is lost from the reception buffer, so that the next data cannot be read is communicated to the data development block via the signal line S704. At the same time, the CPU 9 is informed that there is no data to be read out on the reception buffer 2 through the interrupt signal line of the signal line S904.

  The above is the processing content of the data writing / reading control to the reception buffer 2. Next, the processing contents for writing the data read out from the reception buffer 2 and developed into the recording buffer or reading the data from the recording buffer will be described.

<Record buffer read / write control>
The data development block 3 writes image data to the recording buffer 4, and the recording data generation block 5 reads the written image data. At this time, the recording buffer controls the writing address and the reading address. This is a ring structure control circuit 8.

  The recording buffering structure control circuit 8 manages the start address, the end address, the write address, and the read address of the recording buffer.

  The recording buffering structure control circuit 8 adds one address each time it receives a write request signal (S801) received from the data development block 3, and outputs this to the recording buffer 4 as write address information (signal line S802). . Then, the recording buffering structure control circuit 8 performs control to return the write address to the top address of the recording buffer 4 when the final address of the recording buffer 4 is reached.

  When the write address reaches (matches) the read address, the recording buffer 4 is full of image data, and the data development block 3 is notified via the signal line S803 that the next image data cannot be written.

  When the data expansion block 3 reads the color change code from the reception buffer 2, the data expansion block 3 notifies that via the signal line S804, and the recording buffering structure control circuit 8 reads the next color data. Is prepared to output from the signal line S802. The structure of the recording buffer 4 can be set by the CPU 9 writing to an internal register using the bus of the signal line S907.

  When the recording data generation block 5 requests the read address for each color via the data read request signal line S805, the read address is added one address at a time via the signal line S806 and output to the recording buffer 4.

  The recording buffering structure control circuit 8 performs control to return the reading address to the head address of the recording buffer 4 when the reading address reaches the final address.

  The recording data generation block 5 sets the data structure of the image data block currently being read out from the CPU 9 to a register in the recording data generation block 5 via the signal line S908 bus. When all the image data in the set image data block structure is read, the end signal S909 is notified to the CPU 9 as an interrupt signal. At this time, if the next image data block is already developed on the recording buffer 4, the image data block structure is written in the register.

  Since the recording buffer 4 controls data writing in units of one image data block and does not activate a recording data generation block for an unwritten image data block, the read address of the recording buffer exceeds the write address. Absent. Reference numeral 11 denotes a buffer structure information memory. This is a working memory (work RAM) for controlling the recording buffer, and is an area for temporarily storing information about the recording buffer structure described later.

  The outline of the flow of recording data in the recording control unit has been described above. Hereinafter, detailed functions of each control block will be described.

<Interface controller>
FIG. 4 is a block diagram showing the inside of the interface controller 1, which includes a command analysis unit 101 and a data latch unit 102.

  The command analysis unit 101 determines whether the data string sent from the host computer via the interface signal line S1 is command information for confirming the state of the recording apparatus or the like, or data related to image data, and the received data is If it is command information for confirming the status or the like of the recording apparatus, a status for identifying the status of the apparatus is automatically responded, and if it is image data, control for temporarily storing it in the data latch unit 102 is performed. The command analysis unit 101 has a register for storing status information of the recording apparatus, and the CPU 9 writes the information in the register via the bus (S901).

  When the command analysis unit 101 receives data (command information, image data) through the interface signal line S1, the command analysis unit 101 outputs an interrupt signal (INT1) S902 to the CPU 9 to notify the completion of data reception. The CPU 9 receives the interrupt signal and starts data processing.

  The data latch unit 102 is a storage device of several bytes and has a FIFO structure. When the data latch unit 102 has data, the data latch unit 102 outputs a write request signal S701 to the reception buffering structure control circuit unit 7, and the data latch unit The write request signal S701 is output until there is no more data in 102. However, when the reception buffer 2 is full and cannot be written, or when data is not accepted due to some abnormality, the reception buffering structure control circuit unit 7 outputs a data transfer standby signal S703 and receives the standby signal S703 to receive the data latch unit. 102 stops the data transfer.

  When the data transfer is stopped, the FIFO of the data latch unit 102 is immediately filled with data and cannot receive data from the host computer side. In this case, the state of the apparatus body is set to the busy state, and the command analysis unit 101 receives the data. A retransmission request is output to the host computer as a result of being sent but not received.

<Reception buffering structure control circuit>
FIG. 5 is a block diagram showing details of the reception buffering structure control circuit unit 7, a write address register (WP) 701 for outputting an address (write pointer) for writing data of the interface controller 1 to the reception buffer 2, and reception It has a read address register (RP) 702 that outputs a read address (read pointer) for outputting data on the buffer 2 to the data development block 3, and outputs them as a write address signal line S702 and a read address signal line S706, respectively. . Furthermore, a start address register (top_adr) 703 and a last address register (bottom_adr) 704 for specifying the start address and the end address of the reception buffer 2 are provided. The initial values of these registers are set by the CPU 9.

  For example, the start address of the reception buffer 2 is set as the 1000h address in the start address register 703, the last address is set as the FFFFh address in the final address register 704, and there is no data on the reception buffer 2 at first. 1000h is set in the write address register 701 and the read address register 702.

  When there is no data in this initial state, the address control block 705 accepts the write request signal S701 from the interface controller 1, but outputs a buffer empty signal line S704 to notify the data development block 3 that there is no data, Notify that the read request signal S705 is not output. When the write request signal S701 from the interface controller 1 is received and the first data is written to the reception buffer 2, the address control block 705 adds one value of the write address register 701 and writes it back. The above control is performed every time there is a write request, and when the next write address exceeds the value set in the final address register 704, the value set in the start address register 703 as the next address is stored in the write address register 701. Value.

  When the value of the write address register 701 matches the value of the read address register 702, the reception buffer 2 is filled with unread data, and the next data cannot be written. Therefore, the address control block 705 is an interface control block. 1 outputs a buffer full signal line S703 to suppress the output of the write request signal S701.

  The state in which there is even one piece of data on the reception buffer 2 is when the value of the write address register 701 and the value of the read address register 702 are different. In this case, the address control block 705 stops outputting the buffer empty signal S704. When the data read request signal S705 from the data expansion block 3 is output and the data read from the reception buffer 2 is completed, the address control block 705 adds one value of the read address register 702 and writes it back.

  The above control is performed every time there is a read request, and when the next read address exceeds the value set in the final address register 704, the value set in the start address register 703 as the next address is stored in the read address register 701. Value.

  When the value of the read address register 702 matches the value of the write address register 701, there is no unread data on the reception buffer 2, and the next data cannot be read. Therefore, the address control block 705 is a data expansion block. 3 outputs a buffer empty signal line S704 to suppress the output of the read request signal S705.

  The address control block 705 outputs a reception buffer interrupt signal line S904 (INT2) to notify the CPU 9 when the reception buffer 2 is in a buffer empty state or a buffer full state, or when these states are released. To do.

  FIG. 6 is a diagram showing the operation timing of the reception buffering structure control circuit 7. The write request signal S701, the write address signal line S702, the buffer full signal line S703, the buffer empty signal line S704, the read request signal S705, and the read address signal. The change of each signal line of line S706 is shown. As described above, the write address signal line S702 is incremented by 1 each time the write request signal S701 is input, and the read address signal line S706 is incremented by 1 each time the read request signal S705 is input. When there is no data on the reception buffer, the buffer empty signal S704 is output (timing A and B in FIG. 6), and when the data is full on the reception buffer, the buffer full signal S703 is output (timing C in FIG. 6). .

<Recording buffer write address control>
The recording buffering structure control circuit will be described with reference to FIGS. In the processing of the recording buffering structure control circuit, FIG. 7 is a diagram for explaining mainly the write address control, and FIG. 10 is a diagram for explaining the reading address control of the recording buffering structure control circuit 8.

  The recording buffering structure control circuit 8 shown in FIG. 7 includes a read control unit 8A and a write address control unit 8B. In the buffer area of the recording buffer 4, the top address of the recording buffer is indicated by top_adr, and the final address is indicated by bottom_adr. The head address is stored in the register 803 in the write address control unit 8B, and the final address is stored in the register 804 in the write address control unit 8B.

  “RP” shown in the recording buffer 4 indicates a read pointer, and “WP” indicates a write pointer. A hatched portion between RP and WP in the recording buffer indicates that recording data is stored. The white portion of the recording buffer 4 indicates that recording data is not stored.

  802 in the read address control unit 8A is a register indicating a data read address (RP: read pointer). A read address control unit 8B 812 ′ is a register that stores information on the height (the same height) of each color for the first to eighth colors, and is a step register that stores an offset value from top_adr in advance. Reference numeral 813 denotes a register for storing information on the width of each block. A register 815 stores the address of the next block. This address is determined by height information (not shown) and a value of 813. A register 816 stores a data write address (WP: write pointer). An address control register 814 manages the writing process so that the write address does not overtake the read address, as will be described later with reference to FIG.

<Storing data in the recording buffer>
FIG. 8 is a diagram for explaining how image data is stored in the recording buffer. In the present embodiment, the buffer shown in FIG. 8 is described as having a configuration in which an area having the same size as the color block area necessary for the recording operation is secured as the color data storage area.

  FIG. 8A shows a state in which the first color data is stored in the order of four words in the vertical direction. Here, one word corresponds to 16 pixels. The stored address is incremented by one. Accordingly, the write pointer (WP) is advanced from 1 to 2, 3, 4, 5 in order. In this case, the value of the register 813 (block width) is “28”.

  FIG. 8B shows that when there is the second color data, the light pointer (WP) indicated by the arrow moves to the start address of the second color after all the data is stored in the first color storage area. The second color data is stored.

  FIG. 8C shows how the second color data is stored when there is a blank portion in the first color data storage area. In this embodiment, the next color data is stored without filling the blank portion. After storing the first color data, the data development block 3 identifies the color change code, so that it is determined that the storage of the first color data is completed, and the value of the register 815 described in FIG. Based on this, as shown by the arrow, the write pointer (WP) moves to the head of the second color address and stores the second color data therefrom.

  FIG. 8D shows a state where there is no second color data. In the present embodiment, if there is no next color data, the storage area for the color data is not secured after the storage area for the previous color data. Therefore, although the storage area for the second color data should normally be secured following the first color data, the data development block 3 identifies the two color change codes in succession, Three colors of data are stored at the next address.

  FIG. 8E shows that for the second color data, the write pointer (WP) indicating the write position stops writing before the read pointer (RP) indicating the read position. This is because control is performed to prevent overwriting by prohibiting data writing at a position where reading is not completed. The above control is performed similarly for the third to eighth color regions.

<Recording buffer read address control>
Hereinafter, read address control of the recording buffer will be described with reference to FIG. The left side of the figure shows the read address control unit 8A of the recording buffering structure control circuit 8, and the right side of the figure shows the recording buffer 4.

  The buffer area of the recording buffer 4 is represented by top_adr, which is the top address of the recording buffer, and the final address is represented by bottom_adr. The start address is stored in the register 803 and the final address is stored in the register 804. “RP” shown in the recording buffer is a read pointer as in FIG. 7, and “WP” is a write pointer. A hatched portion between RP and WP in the recording buffer 4 indicates that recording data is stored, and a white portion of the recording buffer indicates that recording data is not stored.

  Reference numeral 802 in the read address control unit 8A is a register indicating a data read address (RP: read pointer). 900 surrounded by a broken line frame is a first register group, and 901 surrounded by a solid line frame is a second register. Is a group.

  When recording image data from the first block to the eighth block, for example, at the start of scanning, information about the first block is stored in the first register group 900. The second register group 901 stores information about the second block. When the recording of the first block is completed, the information of the second register group 901 is copied to the first register group 900, and the information of the second block is stored in the first register group 900. The second register group 901 stores information on the third block. Thereafter, the processing is performed in order until the data of the last eighth block is stored. At the start of the next scan, the first block information is again stored in the first register group 900 and the second block information is stored in the second register group 901.

  A register (1st_hight 1 color bit) 819 in the first register group is a register for setting height information about the first color and presence / absence information of color data. Each of the registers 822, 824, 826, 828, 830, 832, and 834 is a register for setting height information and color data presence / absence information for the second to eighth colors. The information on the presence / absence of the color data is copied from the data presence / absence register information of the data development block 3 described above. This copying is performed by processing by the CPU or data setting means (circuit).

  A register 820 stores the width of each block. This width information is a value that is commonly used in units of blocks from the first color to the eighth color.

  A register (1st_color_adr) 818 is a register for storing the read address of the first color. When the data is read from the recording buffer 819 in which the first color data is stored, the address is updated. For example, as shown in FIG. 8A, data for one column is read out in the order of 1, 2, 3, 4 in the first color data. Registers 821, 823, 825, 827, 829, 831, and 833 are registers for storing read addresses of the second to eighth colors, respectively, and the color data of the second to eighth colors are also the color data of the first color. Similarly, the data for one column is read in order.

  Since the data stored in the recording buffer 4 includes a plurality of color data, for example, when the color data of the first, second color,... Are mixed, the address for storing the color data of each color unit is It will not be continuous. Therefore, if there is only one read address register, it is necessary to calculate an address when reading one address of the second color recording buffer next to the address of the first color recording buffer 4, for example. By preparing a register for storing the read address for each color in the recording buffer 4, it is possible to omit the address calculation when reading in units of columns.

  Reference numeral 817 denotes an address control register. When the recording data generation block 5 requests the read address for each color via the data read request signal line S805, the address control register 817 adds the read address by one address via the signal line S806 and outputs the read address to the recording buffer 4. To do.

  A register 835 stores the address of the next block. If the block currently being read is the first block, this register stores the start address of the second block. The value of this register is copied to the register 802 when reading of the block data currently being read is completed. As a result, the next block data can be read smoothly.

  The register 836 is a table that stores information for specifying the reading order among the first to eighth colors. The order of reading data from the recording buffer can be freely set by the values set in this table. For example, the first color, the second color,..., And the eighth color can be read in this order. It is also possible to change the value and skip reading of data of the third color and the fourth color such as the first color, the second color, the fifth color, the sixth color, the seventh color, and the eighth color. . As a result, it is possible to accurately read out image data of colors that are not stored.

  The second register group 901 is a collection of buffers for storing information relating to the next block data. When each register in the first register group is read, the value set in each register in the second register group is set in the corresponding register in the first register group. For example, the value set in the register 838 is set in the register 819. Registers 839 to 845 are registers in which similar information is set for the second to eighth color data in the next block data.

  The register 838 (819) stores the buffer height information of the first color data and information indicating the presence or absence of the first color data.

  846 (820) is a register for setting block width information. This width information is a value that is commonly used in units of blocks from the first color to the eighth color.

  The register 878 can reset the same value in the first register group by setting this value to “1” when the same block size as the previously set block size is the same. In this case, the setting of the registers 838 to 846 can be omitted. When the value of the register 878 is “0”, the respective values are set in the registers 838 to 846. If the block size is the same by the register (same_type) 878, the register can be easily set.

<Relationship between recording area and recording data>
FIG. 9A is a diagram schematically illustrating a relationship between a recording area recorded in one scan and image data recorded in the area. FIG. 9A shows that there is no image data in the area D indicated by the arrow and the area corresponding to the eighth block. This region D is a region including the right side of the third block, all of the fourth blocks, and the left side of the fifth block.

  FIG. 9B is an explanatory diagram of image data written in the recording buffer corresponding to FIG. 9A. Since there is no image data in the area corresponding to the fourth block in the area D of FIG. 9A, the fourth block is not secured in the recording buffer.

  In FIG. 9B (a), the data stored in the second block does not include the third color data and the fourth color data. Stored. Only the first color data and the second color data are stored in the third block, and no color data after the third color is stored. The hatched portions of the second block and the third block indicate that no buffer is allocated because there is no data. Accordingly, the next address after the last address of the eighth color data in the second block is the first address of the first color data in the third block. In this way, since the image data can be packed and stored in the recording buffer, the recording buffer can be used efficiently.

  Therefore, for example, even when the recording buffer area cannot be secured by storing the recording buffer area uniformly even in the area where there is no image data, as shown in the present embodiment. By controlling the storage of data based on the presence / absence of color data stored in the register, the presence or absence of image data can be stored.

<Description of recording operation>
FIG. 11 is a flowchart for explaining the flow of processing of image data processing and recording operation. In step S1201, the data analysis flag is checked. If the data analysis flag is set (S1201-Yes), the process proceeds to step S1202, the data analysis process is executed, and the data analysis flag is cleared. If the data analysis flag is cleared (S1201-No), step S1202 is skipped and the process proceeds to step S1203.

  In step S1203, the data development processing flag is checked. If the data expansion process flag is set (S1203-Yes), the process proceeds to step S1204, the data expansion process is executed, and the data expansion process flag is cleared. If the flag is not set (S1203-No), step S1204 is skipped.

  In step S1205, the scan flag is checked. If the scan flag is set (S1205-Yes), the process proceeds to step S1206, and the scan (recording) process is performed (S1206). If the scan process is completed, the process returns to step S1201.

  If it is determined in step S1205 that the scan flag is not set (S1205-No), the process in step S1206 is skipped and the process returns to step S1201.

  FIG. 12 is a flowchart for explaining the flow of reception buffer interrupt (INT1, INT2) processing. In step S1301, an interrupt factor is determined. If the interrupt factor is data reception, the process proceeds to step S1302, and the data analysis processing flag is set. Here, whether or not the set data analysis flag is set is determined in step S1201 in the flowchart of FIG.

  FIG. 13 is a flowchart for explaining a control flow in the data analysis process. This data analysis process is a process executed in step S1202 of FIG. First, in step S1401, received data is captured.

  Next, it is checked in step S1402 whether the received data is recording data. If the data is recording data (S1402-Yes), the process proceeds to step S1404, and write address information to the recording buffer is set (S1404). In step S1405, pack bits are not activated, and the data read into the recording buffer is expanded.

  If it is determined in step S1402 that the received data is not recording data (S1402-No), the process proceeds to step S1403 to perform command processing and data setting processing. In step S1403, information about the buffer width and the buffer height is set in the transfer buffer. This transfer buffer is the buffer structure information memory 11 shown in FIG.

  FIG. 14 is a flowchart for explaining the processing flow of the pack bits end interrupt (INT3). When the pack bits process is completed, the data development flag is set in step S1501 and the process ends. It is determined whether or not the data expansion flag is set in step S1203 (FIG. 11) in the flowchart of FIG.

  FIG. 15 is a flowchart for explaining the flow of data expansion processing. In step S1601, the value set in the recording block register is set in the transfer buffer. The transfer buffer is the buffer structure information memory 11 of FIG. 1, and the recording block register is a register (900, 901) set for each block shown in FIG. 10, for example.

  In step S1602, a scan start determination is performed. It is determined whether or not the development of data of a predetermined block or more is completed (for example, data for one block or one scan is finished). If the data expansion has ended (S1602-Yes), the process proceeds to step S1603, and a scan flag is set for the scan request, and the process ends (S1603).

  The process of the flowchart shown in FIG. 15 corresponds to the process of step S1204 of FIG.

  FIG. 16 is a flowchart for explaining the scan processing. In step S1701, the data stored in the transfer buffer described in step S1601 in FIG. 15 is set in the recording block register (900, 901). In step S1702, the image data set in the recording block register is scanned (recorded).

  FIG. 17 is a flowchart for explaining interrupt (INT4) processing when recording block data. This interruption process is executed if the process is completed in units of blocks during the recording operation. For example, if the data to be recorded is stored in eight blocks, eight interruption processes are executed. In the recording of the block data, the generated interrupt factor is determined (S1801). If the interrupt factor is the end of block data, the process advances to step S1802.

  On the other hand, the interrupt factor is that there is no block data to be recorded, that is, there is no recorded data (for example, the value of the write address pointer (WP) and the value of the read address pointer (RP) are examined and the data is stored in the block) If not, the process proceeds to step S1804, a recording failure process is performed, and the scan is stopped (S1804). In this case, since the recording has been performed up to an intermediate block, unrecorded data is stored, the scan is performed again, and the unrecorded area is recorded.

  In step S1802, it is determined whether the block whose recording has been completed is the last block. If it is the last block (S1802-Yes), the process is terminated. If it is not the last block (S1802-No), the process proceeds to step S1803, and the block data of the next image data is set in the register.

[Second Embodiment]
Hereinafter, a second embodiment according to the present invention will be described. In the following description, description of parts similar to those of the first embodiment will be omitted, and description will be made focusing on characteristic parts of the present embodiment.

  In the first embodiment, each color block has the same length, but in the second embodiment, two types of blocks having different lengths are used.

  FIG. 9B (b) is a diagram illustrating a case where the memory is used more effectively than FIG. 9B (a) in the first embodiment. In FIG. 9B (a), the width information in the scanning direction of each block obtained by dividing the recording area into a plurality of blocks was equal to each other. However, if there is no image data to be recorded in the block, the minimum necessary width information is displayed. Just hold it. Focusing on the third block and the fifth block in FIG. 9A, the third block has image data only on the left side, and the fifth block has image data only on the right side. Therefore, the lengths of the third block and the fifth block can be shortened according to the number of image data.

  In this case, in the present embodiment, the control is performed using two size blocks, a full-length block and a half-size block. Since the half-length block uses the color change code as a delimiter, and the full-size block has a predetermined length, the color change code is not used. That is, when the data in the reception buffer is written (transferred) to the recording buffer, if the color change code does not appear even if it exceeds the half block size, it is recognized as a full size block. Focusing on the third block and the fifth block, the third block has image data only on the left side, and the fourth block has image data only on the right side. Therefore, the lengths of the third block and the fifth block are set to half of the lengths of the other blocks according to the number of image data.

  As a result, the recording buffer can be used efficiently even when the memory capacity is small. For example, even when the recording buffer cannot secure an area for storing all the data for one scan, the data for one scan can be stored.

  In this case, on the host device side, when the image data extends over a plurality of blocks and null data continues, the image data may be generated so that the lengths of the blocks are different.

[Other Embodiments]
Although the embodiment according to the present invention has been described above, the gist of the present invention is not limited to the number of nozzles of the recording head being 64 per nozzle row and the number of colors used for recording being four.

  In this embodiment, the recording area is divided into eight in the main scanning direction, but the number of blocks is not limited to this number. Further, as shown in FIG. 7 and FIG. 10, the register of the recording buffering structure circuit does not store the recording buffer height information and the presence / absence information of the color data in one register. Only the code representing the color change needs to be present.

  In the above embodiment, the data development block 3 is in charge of analyzing the color change code, but the same processing may be performed in the I / F controller block.

  In the above embodiment, the liquid droplets ejected from the recording head have been described as ink, and the liquid stored in the ink tank has been described as ink. However, the storage is limited to ink. It is not a thing. For example, a treatment liquid discharged to the recording medium may be accommodated in the ink tank in order to improve the fixability and water resistance of the recorded image or to improve the image quality.

  The above embodiment has been described by taking a recording apparatus adopting an ink jet recording method as an example. However, the present invention is not limited to an ink jet method, and a plurality of recording elements corresponding to colors used for recording in order to perform color recording. The present invention can be applied to any so-called serial type recording apparatus in which recording is performed by scanning a recording head having a row or a number of recording heads corresponding to the color used for recording in a direction crossing the recording element arrangement method.

  Among ink jet recording methods, a method that includes means (for example, an electrothermal converter, laser light, etc.) that generates thermal energy as energy used to perform ink ejection, and causes a change in the state of ink by the thermal energy. Is preferable because high density and high definition of the recording can be achieved.

  In addition, as a form of the recording apparatus according to the present invention, a copying apparatus combined with a reader or the like, and a transmission / reception function are provided as an image output terminal of an information processing apparatus such as a computer or the like. It may take the form of a facsimile machine.

FIG. 3 is a block diagram showing a recording control unit of the recording apparatus in the embodiment of the recording apparatus according to the present invention. It is a figure which shows the data structure at the time of storing the data transferred from a host computer in a receiving buffer. It is a figure which shows the data structure of the recording buffer which hold | maintains image data. 2 is a block diagram showing the inside of an interface controller 1. FIG. 7 is a block diagram showing details of a reception buffering structure control circuit unit 7. FIG. It is explanatory drawing of the operation timing of a reception buffering structure control circuit. It is a figure explaining a recording buffering structure control circuit. It is a figure explaining how image data is stored in the recording buffer. It is a figure explaining the relationship between the recording area recorded by one scan, and the image data of the area. It is a figure explaining the structure of the image data stored in a recording buffer. It is a figure explaining a recording buffering structure control circuit. It is a flowchart explaining the flow of processing of image data and recording operation. It is a flowchart explaining the flow of a reception buffer interruption process. It is a flowchart explaining the control flow in a data analysis process. It is a flowchart explaining the flow of a process of a pack bits end interruption. It is a flowchart explaining the flow of a data expansion process. It is a flowchart explaining a scanning process. It is a flowchart explaining the interruption process at the time of recording block data. 1 is a diagram illustrating an appearance of a printer that is a preferred embodiment of the present invention. FIG. It is a block diagram which shows the control structure of the printer of FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Interface controller 2 Reception buffer 3 Data expansion block 4 Recording buffer 5 Recording data generation block 6 Recording head 7 Reception buffering structure control circuit 8 Recording buffering structure control circuit 8A Read address control part 8B Write address control part 9 CPU
10 Carriage encoder 11 Buffer structure information memory 900 First register group 901 Second register group RP Read pointer WP Write pointer

Claims (7)

In order to perform color recording with a plurality of colors by scanning a carriage mounted with a recording head on a recording medium, the recording area in the scanning direction of the recording head is divided into a plurality of areas, and the divided area unit images A recording device having a recording buffer for storing data,
A reception buffer that stores image data in units of divided areas that are transmitted from a connected host device and that includes information indicating a delimiter of each color data;
A data processing unit that generates presence / absence information of each color data based on the information indicating the separation of each color data;
A write control unit for controlling to store the write address information of the image data for each area together with the color data in the recording buffer based on the image data stored in the reception buffer and the presence / absence information of each color data;
A read controller for controlling read address information for reading image data stored in the recording buffer for each color data;
According to the image data read based on the read address information, a recording data generating means for generating the divided area unit recording data;
A recording apparatus comprising:   The recording apparatus according to claim 1, wherein the read control unit includes a register that holds information on the presence / absence of each color data, and holds the presence / absence information on each color data generated by the data processing unit.   The recording apparatus according to claim 1, wherein the write control unit stores data of each color with the same size in the recording buffer.   2. The writing control unit according to claim 1, wherein when the data of a certain color is less than a predetermined size, information indicating a separation of the color data is added to the color data and stored in the recording buffer. 2. The recording apparatus according to 2.   5. The image recording apparatus according to claim 1, wherein the image data can be stored in the recording buffer by being circulated between areas set by start address information and end address information. 6. The recording device described.   6. The recording apparatus according to claim 1, wherein the number of data that can be stored in the recording buffer is the number of data in a recording area that is smaller than a recording area for one scan. In order to perform color recording with a plurality of colors by scanning a carriage mounted with a recording head on a recording medium, the recording area in the scanning direction of the recording head is divided into a plurality of areas, and the divided area unit images A control method of a recording apparatus having a recording buffer for storing data,
A receiving step of storing the image data of the divided region units including information indicating a delimiter of each color data transmitted from the connected host device in a reception buffer;
A data processing step of generating presence / absence information of each color data based on the information indicating the separation of each color data;
A write control step for controlling to store the write address information of the image data for each area together with the color data in the recording buffer based on the image data stored in the reception buffer and the presence / absence information of each color data;
A read control process for controlling read address information for reading image data stored in the recording buffer for each color data;
According to the image data read based on the read address information, a recording data generation step for generating recording data for the divided area units;
A control method for a recording apparatus comprising:

Images