JP2005153186A - Printing apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a printing apparatus which has a memory/IO control part with the function of receiving packets of the same system in a plurality of simultaneously coming received data by one channel together, and at the same time measuring and setting a packet size. <P>SOLUTION: The printing apparatus is equipped with a CPU 11, the memory/IO control part 12 and a memory 13, and receives by controlling input systems of 3 chs of a USB connecting part 19, a LAN connecting part 20 and a parallel connecting part 14. The memory/IO control part 12 consists of an IO control part 27 and a memory control part 28. The IO control part 27 receives data by an 8-bit bus, gathers the data into 64 bits and writes into the memory 13 by DMA by controlling of the memory control part 28. When the packet size is not set yet, a negate time interval of a data reception request signal DREQ1 is measured by a timer counter. It is judged as the reception end of one packet when a timer setting value 11 of not smaller than an intrinsic time and smaller than a time between packet receptions is measured. A value of a packet size counter at the time is set as the packet size. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to control of DMA reception in data reception of a printing apparatus.

In a conventional printing apparatus, when image data is simultaneously input from a LAN, Centronics, USB or the like, the data reception is performed by a plurality of DMAs. DMA is an abbreviation for Direct Memory Access, and DMA performs data transfer control by a DMA controller instead of a CPU, and performs data transfer at high speed.
When image data is input simultaneously from a plurality of input systems, each DMA allocates a part of the image data, and performs control to access in order and receive evenly. That is, a plurality of DMAs perform control to handle a large number of image data. This is a method in which one image data packet is processed by a plurality of DMAs for each data amount depending on the transfer status such as the free capacity of the memory. For example, these are performed by bulk transfer or the like.

  Patent Document 1 is a DMA control device that transfers the USB packet data according to the transfer amount of the USB packet data when the free space of the bulk-in endpoint is notified in the DMA transfer of the USB packet data, and writes to the USB bulk-in endpoint. In this invention, the packet size is transferred according to the transfer amount.

Further, in Patent Document 2, in USB interface data transfer, the DMA reception size is increased when a DMA end interrupt occurs first, and the reception size is decreased when a data request occurs first. Increase efficiency. In addition, the number of packets and the packet size are set for efficient transfer to a plurality of devices.
Japanese Patent Laid-Open No. 2003-256152 Japanese Patent Laid-Open No. 2001-211227

However, since a plurality of DMAs receive data evenly in order when a plurality of image data arrives at the same time, it is not always efficient if data is sent with a certain packet size such as USB or LAN. Was not good. The maximum USB packet size is 64 bytes in the USB 1.1 specification and 512 bytes in the USB 2.0 specification. Therefore, there is a problem in that when data is received by a plurality of DMAs, it cannot be received efficiently and printing is not accelerated.
Further, both Patent Documents 1 and 2 are methods in which the data amount and the packet size of the data transfer amount are adjusted and transferred in accordance with the free capacity of the memory or the free time in the frame. That is, the packet size is changed flexibly.

  The present invention relates to a printing apparatus having a memory / IO control unit that measures and sets a packet size while efficiently and continuously receiving packets of the same system among a plurality of received data that come simultaneously through one channel. I will provide a.

  According to the present invention, there is provided a plurality of external input connection means for image data, and a plurality of channels corresponding to the plurality of external inputs for receiving the image data while counting the input data by a packet size counter and an input counter, respectively. And a transmission unit for each of a plurality of channels that DMA-transfers the image data of the predetermined value when the input counter reaches a predetermined value, and the packet size counter reaches a set value of the packet size. For example, the reception of one packet of the image data and the DMA transfer are completed, and the next or other channel receiving unit receives another image data or stops another channel and continues receiving the same channel. An output control means; and a plurality of channels corresponding to the external inputs, the transmission of the input / output control means A memory control means for performing the DMA transfer of the image data in the same channel as the color to the storage means is provided by a printing apparatus having said storage means for storing image data to receive the DMA transfer.

  The input / output control means and the memory control means constitute a memory / IO control unit, which receives image data and DMA-transfers it to the storage means. Data reception and DMA transfer in the memory / IO control unit are performed by signals of the same channel (ch). For example, data reception and transfer are controlled in units of one packet while repeating reception by 1 byte and 64-bit DMA transfer.

Assume that the input data is counted by an input / output control unit that counts data reception request signal inputs from the external input connection unit. Since the data reception request signal input is sent in bytes, it is counted.
The set value of the packet size to be compared by the packet size counter is also provided by the printing apparatus having the preset input / output control means.

  The set value of the packet size includes a timer counter corresponding to the channel for measuring the time of inactive state of the data reception request signal input, and the timer counter is a specific time after receiving one packet or more and less than the time between packet reception. Also provided is the above-described printing apparatus having input / output control means for setting the value of the packet size counter when the set value is measured as the set value of the packet size.

  It is assumed that a setting value that is greater than a specific time after packet reception compared by the timer counter and less than the time between packet receptions has input / output control means set in advance in the timer counter. A unique time during which data cannot be input after receiving a packet is detected by a timer counter to determine the completion of reception of one packet.

According to the present invention, even if data comes to a plurality of connection parts, data for one packet size can be collected by one access signal system and continuously received by one channel of one DMA. Can receive data well.
Also, the end of reception of one packet is determined from comparison with the set value by the timer counter, and the value of the packet size counter at this time is set as the size of one packet. Accordingly, since the packet size can be automatically measured and set, it is possible to efficiently receive data in units of packets even if the packet size is not set in advance.

Embodiments of the present invention will be described below with reference to the drawings.
(Embodiment 1)
FIG. 1 shows a configuration diagram of a printing apparatus according to the present embodiment. The printing apparatus includes an IF controller 10 and a printer engine 22. The IF controller 10 is connected to the printer engine 22. The printer engine 22 is connected to the operation panel 23. The IF controller 10 includes the following. The CPU 11 is connected to the memory / IO control unit 12 and performs control in the IF controller 10 and interface with the outside. The memory / IO control unit 12 is connected to each memory of the memory 13, the flash ROM 15, the mask ROM 16, the EEPROM 17, and the EM board (expansion memory board) unit 18 to perform control.

  The memory / IO control unit 12 is also connected to I / Os of the parallel connection unit 14, the USB connection unit 19, and the LAN connection unit 20 to input / output image data. The parallel connection unit 14 is connected to the PC 24 and performs input / output in parallel using Centronics. The USB connection unit 19 is connected to the PC 25 and performs input / output via USB. The LAN connection unit 20 is connected to the PC 26 and performs input / output. The parallel connection unit 14, the USB connection unit 19, and the LAN connection unit 20 each constitute an external input connection unit.

Further, the memory / IO control unit 12 is connected to the video control unit 21 and controls transmission of image data from the memory 13. The video control unit 21 performs control to receive image data from the memory / IO control unit 12 and transmit it to the printer engine 22.
Accordingly, the IF controller 10 receives image data from the external PCs 24, 25, and 26 via the USB connection unit 19 for USB, the LAN connection unit 20 for LAN, and the parallel connection unit 14 for Centronics, for example. The CPU 11 of the IF controller 10 develops the input image data as print data on the memory 13 by the memory / IO control unit 12. When the CPU 11 generates one page of image data, the CPU 11 transmits the image data to the video control unit 21 through the memory / IO control unit 12 and outputs it to the printer engine 22 for printing.

  Next, FIG. 2 shows a detailed configuration diagram. The detailed configuration diagram shows the configuration of the CPU 11, the memory / IO control unit 12, the memory 13, the USB connection unit 19, the LAN connection unit 20, and the parallel connection unit 14 in detail. The memory / IO control unit 12 is divided into an IO control unit 27 and a memory control unit 28.

  One 64-bit DMA data bus is connected to the memory control unit 28 from the IO control unit 27. The 64-bit data bus is shared by three channels (channels) of DMA access signals. It is assumed that the IO control unit 27 has a buffer for storing byte data (not shown) having three channels. The three channels of DMA access signals correspond to the respective buffers. In addition, it has a packet size counter for three channels (not shown), a register for setting a packet size setting value 1, a setting value 2, and a setting value 3. There is also a 3ch byte data counter that counts 8-bit input of data. The byte data counter constitutes an input counter.

  The I / O control unit 27 constitutes a reception unit with signals of the USB connection unit 19, the LAN connection unit 20, and the parallel connection unit 14, corresponding portions of the data bus, a packet size counter, a byte data counter, and a buffer. A transmission unit is constituted by a corresponding part of the data bus corresponding to the byte data counter and the memory control unit 28.

The memory control unit 28 functions as a DMA controller having three channel access signals. Data is transferred between the buffer of the IO controller 27 and the memory 13 at high speed under the control of the DMA controller.
The CPU 11 is connected to the memory control unit 28 in the memory / IO control unit 12 by a 64-bit bus. The memory 13 is connected to the memory control unit 28 in the memory / IO control unit 12 by a 64-bit bus.

An 8-bit data bus is provided from each of the USB connection unit 19, the LAN connection unit 20, and the parallel connection unit 14, and is joined to the IO control unit 27 in the memory / IO control unit 12. The 8-bit data bus is shared.
The USB connection unit 19, the LAN connection unit 20, and the parallel connection unit 14 each output a data reception request signal, and the IO control unit 27 returns an acknowledge signal if it is acceptable. The IO control unit 27 also has a function of not accepting the DREQ signal. The USB connection unit 19 has a data reception request signal “DREQ1” and an acknowledge signal “DACK1”. The LAN connection unit 20 has a data reception request signal “DREQ2” and an acknowledge signal “DACK2”. The parallel connection unit 14 has a data request signal “DREQ3” and an acknowledge signal “DACK3”.

  Next, signals between the IO control unit 27 and the memory control unit 28 in the memory / IO control unit 12 are shown. The three channels of DMA access signals have a one-to-one correspondence with external access to the IO control unit 27. There are three sets of DMA data reception request signals and their acknowledge signals. These are independent of the data reception request signal. The DMA data reception request signal and its acknowledge signal are three sets of “DMAREQ1” and “DMAACK1”, “DMAREQ2”, “DMAACK2”, “DMAREQ3”, and “DMAACK3”.

  The three ch signal systems are divided into 1 system, 2 system, and 3 system. System 1 handles input from the USB connection unit 19 and includes a DREQ1 signal, a DACK1 signal, a DMAREQ1 signal, and a DMAACK1 signal. System 2 handles input from the LAN connection unit 20 and includes a DREQ2 signal, a DACK2 signal, a DMAREQ2 signal, and a DMAACK2 signal. The third system handles input from the parallel connection unit 14 and includes a DREQ3 signal, a DACK3 signal, a DMAREQ3 signal, and a DMAACK3 signal.

  Therefore, reception of one packet is handled with signals of the same system number. What is received by the DREQ1 signal is transferred by the DMAREQ1 signal. What is received with the DREQ1 signal is not transferred with the DMAREQ2 signal. When data is input to all three channels, processing is performed by changing the channel for each packet, or packets of the same channel are processed continuously.

  The operation of the detailed configuration diagram of FIG. 2 will be described using the USB connection unit 19 as an example. When a PC 25 having a USB function is connected and receives data transmission, the USB connection unit 19 sends a data reception request signal DREQ1 to the IO control unit 27 in the memory / IO control unit 12 so as to receive 8-bit image data. Is asserted L. If the data can be received, the IO control unit 27 asserts and returns an acknowledge signal DACK1 to L. The USB connection unit 19 first transmits image data to the IO control unit 27 eight times as 8-bit data on the data bus. The IO control unit 27 receives 8-bit data eight times.

  The USB connection unit 19 asserts the DREQ1 signal every time 8-bit data transmission and negates it after data transmission. The IO control unit 27 also receives the DREQ1 signal, asserts the DACK1 signal, and receives the DREQ1 negation after receiving the data. Negates the DACK1 signal. Next, when the 64-bit data is ready, the IO control unit 27 requests the memory control unit 28 to assert the DMA data reception request signal DMAREQ1 to L and take the 64-bit data. If the data can be received, the memory control unit 28 asserts the acknowledge signal DMAACK 1 to L and returns it to the IO control unit 27. The IO control unit 27 transmits 64-bit data by DMA using a 64-bit bus. The memory control unit 28 continuously writes the received 64-bit data in the memory 13 by DMA using a 64-bit bus. The IO control unit 27 negates the DMAREQ1 signal, and the memory control unit 28 also negates the DMAACK1 signal. In this way, the image data is stored in the memory 13. This is repeated to receive one packet of image data.

Next, in FIG. 3 to FIG. 5, data is received by the IO control unit 27 in the memory / IO control unit 12 from each connection unit to the outside, and the data from the IO control unit 27 and the memory control unit 28 to the memory 13. 2 shows a flowchart of DMA transfer.
This is the control of the CPU 11 and the memory / IO control unit 12. One packet is handled by one channel DMA access signal and processed in units of one packet. When changing the DMA channel, it is performed in units of one packet. That is, ch is not changed in the middle of the packet. When continuously receiving packet data from one external input connection means, it is performed by not accepting data reception request signals of other channels.

  First, the power is turned on (S10). An initial value 0 is set in the packet size counters COUNT1, COUNT2, and COUNT3. Also, the setting value 1, the setting value 2, and the setting value 3 are set for each channel as the setting value of the packet size to be compared with the packet size counter. Assume that the input packet size is already known. Alternatively, the value is set when the operator inputs a value from the operation panel. Further, in order to align the data to 64 bits, an initial value 0 is set in the byte data counters CUN1, CUN2, and CUN3 that count the reception of 8 bits of data 8 times (S11).

  It is determined whether or not the input of the data reception request signal DREQ1 signal of the USB connection unit 19 is accepted. In order to control the input of the ch in the memory / IO control unit 12, the input of the DREQ signal can be disabled. When the input of the DREQ1 signal is not accepted, that is, when the DREQ1 signal is stopped, the process goes to S14. (S13) When the DREQ1 signal is received, that is, when DREQ1 is not stopped, the DREQ1 signal is asserted as L, and it is determined whether data input is requested. If the DREQ1 signal is not L, the process goes to S14. That is, it goes to the processing of the connection part of the other system. If the DREQ1 signal is L, the process goes to S18 through A (S13).

  If the DREQ1 signal is L, the value of the packet size counter COUNT1 is incremented by 1 and held. Next, the DACK 1 signal is asserted to L and returned to the USB connection unit 19. The value of the byte data counter CUN1 is incremented by 1 and held. (S18) Next, it is determined whether the DREQ1 signal becomes H and negated. If the DREQ1 signal is not H, this determination is repeated (S19). When the DREQ1 signal becomes H and negates, the DACK1 signal is set to H and negated. Then, 8-bit data reception is completed (S20).

Next, it is determined whether the byte data counter CUN1 is 8. It is determined whether data of 64 bits has been accumulated. If the byte data counter CUN1 is 8, go to S22. If the byte data counter CUN1 is not 8, go to S25 (S25).
If the byte data counter CUN1 is not 8, it is determined whether the packet size counter COUNT1 is equal to the set value 1 of the packet size. If equal, this is the case when DMA data transfer, which will be described later, of packet data having a packet size equal to the set value 1 of the packet size is completed, that is, when reception of one packet is completed, and the process goes to S26. If the packet size counter 1 is not equal to the set value 1 of the packet size, the process returns to S12 through D, and the 8-bit data input and DMA transfer are repeated (S25). When the packet size counter COUNT1 is equal to the packet size setting value 1, the packet size counter COUNT1 is initialized to zero. Then, it goes to S14 through E and goes to the processing of the connecting part of the other system (S26).

  If the byte data counter CUN1 is 8 in S21, the DMAREQ1 signal is asserted to L and sent to the memory control unit 28 (S22). Next, it is determined whether the DMAACK1 signal is asserted and returned from the memory control unit 28 at L level. If the DMAACK1 signal is not returned, this determination is repeated. (S23) When DMAACK1 = L, 64-bit data is collectively written into the memory 13 by DMA transfer under the control of the memory control unit 28. Then, the DMAREQ1 signal is negated to H. Also, the byte data counter CUN1 is initialized to zero. Thereafter, the process goes to S25 described above.

The above is the process of receiving one packet from the USB connection unit 19 of the memory / IO control unit 12.
The processing starting from E in S26 and subsequent steps is the same as the processing of the DREQ2 signal system, and the processing starting from F is the same processing as the processing of the DREQ1 signal system. Following the processing of the DREQ2 signal system of S14, S15, S27 to S35, the processing of the DREQ3 signal system is performed through F. After the processing of the DREQ3 signal system in S16, S17, and S36 to S44, the process returns to the DREQ1 signal system processing through D. A description of the processing of other systems is omitted.

When a large number of packets are processed in the same channel, the DREQ signals of other channels can be used without being accepted and used exclusively by the receiving channel. For example, when packet reception is continuously performed using the DREQ1 signal system ch, even if the process proceeds from S26 to E through S14, the DREQ2 signal is not accepted, so the process proceeds to S16, and even the DREQ3 signal is not accepted even in S16, so the DREQ1 signal system ch. The process returns to S12. Therefore, continuous packet reception can be performed. The same control can be performed when data is coming to a plurality of channels.

(Embodiment 2)
Next, Embodiment 2 of the present invention will be described. This example is a packet size measurement / setting method and reception method when the size of a transmitted packet is unknown.

The IO control unit 27 is provided with timer counters 1, 2, and 3 for each system. Timer counters 1, 2, and 3 (not shown) have registers for holding timer setting values 11, 22, and 33 to be compared, respectively.
FIG. 6 shows the relationship between the DREQ1 signal, the 8-bit data bus, and the timer set value 11 when receiving packet data. As shown in the figure, it is used that a certain time or more is left between reception of one packet and reception of one packet.

  Data input blank time, that is, after the packet is received, the DREQ1 signal is negated after receiving one packet and asserted when the next packet is received. Take advantage of that. This unique time repeats the operation in which the DREQ1 signal becomes L when the 8-bit data is repeatedly received and then becomes H, but is at least longer than the time when the DREQ1 signal becomes H in the meantime. , It is longer than the time when it can be confirmed that the signal does not become H during the reception of the 8-bit data of the DREQ1 signal. For example, the period of time in which the DREQ1 signal becomes H during the time during which the 8-bit data is repeatedly received, that is, the time of 10 times or more of the period including the time when the signal is H, or the like.

  In addition to the above, the unique time and the time between packet receptions are not dependent on the packet but are based on hardware or software. This inherent time and the time between packet receptions are known from the beginning. Also, this inherent time is less than the time between packet receptions, and both may be substantially equal.

  Therefore, the reception end of one packet is recognized by recognizing that the negation time of the DREQ1 signal is counted and measured by the timer counter and the negation is over a specific time. Then, the value of the packet size counter COUNT1 at that time is set as the packet size, and is set to the set value 1 of the packet size. The value of the packet size counter COUNT1 is a value as it is received and counted and is the size of one packet.

  A timer setting value 11 that is a setting value of the timer counter sets a time that is equal to or more than a specific time after the packet reception and less than the time between packet receptions. The range of the timer set value 11 is shown in FIG. When the timer counter counts the timer set value 11 and recognizes that the negation time of the DREQ1 signal is negated for a specific time or more, the reception end of one packet is recognized. When recognizing the end of reception of one packet, the value of the packet size counter COUNT1 is overwritten with the set value 1 of the packet size as the packet size and rewritten. As a result, the packet size is measured and set. Other systems are equivalent.

Therefore, even if the packet size is not known in advance, after the packet size is recognized, data reception is efficiently performed in units of packets. This is effective when data is transmitted with the same packet size to the same channel.
Next, flowcharts are shown in FIGS.

  First, the power is turned on (S50). The initial value 0 is set in the packet size counters COUNT1, 2, and 3. The byte data counters CUN1, CUN2, and CUN3 are set to an initial value 0. The packet size temporary setting values are set in the packet size setting values 1, 2, and 3 to be compared with COUNT 1, 2, and 3, respectively. That is, an arbitrary temporary packet size is set. As the packet size temporary setting value to be set, a value considerably larger than the expected packet size is set. The timer setting values 11, 22, and 23 of the timer counters 1, 2, and 3 are set to a time that is longer than the inherent time after the negation of the DREQ signal after writing the packet and less than the time between packet receptions. Also, the timer counters 1, 2, and 3 are set to 0 (S51).

Next, it is determined whether to accept the DREQ1 signal. When the input of the DREQ1 signal is not accepted, that is, when the DREQ1 signal is stopped, the input from the USB connection unit 19 is not processed, and the process goes to S60 (S52).
When accepting the DREQ1 signal, it is determined whether the DREQ1 signal is asserted to L (S53). When the DREQ1 signal is asserted to L, the same processes as S12 and S13 are performed through S through S76 to S84, S52 and S53, and S18 through S26 of FIG. That is, data reception and data transfer to the memory 13 by DMA are performed. However, in S83, in the reception of the first packet, since the value substantially larger than the expected packet size is set as the packet size setting value 1 in the reception of the first packet size, the determination is N. After receiving one packet, the packet size measurement result is output and the packet size setting value 1 is overwritten. Then, the packet size counter COUNT1 is equal to the packet size setting value 1, and the reception of one packet may end. Come.

  When the DREQ1 signal is H in S77, the process goes to S78, and the processing continues. However, it is assumed that the DREQ1 signal from the USB connection unit 19 is asserted to L by S53 during packet reception. Therefore, if the DREQ1 signal is not asserted to L in S53 or is negated, it means that reception of one packet of data has been completed. However, before the start of packet reception. From here, it becomes a routine for determining the packet size.

  First, it is determined whether the value read from the packet size counter COUNT1 has been written, that is, overwritten, to the packet size setting value 1. This is written in S58 described later. When counting by the timer counter 1 from S54 to S59 to be described later is repeated and writing is completed, the process goes to S60. This means that the packet size measurement is over and the packet size setting value 1 is overwritten. Whether it has been written may be determined using a flag. (S54) If it has not been written, it is determined whether the DREQ1 signal has become L in the past. Determine whether there was a data input request. Confirm that the current DREQ1 = H has not been continued since the power was turned on. If the DREQ1 signal has never become L, the process goes to S60 (S55).

When the DREQ1 signal has become L in the past, 1 is added to the timer counter 1. The time when the DREQ1 signal is H, that is, the time during packet reception or the specific time after reception of one packet is measured (S56).
Next, it is determined whether the value of the timer counter 1 is greater than the set timer set value 11. If not, go to S59 (S57). If the value of the timer counter 1 is greater than the timer set value 11, it is determined that the reception of one packet has been completed because a specific time after reception has elapsed. Then, the value of the packet size counter COUNT1 is read and overwritten on the set value 1 of the packet size. The packet size is now determined and recorded. Then, 0 is set in the packet size counter COUNT1. The packet size counter COUNT1 has been used for measuring the packet size so far, but thereafter it is used for comparing the packet size.

  Next, it is determined whether the DREQ1 signal is L (S59). If the DREQ1 signal is L, it means that there has been a request for receiving a new packet data, and the process goes to S76 through A to start receiving new packet data. However, this route is not used in principle. If the DREQ1 signal is not L, the process goes to S54 to repeat the measurement by the timer counter. Since the state where the DREQ1 signal is H continues, measurement of the timer counter is continued (S59).

The processing after the setting value of the packet size is set as described above is the same as that of the first embodiment.
When there is no data input in the channel of the DREQ1 signal system, the same processing is performed with the DREQ2 signal system channel of S60 to S67 and S85 to S93, that is, the input from the LAN connection unit 20. When there is no data input in the DREQ2 signal system ch, the same processing is performed for the DREQ3 signal system ch in S68 to S75 and S94 to S102, that is, the input from the parallel connection unit 14.

When packet data is continuously received by one channel, for example, a channel of the DREQ1 signal system, processing is performed without receiving the DREQ2 signal and the DREQ3 signal, which are data reception requests of other systems. These are the same as in the first embodiment.
If there is a strobe signal in units of packets instead of the timer counter, the end of reception of one packet is determined by negating the strobe signal, and the value of the packet size counter at that time may be used as the packet size. .

  Further, the timer counter may be shared, and the registers of the timer set values 11, 22, and 33 may be provided in the IO control unit 27.

1 is a system configuration diagram of a printing apparatus according to the present invention. It is a figure which shows the detailed structure of a system centering on memory I / O. It is a flowchart in case the packet size has been set in this example. It is a flowchart in case the packet size has been set in this example. It is a flowchart in case the packet size has been set in this example. It is a figure explaining the timer setting value of this example. 5 is a flowchart showing packet size automatic measurement and setting processing. 5 is a flowchart showing packet size automatic measurement and setting processing. 5 is a flowchart showing packet size automatic measurement and setting processing. 5 is a flowchart showing packet size automatic measurement and setting processing.

Explanation of symbols

10 ... IF controller 11 ... CPU
12: Memory / IO control unit 12
13 ... Memory 14 ... Parallel connection 15 ... FLASHROM
16 ... MASKROM
17 ... EEPROM
18 ... EM board 19 ... USB connection 20 ... LAN connection 21 ... Video control unit 22 ... Printer engine 23 ... Operation panels 24, 25, 26 ... PC
27: IO control unit 28: Memory control unit

Claims (5)

A plurality of external input connection means for image data;
A receiving unit having a plurality of channels corresponding to the external inputs for receiving the image data while counting input data by a packet size counter and an input counter, respectively, and the predetermined value when the input counter reaches a predetermined value; A transmission unit for each of a plurality of channels for DMA transfer of the image data, and when the packet size counter reaches a set value of the packet size, reception of one packet of the image data and the DMA transfer are completed, or other Input / output control means for receiving other image data at the receiving section of the channel, or stopping other channels and continuing reception of the same channel;
A memory control unit comprising a plurality of channels corresponding to the external inputs, and performing the DMA transfer of the image data to the storage unit through the same channel as the transmission unit of the input / output control unit;
The storage means for receiving the DMA transfer and storing image data;
A printing apparatus comprising:   The printing apparatus according to claim 1, further comprising: the input / output control unit configured to count the input data by counting data reception request signals input from the external input connection unit.   3. The printing apparatus according to claim 1, wherein the set value of the packet size has input / output control means set in advance.   The set value of the packet size includes a timer counter corresponding to the channel that measures the time of the inactive state of the data reception request signal input, and the timer counter has a period between packet receptions longer than a specific time after receiving one packet. 3. The printing apparatus according to claim 1, further comprising: an input / output control unit configured to set a value of a packet size counter when the set value less than the time is measured as the set value of the packet size. 5. The printing apparatus according to claim 4, further comprising: an input / output control unit having a timer counter that is set in advance for a set value that is greater than a specific time after the packet is received and less than a time between packet receptions.

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