JP2005151284A - Dynamic frequency divider - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To stably obtain frequency dividing ratios 4, 8, 12, ..., 4N in a configuration of a small circuit scale and low power consumption. <P>SOLUTION: Two stages of the same elements each composed of an inverter circuit 21, a capacitor 41 and a switch circuit 31 are cascade-connected. An element composed of an inverter circuit 23 and a capacitor 43 is connected to the final stage thereof. The output of the inverter circuit 23 is connected to an output terminal 2 and fed back to the input of the inverter circuit 21. The control terminals of switches 31, 32 are connected to an input terminal 1. Capacities of capacitors 41 and 43 are set to a half that of a capacitor 42. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a frequency divider used in a frequency synthesizer in a microwave frequency band, and more particularly to a dynamic frequency divider that directly divides a high frequency signal from a voltage controlled oscillator.

  An example of a conventional dynamic frequency divider is described in Patent Document 1, for example. FIG. 11 shows a configuration example of a conventional dynamic frequency divider. Three elements are connected in cascade by an element 51 composed of an inverter circuit 21 and a switch circuit 31 connected to this output, and the same elements 52 and 53, and the output of the last-stage switch circuit 33 is the output terminal 2 Are connected to the input of the inverter circuit 21 of the first stage, and the control terminals of the switch circuits of the stages are connected to the input terminal 1 in common. Each switch 31, 32, 33 is in a conductive state when the input of its control terminal is at a high level, and is in an open state when it is at a low level. In addition, each inverter circuit 21, 22, 23 has a delay in operation, and its output is inverted to a level opposite to the input after an operation delay time td after the input is inverted.

  The conventional dynamic frequency divider realizes the frequency dividing operation as follows. Each time the input terminal 1 becomes high level, the output voltage of each inverter circuit is transmitted as the input voltage of the next stage inverter circuit. Therefore, when the input terminal 1 becomes high level three times, the output terminal 2 is inverted. Further, when the input terminal 1 becomes high level three times, the output terminal 2 returns to the original state. That is, one output pulse is generated by six pulses at the input terminal 1. That is, the frequency division ratio is 6.

  FIG. 12 shows a time chart of the operation of the conventional dynamic frequency divider. V1 is the voltage of the input terminal 1, V21, V22, and V23 are the input voltages of the inverter circuits 21, 22, and 23, and V31, V32, and V33 are the input voltages of the switch circuits 31, 32, and 33, respectively. When attention is paid to the inverter circuit 21, when V1 becomes high level at time t = 3, the switches 31, 32, and 33 are turned on all at once, and the input voltage V21 becomes high level equal to V33 of the previous stage from the previous low level. To change. Thereafter, when the operation delay time td of the inverter circuit 21 elapses, the voltage V31 is inverted to a level opposite to the input voltage V21, that is, a low level (t = 5). At this time, since V1 has already returned to the low level and each switch circuit 33 is in the open state, the input voltage V21 is maintained at the high level, and then the voltage V33 becomes the low level, and the switch circuit 33 is This is maintained until time t = 12, when the conductive state is reached.

  With respect to the inverter circuit 22 at the next stage and the inverter circuit 23 at the next stage, the same operation is performed by sequentially shifting the time. When six pulses are input to the input terminal 1, all the inverter circuits 21, 22, 23 return to the initial state. That is, the pulse of the output terminal 2 is sent out once by the pulse of the input terminal 1 six times, and operates as a frequency divider having a frequency division ratio of 6.

In order to operate as a frequency divider having a frequency division ratio of 6, the conventional dynamic frequency divider has a condition for realizing the frequency dividing operation between the operation delay time td of the inverter circuit and the input signal period. To do. That is, in an ideal state as shown in the time chart shown above, the operation delay time td is a time width during which the switch circuit is in a conductive state (corresponding to the pulse width of the input signal, and when the duty ratio is 50%, Greater than half the period) and less than the period of the input signal. In a practical circuit, not only does the switch circuit have an operation delay, but the operation waveform is a waveform having an inclination with respect to the time axis, so that the condition for realizing the frequency division operation becomes more severe. The stricter condition means that the range that operates as a frequency divider is practically reduced.
Japanese Patent No. 2747697

  In the conventional dynamic frequency divider, when the elements of the inverter circuit and the switch circuit are connected in an odd number of stages, that is, when the division ratio is set to 2, 6, 10,..., 2 (2N + 1), The frequency dividing operation is realized when the conditions for realizing the frequency dividing operation are satisfied. On the contrary, in the configuration in which this element is connected in an even number of stages, the loop of each element becomes positive feedback, and the logic of the output terminal 2 is stable at a high level or a low level. The operation cannot be realized. Therefore, the frequency division ratio cannot be set to 4, 8, 12,.

Although it is possible in principle to obtain a specific frequency division ratio 2 ⁿ by cascading n stages of conventional dynamic frequency dividers designed to have a frequency division ratio of 2, the dynamics of each stage The type divider must be designed so as to satisfy the conditions for realizing the above dividing operation. That is, the operation delay time td of the dynamic divider connected to the subsequent stage must be designed to be extremely large with respect to the operation delay time td of the first-stage dynamic divider. Increase in drought and power consumption.

  The present invention solves these problems, and the division ratios 4, 8, 12,..., 4N, which could not be realized with the conventional dynamic frequency divider, have a small circuit scale and low power consumption. And it aims at realizing it stably.

The dynamic frequency divider according to the first aspect of the present invention includes an inverter unit and a switch unit that passes or blocks the output of the inverter unit and connects to the inverter unit of the next stage as one element, and the number of the elements is 2N. (N is a natural number) connected in cascade, the 2N + 1-th inverter means is connected to the output of the switch means of the last stage element of the 2N elements, and the output of the 2N + 1-th inverter means is the 2N A dynamic frequency divider that is connected in feedback to the input of the inverter means of the first stage element among the elements, and the control terminal of each switch means of the 2N elements is connected to the input terminal in common. The total delay time of the delay time of the 2N + 1-th inverter means and the delay time of the inverter means of the first-stage element among the 2N elements is the second stage of the 2N-elements. Characterized by being configured to match the delay time of each inverter means 2N-th stage.
According to a second aspect of the present invention, there is provided a dynamic frequency divider that passes or blocks an inverter circuit, a capacitor having one terminal connected to the output of the inverter circuit and the other terminal grounded, and the output of the inverter circuit. The switch circuit connected to the inverter circuit at the next stage is connected as one element, and the elements are connected in cascade with 2N (N is a natural number), and the output of the switch circuit of the last stage element among the 2N elements Are connected to the output of the 2N + 1-th inverter circuit, and the output of the 2N + 1-th inverter circuit is connected to the output of the 2N + 1-th inverter circuit. A feedback connection is made to the input of the inverter circuit of the first stage element of the 2N elements, and the control terminal of each switch circuit of the 2N elements is connected to the input terminal in common. A Namic-type frequency divider, wherein the capacitance value of the first-stage element and the 2N + 1-th capacitance value of the 2N elements are respectively calculated from the second to the 2N-stage of the 2N elements. It is characterized by being set to half the capacity of each element of the eye.
A dynamic frequency divider according to a third aspect of the invention includes an inverter circuit, a capacitor having one terminal connected to the output of the inverter circuit and the other terminal grounded, and passing or blocking the output of the inverter circuit. The switch circuit connected to the inverter circuit at the next stage is connected as one element, and the elements are connected in cascade with 2N (N is a natural number), and the output of the switch circuit of the last stage element among the 2N elements Are connected to the output of the 2N + 1-th inverter circuit, and the output of the 2N + 1-th inverter circuit is connected to the output of the 2N + 1-th inverter circuit. A feedback connection is made to the input of the inverter circuit of the first stage element of the 2N elements, and the control terminal of each switch circuit of the 2N elements is connected to the input terminal in common. A dynamic divider, wherein the driving power of the inverter circuit of the first stage element among the 2N elements and the driving power of the 2N + 1-th inverter circuit are respectively divided into two stages of the 2N elements. The driving power of the inverter circuit of each element in the 2N stage from the first is set to be twice.
According to a fourth aspect of the present invention, there is provided a dynamic frequency divider that passes or cuts off an inverter circuit, a capacitor having one terminal connected to the output of the inverter circuit and the other terminal grounded, and the output of the inverter circuit. The switch circuit connected to the inverter circuit at the next stage is connected as one element, and the elements are connected in cascade with 2N (N is a natural number), and the output of the switch circuit of the last stage element among the 2N elements 2N + 1-th inverter circuit is connected to the output, and the output of the 2N + 1-th inverter circuit is feedback-connected to the input of the inverter circuit of the first stage element of the 2N-th element. A dynamic frequency divider in which a control terminal of a switch circuit is commonly connected to an input terminal, wherein the value of the first stage capacitance of the 2N elements is the second stage of the 2N elements. A value smaller than the value of the 2N-stage capacitance is selected, and the total delay time of the delay time of the 2N + 1-th inverter circuit and the delay time due to the inverter circuit and capacitance of the first-stage element among the 2N elements Is set so as to coincide with the delay time due to the inverter circuit and capacity of each of the 2nd to 2Nth elements of the 2N elements.

  According to the first to fourth aspects of the present invention, the effect of realizing the frequency division ratio of 4, 8, 12,... (Generally 4N) can be obtained. In addition, these inventions can be designed with high accuracy, have a small circuit scale, and have low power consumption as compared with the case of cascading conventional dynamic frequency dividers having a frequency division ratio of 2. can get. For example, when designing an 8-divider, in the conventional example, it is impossible to realize an 8-divider by itself (realizable division ratio = 2, 6, 10,...). It is necessary to design the delay time of the second stage and the third stage to be twice or four times of the first stage, respectively, so that the circuit scale, The power consumption is about 7 times that of the first-stage divide-by-2 divider. On the other hand, according to the present invention, the divide-by-8 circuit can be realized with the configuration shown in FIG. From the above, the circuit scale and power consumption are 7: 5 in the conventional example: the present invention, and in the present invention, the circuit scale and power consumption are about 30% as compared with the case where the conventional two-divider is configured in three stages. Reduction effect is estimated.

  Further, according to the invention of claim 2, “the capacity value of the first stage element of 2N elements and the value of the 2N + 1th capacity are respectively set to 2N from the second stage of 2N elements. The circuit design (parameter determination) is simple and easy because it is sufficient to set the value to half the capacity of each element in the stage. In terms of layout design, in order to design the capacity in half, it is simple and easy to halve the area. Furthermore, since it can be realized simply by adding passive elements to the conventional frequency divider, an increase in power consumption can be suppressed.

  Further, according to the invention of claim 3, “the driving power of the inverter circuit of the first stage of the 2N elements and the driving power of the 2N + 1-th inverter circuit are respectively set to 2 of the 2N elements. The circuit design (determination of parameters) is simple and easy because it is only necessary to set the driving force of the inverter circuit of each element from the 2nd stage to the 2Nth stage. In terms of layout design, in order to design the driving force twice, it is simple and easy if the area of the transistor is doubled. Further, since the driving force is increased as compared with the first aspect, low phase noise (= low jitter) is obtained, which is effective in improving the manufacturing yield and preventing malfunction.

  Further, according to the invention of claim 4, “the capacity value of the first stage of 2N elements is selected to be a value smaller than the capacity value of the 2nd to 2N stages of 2N elements. The total delay time of the delay time of the (2N + 1) th inverter circuit and the delay time due to the inverter circuit and capacitance of the first stage element of the 2N elements is from the second stage to the 2N stage of the 2N elements If each operation delay is not determined by the driving force and each capacitance value of each inverter (by setting the delay time depending on the inverter circuit and capacity of each element of the eye) (the operation delay when no capacity is added) Even when the operation delay when the capacitor is added is not negligible), there is an effect that the frequency operating range can be expanded most widely by giving the margin to the condition for realizing the frequency dividing operation.

  In the present invention, in addition to the conventional configuration in which an even number (2N) of dynamic frequency divider elements are cascade-connected, a 2N + 1-th inverter circuit is connected to realize a frequency division operation with a frequency division ratio of 4N. . However, with this alone, the operation delay time of the element to which the new inverter circuit is added becomes about twice the operation delay time of the other elements, and the condition of the frequency dividing operation already described for each operation delay time. There is no input frequency range that simultaneously satisfies the conditions of each frequency division operation, or even if it exists, the frequency range is significantly narrowed.

  Therefore, in order to solve this problem, the present invention uses the inverter circuit as a single unit or a configuration comprising an inverter circuit and a capacitor having one end connected to the output of the inverter circuit and the other end grounded. The total delay time of the delay time of the inverter means and the delay time of the inverter means of the first stage element of the 2N elements is the delay of each inverter means from the second stage to the 2N stage of the 2N elements. It is based on the fact that it is set to coincide with the time (corresponding to claim 1). The delay time of each inverter means can be set by adjusting the capacity connected to the output of the inverter circuit constituting the inverter means or adjusting the driving force of the inverter circuit.

  As described above, the present invention can be designed so that there is no difference in the operation delay time between the element to which the new inverter circuit is added and other elements by connecting a predetermined capacitor to the output of each inverter circuit. Therefore, even when an even number of elements are connected, a frequency dividing operation is possible if the condition of one frequency dividing operation is satisfied as in the case of a conventional dynamic frequency divider that connects an odd number of elements. The effect that the frequency division ratio 4N can be written without reducing the frequency range is obtained. Since the present invention can realize the frequency dividing operation by the design in which the operation delay time is made equal between the element to which the inverter circuit is newly added and the other elements, the conventional dynamic frequency divider having the frequency dividing ratio of 2 is connected in cascade. Compared with the case where it does, effects, such as high precision, a small circuit scale, and low power consumption, are acquired.

  FIG. 1 is a circuit diagram showing a dynamic frequency divider (corresponding to claim 2) of the first embodiment. An inverter circuit 21, a capacitor 41 having one terminal connected to the output of the inverter circuit 21 and the other terminal grounded, and a switch circuit that passes or blocks the output of the inverter circuit 21 and connects to the inverter circuit of the next stage. 31 constitutes one element, and the same element is connected in two stages in cascade, and the third inverter circuit 23 is connected to the output of the switch circuit 32 in the final stage, and this inverter is connected to one terminal. A capacitor 43 having the output of the circuit 23 connected and the other terminal grounded is connected, and the output of the inverter circuit 23 is feedback connected to the input of the inverter circuit 21 in the first stage. The control terminals of the two switch circuits 31 and 32 are connected to the input terminal 1 in common.

  Each of the switches 31 and 32 is in a conductive state when the input of its control terminal is at a high level, and is in an open state when it is at a low level. The combination of the inverter circuit 21 and the capacitor 41, the combination of the inverter circuit 22 and the capacitor 42, and the combination of the inverter circuit 23 and the capacitor 43 have a delay in operation, and the operation delay times Td1 and Td2 after the input is inverted, respectively. , After Td3, the output is inverted to the opposite level to the input.

  The dynamic frequency divider of the first embodiment realizes the frequency dividing operation as follows. Each time the input terminal 1 becomes high level, the output voltage of the inverter circuits 21 and 22 is transmitted as the input voltage of the inverter circuit at the next stage. Therefore, when the input terminal 1 becomes high level twice, the output terminal 2 is inverted. Further, when the input terminal 1 becomes high level twice, the output terminal 2 is inverted. That is, one output pulse is generated by four pulses at the input terminal 1. That is, the division ratio is 4.

  The difference from the configuration of the conventional dynamic frequency divider (FIG. 11) is that the elements are two stages (even number stages), the first stage element 51 is replaced with an element having two inverter circuits 21 and 23, and each inverter circuit This is because one end of capacitors 41, 42, and 43 whose other ends are grounded is connected to the outputs of 21, 22, and 23. The parameters of each inverter circuit and each capacity are determined as follows.

  The drive powers of the inverter circuits 21, 22, and 23 (the value of mutual conductance gm in the case of FETs and the value of current amplification factor in the case of bipolar transistors) are all designed to be equal. When gm of the FETs used in the inverter circuits 21, 22, and 23 are gm_21, gm_22, and gm_23, respectively, gm_21 = gm_22 = gm_23.

  On the other hand, when the values of the capacitors 41, 42, and 43 are C1, C2, and C3, these values are set so that the condition for realizing the frequency dividing operation has the greatest margin (the frequency operating frequency range becomes the widest). To) decide. Specifically, the design is as follows. The input signals of the inverter circuits 21, 22, 23 are V21, V22, V23, and the output signals are V31, V32, V21. A signal input to the input terminal 1 is V1.

  The conditions for realizing the frequency dividing operation are determined by the time difference between the time when the logic of V31 changes and the pulse time of V1 (first operation delay time), the time when the logic of V32 changes and the pulse time of V1. It is a time difference (second operation delay time). If the time difference (operation delay time) between the two satisfies the condition of the frequency dividing operation, the frequency dividing operation can be realized. However, since there are only two conditions, the frequency operating frequency range is narrowed.

  Therefore, by making the time difference between the two equal and reducing the condition for realizing the frequency dividing operation to one, the condition for realizing the frequency dividing operation is given the most allowance, and the design that widens the frequency operating frequency range is performed. . For this purpose, considering that the pulses of V1 are input at equal intervals, the timing at which the logic of V31 changes and the timing at which the logic of V32 changes alternately appear at equal intervals. For this purpose, the values of the capacitance values C1, C2, and C3 may be determined so as to satisfy Td2 = Td1 + Td3. Assuming that the operation delays Td1, Td2, and Td3 are determined by the driving force of the inverters 21, 22, and 23 and the capacitance values C1, C2, and C3, the values of C1, C2, and C3 are set to C1 = C3 = 0. If the design is such that 5 × C2 holds, Td2 = Td1 + Td3 is established, and the frequency division operating frequency range can be expanded most.

  FIG. 2 is a time chart of the operation of the dynamic frequency divider of the first embodiment. Each of the signals V1, V21, V22, V23, V31, and V32 is originally an analog signal having a continuous voltage value, but here, binarized logic is described for simplicity. Focusing on the inverter circuit 22, when V1 becomes a high level at time t = 6, the switches 31 and 32 are simultaneously turned on, and V22 changes from the previous high level to a low level equal to V31 in the previous stage. Thereafter, when the operation delay time Td2 due to the inverter circuit 22 and the capacitor 42 elapses, the voltage V32 is inverted to a level opposite to V22, that is, a high level (t = 8). At this time, since V1 has already returned to the low level and the switch circuit 31 is in the open state, V22 is maintained at the low level, and then V31 becomes the high level and the switch circuit 31 becomes conductive. This is maintained until time t = 12.

  The combination of the inverter circuit 23 and the capacitor 43 in the next stage (operation delay time Td3) and the combination of the inverter circuit 21 and the capacitor 41 (operation delay time Td1) can be considered as the first element 51 together. The combination of the inverter circuit 22 and the capacitor 42 (operation delay time Td2), that is, the operation equivalent to that of the second element 52 is performed by sequentially shifting the time. This is because the capacitance values are designed so that C1 = C3 = 0.5 × C2 holds, and Td2 = Td1 + Td3 holds. When four pulses are input to the input terminal 1, all the inverter circuits 21, 22, and 23 return to the initial state. That is, the pulse of the output terminal 2 is transmitted once by the pulse of the input terminal 1 four times, and operates as a frequency divider having a frequency division ratio of 4.

  The first embodiment is configured by an even number (2N = 2) of elements, and the capacitance value of the newly provided capacitor is determined to have a predetermined relationship, thereby reducing the condition of the frequency division operation to one. The effect of realizing a frequency division ratio of 4 (generally 4N) can be obtained while maintaining the frequency range of the frequency division operation at the same level as in the prior art. In the first embodiment, since the frequency dividing operation can be realized by using only elements having the same operation delay time, it is possible to design with higher accuracy than the case where the conventional dynamic frequency divider having a frequency dividing ratio of 2 is connected in cascade. Thus, the effect of low circuit consumption and low power consumption can be obtained.

  FIG. 3 is a circuit diagram showing a dynamic frequency divider (corresponding to claim 2) of the second embodiment. An inverter circuit 21, a capacitor 41 having one terminal connected to the output of the inverter circuit 21 and the other terminal grounded, and a switch circuit that passes or blocks the output of the inverter circuit 21 and connects to the inverter circuit of the next stage. 31 constitutes one element, and the same elements are connected in cascade in four stages. Further, the fifth inverter circuit 25 is connected to the output of the switch circuit 34 in the final stage, and this inverter is connected to one terminal. A capacitor 45 having the output of the circuit 25 connected and the other terminal grounded is connected, and the output of the inverter circuit 25 is feedback connected to the input of the inverter circuit 21 in the first stage. The control terminals of the four switch circuits 31, 32, 33, 34 are connected to the input terminal 1 in common.

  Each switch 31, 32, 33, 34 is in a conductive state when the input of its control terminal is at a high level, and is in an open state when it is at a low level. The combination of the inverter circuit 21 and the capacitor 41, the combination of the inverter circuit 22 and the capacitor 42, the combination of the inverter circuit 23 and the capacitor 43, the combination of the inverter circuit 24 and the capacitor 44, and the combination of the inverter circuit 25 and the capacitor 45 There is a delay, and after the input is inverted, the output is inverted to a level opposite to the input after the operation delay times Td1, Td2, Td3, Td4, and Td5, respectively.

  The dynamic frequency divider of the second embodiment realizes the frequency dividing operation as follows. Each time the input terminal 1 becomes high level, the output voltage of the inverter circuits 21, 22, 23, 24 is transmitted as the input voltage of the inverter circuit at the next stage. Therefore, when the input terminal 1 becomes high level four times, the output terminal 2 is inverted. Further, when the input terminal 1 becomes high level four times, the output terminal 2 is inverted. That is, an output pulse is generated once by 8 pulses of the input terminal 1. That is, the frequency division ratio is 8.

  The only difference in configuration from the dynamic frequency divider of the first embodiment is that the elements are changed from two stages to four stages. Each inverter circuit and each capacity parameter are determined as follows.

  The driving powers of the inverter circuits 21, 22, 23, 24, and 25 (the value of mutual conductance gm in the case of FET and the value of current amplification factor in the case of bipolar transistor) are all designed to be equal. Assuming that gm_21, gm_22, gm_23, gm_24, and gm_25 of the FETs used in the inverter circuits 21, 22, 23, 24, and 25 are gm_21 = gm_22 = gm_23 = gm_24 = gm_25, respectively.

  On the other hand, when the values of the capacitors 41, 42, 43, 44, and 45 are C1, C2, C3, C4, and C5, these values are set so that the condition for realizing the frequency dividing operation has the most margin (frequency division). Determine the operating frequency range to be the widest). Specifically, the design is as follows. The input signals of the inverter circuits 21, 22, 23, 24, 25 are V21, V22, V23, V24, and the V25 output signals are V31, V32, V33, V34, V21. A signal input to the input terminal 1 is V1.

  The conditions for realizing the frequency dividing operation are determined by the following four time differences, that is, the time difference between the time when the logic of V31 changes and the pulse time of V1 (first operation delay time), and the time when the logic of V32 changes. And V1 pulse time difference (second operation delay time), V33 logic change time and V1 pulse time difference (third operation delay time), V34 logic change time and V1 Is the time difference (fourth operation delay time) of the pulse times. If these four time differences (operation delay times) satisfy the conditions of the frequency dividing operation, the frequency dividing operation can be realized. However, since there are four conditions alone, the frequency operating frequency range is narrowed. Therefore, by making the time difference between the two equal and reducing the condition for realizing the frequency dividing operation to one, the condition for realizing the frequency dividing operation is given the most allowance, and the design that widens the frequency operating frequency range is performed. .

  To this end, considering that pulses of V1 are input at equal intervals, the timing at which the logic of V31 changes, the timing at which the logic at V32 changes, the timing at which the logic at V33 changes, and the logic at V34 change. What is necessary is just to design so that timings appear alternately at equal intervals. For this purpose, the values of the capacitance values C1, C2, C3, C4, and C5 may be determined so as to satisfy Td2 = Td3 = Td4 = Td1 + Td5. Assuming that each operation delay Td1, Td2, Td3, Td4, Td5 is determined by the driving force of each inverter 21, 22, 23, 24, 25 and each capacitance value C1, C2, C3, C4, C5, C1, If the values of C2, C3, C4, and C5 are designed such that C1 = C5 = 0.5 × C2 = 0.5 × C3 = 0.5 × C4, Td2 = Td3 = Td4 = Td1 + Td5 is established and The circumferential operating frequency range can be expanded most.

  FIG. 4 is a time chart of the operation of the dynamic frequency divider of the second embodiment. Focusing on the inverter circuit 22, when V1 becomes high level at time t = 6, the switches 31, 32, 33, and 34 are all turned on at the same time, and V22 becomes low level equal to V31 in the previous stage from the previous high level. To change. Thereafter, when the operation delay time Td2 of the inverter circuit 22 and the capacitor 42 elapses, the voltage V32 is inverted to a level opposite to V22, that is, a high level (t = 8). At this time, since V1 has already returned to the low level and the switch circuit 31 is in the open state, V22 is maintained at the low level, and then V31 becomes the high level and the switch circuit 31 becomes conductive. This is maintained until time t = 18.

  Combination of inverter circuit 23 and capacitor 43 in the next stage (operation delay time Td3), combination of inverter circuit 24 and capacitor 44 (operation delay time Td4), and combination of inverter circuit 25 and capacitor 45 (operation delay time) In the synthesis circuit of the combination of Td5), the inverter circuit 21 and the capacitor 41 (operation delay time Td1), the operation equivalent to the combination of the inverter circuit 22 and the capacitor 42 (operation delay time Td2) is performed by sequentially shifting the time. Is called. This is because the capacitance values are designed such that C1 = C5 = 0.5 × C2 = 0.5 × C3 = 0.5 × C4, and Td2 = Td3 = Td4 = Td1 + Td5 is established. When eight pulses are input to the input terminal 1, all the inverter circuits 21, 22, 23, 24, 25 return to the initial state. That is, the pulse of the output terminal 2 is sent out once by the pulse of the input terminal 1 8 times, and operates as a frequency divider having a frequency division ratio of 8.

  The second embodiment is configured by an even number (2N = 4) of elements, and the capacitance value of the newly provided capacitor is determined to have a predetermined relationship, thereby reducing the condition of the frequency division operation to one. The effect of realizing a frequency division ratio of 8 (generally 4N) can be obtained while maintaining the frequency range of the frequency division operation at the same level as in the prior art. In the second embodiment, since the frequency dividing operation can be realized by using only elements having the same operation delay time, a highly accurate design is possible as compared with the case where the conventional dynamic frequency divider having a frequency dividing ratio of 2 is connected in cascade. Thus, the effect of low circuit consumption and low power consumption can be obtained.

  FIG. 5 is a circuit diagram showing a dynamic frequency divider (corresponding to claim 3) of the third embodiment. An inverter circuit 21, a capacitor 41 having one terminal connected to the output of the inverter circuit 21 and the other terminal grounded, and a switch circuit that passes or blocks the output of the inverter circuit 21 and connects to the inverter circuit of the next stage. 31 constitutes one element, and the same element is connected in two stages in cascade, and the third inverter circuit 23 is connected to the output of the switch circuit 32 in the final stage, and this inverter is connected to one terminal. A capacitor 43 having the output of the circuit 23 connected and the other terminal grounded is connected, and the output of the inverter circuit 23 is feedback connected to the input of the inverter circuit 21 in the first stage. The control terminals of the two switch circuits 31 and 32 are connected to the input terminal 1 in common.

  Each of the switches 31 and 32 is in a conductive state when the input of its control terminal is at a high level, and is in an open state when it is at a low level. The combination of the inverter circuit 21 and the capacitor 41, the combination of the inverter circuit 22 and the capacitor 42, and the combination of the inverter circuit 23 and the capacitor 43 have a delay in operation, and the operation delay times Td1 and Td2 after the input is inverted, respectively. , After Td3, the output is inverted to the opposite level to the input.

  The dynamic frequency divider of the third embodiment realizes the frequency dividing operation as follows. Each time the input terminal 1 becomes high level, the output voltage of the inverter circuits 21 and 22 is transmitted as the input voltage of the inverter circuit at the next stage. Therefore, when the input terminal 1 becomes high level twice, the output terminal 2 is inverted. Further, when the input terminal 1 becomes high level twice, the output terminal 2 is inverted. That is, one output pulse is generated by four pulses at the input terminal 1. That is, the division ratio is 4.

  The difference from the dynamic frequency divider of the first embodiment is in the parameters of each inverter circuit and each capacitance. Each inverter circuit and each capacity parameter are determined as follows. The values C1, C2, and C3 of the capacitors 41, 42, and 43 are all designed to be the same value. That is, C1 = C2 = C3.

  On the other hand, the condition for the frequency dividing operation to realize the driving force of each inverter circuit 21, 22, 23 (the value of mutual conductance gm in the case of FET and the value of the current amplification factor in the case of bipolar transistor) has the greatest margin. Decide (so that the frequency range of frequency division becomes the widest). Assuming that gm_21, gm_22, and gm_23 of the FETs used in the inverter circuits 21, 22, and 23 are gm_21, gm_22, and gm_23, respectively, these values are specifically designed as follows.

  The input signals of the inverter circuits 21, 22, 23 are V21, V22, V23, and the output signals are V31, V32, V21. A signal input to the input terminal 1 is V1. The conditions for realizing the frequency dividing operation are determined by the time difference between the time when the logic of V31 changes and the pulse time of V1 (first operation delay time), the time when the logic of V32 changes and the pulse time of V1. It is a time difference (second operation delay time). If the time difference (operation delay time) between the two satisfies the condition of the frequency dividing operation, the frequency dividing operation can be realized. However, since there are only two conditions, the frequency operating frequency range is narrowed.

  Therefore, by making the time difference between the two equal and reducing the condition for realizing the frequency dividing operation to one, the condition for realizing the frequency dividing operation is given the most allowance, and the design that widens the frequency operating frequency range is performed. . For this purpose, considering that the pulses of V1 are input at equal intervals, the timing at which the logic of V31 changes and the timing at which the logic of V32 changes alternately appear at equal intervals. For this purpose, the values of the mutual conductances gm_21, gm_22, and gm_23 may be determined so as to satisfy Td2 = Td1 + Td3. If it is determined that the operation delays Td1, Td2, and Td3 are determined by the mutual conductances of the inverters 21, 22, and 23 and the capacitance values C1, C2, and C3, the values of gm_21, gm_22, and gm_23 are gm_21 = 2 × gm_22. = Gm_23 is established, Td2 = Td1 + Td3 is established, and the frequency division operating frequency range can be expanded most.

  FIG. 6 is a time chart of the operation of the dynamic frequency divider of the third embodiment. Each of the signals V1, V21, V22, V23, V31, and V32 is originally an analog signal having a continuous voltage value, but here, binarized logic is described for simplicity. Focusing on the inverter circuit 22, when V1 becomes a high level at time t = 6, the switches 31 and 32 are simultaneously turned on, and V22 changes from the previous high level to a low level equal to V31 in the previous stage. Thereafter, when the operation delay time Td2 of the inverter circuit 22 and the capacitor 42 elapses, the voltage V32 is inverted to a level opposite to V22, that is, a high level (t = 8). At this time, since V1 has already returned to the low level and the switch circuit 31 is in the open state, V22 is maintained at the low level, and then V31 becomes the high level and the switch circuit 31 becomes conductive. This is maintained until time t = 12.

  The combination of the inverter circuit 23 and the capacitor 43 in the next stage (operation delay time Td3) and the combination of the inverter circuit 21 and the capacitor 41 (operation delay time Td1) are a combination of the inverter circuit 22 and the capacitor 42 ( An operation equivalent to the operation delay time Td2) is performed by sequentially shifting the time. This is because each mutual conductance is designed so that gm — 21 = 2 × gm — 22 = gm — 23 holds, and C1 = C2 = C3 holds. When four pulses are input to the input terminal 1, all the inverter circuits 21, 22, and 23 return to the initial state. That is, the pulse of the output terminal 2 is transmitted once by the pulse of the input terminal 1 four times, and operates as a frequency divider having a frequency division ratio of 4.

  The third embodiment is configured by an even number (2N = 2) of elements, a capacity is provided in each stage, and the driving force of each inverter circuit is set to a predetermined value, so that the condition of the frequency dividing operation is set. By reducing it to one, an effect of realizing a frequency division ratio of 4 (generally 4N) can be obtained while maintaining the frequency range of the frequency division operation at the same level as in the prior art. In the third embodiment, since the frequency dividing operation can be realized by using only elements having the same operation delay time, it is possible to design with higher accuracy than the case where the conventional dynamic frequency divider having the frequency dividing ratio of 2 is connected in cascade. Thus, the effect of low circuit consumption and low power consumption can be obtained.

  FIG. 7 is a circuit diagram showing a dynamic type frequency divider of the fourth embodiment (corresponding to claim 4). An inverter circuit 21, a capacitor 41 having one terminal connected to the output of the inverter circuit 21 and the other terminal grounded, and a switch circuit that passes or blocks the output of the inverter circuit 21 and connects to the inverter circuit of the next stage. 31 constitutes one element, and the same element is connected in two stages in cascade. Further, the third inverter circuit 23 is connected to the output of the switch circuit 32 in the final stage, and the output of the inverter circuit 23 is A feedback connection is made to the input of the inverter circuit 21 in the first stage. The control terminals of the two switch circuits 31 and 32 are connected to the input terminal 1 in common.

  In the fourth embodiment, a frequency division operation with a frequency division ratio of 4 is realized as in the first embodiment. In the circuit configuration, the capacitor 43 connected to the output of the inverter circuit 23 in the first embodiment is deleted, and the capacitance values C1 and C2 are determined by a method different from that in the first embodiment.

  Each of the switches 31 and 32 is in a conductive state when the input of its control terminal is at a high level, and is in an open state when it is at a low level. In addition, the combination of the inverter circuit 21 and the capacitor 41, the combination of the inverter circuit 22 and the capacitor 42, and the inverter circuit 23 have a delay in operation, and the outputs are inverted after the operation delay times Td1, Td2, and Td3, respectively, after the input is inverted. Is inverted to the opposite level of the input. The parameters of each inverter circuit and each capacity are determined as follows.

  The drive powers of the inverter circuits 21, 22, and 23 (the value of mutual conductance gm in the case of FETs and the value of current amplification factor in the case of bipolar transistors) are all designed to be equal. When gm of the FETs used in the inverter circuits 21, 22, and 23 are gm_21, gm_22, and gm_23, respectively, gm_21 = gm_22 = gm_23.

  On the other hand, assuming that the values of the capacitors 41 and 42 are C1 and C2, these values are determined so that the condition for realizing the frequency dividing operation has the most margin (the frequency operating frequency range becomes the widest). . Specifically, the design is as follows. The input signals of the inverter circuits 21, 22, 23 are V21, V22, V23, and the output signals are V31, V32, V21. A signal input to the input terminal 1 is V1.

  The conditions for realizing the frequency dividing operation are determined by the time difference between the time when the logic of V31 changes and the pulse time of V1 (first operation delay time), the time when the logic of V32 changes and the pulse time of V1. It is a time difference (second operation delay time). If the time difference (operation delay time) between the two satisfies the condition of the frequency dividing operation, the frequency dividing operation can be realized. However, since there are only two conditions, the frequency operating frequency range is narrowed.

  Therefore, by making the time difference between the two equal and reducing the condition for realizing the frequency dividing operation to one, the condition for realizing the frequency dividing operation is given the most allowance, and the design that widens the frequency operating frequency range is performed. . For this purpose, considering that the pulses of V1 are input at equal intervals, the timing at which the logic of V31 changes and the timing at which the logic of V32 changes alternately appear at equal intervals. For this purpose, the capacitance values C1 and C2 may be determined so as to satisfy Td2 = Td1 + Td3. Assuming that each operation delay Td1, Td2, Td3 is determined by the driving force of each inverter 21, 22, 23 and each capacitance value C1, C2, if the operation delay time of the inverter circuit 23 can be ignored, C1, C2 If the value of C1 = C2 is established, Td2 = Td1 + Td3 is established, and the frequency division operating frequency range can be expanded most. In an actual circuit, since the operation delay time of the inverter circuit 23 cannot be ignored, it is required to design C1 to be smaller than C2 in order to compensate for this, and it may be determined that C1 = 0 in some cases. That is, the values of C1 and C2 are determined so that Td2 = Td1 + Td3 is established. That is, 0 ≦ C1 ≦ C2 (C3 = 0).

  FIG. 8 is a time chart of the operation of the dynamic frequency divider of the fourth embodiment. Each of the signals V1, V21, V22, V23, V31, and V32 is originally an analog signal having a continuous voltage value, but here, binarized logic is described for simplicity. Focusing on the inverter circuit 22, when V1 becomes a high level at time t = 6, the switches 31 and 32 are simultaneously turned on, and V22 changes from the previous high level to a low level equal to V31 in the previous stage. Thereafter, when the operation delay time Td2 of the inverter circuit 22 and the capacitor 42 elapses, the voltage V32 is inverted to a level opposite to V22, that is, a high level (t = 8). At this time, since V1 has already returned to the low level and the switch circuit 31 is in the open state, V22 is maintained at the low level, and then V31 becomes the high level and the switch circuit 31 becomes conductive. This is maintained until time t = 12.

  The inverter circuit 23 (operation delay time Td3) of the next stage and the combination of the inverter circuit 21 and the capacitor 41 (operation delay time Td1) are combined with the combination of the inverter circuit 22 and the capacitor 42 (operation delay time Td2). An equivalent operation is performed by sequentially shifting the time. This is because Td2 = Td1 + Td3 is established by designing each capacitance value. When four pulses are input to the input terminal 1, all the inverter circuits 21, 22, and 23 return to the initial state. That is, the pulse of the output terminal 2 is transmitted once by the pulse of the input terminal 1 four times, and operates as a frequency divider having a frequency division ratio of 4.

  In the fourth embodiment, as in the first embodiment, the effect of realizing a frequency division ratio of 4 (generally 4N) is obtained. Since the present invention can realize the frequency dividing operation with only elements having the same operation delay time, it is possible to design with higher accuracy than the case where the conventional dynamic frequency divider having a frequency dividing ratio of 2 is connected in cascade. There is an effect that the circuit scale is small and the power consumption is low.

  FIG. 9 is a circuit diagram showing a dynamic frequency divider (corresponding to claim 4) of the fifth embodiment. An inverter circuit 21, a capacitor 41 having one terminal connected to the output of the inverter circuit 21 and the other terminal grounded, and a switch circuit that passes or blocks the output of the inverter circuit 21 and connects to the inverter circuit of the next stage. 31 constitutes one element, and the same elements are connected in cascade in four stages. Further, the fifth inverter circuit 25 is connected to the output of the switch circuit 34 in the final stage, and the output of the inverter circuit 25 is the first stage. Is connected to the input of the inverter circuit 21 in a feedback manner. The control terminals of the four switch circuits 31, 32, 33, 34 are connected to the input terminal 1 in common.

  In the fifth embodiment, a frequency division operation with a frequency division ratio of 8 is realized as in the second embodiment. In the circuit configuration, the capacitor 45 connected to the output of the inverter circuit 25 in the second embodiment is deleted, and the capacitance values C1, C2, C3, and C4 are determined by a method different from that of the second embodiment.

  Based on the same idea as the capacity design in the second embodiment, a design for widening the frequency range of frequency division operation is performed by giving the most margin to the condition for realizing the frequency division operation. The combination of the inverter circuit 21 and the capacitor 41, the combination of the inverter circuit 22 and the capacitor 42, the combination of the inverter circuit 23 and the capacitor 43, the combination of the inverter circuit 24 and the capacitor 44, and the inverter circuit 25 have a delay in operation. Assume that the inverted signals are output after the operation delay times Td1, Td2, Td3, Td4, and Td5 after the inversion. In the fifth embodiment, similarly to the second embodiment, if each operation delay time is Td2 = Td3 = Td4 = Td1 + Td5, the frequency division operating frequency range can be expanded most. That is, the values of C1, C2, C3, and C4 are determined so that Td2 = Td3 = Td4 = Td1 + Td5. In the case where the operation delay time of the inverter circuit 25 can be ignored, C1 = C2 = C3 = C4 may be used. However, in an actual circuit, C2, C3, C4 are used as C1 in order to compensate for the operation delay time of the inverter circuit 25. It is necessary to select a small value for. In some cases, C1 = 0 may be designed. That is, 0 ≦ C1 ≦ C2 = C3 = C4 (C5 = 0).

  FIG. 10 is a time chart of the operation of the dynamic frequency divider of the fifth embodiment. Focusing on the inverter circuit 22, when V1 becomes high level at time t = 6, the switches 31, 32, 33, and 34 are all turned on at the same time, and V22 becomes low level equal to V31 in the previous stage from the previous high level. To change. Thereafter, when the operation delay time Td2 of the inverter circuit 22 and the capacitor 42 elapses, the voltage V32 is inverted to a level opposite to V22, that is, a high level (t = 8). At this time, since V1 has already returned to the low level and the switch circuit 31 is in the open state, V22 is maintained at the low level, and then V31 becomes the high level and the switch circuit 31 becomes conductive. This is maintained until time t = 18.

  The combination of the inverter circuit 23 and the capacitor 43 in the next stage (operation delay time Td3), the combination of the inverter circuit 24 and the capacitor 44 (operation delay time Td4), and the inverter circuit 25 (operation delay time Td5) and the inverter circuit 21 And a combination circuit of the capacitor 41 (operation delay time Td1), the operation equivalent to the combination of the inverter circuit 22 and the capacitor 42 (operation delay time Td2) is performed with the time shifted sequentially. This is because Td2 = Td3 = Td4 = Td1 + Td5 is established by designing each capacitance value. When eight pulses are input to the input terminal 1, all the inverter circuits 21, 22, 23, 24, 25 return to the initial state. That is, the pulse of the output terminal 2 is sent out once by the pulse of the input terminal 1 8 times, and operates as a frequency divider having a frequency division ratio of 8.

  As in the second embodiment, the fifth embodiment has the effect of realizing a frequency division ratio of 8 (generally 4N). In the fifth embodiment, the frequency dividing operation can be realized by using only elements having the same operation delay time. Therefore, the design can be made with higher accuracy as compared with the case where the conventional dynamic frequency divider having a frequency dividing ratio of 2 is connected in cascade. Thus, the effect of low circuit consumption and low power consumption can be obtained.

FIG. 3 is a circuit diagram illustrating a dynamic frequency divider according to the first embodiment. 3 is a time chart of the operation of the dynamic divider according to the first embodiment. FIG. 6 is a circuit diagram illustrating a dynamic frequency divider according to a second embodiment. 6 is a time chart of the operation of the dynamic divider according to the second embodiment. FIG. 6 is a circuit diagram illustrating a dynamic frequency divider according to a third embodiment. 10 is a time chart of the operation of the dynamic divider according to the third embodiment. FIG. 6 is a circuit diagram illustrating a dynamic frequency divider according to a fourth embodiment. 10 is a time chart of the operation of the dynamic divider according to the fourth embodiment. FIG. 10 is a circuit diagram illustrating a dynamic frequency divider according to a fifth embodiment. 10 is a time chart of the operation of the dynamic frequency divider according to the fifth embodiment. It is a circuit diagram which shows the structural example of the conventional dynamic type frequency divider. It is a time chart of operation of the conventional dynamic type frequency divider.

Explanation of symbols

1: input terminal 2: output terminal 21, 22, 23, 24, 25: inverter circuit 31, 32, 33, 34: switch circuit 41, 42, 43, 44, 45: capacity 51: first element 52: first Second element 53: Third element

Claims (4)

The inverter means and the switch means that passes or cuts off the output of the inverter means and connects to the next-stage inverter means as one element, and the elements are connected in a cascade of 2N (N is a natural number),
The 2N + 1-th inverter means is connected to the output of the switch means of the last-stage element of the 2N elements, and the output of the 2N + 1-th inverter means is the first-stage element of the 2N elements. A dynamic frequency divider connected in feedback to the input of the inverter means, and the control terminal of each switch means of the 2N elements connected to the input terminal in common;
The total delay time of the delay time of the 2N + 1-th inverter means and the delay time of the inverter means of the first-stage element among the 2N elements is from the second stage to the 2N-stage of the 2N elements. A dynamic frequency divider characterized by being set to coincide with the delay time of each inverter means of the eye. An inverter circuit, a capacitor having one terminal connected to the output of the inverter circuit and the other terminal grounded, and a switch circuit passing through or blocking the output of the inverter circuit and connected to the inverter circuit of the next stage As two elements, 2N elements (N is a natural number) are connected in cascade,
The 2N + 1-th inverter circuit is connected to the output of the switch circuit of the last-stage element of the 2N elements, and the other end of the 2N + 1-th capacitor whose one terminal is grounded is the 2N + 1-th inverter. The output of the 2N + 1-th inverter circuit is connected to the input of the inverter circuit of the first stage of the 2N elements, and the control terminal of each switch circuit of the 2N elements. Is a dynamic divider connected to the input terminal in common,
Of the 2N elements, the capacity value of the first stage element and the capacity value of the 2N + 1th capacity are respectively half of the capacity of each element from the second stage to the 2N stage of the 2N elements. A dynamic type frequency divider characterized by being set to a value. An inverter circuit, a capacitor having one terminal connected to the output of the inverter circuit and the other terminal grounded, and a switch circuit passing through or blocking the output of the inverter circuit and connected to the inverter circuit of the next stage As two elements, 2N elements (N is a natural number) are connected in cascade,
The 2N + 1-th inverter circuit is connected to the output of the switch circuit of the last-stage element of the 2N elements, and the other end of the 2N + 1-th capacitor whose one terminal is grounded is the 2N + 1-th inverter. The output of the 2N + 1-th inverter circuit is connected to the input of the inverter circuit of the first stage of the 2N elements, and the control terminal of each switch circuit of the 2N elements. Is a dynamic divider connected to the input terminal in common,
Of the 2N elements, the driving power of the inverter circuit of the first stage element and the driving power of the 2N + 1-th inverter circuit are respectively calculated from the second stage to the 2N stage elements of the 2N elements. A dynamic frequency divider characterized by being set to twice the driving force of the inverter circuit. An inverter circuit, a capacitor having one terminal connected to the output of the inverter circuit and the other terminal grounded, and a switch circuit that passes or blocks the output of the inverter circuit and connects to the next-stage inverter circuit are 1 As two elements, 2N elements (N is a natural number) are connected in cascade,
The 2N + 1-th inverter circuit is connected to the output of the switch circuit of the last-stage element of the 2N elements, and the output of the 2N + 1-th inverter circuit is the first-stage element of the 2N-th element A dynamic frequency divider in which the control terminal of each of the switch circuits of the 2N elements is connected in common to the input terminal,
The value of the first stage capacity of the 2N elements is selected to be smaller than the capacity value of the second to 2N stages of the 2N elements,
The total delay time of the delay time of the 2N + 1th inverter circuit and the delay time due to the inverter circuit and capacitance of the first stage element of the 2N elements is from the second stage of the 2N elements. A dynamic frequency divider characterized by being set to coincide with a delay time due to an inverter circuit and a capacity of each element of the 2N stage.

Images