JP2005150702A - Spin-on glass composite and method of forming silicone oxide film using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a spin-on glass composite and a method of forming a silicon oxide film using the same. <P>SOLUTION: According to the spin-on glass composite which has the excellent property of flattening a bump and has no void, and a method of forming the silicon oxide film using the same, the spin-on glass composite containing polysilazane whose structural formula is -(SiH<SB>2</SB>NH)<SB>n</SB>-(where n represents a positive integer) and weight-average molecular weight is 3,300 to 3,700 is applied on a semiconductor substrate having a bump formed on its top surface, so that a flat spin-on glass film is formed. The spin-on glass film is cured to be transformed into a flat silicon oxide film. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a spin-on-glass (SOG) composition for forming a silicon oxide film in a semiconductor manufacturing process and a silicon oxide film forming method using the same, and more particularly, the present invention relates to polysilazane ( The present invention relates to a spin-on glass composition containing polysilazane) and a method for forming a silicon oxide film of a semiconductor device using the same.

  Recently, semiconductor devices have also been dramatically developed due to the rapid spread of information media such as computers. In particular, in terms of its function, the semiconductor device is required to operate at a high speed and to have a large capacity storage capability. In response to such demands, the manufacturing technology of semiconductor devices has been developed to improve the degree of integration, reliability, response speed, and the like.

  In general, integrated circuits are manufactured by forming many active devices on a single substrate. After each element is formed and insulated, the specific elements are electrically connected to each other during the manufacturing process to obtain the desired circuit function. For example, MOS, bipolar VLSI, and ULSI devices have a multilevel interconnection structure in which a large number of elements are electrically connected to each other. In such an interconnection structure, as the number of films increases, the top layer topography has a more bent shape.

  For example, a method for manufacturing a semiconductor wafer on which two or more metal layers are formed is as follows. A large number of oxide films, polycrystalline silicon conductive films, and first metal wiring films are formed on a semiconductor wafer. Next, a first insulating film is formed on the semiconductor result. In order to provide a circuit path to the second metal wiring film, a via hole is formed in the first insulating film. At this time, since the film existing below the first insulating film is not flat, the surface of the first insulating film is not flat. When the second metal wiring film is formed directly on the first insulating film, a crack is generated in the second metal wiring film due to a protruding portion or a crack in the first insulating film. Further, when the deposition rate of the metal film becomes poor, the manufacturing yield of the semiconductor element is lowered. Therefore, in general, in a multilevel metal interconnection structure, an insulating film is planarized before forming a via or a second metal wiring layer.

  Various methods for planarizing the insulating film have been developed. Such a method includes a method using a BPSG (Borophosphorous Silicate Glass) film or a spin-on glass (SOG) film having excellent reflow characteristics, and a chemical mechanical polishing (CMP) method. . In general, a method using BPSG has been widely used for an insulating film for filling a gap between metal wirings. However, the process of depositing BPSG has the problem that it preferentially depends on setting specific deposition variables for the equipment used. Furthermore, the gas used in the process is not only expensive, but also highly toxic.

  Further, as the degree of integration increases and the design rule decreases, an interlayer insulating film is formed using BPSG to fill a gap between wirings in order to manufacture a VLSI of 256 mega DRAM class or more. However, the formation of a bridge due to void generation may reduce the yield or damage an etching stopper film used in a subsequent process. Therefore, in order to solve this, it is necessary to perform an additional reflow process and an expensive CMP process.

  On the other hand, the process of forming an insulating film using an SOG film is widely known as a process capable of forming a flat insulating film by simple coating. For example, Patent Document 1 discloses a method of forming a polysilazane layer and then converting the polysilazane layer to a silicon oxide film by heating in a oxygen atmosphere. Patent Document 2 discloses a method in which an inorganic SOG is deposited and then converted into a silicon oxide film through a two-step heat treatment process.

  The basic structure of the polysilazane-based SOG composition is composed of Si—N, Si—H, and N—H bonds. When baking is performed in an atmosphere containing oxygen and water, Si—N bonds are replaced with Si—O bonds. Such a method of converting to a silicon oxide film using an SOG composition can be performed by a simple spin coating method and a curing process, and thus has an advantage that costs are reduced.

However, it is known that not all Si—N bonds are replaced by Si—O bonds (see Patent Document 3). Therefore, since the silicon oxide film has different insulating properties and electrical characteristics from a pure silicon oxide film formed using a BPSG film or a TEOS film, the silicon oxide film is used as an insulating film. Has problems. Furthermore, since the SOG film is formed by a spin coating method, the thickness of the formed silicon oxide film is not sufficient, so that the conductive layer such as the gate electrode and the metal wiring film cannot be completely covered.
US Pat. No. 5,310,720 US Pat. No. 5,976,618 Japanese Unexamined Patent Publication No. 11-145286

  In order to solve such problems, the present applicant can fill a gap between VLSI class metal wirings having a high aspect ratio, and fills a gap in a substrate without performing a mechanical planarization process. And developed a spin-on glass composition containing perhydropolysilazane which can produce an oxide film having the same characteristics as an oxide film formed by chemical vapor deposition by slowing the unevenness of the substrate surface. US Patent Application No. 09 / 686,624 dated 12th (corresponding to Korean Patent Application No. 2000-59635, which is a priority claim application of Korean Patent Application No. 2000-23448) (SPIN-ON GLASS COMPOSTION AND METHOD OF FORMING SILICON OXIDE LAYER IN SEMI ONDUCTOR MANUFACTURING PROCESS USING THE SAME) may be filed as.

According to what was disclosed in the method, structure on a substrate having a stepped portion is _{- (SiH 2 NH 2) n} - ( of the formula, n represents a positive integer), and the weight average molecular weight of from 4000 to 8000 A silicon oxide film having a flat surface can be formed by applying and curing an SOG solution containing polysilazane having a molecular weight distribution of 3.0 to 4.0.

  The silicon oxide film has an STI structure formed on a semiconductor substrate having a step portion formed by a groove and a protrusion for forming an element isolation structure having an STI (Shallow Trench Isolation) structure. An element isolation film is given as an example.

  The curing step includes a preliminary baking step and a main baking step. The pre-baking is performed at a temperature of about 100-500 ° C, preferably about 100-400 ° C for about 1-5 minutes, preferably about 2-3 minutes, and the main baking is performed at a temperature of about 900-1050 ° C.

  The silicon oxide film formed here has excellent gap-filling characteristics for an STI structure including a gap of 0.1 to 1 μm. However, according to the wet etching ratio test, as the main baking temperature increases, the etching ratio decreases, and a silicon oxide film is formed on the silicon substrate surface portion and the active region.

  FIG. 1 is a cross-sectional view of an oxide film formed on the inner surface of a trench. The semiconductor device shown in FIG. 1 is manufactured by the following method. A pad oxide film is formed on the silicon substrate 100, and a nitride film and a high temperature oxide film are sequentially formed on the pad oxide film. The nitride film functions as an etch stop layer in the subsequent CMP process, and the high-temperature oxide film functions as a hard mask layer.

  Next, silicon nitride oxide (SiON) is formed on the high temperature oxide film to form an antireflection film (not shown), and a high temperature oxide film pattern 116 for defining an active pattern by performing a photolithography process. Form.

  Using the high temperature oxide film pattern 116 as an etching mask, the nitride film and the pad oxide film are sequentially etched to form a nitride film pattern 114 and a pad oxide film pattern 112. A trench 118 is formed by etching an upper portion of the substrate adjacent to the nitride pattern.

  Next, when the trench etching process is performed, the exposed portion of the trench 118 is heat-treated in an oxygen atmosphere in order to cure silicon damage caused by high energy ion implantation. At this time, a trench inner wall oxide film 120 is formed inside the trench including the bottom and side surfaces of the trench by an oxidation reaction between the oxidant and the exposed silicon.

  The present applicant forms an SOG film by depositing the SOG composition on the semiconductor substrate 100 while filling the trench 118 with the proposed SOG composition. Thereafter, the SOG film is baked. The preliminary baking is performed at a temperature of about 100 to 500 ° C., preferably about 100 to 400 ° C., for about 1 to 5 minutes, preferably about 2 to 3 minutes. The main baking is performed at a temperature of about 900 to 1050 ° C. to form a silicon oxide film. As a result, as shown in FIG. 1, an oxide film 130 filling the trench is formed. The oxide film 130 is formed of an SOG film. At this time, as in the portion indicated by a circle in FIG. 1, it can be confirmed that the oxide film on the side wall portion of the inner wall oxide film 120 in the trench is thicker than the oxide film on the bottom surface portion. It is estimated that the oxide forming the oxide film is formed by an oxidation reaction of silicon contained in the semiconductor substrate 100 and oxygen contained in the oxidizing gas when the SOG film is cured at 1000 ° C. or higher in an oxidizing atmosphere. Is done.

  The generation of such an oxide induces a morphological defect or changes the size of the active region in a concave portion such as a groove after the CMP process.

  In addition, the present applicant can fill a gap between VLSI metal wirings having a high aspect ratio, and can fill a gap in a substrate without performing a mechanical flattening process. We developed a spin-on glass composition containing perhydropolysilazane that can be slowed down to produce an oxide film having characteristics similar to those of chemical vapor deposition oxides, which was issued on October 24, 2002 as a US patent. Application No. 09 / 985,615 E the METHOD) (filed as corresponding) to the application Korean Patent Application No. 2001-31633, which have received patents in the U.S. Patent No. 6,279,205.

  Accordingly, an object of the present invention is to provide a spin-on glass composition capable of filling a gap between metal wirings arranged very adjacent to each other in a semiconductor device having a high degree of integration and a high aspect ratio. is there.

  Another object of the present invention is to provide a composition capable of filling the gap by slowing the unevenness of the substrate surface without performing a mechanical planarization step.

  Another object of the present invention is to provide a spin-on glass composition having substantially the same characteristics as an oxide film of a semiconductor device produced by a chemical vapor deposition method.

  Another object of the present invention is to provide a method of forming an oxide film in a semiconductor manufacturing process using the spin-on glass composition described above.

In order to achieve the above-described object of the present invention, a preferred embodiment of the present invention includes a structural formula of — (SiH ₂ NH) _n — (wherein n is a positive integer), and a weight average molecular weight. Is about 3000-6000, and provides a spin-on glass composition comprising 10-30 wt% polysilazane and about 70-90 wt% solvent.

To achieve the object of the present invention described above, according to a preferred oxide film forming method according to an embodiment of the present invention, on a semiconductor substrate having a step portion on the top surface, the structural formula - (SiH 2 _{NH) n} - (of the formula, n is a positive integer) is from about 3000 to 6000 weight average molecular weight, the spin-on glass composition comprising 10-30% by weight of polysilazane and about 70 to 90 wt% of the solvent Apply to form a spin-on glass film. The spin-on glass film is cured to form a silicon oxide film.

  According to various embodiments of the present invention, using a spin-on glass composition having an aspect ratio on the order of about 5: 1 to 10: 1 or capable of applying a conductive film with severe surface discontinuity, A uniform silicon oxide film having few voids can be formed.

  Hereinafter, a spin-on glass composition according to a preferred embodiment of the present invention and a method of forming an oxide film in a semiconductor device using the same will be described in detail with reference to the accompanying drawings.

  In this specification, when it is mentioned that a substance, film, or structure is deposited or formed on a different substance, film, or layer, this means that another layer, substance, or structure is formed between them. It can also mean that it is.

The spin-on glass composition of the present invention is disclosed in US patent application Ser. No. 09 / 686,624, preferably having the structural formula — (SiH ₂ NH ₂ ) _n — (where n is a positive integer). A polysilazane having a weight average molecular weight of 4000 to 8000 and a molecular weight distribution of 3.0 to 4.0. In the detailed description of the present invention, the molecular weight distribution means the ratio of the weight average molecular weight to the number average molecular weight.

  Methods for producing polysilazanes are known. As a typical method, a polysilazane is produced by reacting a complex compound formed from the reaction of a halosilane and a Lewis base with ammonia.

Alternatively, a method of synthesizing polysilazane by reacting a silicon halide such as SiCl ₄ or SiH ₂ Cl ₂ with an amine, a method of converting silazane to polysilazane using an alkali metal halide catalyst, a transition metal complex compound (transition complex metal compound) A polysilazane can be produced by a method of dehydrogenating a silane compound with an amine compound.

  US Pat. No. 5,494,978 discloses a method for producing defoamed polysilazane using inorganic polysilazane having a number average molecular weight of 100 to 100,000. US Pat. No. 5,905,130 discloses a reaction between a polyaminosilane compound and a polyhydrogenated nitrogen-containing compound under a base catalyst, or a polyhydrogenated silicon compound. A method of producing polysilazane by reacting a polyhydrogenated silicon compound and a polyhydrogenated nitrogen-containing compound in the presence of a basic solid oxide catalyst is disclosed.

  In addition, U.S. Pat. No. 5,436,398 discloses an example of producing perhydropolysilazane having a number average molecular weight of 1,120, and U.S. Pat. No. 950,381 discloses a method for producing a polysilazane having a desired molecular weight.

  There is no special restriction | limiting in the manufacturing method of the polysilazane used by this invention. Polysilazane can be easily produced by the method described above. The perhydropolysilazane produced by the above-mentioned known method is fractionated using molecular weight fractionation so that it can be used in the present invention.

  If the weight average molecular weight of the polysilazane used in the present invention is less than 4000, outgassing increases, and perhydropolysilazane is rapidly converted into silicon oxide due to the small molecular weight, and cracks are generated. Conversely, when the weight average molecular weight exceeds 8000, the viscosity of the SOG composition solution increases, and the uniformity of the spin-on glass film produced during coating decreases. Therefore, the weight average molecular weight of the perhydropolysilazane used in the present invention is 4000 to 8000. More specifically, when an SOG film for filling a trench is formed, the weight average molecular weight of perhydropolysilazane is preferably 6000 to 8000, more preferably 6500 to 7000.

In another embodiment, when the perhydropolysilazane used in the present invention has a weight average molecular weight of less than 3000, degassing increases, and the degassed SiH ₄ reacts with oxygen gas, such as SiO ₂ Particles form and contaminate the reaction chamber. The particles contaminate the wafer in a subsequent process. On the other hand, if the weight average molecular weight exceeds about 6000, the viscosity of the SOG solution increases and the uniformity of the spin-on glass film produced decreases. Accordingly, the molecular weight of the perhydropolysilazane used in the present invention is about 3000 to 6000, more preferably about 3300 to 3700.

  Also, if the molecular weight distribution, which is the ratio of the weight average molecular weight to the number average molecular weight of the polysilazane, is less than about 3.0, the efficiency during fractionation of the polysilazane is lowered, and the production yield of polysilazane is extremely low. Become. On the other hand, when the distribution degree exceeds about 4, the converted silicon oxide film becomes non-uniform. Accordingly, the molecular weight distribution of the polysilazane used in the present invention is preferably about 3.0 to 4.0. However, polysilazane having a molecular weight distribution outside the above-mentioned molecular weight distribution range can also be used when necessary.

  The perhydropolysilazane used in another embodiment of the present invention has a molecular weight distribution of about 2.5 to 3.5, more preferably 2.8 to 3.2. When the weight average molecular weight of the perhydropolysilazane is about 3000 to 6000, the molecular weight distribution of the perhydropolysilazane is about 2.5 to 3.5. If the molecular weight distribution is less than about 2.5, the efficiency when fractionating perhydropolysilazane is deteriorated, and the production yield of perhydropolysilazane becomes very low. On the other hand, when the molecular weight distribution of perhydropolysilazane exceeds about 3.5, the converted silicon oxide film becomes non-uniform.

  The SOG composition is preferably an SOG solution produced by dissolving the aforementioned polysilazane in a solvent, preferably an organic solvent. Various other organic solvents, or other solvents can be used without limitation in the present invention. Preferably, aromatic solvents such as xylene or other solvents such as dibutyl ether can be usefully used as the solvent. If the concentration of polysilazane in the SOG solution is greater than about 30% by weight, the polysilazane becomes unstable, the life of the SOG solution decreases, and cracks occur in the SOG film. If the concentration of polysilazane in the SOG solution is less than about 10% by weight, it is not easy to adjust the thickness of the SOG film. Therefore, the concentration of the polysilazane in the SOG solution is preferably about 10 to 30% by weight and 18 to 25% by weight. The concentration of the solvent in the SOG solution is preferably about 70 to 90% by weight, more preferably about 75 to 82% by weight.

  The SOG composition containing polysilazane preferably has a contact angle of about 4 ° or less with respect to a lower film, for example, a silicon nitride film. When the contact angle is larger than 4 °, the adhesive force between the SOG composition and the lower film is deteriorated.

  As described above, the SOG composition, preferably the SOG solution, is prepared by dissolving the perhydropolysilazane in a solvent such as an organic solvent. Various other organic solvents or other solvents can be used without limitation in the present invention. Solvents that can be used preferably include aromatic solvents such as xylene or other solvents such as dibutyl ether. If the concentration of perhydropolysilazane in the SOG solution is greater than about 30% by weight, the perhydropolysilazane becomes unstable, the life of the SOG solution is shortened, and cracks are generated in the SOG film. If the concentration of perhydropolysilazane is less than about 10% by weight, it is not easy to adjust the thickness of the SOG film. Therefore, according to another embodiment of the present invention, the concentration of the perhydropolysilazane in the SOG solution is preferably about 10-30% by weight, more preferably about 20-23% by weight. The SOG composition containing polysilazane preferably has a contact angle of about 4 ° or less with respect to a lower film, for example, a silicon nitride film. When the contact angle is larger than 4 °, the adhesive force between the SOG composition and the lower film is deteriorated.

  In order to make the surface of the SOG film uniform during the coating process and the curing process, the SOG solution preferably has a viscosity of about 1 to 10 mPa · s, more preferably about 1 to 8 mPa · s under a predetermined shear rate. Have.

  FIG. 2 is a graph for explaining the relationship between the viscosity of the SOG solution and the shear rate. In FIG. 2, the ordinate of the graph indicates viscosity (mPa · s), and the abscissa indicates the shear rate (1 / s). As shown in FIG. 2, the SOG solution according to the present invention preferably has a viscosity of about 1 to 10 mPa · s at a shear rate of about 54 to 420 (1 / s). It can also be seen from FIG. 2 that at a shear rate of about 10 to 1000 (1 / s), the viscosity of the SOG composition is in the range of about 1 to 10 mPs.

  The viscosity of the SOG composition determines the flatness of the oxide film by affecting the flowability of the SOG composition. As the weight average molecular weight of the perhydropolysilazane increases, the viscosity of the SOG composition also increases. When the weight average molecular weight of the perhydropolysilazane is about 3000 to 6000, the viscosity of the SOG composition is about 1.54 to 1.70 mPa · s (cP).

  The SOG composition may optionally include at least one impurity including boron, fluorine, phosphorus, arsenic, carbon, oxygen, or a mixture thereof. Among these impurities, when adding at least one element selected from boron, fluorine, phosphorus, or arsenic to the SOG solution, the silicon oxide film generated from the SOG composition contains impurities, The BSG film, the BPSG film, the PSG film, and the like have similar characteristics. Further, when an element such as carbon or oxygen is added as an impurity to the SOG solution, the rate at which the SOG film is converted into a silicon oxide film can be accelerated.

  The SOG composition described above is preferably applied by a spin coating method onto a substrate having a non-uniform surface, for example, a semiconductor substrate having a conductive wiring pattern. In particular, the spin coating method is useful for forming a flat SOG film.

  The non-planar surface of the substrate can be generated due to the conductive pattern. For example, a conductive metal wiring pattern such as a gate electrode pattern or a bit line forms a step portion on the surface of the substrate. The distance between the two conductive layer patterns is not limited. However, if the distance is longer than 1 μm, it is suitable to use the conventional BPSG in the method for forming the oxide film. On the other hand, if the distance is shorter than 0.04 μm, the use of the method using the SOG solution of the present invention increases the possibility that voids are formed in the SOG film. Therefore, the method of the present invention is applied to a semiconductor substrate having a gap of about 0.04 to 1 μm.

  In addition, the method according to various embodiments of the present invention can be applied to a conductive pattern gap having a low aspect ratio, which is a ratio of depth to width. However, the method of the present invention is preferably applied to a conductive layer pattern having an aspect ratio of about 5: 1 to 10: 1.

  Generally, a conductive pattern is densely formed in a finely spaced gap such as a cell array region including a gate electrode. Such a gap can be formed on a semiconductor substrate. Furthermore, the conductive pattern is formed so as not to be dense in a global stepped portion such as a peripheral circuit region or in an independent gap. Such a global stepped portion can also be formed on the semiconductor substrate. The method of the present invention can be applied to a semiconductor substrate having a finely spaced gap having an aspect ratio of about 5: 1 to 10: 1 and a global step having an aspect ratio of about 1: 1 or less. .

  Further, the stepped portion can be formed by a protruding portion / depressed portion of the semiconductor substrate. Specifically, an oxide film can be formed by the method of the present invention on a protruding portion of a semiconductor substrate having a groove and a protruding portion. Forming an oxide film by such a method is useful when forming an element isolation structure having a shallow trench isolation (STI) structure. The step portion may be formed of a metal wiring formed on the insulating film. That is, the silicon oxide film formed by the method of the present invention can be used as an interlayer insulating film for insulating a metal wiring formed on the insulating film.

  Hereinafter, a method for curing the applied SOG film will be described in detail.

  The SOG film formed by the above-described method is cured and converted into a silicon oxide film having a flat surface. The curing stage is performed by a preliminary baking stage and a main baking stage. Based on the contents disclosed herein, those skilled in the art can cure the SOG film and convert it to a silicon oxide film having a flat surface.

  The preliminary baking is preferably performed at a temperature of about 100 to 500 ° C. for about 1 to 5 minutes. If the pre-baking is performed at about 100 ° C. or lower, the organic solvent may remain in the film. When pre-baking is performed at a temperature of about 500 ° C. or more, polysilazane located below a predetermined depth is not completely converted into silicon oxide in the subsequent main baking process, and the surface is rapidly converted into silicon oxide. Cracks are generated and the final silicon oxide film becomes non-uniform.

  When the pre-baking time is about 1 minute or less, the organic solvent remains in the film and is not completely removed. On the contrary, when the pre-baking time exceeds about 5 minutes, the organic solvent is completely removed, but partial conversion to silicon oxide is induced on the surface of the SOG film containing perhydropolysilazane. Cracks occur. Accordingly, the preliminary baking is performed at a temperature of about 100 to 500 ° C., preferably 100 to 400 ° C., for about 1 to 5 minutes, preferably about 2 to 3 minutes.

  The main baking stage is performed at a high temperature for a long time with respect to the preliminary baking. The basic structure of polysilazane-based SOG includes Si—N bonds. When baking is performed in an atmosphere containing oxygen and water, Si—N bonds are replaced with Si—O bonds. According to the above-described conventional method using the SOG composition, not all Si—N bonds are replaced by Si—O bonds. Therefore, even after coating and baking with the SOG solution, some of the Si—N bonds are replaced. Bonds remain in the silicon oxide film. However, according to the method of the present invention, after the SOG film is formed by coating the SOG solution containing polysilazane, the Si—N bond does not remain in the SOG film even after the curing process. Accordingly, the silicon oxide film formed according to various embodiments of the present invention has substantially the same characteristics as a pure silicon oxide film formed by a conventional CVD method.

  In order to convert polysilazane into silicon oxide, the main baking is preferably performed at a temperature of about 400 to 1200 ° C. When the main baking temperature is about 400 ° C. or lower, since the curing is not sufficient, Si—N bonds remain and deteriorate the characteristics of the oxide film. When the main baking temperature is higher than about 1200 ° C., the flatness of the generated silicon oxide film may be reduced or cracks may occur. Therefore, the main baking is performed at a temperature of about 400 to 1200 ° C, preferably about 400 to 1000 ° C.

  In particular, the main baking process is preferably performed for about 10 to 180 minutes. When the main baking process time is shorter than about 10 minutes, the SOG film is not completely converted into the silicon oxide film. On the contrary, when the main baking process time exceeds about 180 minutes, the stress in the generated silicon oxide film increases. Accordingly, the main baking step is preferably performed for about 10 to 180 minutes, more preferably about 30 to 120 minutes.

  The main baking step is performed in an oxidizing atmosphere or an inert atmosphere which is an atmosphere suitable for converting Si—N bonds into Si—O bonds. For example, an oxygen atmosphere, a water vapor atmosphere, a mixed atmosphere of oxygen and water vapor, a nitrogen atmosphere, or a mixed atmosphere of oxygen, water vapor, and nitrogen is useful for the main baking process. In particular, it is preferably performed in a steam atmosphere. The water vapor atmosphere preferably contains 1.2 to 86% by weight of water.

  The main baking temperature is determined in consideration of the influence on the substructure. For example, when the lower structure includes a trench formed by partially etching the upper portion of the semiconductor substrate and an SOG film filling the trench, the main baking temperature is preferably about 900 to 1200 ° C. in the curing stage. When the lower structure part includes a large number of gate electrodes formed on a semiconductor substrate and an SOG film that completely covers the gate electrodes, the temperature of the main baking is preferably about 600 to 900 ° C. When the lower structure includes a number of metal wiring patterns formed on an insulating film on a semiconductor substrate and an SOG film that completely covers the metal wiring patterns, the main baking temperature is preferably about 400 to 450 ° C. A person skilled in the relevant art can determine a suitable temperature for main baking with reference to the present invention, and the present invention is not limited to the specific temperature range described above.

  The SOG composition is coated only once by the method according to the present invention to form a silicon oxide film having a thickness of about 4000 to 6500 mm. In addition, before applying the SOG composition, a silicon nitride film can be formed on the upper and side surfaces of the conductive pattern with a thickness of about 200 to 600 mm as an etching stop film.

  The SOG composition can be used for planarizing gate electrodes and / or metal patterns or filling trenches during the manufacture of semiconductor devices. Alternatively, the SOG composition according to the present invention may be used to fill trenches, and the gate electrode and / or metal pattern may be planarized using conventional SOG compositions or other methods. That is, the SOG composition of the present invention can be applied to fill a trench or planarize a gate electrode and / or a metal pattern, but does not necessarily need to be applied to all of them. It can also be applied to only one of these.

  According to another embodiment of the present invention, the main baking process is performed in a two-stage heat treatment process. When the heat treatment process is performed in one stage, as described with reference to FIG. 1, the silicon oxide is formed on the sidewalls of the trench through the reaction between oxygen contained in the oxidizing atmosphere and the silicon source supplied from the semiconductor substrate. As a result of forming, the dimensions of the active region change. Accordingly, when an SOG film is formed by curing an SOG composition containing polysilazane on a semiconductor substrate supplied with a silicon source, the SOG film is converted into a silicon oxide film by performing heat treatment in two stages. be able to.

  First, a first heat treatment step is performed on the SOG film to convert polysilazane into an oxide. At this time, the first heat treatment step is performed in an oxidizing atmosphere such as an oxygen atmosphere, a water vapor atmosphere, or a mixed atmosphere of oxygen and water vapor at a temperature of about 500 to 1000 ° C., preferably about 600 to 900 ° C. More preferably, the first heat treatment step is performed at a temperature of about 800 to 900 ° C. for about 10 to 120 minutes.

  Thereafter, a second heat treatment step is performed on the oxide obtained through the first heat treatment step in an oxidizing atmosphere, an inert gas atmosphere, a mixed atmosphere of an oxidizing atmosphere and an inert gas atmosphere, or a vacuum atmosphere. Refine the organization. In particular, the second heat treatment step is performed in an inert gas atmosphere containing nitrogen. The second heat treatment step is performed at a temperature of about 600 to 1200 ° C., preferably about 900 to 1100 ° C. for about 10 to 120 minutes.

  Specifically, when the SOG composition is formed so as to fill a trench formed by partially etching the upper portion of the semiconductor substrate, the second heat treatment process of the main baking is performed at a temperature of about 900 to 1000 ° C. Preferably it is done.

The present invention will be described in more detail through the following examples, experimental examples, and comparative examples.
<Example 1>

Production of SOG Composition Perhydropolysilazane on the market was fractionated to obtain perhydropolysilazane having a weight average molecular weight of about 4500 to 7000 and a molecular weight distribution of about 3.0 to 4.0. The fractionated perhydropolysilazane was dissolved in xylene to produce an SOG composition having a perhydropolysilazane concentration of about 22-25% by weight relative to the total weight percent of the composition. As a result of measuring the contact angle of the SOG composition with respect to the silicon nitride film as the base film, a contact angle of 4 ° or less was shown.

  The viscosity of the SOG composition was measured by shear rate. The viscosity characteristics are illustrated in FIG. FIG. 2 is a graph showing changes in viscosity due to changes in the shear rate of the SOG solution. In FIG. 2, the vertical axis represents the viscosity (mPa · s), and the horizontal axis represents the shear rate (1 / s). As can be seen from FIG. 2, the SOG solution has a shear rate of about 1 to 10 mPa · s when the shear rate is about 10 to 1000 (1 / s), preferably about 54 to 420 (1 / s). Has a uniform viscosity.

Formation of Oxide Film FIGS. 3 to 13 are sectional views showing a method of forming a silicon oxide film in a semiconductor manufacturing process according to an embodiment of the present invention.

  Referring to FIG. 3, a p-type substrate 10 made of a semiconductor material such as silicon (Si) is provided. A trench 12 was formed on the substrate 10 by etching the element isolation region. At this time, the trench 12 had a depth of 4600 mm and a width of 1250 mm. A SOG solution containing perhydropolysilazane having a weight average molecular weight of about 6000 to 8000 was applied to the substrate 10 on which the trench 12 was formed to a thickness of about 6000 to 7000 mm to form a first SOG film 13.

  Referring to FIG. 4, the first SOG film 13 is subjected to a preliminary baking process at a temperature of about 100 to 500 ° C. for about 1 to 5 minutes, and then a main baking process is performed at a temperature of about 900 to 1000 ° C. for about 30 minutes. The first SOG film was converted to the first silicon oxide film 13a. At this time, the baking process was performed in a water vapor atmosphere containing about 86% by weight of water.

  Referring to FIG. 5, the first silicon oxide film 13 a is polished by chemical mechanical polishing (CMP) until the upper surface of the semiconductor substrate 10 is exposed, and the inside of the trench 12 is filled with the silicon oxide 14. An element isolation region was formed.

  Referring to FIG. 6, an n-type semiconductor region 20 is formed by ion-implanting an n-type impurity such as phosphorus (P) into the semiconductor substrate 10 in a region where a memory cell is to be formed. A p-type well 30 is formed by ion-implanting a p-type impurity, for example, boron (B), in part of the cell array region and the peripheral circuit region. An n-type well 40 was formed by ion-implanting an n-type impurity such as phosphorus (P) into the remaining part of the peripheral circuit region.

Thereafter, an impurity for adjusting the threshold voltage, for example, BF ₂ (boron fluoride) was ion-implanted into the p-type well 30 and the n-type well 40. Next, each surface portion of the p-type well 30 and the n-type well 40 was cleaned using a hydrofluoric acid-based cleaning solution. The semiconductor substrate 10 was wet oxidized to form a gate oxide film 16 on each surface of the p-type well 30 and the n-type well 40. At this time, the substrate portion in the trench 12 was also partially oxidized, and the gate oxide film 16 was continuously formed. At this time, the thickness of the gate oxide film 16 was about 40 to 200 mm.

  Referring to FIG. 7, a polysilicon film is formed on the substrate 10 on which the silicon oxide 14 and the gate oxide film 16 filling the trench 12 are formed as field oxides. The polysilicon film has a thickness of about 500 to 4000 mm, and a polycrystalline silicon film doped with an n-type impurity such as phosphorus (P) is deposited by a low pressure chemical vapor deposition (LPCVD) method. Formed. Thereafter, tungsten silicide and tungsten were deposited on the polysilicon film by a sputtering method to form a tungsten silicide film having a thickness of about 1000 mm and a tungsten film having a thickness of 2000 mm. A silicon nitride film was laminated on the tungsten film. The silicon nitride film was formed to have a thickness of about 500 to 2000 mm by using low pressure chemical vapor deposition or plasma enhanced chemical vapor deposition (PECVD).

  After forming a photoresist film on the silicon nitride film, the photoresist film was selectively exposed using a mask. Thereafter, the photoresist film was developed to form a photoresist pattern 22 for forming a gate electrode. Using the photoresist pattern 22 as an etching mask, the silicon nitride film, tungsten film, tungsten nitride film, and polysilicon film are sequentially etched to form a polysilicon pattern 24a, a tungsten silicide pattern 24b, a tungsten pattern 24c, and silicon. Gate electrodes and word lines 24Ga, 24Gb, 24Gc, and 24WL constituted by the nitride film pattern 24d were formed. As a result, the gate electrode 24Ga and the word line 24WL were formed in the cell array region, and the gate electrodes 24Gb and 24Gc were formed in the peripheral circuit region, respectively.

  The gap between the gate electrode formed in the cell array region and the word lines 24Ga and 24WL was about 0.4 to 1 μm. In order to form the dense stepped portion in the gap, the aspect ratio, which is the ratio of the height of the gate electrode and the word lines 24Ga and 24WL to the width of the gap, was about 5: 1 to 10: 1. On the other hand, in order to form the global step portion in the gap, the aspect ratio, which is the ratio of the height of the gate electrodes 24Gb and 24Gc formed in the peripheral circuit region to the gap, was 1: 1 or less.

  Referring to FIG. 8, the photoresist pattern 22 is removed. In FIG. 8, a p-type impurity, for example, boron (B) is ion-implanted into the n-type well 40 to form a p-type impurity region 25 in the n-type well 40 on both sides of the gate electrode 24Gc. Further, an n-type impurity, for example, phosphorus (P) is ion-implanted into the p-type well 30 to form n-type impurity regions 27 in the p-type well 30 on both sides of the gate electrode 24Gb, and p-type on both sides of the gate electrode 24Ga. An n-type impurity region 26 is formed in the well 20.

  Referring to FIG. 9, silicon nitride was deposited on the semiconductor substrate 10 by chemical vapor deposition (CVD) to form a silicon nitride film 32 having a thickness of about 200 to 600 mm. Thereafter, the silicon nitride film 32 on the cell array region was covered with a photoresist film, and the silicon nitride film 20 on the peripheral circuit was anisotropically etched to form spacers 32a on the side walls of the gate electrodes 24Gb and 24Gc of the peripheral circuit.

Next, p ⁺ -type impurity regions (source and drain regions) 42 were formed by ion implantation of p-type impurities such as boron into the n-type well 40 of the peripheral circuit. Further, the p-type well 30 of the peripheral circuit, n-type impurity, e.g., arsenic (As) is ion-implanted n ⁺ -type impurity regions (source and drain regions) of the formation of the 44.

  Referring to FIG. 10, the SOG solution is applied on the semiconductor substrate 10 to form the second SOG film 50. The second SOG film 50 was also applied by a spin coating method. At this time, the rotation speed was about 500 to 2500 rpm. The perhydropolysilazane contained in the SOG solution had a weight average molecular weight of about 4000 to 6000. The second SOG film 50 has a thickness of about 7500 to 8200 and is formed so as to completely cover the gate electrode and the word lines 24Ga, 24Gb, 24Gc, and 24WL. Thereafter, the second SOG film 50 was pre-baked at a temperature of about 100 to 500 ° C. for about 1 to 5 minutes, and then main baked at a temperature of about 600 to 900 ° C. for about 10 to 180 minutes. At this time, the baking process was performed in an oxygen atmosphere, a water vapor atmosphere, a mixed atmosphere of water vapor and oxygen, a nitrogen atmosphere, or a mixed atmosphere thereof. If the baking process is performed in a steam atmosphere, the moisture content of the steam atmosphere was adjusted to be about 1.2 to 86% by weight.

  During the curing process, the Si—N bonds of the second SOG film 50 were replaced with Si—O bonds, and the second SOG film was converted to the second silicon oxide film 50a. As a result, as shown in FIG. 11, a second silicon oxide film 50a having a thickness contracted by about 19 to 20% from the thickness of the second SOG film was obtained.

  Referring to FIG. 12, a metal film having a thickness of about 5000 mm was formed on the second silicon oxide film 50a by depositing a metal such as aluminum or tungsten by an ordinary sputtering method. The metal film was patterned by a photolithography process to form a metal layer pattern 52 having a width of 6600 mm and a gap of 8400 mm. Thereafter, a third SOG film 54 having a thickness of about 3800 to 4500 mm was formed so as to completely cover the metal layer pattern 52 by spin coating the SOG solution. In this case, the weight average molecular weight of perhydropolysilazane contained in the third SOG film 54 was about 4500 to 7500.

  Referring to FIG. 13, the third SOG film 54 is pre-baked at a temperature of about 100 to 500 ° C. for about 1 to 5 minutes, and then main baked at a temperature of about 400 to 450 ° C. for about 10 to 180 minutes. The main baking process was performed in a steam atmosphere. Through the curing process, the Si—N bonds of the third SOG film 54 are replaced with Si—O bonds, whereby the third SOG film 54 is converted into a third silicon oxide film 54 a having a flat surface.

  Thereafter, a semiconductor element was manufactured through a normal semiconductor manufacturing process. One skilled in the art will be able to manufacture semiconductor devices through the SOG composition according to the present invention and the methods according to various embodiments of the present invention.

Light Absorption of Silicon Oxide Film An oxide film was formed on the semiconductor substrate by the method described with reference to FIGS. The oxide film was formed on a substrate having a large number of wiring layers having an aspect ratio of about 5: 1 to 10: 1 and a gap of about 0.04 to 1 μm between the wiring layers. A silicon nitride film having a thickness of about 400 mm was formed while covering the numerous metal wiring layers and the semiconductor substrate.

  A SOG solution containing polysilazane was spin-coated on a semiconductor substrate to form a second SOG film having a thickness of about 7582 mm. At this time, the rotation speed was about 1000 rpm.

  The second SOG film was pre-baked at 150 ° C. for 3 minutes, and then the light absorption of the SOG film was measured using an FT-IR method (Fourier Transform InfraRed method).

FIG. 14 is an FT-IR chart showing the light absorbance measured after pre-baking the SOG film. As shown in FIG. 14, after preliminary baking, the highest point of light absorption was shown in a number of wavenumber regions indicating bonds such as N—H, Si—H, Si—N, and Si—H. At this time, the stress measured with a stress meter was about 3.63 × 10 ⁸ (dyne / cm ² ).

Further, after the SOG film was pre-baked, it was further baked at 700 ° C. for 30 minutes to convert it into a silicon oxide film. FIG. 15 is an FT-IR chart showing the light absorption of the silicon oxide film according to the wave number and weight average molecular weight measured after the SOG film was mainly baked. Referring to FIG. 15, only the highest point in the wave number region corresponding to the Si—O bond remained after the main baking. At this time, the stress was -1.22 × 10 ⁸ (dyne / cm ² ). FIG. 15 shows that the Si—N bonds of all the SOG films are replaced with Si—O bonds, which confirms that the spin-on glass film has been completely converted into a silicon oxide film.

  In addition, any void is found in the silicon oxide film formed on the surface of the semiconductor substrate having a large number of wiring patterns having an aspect ratio of about 5: 1 to 10: 1 and a gap of about 0.04 to 1 μm. There wasn't.

Measurement of etching rate of silicon oxide film Formation of Silicon Oxide Film Using SOG Composition An SOG film was formed by applying an SOG solution onto a bare wafer. The SOG solution was applied by a spin coating method, and the rotation speed was 1000 rpm. The SOG film was formed to have a thickness of about 7500-8200 mm. Thereafter, the SOG film was pre-baked at a temperature of about 150 ° C. for 3 minutes, and then main baked at a temperature of about 700 ° C. for about 30 minutes. At this time, the main baking was performed in a steam atmosphere having a moisture content of about 1.2 to 86% by weight. Through the curing process, Si—N bonds of the SOG film were replaced with Si—O bonds, and the SOG film was converted into a silicon oxide film. The thickness of the oxide film formed at this time was 6400 mm.

B. Formation of Oxide Film by CVD Method A high density plasma CVD-oxide film was formed on a bare wafer using silane gas and oxygen as source gases and argon gas as carrier gas. The thickness of the CVD-oxide film formed at this time was about 6000 mm.

C. Wet etching rate measurement The silicon oxide film formed by the present invention and the CVD-oxide film formed by the CVD method were respectively etched. Each wet etching process was performed using the same etching solution for a certain time, and the etching rate was examined at a certain time interval. The results are shown in FIGS. 16 to 21.

FIG. 16 is a graph showing the results of measuring the etching rate of the oxide film formed according to the present invention and the oxide film formed by the CVD method at intervals of 1 minute. The wet etching is performed at room temperature (25 ° C.) using a solution obtained by diluting a buffer etching solution containing ammonium fluoride in distilled water (NH ₄ F and HF diluted in dispersed water). It was.

  FIG. 17 is a graph showing the results of measuring the etching rate of the oxide film formed according to the present invention and the oxide film formed by the CVD method at intervals of 1 minute. Wet etching was performed at room temperature (25 ° C.) using an aqueous solution diluted with hydrofluoric acid (distilled water: hydrofluoric acid (HF) = 100: 1).

FIG. 18 is a graph showing the results of investigating the etching rate of the oxide film formed according to the present invention and the oxide film formed by the CVD method at intervals of 10 minutes. The wet etching is performed at 70 ° C. using an etching solution in which ammonium hydroxide (NH ₄ OH), hydrogen peroxide (H ₂ O ₂ ), and water (H ₂ O) are mixed at a ratio of 0.25: 1: 5. At a temperature of

  FIG. 19 is a graph showing the results of examining the etching rate of the oxide film formed according to the present invention and the oxide film formed by the CVD method at intervals of 10 minutes. The wet etching was performed at a temperature of 165 ° C. using phosphoric acid.

  FIG. 20 is a graph showing the results of examining the etching rate of the oxide film formed according to the present invention and the oxide film formed by the CVD method at intervals of 10 minutes. The wet etching was performed at a temperature of 130 ° C. using an etching solution in which sulfuric acid and hydrogen peroxide were mixed at a ratio of about 6: 1.

FIG. 21 is a graph showing the results of examining the etching rate of the oxide film formed according to the present invention and the oxide film formed by the CVD method at intervals of 10 minutes. Wet etching is performed at 50 ° C. using an etching solution in which ammonium hydroxide (NH ₄ OH), hydrogen peroxide (H ₂ O ₂ ), and water (H ₂ O) are mixed at a ratio of 0.25: 1: 5. At a temperature of

D. Investigation of Dry Etching Rate The oxide film formed according to the present invention and the oxide film formed by the CVD method were introduced into the same chamber, and the etching rate was repeatedly investigated using the same etching gas. The pressure in the chamber was adjusted to 30 mTorr, and the output voltage was adjusted to 1700 W. The etching gas is octafluoropentene (C ₅ F ₈ ), octafluorobutene (C ₄ F ₈ ), oxygen (O ₂ ), and argon (Ar) at flow rates of 8 sccm, 4 sccm, 6 sccm, and 500 sccm, respectively. The investigation results of the etching rate are shown in a graph in FIG.

  16 to 22, the wet etching rate and the dry etching rate of the silicon oxide film formed according to the present invention are very similar to the wet etching rate and the dry etching rate of the silicon oxide film formed by the normal CVD method. I understand that. Therefore, the interlayer insulating film and the planarized film formed using the SOG film according to the present invention have characteristics similar to those of a normal CVD-oxide film.

Through repeated experiments by the inventor, there is no void using a SOG composition according to the present invention on a wiring layer having an aspect ratio of about 5: 1 to 10: 1 and a semiconductor substrate having a gap of about 0.04 to 1 μm. An oxide film could be formed. According to the present invention, a silicon oxide film having flatness required for 256M DRAM and free from voids can be formed using the SOG composition.
<Example 2>

Production of SOG Composition A perhydropolysilazane having a weight average molecular weight of about 6000 to 8000 and a molecular weight distribution of about 3.0 to 4.0 was produced using the same method as in Example 1. The perhydropolysilazane was dissolved in xylene at a concentration of about 22 to 25% by weight to prepare an SOG composition.

When the field oxide film shown in FIGS. 3 to 13 is formed by shallow trench isolation example 1 to fill the trench of the highly integrated semiconductor device, a thick oxide film is formed on the inner wall of the trench as shown in FIG. It is formed.

  23 to 29 are cross-sectional views illustrating a shallow trench isolation method according to another embodiment of the present invention.

  Referring to FIG. 23, a thermal oxidation process is performed on a semiconductor substrate including silicon to form a pad oxide film 201 having a thickness of about 100 to 200 mm. Thereafter, a nitride having a thickness of about 100 to 1000 mm was deposited on the pad oxide film 201 using a low pressure chemical vapor deposition (LPCVD) method to form a polishing stopper film 203. The polishing stopper film 203 was formed to prevent polishing in the subsequent CMP process.

  Thereafter, a high temperature oxide (HTO) having a thickness of about 500 to 1000 mm was deposited on the polishing stopper film 203 using an LPCVD method to form a hard mask film 205. Silicon nitride oxide (SiON) was deposited on the hard mask film 205 to a thickness of about 200 to 800 mm by the LPCVD method to form an antireflection film (not shown). The antireflection film prevents scattered light when performing a photolithography process, and is removed in a subsequent process of forming a trench.

  Referring to FIG. 24, a hard mask pattern 206 for forming an active pattern is formed by dry etching the antireflection film and the hard mask film 205 through a photolithography process. Thereafter, the polishing stopper film 203 and the pad oxide film 201 were etched using the hard mask pattern 206 as an etching mask, thereby forming an etching stopper film pattern 204 and a pad oxide film pattern 202.

  Referring to FIG. 25, the trench 210 is formed by etching the exposed portion of the substrate 200 to a depth of about 2000 to 5000 mm using the hard mask pattern 206. The trench 210 preferably has a depth of 4600 inches and a width of 1250 inches. At this time, the antireflection film was removed, and the hard mask pattern 206 was etched to have a certain thickness.

  Referring to FIG. 26, the exposed portion of the trench 210 was heat-treated in an oxidizing atmosphere in order to cure silicon damage generated on the semiconductor substrate 200 by high energy ion implantation during the trench etching process. Thereafter, a trench inner wall oxide film 212 having a thickness of about 20 to 300 mm was formed on the inner wall of the trench 210 including the bottom and side surfaces of the trench 210 through an oxidation reaction between the exposed silicon and an oxidizing agent.

  After the trench inner wall oxide film 212 was formed as described above, the trench 210 was filled with an SOG composition to form an SOG film 213 having a thickness of about 6000 to 7000 mm.

  Referring to FIG. 27, after the SOG film 213 is pre-baked at a temperature of about 100 to 500 ° C. for about 1 to 5 minutes, it is about 800 to 900 ° C., preferably about 850 ° C. for about 10 to 120 minutes. Preferably, the first heat treatment step is further performed for about 60 minutes to convert the SOG film 213 into a silicon oxide film. At this time, the first heat treatment step was performed in a steam atmosphere containing 86% by weight of water.

  Thereafter, a second heat treatment step was performed to convert the converted silicon oxide into a silicon oxide film 214 by densification. The second heat treatment step was performed in an oxidizing atmosphere, an inert gas atmosphere, or a mixed atmosphere thereof, preferably in an inert gas atmosphere such as a nitrogen gas atmosphere. The second heat treatment step was performed at a temperature of about 900 to 1100 ° C., preferably about 1000 ° C., for about 10 to 120 minutes, preferably about 30 minutes.

  Referring to FIG. 28, the silicon oxide film 214 is polished until the polishing stopper film 204 on the semiconductor substrate 200 is exposed by the CMP process, and the trench 210 is filled with the silicon oxide 216.

  Referring to FIG. 29, the isolation process is completed as shown in FIG. 29 by removing the polishing stopper film pattern 204 by performing a stripping process using phosphoric acid.

Substrate oxide formation investigation
Experimental example 1
After an SOG film was formed on a blanket wafer by the same method as in Example 1, a preliminary baking process and a main baking process were performed.

Experimental example 2
After forming the SOG film on the blanket wafer by the same method as in Example 2, the preliminary baking step, the first heat treatment step for 1 hour in the water vapor atmosphere at 850 ° C., and the second heat treatment step for 30 minutes in the oxygen atmosphere at 1000 ° C. A silicon oxide film was formed.

Experimental example 3
A silicon oxide film was formed by the same method as in Experimental Example 2 except that the second heat treatment step was performed in a nitrogen gas atmosphere.

Experimental Example 4
A silicon oxide film was formed by the same method as in Experimental Example 2 except that the second heat treatment step was performed at 1050 ° C.

Experimental Example 5
A silicon oxide film was formed by the same method as in Experimental Example 2 except that the first heat treatment step was performed at 900 ° C.

FT-IR analysis on the stretching peak of the Si—O bond on the substrate surface was performed on the wafer subjected to the baking process in Experimental Example 1 to Experimental Example 5 for examining the oxidation state of the substrate surface.

  FIG. 30 is a bar graph showing normalized light absorption and intensity obtained by performing FT-IR analysis on silicon oxide formed in the active region of the substrate according to the present invention. From FIG. 30, the silicon oxide film obtained by performing the two-stage heat treatment process as in Experimental Examples 2 to 5 is compared with the silicon oxide film obtained through the one-stage heat treatment process as in Experimental Example 1. It can be seen that it contains a larger amount of oxide. It can also be confirmed that among the oxides formed from the substrates in Experimental Examples 2 to 5, the amount of oxide formed in Experimental Example 3 is the smallest.

Investigation of wet etching rate and etching uniformity Silicon oxide film formed by converting the SOG composition according to Experimental Example 2 to Experimental Example 4 and silicon formed by high-density plasma chemical vapor deposition (HDP-CVD) The etching rate according to the kind of the etching solution of the oxide film was investigated. Wet etching was performed for a certain period of time using the same etching solution, and the etching rate was investigated at regular time intervals. As the etching solution, SC-1 solution (a mixture of ammonia, hydrogen peroxide, and deionized water), an LAL solution (a mixture of ammonium fluoride and hydrogen fluoride), and a phosphoric acid solution were used. The results are shown graphically in FIG. 31, in which the vertical axis indicates the etching rate and the horizontal axis indicates the etching solution and the type of etched oxide.

  From FIG. 31, it can be seen that the silicon oxide films formed from Experimental Example 2 to Experimental Example 5 have an etching rate similar to that of the silicon oxide film generated from Experimental Example 1.

Example 2 Using a silicon oxide film formed by a polishing test high-density plasma chemical vapor deposition method and a silicon oxide film formed by Example 2 (the baking process was performed as in Experimental Example 3) After filling the trench of the semiconductor substrate having the same pattern as described in 1., a chemical mechanical polishing process was performed. The polishing process was performed until the polishing stopper film was exposed, and the profile of the oxide film was inspected to investigate the polishing uniformity. The result is illustrated in FIG.

  In FIG. 32, the graphs show the result after polishing the silicon oxide film formed by the high-density plasma chemical vapor deposition method and the result after polishing the silicon oxide film formed by Experimental Example 3, respectively. During polishing, the same silicon dioxide used for slurry production was used. In FIG. 32, the vertical axis indicates the degree of polishing after the polishing is completed (unit: Å). At this time, the polishing process is performed for about 180 to 200 seconds for the silicon oxide film formed by the high-density plasma chemical vapor deposition method, and for about 100 seconds for the silicon oxide film formed by Experimental Example 3. went. As shown in FIG. 32, the polishing amount of the silicon oxide film formed by the high-density plasma chemical vapor deposition method was about 300 to 500 mm, whereas the polishing amount of the silicon oxide film formed in Experimental Example 3 was It was about 100-200cm.

  From FIG. 32, the polishing uniformity of the silicon oxide film formed according to Example 2 is about twice as good as the polishing uniformity of the silicon oxide film formed by a normal high-density plasma chemical vapor deposition method. It can be confirmed that the polishing time of the silicon oxide film formed by Example 2 is about half of the polishing time of the silicon oxide film formed by the normal high-density plasma chemical vapor deposition method.

  In addition, the silicon oxide film formed according to Example 2 has no voids and has excellent gap filling characteristics. On the other hand, the oxide film formed by the high-density plasma chemical vapor deposition method has many in the trench portion. Had voids. Furthermore, silicon in the active region is not oxidized, and an oxide film is densely formed at the bottom of the trench, so that it has excellent oxide film characteristics.

  FIG. 33 is a flowchart illustrating a method of forming an oxide film using an SOG composition according to an embodiment of the present invention. Referring to FIG. 33, after forming an SOG film by applying an SOG composition on a substrate in step S100, an oxide film can be formed by curing the SOG film in steps S210 and S220.

  In step S100, the SOG composition having a flat surface can be formed on the substrate by applying the SOG composition onto the semiconductor substrate having the stepped portion. The step portion may be formed by at least two conductive patterns formed on the substrate. For example, the conductive pattern may include a metal conductive wiring pattern such as a gate electrode pattern and / or a bit line pattern.

  In steps S210 and S220, the SOG film is cured to convert the SOG film into a flat silicon oxide film. The curing process can be performed in a preliminary baking process and a main baking process. The preliminary baking process (step S210) can be performed at a temperature of about 100 to 500 ° C, while the main baking process (step S220) can be performed at a temperature of about 400 to 1200 ° C.

  If the preliminary baking process (step S210) is performed at a temperature lower than about 100 ° C., the organic solvent may remain in the silicon oxide film. When it is performed at a temperature of about 500 ° C. or higher, there is a possibility that the perhydropolysilazane may not be completely converted into silicon oxide in the subsequent main baking process, and the surface portion of the SOG film is rapidly converted into silicon oxide and cracks are generated. By doing so, non-uniformity of the silicon oxide film can be caused.

  If the pre-baking step (S210) is performed within 1 minute, the organic solvent may remain in the film. If it is performed over 5 minutes, the perhydropolysilazane may be removed even if the organic solvent is completely removed. Partial conversion to silicon oxide may occur on the surface of the SOG film containing, resulting in partial cracking. Therefore, the preliminary baking step is performed at a temperature of about 100 to 500 ° C., preferably about 100 to 400 ° C. for about 1 to 5 minutes, preferably about 2 to 3 minutes.

  The preliminary baking step (step S210) can be performed in an oxygen atmosphere, a water vapor atmosphere, a mixed atmosphere of oxygen and water vapor, a nitrogen atmosphere, or a vacuum atmosphere, and is preferably performed in a water vapor atmosphere.

  The main baking process (step S220) is preferably performed at a high temperature for a long time with respect to the preliminary baking process (step S210). The basic structure of perhydropolysilazane-based SOG includes Si—N bonds, and such Si—N bonds are replaced with Si—O bonds when baked in an atmosphere containing oxygen and water. According to the usual method using an SOG composition, generally not all Si—N bonds are replaced by Si—O bonds. However, when an SOG film is formed by coating with an SOG solution containing perhydropolysilazane according to an embodiment of the present invention and then a curing step is performed, no Si-N bonds are left.

  Preferably, the main baking process (step S220) is performed at a temperature of about 400 to 1200 ° C. If the temperature of the main baking is less than about 400 ° C., some Si—N bonds may remain, which may adversely affect the characteristics of the oxide film. When the temperature is higher than 1200 ° C., the flatness of the generated silicon oxide film is lowered or cracks are generated, which is not preferable. Therefore, the main baking (step S220) is performed at a temperature of about 400 to 1200 ° C, preferably about 400 to 1000 ° C.

  The main baking process (step S220) is performed for about 10 to 180 minutes, preferably about 30 to 120 minutes. If the execution time of the main baking process (step S220) is shorter than about 10 minutes, it is not preferable because the SOG film is not sufficiently converted to a silicon oxide film. The stress of the silicon oxide film to be increased is not preferable.

  The main baking process (step S220) is performed in an oxidizing atmosphere and / or an inert atmosphere, which is an atmosphere suitable for converting Si—N bonds into Si—O bonds. For example, the main baking process (Step S220) can be performed in an oxygen atmosphere, a water vapor atmosphere, a mixed atmosphere of oxygen and water vapor, a nitrogen atmosphere, or a vacuum atmosphere. In particular, it is preferably carried out in a steam atmosphere, and in this case, the water content is preferably maintained at about 1.2 to 86% by weight.

  By the method according to the present invention, a silicon oxide film having a thickness of about 1000 to 10000 mm is formed in one step using the SOG composition. When the silicon oxide film has a thickness within the above range, the silicon oxide film can sufficiently cover a conductive layer such as a gate electrode and a metal pattern which are economically lower structures. Before applying the SOG composition, a silicon nitride film having a thickness of about 200 to 600 mm may be formed on the upper and side surfaces of the conductive layer pattern as an etching stop film.

  FIG. 34 is a graph illustrating the FT-IR result according to the temperature of the main baking process (when the water vapor content is 80% by weight) according to an embodiment of the present invention. As shown in FIG. 34, it can be confirmed that all the bonds of perhydropolysilazane were effectively substituted with Si—O bonds.

  FIG. 35 is a graph illustrating the FT-IR result according to the temperature of the main baking process (when the water vapor content is 10 wt% or less) according to an embodiment of the present invention. As shown in FIG. 35, when the main baking process is performed in an atmosphere containing water having a water content of 10% by weight or less, the Si—O bond is more effectively replaced as the temperature of the main baking increases. Can be confirmed. The main baking step can be performed in a mixed atmosphere of oxygen and water vapor that exists in an inert atmosphere such as nitrogen. Si—N bonds, Si—H bonds, and N—H bonds are all replaced with Si—O bonds in a water vapor atmosphere. The water content in the water vapor atmosphere is about 1.2 to 86% by weight, and the lower the main baking temperature, the more water is required.

FIG. 36 is a graph showing FT-IR results by main baking according to an embodiment of the present invention. As shown in FIG. 36, when the main baking process is performed in a water vapor atmosphere, Si—N bonds, Si—H bonds, and N—H bonds are more effectively replaced with Si—O bonds, compared with the case where the main baking process is performed in a nitrogen atmosphere. Can be confirmed.
<Example 3>

Production of spin-on glass composition Perhydropolysilazane on the market was fractionated to obtain perhydropolysilazane having a weight average molecular weight of about 3000 to 6000. The molecular weight distribution of perhydropolysilazane was about 2.5 to 3.5. The produced perhydropolysilazane was dissolved in xylene at a concentration of about 20 to 30% by weight to prepare an SOG composition. The SOG composition showed a contact angle of 4 ° or less as a result of measuring the contact angle with the silicon nitride film as the underlayer.

The viscosity of the produced SOG composition was measured at various shear rates. In this case, the SOG composition exhibited a constant viscosity within the range of about 1.54 to 1.70 cP.
<Example 4>

Perhydropolysilazane having a weight average molecular weight of 3000 was obtained by the production fractionation method of the SOG composition . The molecular weight distribution of the obtained perhydropolysilazane was 2.8. This is shown in Table 1 below and FIG. The prepared perhydropolysilazane was dissolved in dibutyl ether at a concentration of 22.6% by weight to prepare an SOG composition. The viscosity and solid content concentration of the produced SOG composition are shown in Table 1, FIG. 37, FIG. 38, and FIG.

FIG. 37 is a graph showing the molecular weight distribution of the SOG composition according to the weight average molecular weight (Mw) according to an embodiment of the present invention. FIG. 38 is a graph showing the viscosity of the SOG composition according to weight average molecular weight (Mw) according to an embodiment of the present invention. FIG. 39 is a graph showing the solid content concentration (% by weight) of the SOG composition according to the weight average molecular weight (Mw) according to an embodiment of the present invention. Further, the obtained SOG composition exhibited a contact angle of 4 ° or less with respect to the silicon nitride film as a base film.
<Example 5 to Example 7>

Production of SOG Composition The SOG composition is produced in the same manner as in Example 4 except that the weight average molecular weight is changed. According to each example, perhydropolysilazane having a weight average molecular weight of 3500 (Example 5), 4500 (Example 6), and 5500 (Example 7) is used. The viscosity and solid concentration of the SOG composition according to each example are shown in Table 1 below, FIG. 37, FIG. 38, and FIG.
<Comparative Example 1>

Production of SOG Composition An SOG composition was produced in the same manner as in Example 4 except that perhydropolysilazane having a weight average molecular weight of 8000 was used. The viscosity and solid concentration of the SOG composition according to Comparative Example 1 are shown in Table 1 below, FIG. 37, FIG. 38, and FIG.

＜実施例８＞

<Example 8>

Formation of Oxide Film FIGS. 40 to 50 are sectional views for explaining a method of forming an oxide film in a semiconductor manufacturing process according to another embodiment of the present invention. Referring to FIG. 40, a p-type substrate 10 made of a semiconductor material such as silicon (Si) was prepared. A trench 12 was formed on the substrate 10 by etching the element isolation region. At this time, the trench 12 had a depth of 4600 mm and a width of 1250 mm. An SOG solution containing perhydropolysilazane having a weight average molecular weight of about 3000 to 6000 (for example, 3000) is applied to the substrate 10 on which the trench 12 is formed to a thickness of about 6000 to 7000 (for example, 6000). Thus, the first SOG film 13 was formed.

  Referring to FIG. 41, the first SOG film 13 is pre-baked on a hot plate at about 100 to 500 ° C. (eg, 300 ° C.) for 1 to 5 minutes, and then about 900 to 1000 ° C. (eg, about 950 ° C. The main baking process was performed for 30 minutes at a temperature of) to convert the first silicon oxide film 13a. At this time, the baking process was performed in a water vapor atmosphere containing about 86% by weight of water.

  Referring to FIG. 42, the obtained first silicon oxide film 13a is polished by chemical mechanical polishing (CMP) until the upper surface of the semiconductor substrate 10 is exposed, and as shown in FIG. An element isolation region filled with silicon oxide 14 was formed.

  Referring to FIG. 43, an n-type impurity, for example, phosphorus (P) is implanted into a semiconductor substrate 10 in a memory cell forming region (cell array region) to form an n-type semiconductor region 20, and the cell array region and peripheral circuit are formed. A p-type impurity, for example, boron (B) is ion-implanted into a part of the region to form a p-type well 30, and an n-type impurity, for example, phosphorus (P) is implanted into the remaining part of the peripheral circuit region. Thus, an n-type well 40 was formed.

Thereafter, an impurity for adjusting the threshold voltage, for example, boron fluoride (BF ₂ ) was ion-implanted into the p-type well 30 and the n-type well 40. Next, after cleaning each surface portion of the p-type well 30 and the n-type well 40 using a hydrofluoric acid-based cleaning solution, the semiconductor substrate 10 is wet-oxidized to form each surface portion of the p-type well 30 and the n-type well 40. A gate oxide film 16 was formed. At this time, a part of the substrate on the inner surface portion of the trench 12 was also partially oxidized to form the gate oxide film 16 continuously. At this time, the thickness of the gate oxide film 16 was about 40 to 120 mm (for example, 120 mm).

  Referring to FIG. 44, the upper portion of the substrate 10 on which the silicon oxide 14 buried in the trench 12 as the field oxide film and the gate oxide film 16 are formed is doped with an n-type impurity such as phosphorus (P). A crystalline silicon film was deposited by a low pressure chemical vapor deposition (LPCVD) method to form a polysilicon film having a thickness of about 500 to 4000 mm (for example, 2300 mm). Thereafter, a tungsten silicide film and a tungsten film were formed on the polysilicon film by a sputtering method so as to have a thickness of about 1000 to 2000 mm, respectively, and then a silicon nitride film was formed on the tungsten film. The silicon nitride film is formed to have a thickness of about 500 to 2000 mm (for example, 1000 mm) by using low pressure chemical vapor deposition or plasma enhanced chemical vapor deposition (PECVD).

  After forming a photoresist film on the silicon nitride film, the photoresist film was selectively exposed using a mask. Thereafter, the photoresist film was developed to form a photoresist pattern 22 for forming a gate electrode. Using the photoresist pattern 22 as an etching mask, the silicon nitride film, tungsten film, tungsten nitride film, and polysilicon film are sequentially etched to form a polysilicon pattern 24a, a tungsten silicide pattern 24b, a tungsten pattern 24Gc, and Gate electrodes and word lines 24Ga, 24Gb, 24Gc, and 24WL constituted by the silicon nitride film pattern 24d were formed. Then, as shown in the figure, it can be confirmed that the gate electrode 24Ga and the word line 24WL are formed in the cell array region, and the gate electrodes 24Gb and 24Gc are formed in the peripheral circuit region, respectively.

  The gap between the gate electrode formed in the cell array region and the word lines 24Ga and 24WL was about 0.4 to 1 μm. In order to form the dense stepped portion, the aspect ratio, which is the ratio of the depth to the gap between the gate electrode and the word lines 24Ga and 24WL, was about 5: 1 to 10: 1. In order to form the global stepped portion, the gate electrodes 24Gb and 24Gc formed in the peripheral circuit region had an aspect ratio of 1: 1 or less.

  Referring to FIG. 44, the photoresist pattern 22 is removed. 45, a p-type impurity, for example, boron (B) is ion-implanted into the n-type well 20 to form a p-type impurity region 25 in the n-type well 40 on both sides of the gate electrode 24Gc. Further, an n-type impurity, for example, phosphorus (P) is ion-implanted into the p-type well 30 to form n-type impurity regions 27 in the p-type well 30 on both sides of the gate electrode 24Gb, and p-type on both sides of the gate electrode 24Ga. An n-type impurity region 26 is formed in the well 20.

  Referring to FIG. 46, silicon nitride was deposited on the semiconductor substrate 10 by chemical vapor deposition to form a silicon nitride film 32 having a thickness of about 200 to 600 mm. Thereafter, the silicon nitride film 32 in the cell array region was covered with a photoresist film, and the silicon nitride film 32 in the peripheral circuit region was anisotropically etched to form spacers 32a on the side walls of the gate electrodes 24Gb and 24Gc in the peripheral circuit.

Thereafter, a p-type impurity, for example, boron was ion-implanted into the n-type well 40 of the peripheral circuit to form p ⁺ -type impurity regions (source and drain regions). Also, n ⁺ -type impurity regions (source and drain regions) were formed by ion-implanting n-type impurities such as arsenic (As) into the p-type well 30 of the peripheral circuit.

  Referring to FIG. 47, the SOG composition is applied on the semiconductor substrate 10 to form the second SOG film 50. The second SOG film 50 is also applied by a spin coating method. At this time, the rotation speed was about 500 to 2500 rpm (for example, 1000 rpm). The weight average molecular weight of perhydropolysilazane contained in the SOG solution is about 3000 to 6000 (for example, 3000), and the second SOG film 50 has a thickness of about 7500 to 8200 (for example, 7900). The gate electrode and the word lines 24Ga, 24Gb, 24Gc, and 24WL are completely covered.

  Thereafter, the second SOG film 50 is pre-baked in air having a temperature of about 100 to 500 ° C. (for example, 150 ° C.), and then about 10 to 10 in a steam atmosphere having a temperature of about 600 to 900 ° C. (for example, 700 ° C.). Main baked for 180 minutes (eg, 30 minutes). At this time, the preliminary baking and the main baking can be performed in any one of an oxygen atmosphere, a water vapor atmosphere, a mixed atmosphere of oxygen and water vapor, a nitrogen atmosphere, or a mixed atmosphere of oxygen, water vapor, and nitrogen. If the baking process is performed in a steam atmosphere, the water content is preferably maintained in the range of about 1.2 to 86% by weight (for example, 86% by weight).

  Through the above-described curing process, the Si—N bonds of the second SOG film 50 are replaced with Si—O bonds and converted into silicon oxide films. As a result, as shown in FIG. 48, the second silicon oxide film 50a having a thickness contracted to about 19 to 23% (for example, 22.1%) with respect to the thickness of the second SOG film was obtained. .

  Referring to FIG. 49, a metal layer having a thickness of 5000 mm is formed on the second silicon oxide film 50a by depositing a metal such as aluminum or tungsten by a conventional sputtering method. The metal layer was patterned by a photolithography process to form a metal layer pattern 52 having a width of 6600 mm and a gap of 8400 mm.

  Thereafter, a SOG solution was spin-coated to form a third SOG film 54 having a thickness of about 3800 to 4500 mm (for example, 4200 mm) so as to completely cover the metal layer pattern 52. In this case, the weight average molecular weight of perhydropolysilazane contained in the third SOG film 54 was about 3000 to 6000 (for example, 3000).

  Referring to FIG. 50, after the third SOG film 54 is pre-baked in air at a temperature of about 100 to 500 ° C. (eg, 150 ° C.) for about 1 to 5 minutes (eg, 3 minutes), Main baking at a temperature of 450 ° C. (eg, 400 ° C.) for about 10-180 minutes (eg, 30 minutes). At this time, the main baking is performed in a steam atmosphere. Then, the Si—N bond of the third SOG film 54 is replaced with the Si—O bond through the curing process, and converted to the third silicon oxide film 54 a having a flat surface.

Thereafter, a semiconductor element was completed through a normal semiconductor manufacturing process. Those skilled in the art will be able to manufacture semiconductor devices using the SOG composition through methods according to various embodiments of the present invention.
<Example 9 to Example 11>

Production of SOG Composition A silicon oxide film and a semiconductor device were produced using an SOG composition different from the SOG composition prepared in Example 4. More specifically, in Examples 9 to 11, a silicon oxide film and a semiconductor device were manufactured using the SOG compositions manufactured in Examples 5 to 7, respectively.
<Comparative example 2>

Production of SOG Composition A silicon oxide film and a semiconductor device were produced by the method of Example 8 using the SOG composition prepared in Comparative Example 1 instead of the SOG composition produced in Example 4.

Investigation of substrate oxide formation
Experimental Example 6 (number of particles of SOG composition)
The number of particles exceeding 0.3 to 0.5 μm and exceeding 0.5 μm in 1 cc of the SOG composition produced by Examples 4 to 7 and Comparative Example 1 was measured, and the results are shown in Table 2 and FIG. It was shown to. FIG. 51 is a graph showing the number (particles / cc) of particles according to weight average molecular weight (Mw) according to an embodiment of the present invention. In this case, the number of particles was observed before the SOG composition was cured. There were a similar number of liquid phase particles.

Experimental Example 7 (light absorption)
The light absorptivity of the second SOG film 50 and the second silicon oxide film 50a according to the eighth embodiment illustrated in FIG. 48 was measured by the FT-IR method. The light absorbance was measured after depositing the SOG composition and subsequently performing a pre-baking step at about 150 ° C. for 3 minutes. Typical chemical composition of perhydropolysilazane _{is (SiH} 2 _{NH) n.} When a heat treatment step is performed in an oxygen or water vapor atmosphere, the Si—N bond, Si—H bond, and N—H bond contained in the SOG composition are separated, and all the bonds are replaced with Si—O bonds.

The changes in the FT-IR spectrum depending on the curing temperature and molecular weight are shown in FIGS. FIG. 52 is a graph showing the optical absorptance (au) according to the wave number (cm ⁻¹ ) measured after the preliminary baking according to one embodiment of the present invention, and FIG. It is a graph which shows the light absorptivity (au) by the weight average molecular weight (Mw) and wave number (cm < ^-1 >) which were measured after baking.

From FIG. 52, it can be confirmed that the N—H bond, the Si—H bond, and the Si—N bond substantially remain even after the preliminary baking. Referring to FIG. 52, absorption peaks showing N—H bonds, Si—H bonds, and Si—N bonds in a wave number range of 400 to 4000 cm ⁻¹ can be confirmed.

  Further, the pre-baked SOG film was further baked at 700 ° C. for 30 minutes to convert the silicon oxide film, and the light absorption was measured by FT-IR. As shown in FIG. 53, the absorption peak of N—H bond, Si—H bond, and Si—N bond disappears in the main baking stage, and only the absorbance peak of Si—O bond is shown. According to this, it can be confirmed that the Si—N bonds, Si—H bonds, and N—H bonds contained in the polysilazane-based SOG film are all replaced with Si—O bonds after the main baking process. .

  The same experimental method was used for Examples 9 to 11 and Comparative Example 2, and the results are shown in FIG. 52 and FIG. According to this result, it can be confirmed that an excellent characteristic as an interlayer insulating film is exhibited regardless of the weight average molecular weight of the test object.

Experimental Example 8 (silicon oxide film thickness and shrinkage)
The thickness of the oxide film after the preliminary baking and the main baking was measured for the same SOG film and the same silicon oxide film as those of the experimental example 7, and the shrinkage rate was calculated. The results are shown in Table 3 and FIG. It was shown to. FIG. 54 is a graph showing thickness and shrinkage ratio according to weight average molecular weight after preliminary baking and main baking according to an embodiment of the present invention.

Here, the shrinkage rate is calculated by the following formula 1.
[Formula 1]
Shrinkage rate = [Thickness of SOG film after preliminary baking−Thickness of SOG film after main baking] / [Thickness of SOG film after preliminary baking] × 100

  The same experiment was performed on Examples 9 to 11 and Comparative Example 2 in the same manner, and the results are shown in Table 3 and FIG. As can be seen from Table 3 below and FIG. 54, the thickness and shrinkage of the polysilazane SOG film showed the same behavior regardless of the weight average molecular weight.

Experimental Example 9 (Wafer non-uniformity)
With respect to the same SOG film as in Experimental Example 8 and the same silicon oxide film, the in-wafer non-uniformity (WIWNU) after preliminary baking and main baking was measured, and the results are shown in Table 4 and This is shown in FIG. The same experiment was performed on Examples 9 to 11 and Comparative Example 2 in the same manner, and the results are shown in Table 4 below and FIG. FIG. 55 is a graph showing WIWNU according to weight average molecular weight according to an embodiment of the present invention. As can be seen from Table 4 below and FIG. 55, after pre-baking and main baking, the WIWNU of the film showed a very good value of less than 2.5% regardless of the weight average molecular weight.

Experimental Example 10 (Normalized number of particles and scratch number of silicon oxide film)
For the same SOG composition as in Experimental Example 8 and the same silicon oxide film, the number of normalized particles and the number of scratches in the silicon oxide film after preliminary baking and main baking were measured. The results are shown in Table 5 below and FIG. In the same way, the same experiment was performed on Examples 9 to 11 and Comparative Example 2, and the results are shown in Table 5 and FIG. FIG. 54 is a graph showing normalized particles and the number of scratches according to the weight average molecular weight according to an embodiment of the present invention. At this time, the standard for normalizing the number of particles was when the molecular weight was 4500.

  As can be seen from Table 5 and FIG. 56, the smallest number of particles and scratches in the oxide film were measured when the molecular weight was 3500 or 4500. Compared with the fact that the number of particles in the SOG composition measured in Example 6 did not have a large difference depending on the weight average molecular weight, generation of particles was particularly suppressed when the oxide film formation conditions of the present invention were satisfied. Can be confirmed.

  As can be seen from the results of the above experimental examples, all of the examples and comparative examples are excellent in terms of the number of particles in the spin-on glass, the shrinkage rate, and the WIWNU side, but considering the particle and scratch generation side, the weight average molecular weight is about 3000 to 6000. When it is, it can be confirmed that not only other characteristics but also particle suppression characteristics are excellent.

Even after the usual SOG solution is baked and cured, many particles remain in the silicon oxide film. Specifically, for example, SiH ₄ that is degassed in the process of annealing the SOG solution applied on the substrate for curing the SOG solution reacts with the oxidizing atmosphere gas to generate particles such as SiO _2. And the reaction chamber is contaminated.

  Such particles have a size of several tens of nanometers or more, and act as a contamination source during the subsequent wafer annealing process, causing damage to the semiconductor device. If the polysilazane coating film is formed thicker around the particles, and the thickness of the coating film after annealing is more than the maximum crack free thickness of 15000 mm or more, cracks are always generated. There is a problem.

  When the SOG composition according to the present invention is used, it is possible to form a silicon oxide film free from voids while maintaining the flatness required from a 256 Mbit semiconductor device. In addition, in order to suppress silicon oxidation in the active region, the SOG composition is converted to silicon oxide by the first heat treatment process, and the converted silicon oxide is further densified to ensure numerical stability. can do.

  As described above, the embodiments of the present invention have been described in detail. However, the present invention is not limited to the embodiments, and as long as it has ordinary knowledge in the technical field to which the present invention belongs, without departing from the spirit and spirit of the present invention, The present invention can be modified or changed.

It is sectional drawing of the oxide film formed in the inner wall of a trench when spin-on-glass film | membrane is baked by one heat processing process. It is a graph for demonstrating the relationship between the viscosity of the spin-on glass composition of this invention, and a shear rate. It is sectional drawing for showing the silicon oxide film formation method of the semiconductor device by one Example of this invention. It is sectional drawing for showing the silicon oxide film formation method of the semiconductor device by one Example of this invention. It is sectional drawing for showing the silicon oxide film formation method of the semiconductor device by one Example of this invention. It is sectional drawing for showing the silicon oxide film formation method of the semiconductor device by one Example of this invention. It is sectional drawing for showing the silicon oxide film formation method of the semiconductor device by one Example of this invention. It is sectional drawing for showing the silicon oxide film formation method of the semiconductor device by one Example of this invention. It is sectional drawing for showing the silicon oxide film formation method of the semiconductor device by one Example of this invention. It is sectional drawing for showing the silicon oxide film formation method of the semiconductor device by one Example of this invention. It is sectional drawing for showing the silicon oxide film formation method of the semiconductor device by one Example of this invention. It is sectional drawing for showing the silicon oxide film formation method of the semiconductor device by one Example of this invention. It is sectional drawing for showing the silicon oxide film formation method of the semiconductor device by one Example of this invention. It is a FT-IR chart which shows the light absorptivity measured after pre-baking a spin-on glass film. It is a FT-IR chart which shows the light absorptivity of the silicon oxide film measured after main baking the spin-on glass film. 6 is a graph showing etching rates of a silicon oxide film according to another embodiment of the present invention and a silicon oxide film formed by a general CVD method. 6 is a graph showing etching rates of a silicon oxide film according to another embodiment of the present invention and a silicon oxide film formed by a general CVD method. 6 is a graph showing etching rates of a silicon oxide film according to another embodiment of the present invention and a silicon oxide film formed by a general CVD method. 6 is a graph showing etching rates of a silicon oxide film according to another embodiment of the present invention and a silicon oxide film formed by a general CVD method. 6 is a graph showing etching rates of a silicon oxide film according to another embodiment of the present invention and a silicon oxide film formed by a general CVD method. 6 is a graph showing etching rates of a silicon oxide film according to another embodiment of the present invention and a silicon oxide film formed by a general CVD method. 6 is a graph showing etching rates of a silicon oxide film according to another embodiment of the present invention and a silicon oxide film formed by a general CVD method. It is sectional drawing explaining the shallow trench element isolation | separation method by the further another Example of this invention. It is sectional drawing explaining the shallow trench element isolation | separation method by the further another Example of this invention. It is sectional drawing explaining the shallow trench element isolation | separation method by the further another Example of this invention. It is sectional drawing explaining the shallow trench element isolation | separation method by the further another Example of this invention. It is sectional drawing explaining the shallow trench element isolation | separation method by the further another Example of this invention. It is sectional drawing explaining the shallow trench element isolation | separation method by the further another Example of this invention. It is sectional drawing explaining the shallow trench element isolation | separation method by the further another Example of this invention. It is a bar graph which shows the standard intensity | strength of the light absorbency obtained by performing FT-IR analysis with respect to the silicon oxide formed in the active area | region of the board | substrate by this invention. 5 is a graph showing the etching rate of a silicon oxide film formed according to the present invention according to the type of etching solution. The graph which shows the polish uniformity after grind | polishing the silicon oxide film formed by the 2nd Example of this invention and the silicon oxide film formed by the high-density plasma chemical vapor deposition method with the chemical mechanical polishing method. It is. 3 is a flowchart for explaining a method of forming an oxide film using a spin-on glass composition according to an embodiment of the present invention. 4 is a graph showing FT-IR results according to a main baking temperature having a water vapor concentration of 80% according to an embodiment of the present invention. 4 is a graph showing FT-IR results according to a main baking temperature having a water vapor concentration of 10% or less according to an embodiment of the present invention. It is a graph which shows the FT-IR result by the atmosphere of the main baking by one Example of this invention. It is a graph which shows the molecular weight distribution of the spin-on glass composition by the weight average molecular weight (Mw) by one Example of this invention. 4 is a graph showing the viscosity of a spin-on glass composition according to weight average molecular weight (Mw) according to an embodiment of the present invention. It is a graph which shows the density | concentration (weight%) of the spin-on glass solid content by the weight average molecular weight (Mw) by one Example of this invention. It is sectional drawing for demonstrating the method of forming the silicon oxide film of the semiconductor device by the other Example of this invention. It is sectional drawing for demonstrating the method of forming the silicon oxide film of the semiconductor device by the other Example of this invention. It is sectional drawing for demonstrating the method of forming the silicon oxide film of the semiconductor device by the other Example of this invention. It is sectional drawing for demonstrating the method of forming the silicon oxide film of the semiconductor device by the other Example of this invention. It is sectional drawing for demonstrating the method of forming the silicon oxide film of the semiconductor device by the other Example of this invention. It is sectional drawing for demonstrating the method of forming the silicon oxide film of the semiconductor device by the other Example of this invention. It is sectional drawing for demonstrating the method of forming the silicon oxide film of the semiconductor device by the other Example of this invention. It is sectional drawing for demonstrating the method of forming the silicon oxide film of the semiconductor device by the other Example of this invention. It is sectional drawing for demonstrating the method of forming the silicon oxide film of the semiconductor device by the other Example of this invention. It is sectional drawing for demonstrating the method of forming the silicon oxide film of the semiconductor device by the other Example of this invention. It is sectional drawing for demonstrating the method of forming the silicon oxide film of the semiconductor device by the other Example of this invention. It is a graph which shows the number (particles / cc) of the particle by the weight average molecular weight (Mw) by one Example of this invention. It is a graph which shows the light absorption (au) by the wave number (cm ^<-1 >: wave number) after the preliminary | backup baking by one Example of this invention. It is a graph which shows the light absorptivity (au) by the weight average molecular weight (Mw) and wave number (cm < ^-1 >) after the main baking by one Example of this invention. 4 is a graph showing thickness and shrinkage ratio according to weight average molecular weight after pre-baking and main baking according to an embodiment of the present invention. 2 is a graph showing a Whit Wafer Non-Uniformity (WIWNU) according to a weight average molecular weight according to an embodiment of the present invention. 4 is a graph showing the number of standard particles and scratches according to weight average molecular weight according to an embodiment of the present invention.

Explanation of symbols

10, 100, 200 Semiconductor substrate 12, 118, 210 Trench 13 First spin-on glass film 13a First silicon oxide film 14, 130, 214, 216 Silicon oxide film 16 Gate oxide film 20 N-type semiconductor region 22 Photoresist pattern 24Ga, 24 Gb, 24 Gc Gate electrode 24 WL Word line 24 a Polysilicon pattern 24 b Tungsten silicide pattern 24 c Tungsten pattern 24 d Silicon nitride pattern 25 p-type impurity region 26, 27 n-type impurity region 30 p-type well 32 Silicon nitride film 32 a Spacer 40 n-type well 42, 44 Impurity region 50 Second spin-on glass film 50a Second silicon oxide film 52 Metal layer pattern 54 Third spin-on glass film 54a Third silicon oxide film 112, 202 Pad oxide film pattern Down 114 the nitride film pattern 116 high-temperature oxide film pattern 120,212 trench inner wall oxide film 201 pad oxide film 203 polishing stop layer 204 polish stop layer pattern 205 a hard mask layer 206 hard mask pattern 213 SOG film

Claims (34)

The structural formula is — (SiH ₂ NH) _n — (wherein n is a positive integer), has a weight average molecular weight of 3000 to 6000% by weight, and 10 to 30% by weight relative to the total weight of the composition Of polysilazane,
A spin-on glass composition comprising 70 to 90% by weight of a solvent. 20 to 23% by weight of the polysilazane;
The spin-on glass composition according to claim 1, comprising 77 to 80% by weight of the solvent.   The spin-on glass composition according to claim 1, wherein the polysilazane has a weight average molecular weight of 3300 to 3700.   The spin-on glass composition according to claim 1, wherein the polysilazane has a molecular weight distribution of 2.5 to 3.5.   The spin-on glass composition according to claim 1, wherein the polysilazane has a molecular weight distribution of 2.8 to 3.2.   The spin-on glass composition according to claim 1, wherein the solvent is xylene or dibutyl ether.   The spin-on glass composition according to claim 1, wherein the composition has a viscosity of 1.54 to 1.70 cP.   The spin-on glass composition according to claim 1, wherein a contact angle with respect to the lower film to which the composition is applied is 4 ° or less.   The spin-on glass composition according to claim 1, further comprising at least one impurity selected from the group consisting of boron, fluorine, phosphorus, arsenic, carbon, and oxygen. A semiconductor substrate having a step portion formed on the upper surface, structural formula _{- (SiH 2 NH) n -} ( of the formula, n represents a positive integer), and a weight average molecular weight of 3,000 to 6,000, Applying a spin-on glass composition comprising 10-30 wt% polysilazane and 70-90 wt% solvent relative to the total weight of the composition to form a spin-on glass film;
Curing the spin-on glass film to form a silicon oxide film.   11. The method of forming a silicon oxide film according to claim 10, wherein the step portion is formed by at least two conductive patterns.   12. The method of forming a silicon oxide film according to claim 11, wherein a distance between the two conductive patterns is 0.04 to 1 [mu] m.   12. The method for forming a silicon oxide film according to claim 11, wherein the two conductive patterns are gate electrodes or metal wiring patterns of a semiconductor device.   11. The method for forming a silicon oxide film according to claim 10, wherein an aspect ratio of a step portion between the two conductive patterns is 5: 1 to 10: 1.   11. The silicon oxide film according to claim 10, wherein the step portion includes a dense step portion having an aspect ratio of 5: 1 to 10: 1 and a global step portion having an aspect ratio of 1: 1 or less. Forming method. The composition comprises
20 to 23% by weight of the polysilazane;
The silicon oxide film forming method according to claim 10, comprising 77 to 80 wt% of the solvent.   The method for forming a silicon oxide film according to claim 10, wherein the polysilazane has a weight average molecular weight of 3300 to 3700.   11. The method of forming a silicon oxide film according to claim 10, wherein the polysilazane has a molecular weight distribution of 2.5 to 3.5.   11. The method of forming a silicon oxide film according to claim 10, wherein the polysilazane has a molecular weight distribution of 2.8 to 3.2.   11. The method for forming a silicon oxide film according to claim 10, wherein the viscosity of the composition is 1.54 to 1.70 cP. Curing the spin-on glass film comprises:
Pre-baking the spin-on glass film at a temperature of 100-500 ° C .;
The method for forming a silicon oxide film according to claim 10, further comprising: main baking the spin-on glass film at a temperature of 400 to 1200 ° C.   The silicon oxide according to claim 21, wherein the preliminary baking is performed in an oxygen atmosphere, a water vapor atmosphere, a mixed atmosphere of oxygen and water vapor, a nitrogen atmosphere, or a mixed atmosphere of oxygen, water vapor, and nitrogen for 1 to 5 minutes. Film forming method.   The silicon oxide according to claim 21, wherein the main baking is performed in an oxygen atmosphere, a water vapor atmosphere, a mixed atmosphere of oxygen and water vapor, a nitrogen atmosphere, or a mixed atmosphere of oxygen, water vapor, and nitrogen for 10 to 180 minutes. Film forming method.   11. The method of forming a silicon oxide film according to claim 10, wherein the oxide film has a thickness of 1000 to 10,000 mm. The step portion is formed by forming a plurality of gate electrodes on the semiconductor substrate,
The spin-on glass film is formed by coating the substrate so as to cover the gate electrode with the spin-on glass composition,
The step of curing the spin-on glass film includes pre-baking the spin-on glass film at a temperature of 100 to 500 ° C. and main baking the spin-on glass film at a temperature of 400 to 1200 ° C. The method of forming a silicon oxide film according to claim 10. The step portion is formed by forming a plurality of metal wiring patterns on the insulating film after forming an insulating film on the substrate,
The spin-on glass film is formed by coating the spin-on glass solution on the substrate so as to cover the metal wiring pattern,
The step of curing the spin-on glass film includes pre-baking the spin-on glass film at a temperature of 100 to 500 ° C. and main baking the spin-on glass film at a temperature of 400 to 1200 ° C. The method of forming a silicon oxide film according to claim 10.   11. The method of forming a silicon oxide film according to claim 10, further comprising a step of forming a silicon nitride film on the semiconductor substrate to a thickness of 200 to 600 mm before applying the spin-on glass composition. Comprising at least one flat film comprising a spin-on glass composition;
The spin-on glass composition is
The structural formula is — (SiH ₂ NH) _n — (wherein n is a positive integer), the weight average molecular weight is 3000 to 6000, and 10 to 30% by weight of polysilazane based on the total composition;
A semiconductor device comprising 70 to 90% by weight of a solvent.   29. The semiconductor device according to claim 28, wherein the polysilazane has a weight average molecular weight of 3300 to 3700.   30. The semiconductor device according to claim 29, wherein the solvent is xylene or dibutyl ether. The spin-on glass is
20 to 23% by weight of the polysilazane;
30. The semiconductor device according to claim 29, comprising 77 to 80% by weight of the solvent.   30. The semiconductor device according to claim 29, wherein the spin-on glass composition has a viscosity of 1.54 to 1.70 cP.   30. The semiconductor device according to claim 29, wherein the spin-on glass composition has a contact angle of 4 [deg.] Or less with respect to a film formed under the composition. 30. The semiconductor device according to claim 29, wherein the spin-on glass composition further includes an impurity containing at least one element selected from the group consisting of boron, fluorine, phosphorus, arsenic, carbon, and oxygen.

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