JP2005150336A - Manufacturing method of nonvolatile semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of manufacturing a reliable nonvolatile semiconductor memory device through a few processes. <P>SOLUTION: A series of processing are carried out for the bit line contact holes, peripheral contact holes, and bit line metal interconnect lines of an NAND non-volatile semiconductor memory device. A silicon nitride film 202 is formed as a stopper film in an interlayer dielectric 209, so that the bit line contact holes, the peripheral contact holes, and the bit line interconnect line grooves can be collectively processed, plug metal and interconnect line metal can be collectively embedded in the bit line contact holes, the peripheral contact holes, and the bit line interconnect line grooves, a resist coating film formed through a lithography technique can be improved in film thickness stability in processing of the bit line interconnect line grooves, and the depth of the grooves can be improved in controllability when the bit line interconnect line grooves are processed. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a nonvolatile semiconductor memory device, and more particularly to a method for manufacturing a contact hole or a metal wiring layer in a NAND type nonvolatile semiconductor memory device.

  1 to 17 describe a process after the gate wiring processing of a conventional nonvolatile semiconductor memory device, that is, a bit line contact hole, a peripheral contact hole, and a bit line metal wiring processing method, using process cross sections.

  First, as shown in FIG. 1, a plurality of nonvolatile memory elements are formed in the bit line contact hole forming portion on the semiconductor silicon substrate (101), and silicon nitride covering the gate wiring is formed on these surfaces. A film (102) is formed. Here, each nonvolatile memory element includes a gate wiring mask oxide film (103), a gate wiring tungsten-silicon reaction film (104), a gate wiring phosphorus-added polysilicon (105), and an inter-polysilicon oxide film (106). ), Phosphorous doped polysilicon for floating gate wiring (107) and gate insulating oxide film (108). The silicon nitride film (102) is also formed on the surface of the semiconductor silicon substrate (101) in the peripheral contact hole forming portion. In this way, a reflow oxide film such as BPSG is reflowed on the surfaces of the bit line contact hole forming portion and the peripheral contact hole forming portion covered with the silicon nitride film (102) by using the CVD technique. One interlayer insulating film (109) is formed.

  Next, as shown in FIG. 2, the silicon nitride film (102) covering the gate wiring is used as a stopper, and planarization is performed using the CMP technique. Next, as shown in FIG. 3, an oxide film (110) such as TEOS is formed as a second interlayer insulating film by using the CVD technique. Next, as shown in FIG. 4, the bit line contact hole is patterned using a lithography technique on the resist (111). Next, as shown in FIG. 5, using the pattern resist (111) as a mask, the interlayer insulating films (110) and (109) are processed using a dry etching technique. Next, as shown in FIG. 6, the pattern resist (111) is removed using an ashing technique. Next, as shown in FIG. 7, the silicon nitride film (102) at the bottom of the contact hole is removed using a dry etching technique. Next, as shown in FIG. 8, phosphorus-added polysilicon (112) is formed by using the CVD technique. Next, as shown in FIG. 9, etch back of the phosphorus-added polysilicon (112) is performed using a dry etching technique. Next, as shown in FIG. 10, peripheral contact holes are patterned in the resist (113) by using a lithography technique. Next, as shown in FIG. 11, using the pattern resist (113) as a mask, the interlayer insulating films (110) and (109) in the peripheral contact portion are processed using a dry etching technique. Next, as shown in FIG. 12, the pattern resist (113) is removed using an ashing technique. Next, as shown in FIG. 13, the bit line wiring is patterned with a resist (114) using a lithography technique. Next, as shown in FIG. 14, using the pattern resist (114) as a mask, the interlayer insulating film (110) is processed using a dry etching technique. Next, as shown in FIG. 15, the pattern resist (114) is removed using an ashing technique. Next, as shown in FIG. 16, a barrier metal (115) such as Ti and a plug + wiring metal (116) such as W are formed by sputtering. Next, as shown in FIG. 17, the barrier metal (115), the plug, and the wiring metal (116) on the interlayer insulating film (110) are removed using CMP technology.

  Through these steps, a bit line contact hole, a peripheral contact hole, and a bit line metal wiring are formed.

  In the conventional bit line contact hole, peripheral contact hole, and bit line metal wiring manufacturing process as described above, bit line contact hole, peripheral contact hole, bit line metal wiring processing and plug and wiring are embedded individually, The number of processes is increasing. Further, when using the lithography technique in the bit line wiring groove processing, the resist film thickness becomes unstable due to the resist flowing into the peripheral contact hole, and the stability of the lithography technique is lowered. Further, when using the dry etching technique in the bit line wiring groove processing, since there is no stopper film, the groove depth becomes unstable, and the stability of wiring resistance and the like is lowered.

  An object of the present invention is to provide a manufacturing method capable of improving the problems of the conventional manufacturing apparatus and capable of manufacturing a highly reliable nonvolatile semiconductor memory device with a small number of steps.

  The method for manufacturing a NAND-type nonvolatile semiconductor memory device according to the present invention forms a first interlayer insulating film on the surface of an element region in which a plurality of nonvolatile semiconductor memory elements formed on a semiconductor substrate are formed and its peripheral region. A step of forming a silicon nitride film on the first interlayer insulating film, a step of processing the silicon nitride film to form a hard mask of the bit line contact hole and the peripheral contact hole, A step of simultaneously forming a bit line contact hole, a peripheral contact hole and a bit line wiring groove, and a step of simultaneously embedding wiring metal in the bit line contact hole, the peripheral contact hole and the bit line wiring groove. It is characterized by.

  According to the present invention, a bit line contact hole, a peripheral contact hole, and a bit are formed by forming a silicon nitride film on the first interlayer film and forming a hard mask for the bit line contact hole and the peripheral contact hole in advance. Batch processing of wire metal wiring and batch embedding of metal for wiring with a plug become possible, and the number of processing steps is reduced as compared with the conventional technique.

  Further, in the prior art, there is a problem that when the bit line wiring is patterned by the lithography technique, the resist flows into the peripheral contact and the resist film thickness becomes unstable. Technology stability is improved.

  Further, in the prior art, when processing the bit line wiring, there is a problem that the wiring groove depth becomes unstable because only the oxide film is dry-etched. However, in the present invention, the silicon nitride film serves as a stopper film, and the wiring groove depth is reduced. Stability, that is, the stability of wiring resistance is improved.

  Hereinafter, embodiments of a method for manufacturing a nonvolatile semiconductor memory device of the present invention will be described with reference to FIGS. 18 to 30 are cross-sectional process diagrams illustrating a method of processing the bit line contact hole, the peripheral contact hole, and the bit line metal wiring in the nonvolatile semiconductor memory device.

  First, as shown in FIG. 18, a plurality of nonvolatile memory elements are formed in the bit line contact hole forming portion on the semiconductor silicon substrate (201), and silicon nitride covering the gate wiring is formed on these surfaces. A film (202) is formed. Here, each nonvolatile memory element includes a gate wiring mask oxide film (203), a gate wiring tungsten-silicon reaction film (204), a gate wiring phosphorus-doped polysilicon (205), and an inter-polysilicon oxide film (206). ), Phosphorus-doped polysilicon (207) for floating gate wiring, and a gate insulating oxide film (208). The silicon nitride film (202) is also formed on the surface of the semiconductor silicon substrate (201) in the peripheral contact hole forming portion. In this way, a reflow oxide film such as BPSG is reflowed on the surfaces of the bit line contact hole forming portion and the peripheral contact hole forming portion covered with the silicon nitride film (202) by using the CVD technique, One interlayer insulating film (209) is formed. As shown in FIG. 19, the first interlayer insulating film (209) is removed using the CMP technique until the surface of the silicon nitride film (202) covering the gate wiring is exposed.

Next, as shown in FIG. 20, a silicon nitride film (210) is formed using the CVD technique. Next, as shown in FIG. 21, the bit line contact hole and the peripheral contact hole are patterned by a resist (211) using a lithography technique. Next, as shown in FIG. 22, using the pattern resist (211) as a mask, the silicon nitride film (210) is removed using a dry etching technique. Next, as shown in FIG. 23, the pattern resist (211) is removed using an ashing technique. Next, as shown in FIG. 24, an oxide film (212) such as TEOS is formed using the CVD technique. Next, as shown in FIG. 25, the bit line wiring is patterned by a resist (213) using a lithography technique. Next, as shown in FIG. 26, using the pattern resist (213) as a mask, the interlayer insulating films (212) and (209) are processed using a dry etching technique. Next, as shown in FIG. 27, the pattern resist (213) is removed using an ashing technique. Next, as shown in FIG. 28, the silicon nitride film 202 at the bottom of the contact hole is removed using a dry etching technique. Next, as shown in FIG. 29, a barrier metal (214) such as Ti and a plug + wiring metal (215) such as W are formed by sputtering. Next, as shown in FIG. 30, the barrier metal (214) and the wiring metal with plug (215) on the interlayer insulating film (212) are removed using the CMP technique. Through these steps, a bit line contact hole, a peripheral contact hole, and a bit line metal wiring are formed.

  According to such a method for manufacturing a nonvolatile semiconductor memory device of the present invention, the bit line contact hole and the peripheral contact hole are patterned at once, and only the silicon nitride film is processed. A second interlayer film is formed thereon, the bit line wiring groove is patterned, and the oxide film used for the interlayer insulating film is etched. Since the silicon nitride film is difficult to be etched with respect to the oxide film, the bit line wiring groove depth is determined when the silicon nitride film is etched. If the etching is continued as it is, since the bit line contact hole and the peripheral contact hole are patterned in advance in the silicon nitride film, the bit line contact hole and the peripheral contact hole are formed using this as a mask. In this manner, by processing the silicon nitride film in advance and placing it in the interlayer film, the bit line contact hole, the peripheral contact hole, and the bit line wiring groove are collectively formed. Plugs to processing parts + wiring metal are also embedded together.

Sectional process drawing explaining the manufacturing method of the conventional bit line contact hole, peripheral contact hole, and bit line metal wiring formation. Sectional process drawing explaining the manufacturing method of the conventional bit line contact hole, peripheral contact hole, and bit line metal wiring formation. Sectional process drawing explaining the manufacturing method of the conventional bit line contact hole, peripheral contact hole, and bit line metal wiring formation. Sectional process drawing explaining the manufacturing method of the conventional bit line contact hole, peripheral contact hole, and bit line metal wiring formation. Sectional process drawing explaining the manufacturing method of the conventional bit line contact hole, peripheral contact hole, and bit line metal wiring formation. Sectional process drawing explaining the manufacturing method of the conventional bit line contact hole, peripheral contact hole, and bit line metal wiring formation. Sectional process drawing explaining the manufacturing method of the conventional bit line contact hole, peripheral contact hole, and bit line metal wiring formation. Sectional process drawing explaining the manufacturing method of the conventional bit line contact hole, peripheral contact hole, and bit line metal wiring formation. Sectional process drawing explaining the manufacturing method of the conventional bit line contact hole, peripheral contact hole, and bit line metal wiring formation. Sectional process drawing explaining the manufacturing method of the conventional bit line contact hole, peripheral contact hole, and bit line metal wiring formation. Sectional process drawing explaining the manufacturing method of the conventional bit line contact hole, peripheral contact hole, and bit line metal wiring formation. Sectional process drawing explaining the manufacturing method of the conventional bit line contact hole, peripheral contact hole, and bit line metal wiring formation. Sectional process drawing explaining the manufacturing method of the conventional bit line contact hole, peripheral contact hole, and bit line metal wiring formation. Sectional process drawing explaining the manufacturing method of the conventional bit line contact hole, peripheral contact hole, and bit line metal wiring formation. Sectional process drawing explaining the manufacturing method of the conventional bit line contact hole, peripheral contact hole, and bit line metal wiring formation. Sectional process drawing explaining the manufacturing method of the conventional bit line contact hole, peripheral contact hole, and bit line metal wiring formation. Sectional process drawing explaining the manufacturing method of the conventional bit line contact hole, peripheral contact hole, and bit line metal wiring formation. Sectional process drawing explaining the manufacturing method of the bit line contact hole of this invention, a peripheral contact hole, and bit line metal wiring formation. Sectional process drawing explaining the manufacturing method of the bit line contact hole of this invention, a peripheral contact hole, and bit line metal wiring formation. Sectional process drawing explaining the manufacturing method of the bit line contact hole of this invention, a peripheral contact hole, and bit line metal wiring formation. Sectional process drawing explaining the manufacturing method of the bit line contact hole of this invention, a peripheral contact hole, and bit line metal wiring formation. Sectional process drawing explaining the manufacturing method of the bit line contact hole of this invention, a peripheral contact hole, and bit line metal wiring formation. Sectional process drawing explaining the manufacturing method of the bit line contact hole of this invention, a peripheral contact hole, and bit line metal wiring formation. Sectional process drawing explaining the manufacturing method of the bit line contact hole of this invention, a peripheral contact hole, and bit line metal wiring formation. Sectional process drawing explaining the manufacturing method of the bit line contact hole of this invention, a peripheral contact hole, and bit line metal wiring formation. Sectional process drawing explaining the manufacturing method of the bit line contact hole of this invention, a peripheral contact hole, and bit line metal wiring formation. Sectional process drawing explaining the manufacturing method of the bit line contact hole of this invention, a peripheral contact hole, and bit line metal wiring formation. Sectional process drawing explaining the manufacturing method of the bit line contact hole of this invention, a peripheral contact hole, and bit line metal wiring formation. Sectional process drawing explaining the manufacturing method of the bit line contact hole of this invention, a peripheral contact hole, and bit line metal wiring formation. Sectional process drawing explaining the manufacturing method of the bit line contact hole of this invention, a peripheral contact hole, and bit line metal wiring formation.

Explanation of symbols

(101) Semiconductor silicon substrate,
(102) Gate wiring protection silicon nitride film,
(103) Gate wiring mask oxide film,
(104) Tungsten-silicon reaction film for gate wiring,
(105) Phosphorus-doped polysilicon for gate wiring,
(106) inter-polysilicon oxide film,
(107) Phosphorus-doped polysilicon for floating gate wiring,
(108) Gate insulating oxide film,
(109) a first interlayer insulating oxide film,
(110) second interlayer insulating oxide film,
(111) bit line contact hole pattern resist,
(112) Phosphorus-doped polysilicon for bit line contact plugs,
(113) Peripheral contact hole pattern resist,
(114) Bit line wiring pattern resist,
(115) Embedded plug + barrier metal for wiring,
(116) Embedded plug + metal for wiring
(201) Semiconductor silicon substrate,
(202) Gate wiring protection silicon nitride film,
(203) Gate wiring mask oxide film,
(204) Tungsten-silicon reaction film for gate wiring,
(205) Phosphorus-doped polysilicon for gate wiring,
(206) Inter-polysilicon insulating film,
(207) Phosphorus-doped polysilicon for floating gate wiring,
(208) Gate insulating oxide film,
(209) First interlayer insulating oxide film,
(210) Silicon nitride film for stopper,
(211) Bit line contact hole and peripheral contact hole pattern resist,
(212) Second interlayer insulating oxide film,
(213) Bit line wiring pattern resist,
(214) Embedded plug and wiring barrier metal,
(215) Embedded plug and metal for wiring

Claims (2)

  Forming a first interlayer insulating film on a surface of an element region formed on the semiconductor substrate on which the plurality of nonvolatile semiconductor memory elements are formed and a peripheral region thereof; and silicon nitride on the first interlayer insulating film A step of forming a film, a step of processing the silicon nitride film to form a hard mask of the bit line contact hole and the peripheral contact hole, and the bit line contact hole, the peripheral contact hole and the bit line wiring groove through the hard mask And a step of simultaneously embedding wiring metal in the bit line contact hole, the peripheral contact hole and the bit line wiring groove. A method for manufacturing a NAND type nonvolatile semiconductor memory device, comprising:   Forming a second interlayer insulating film on the silicon nitride film; and forming a bit line wiring groove resist mask on the second interlayer insulating film; The bit line contact hole, the peripheral contact hole and the bit line wiring groove are formed simultaneously, and wiring metal is simultaneously embedded in the bit line contact hole, the peripheral contact hole and the bit line wiring groove. A manufacturing method of a NAND type nonvolatile semiconductor memory device according to Item 1.

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