JP2005150288A - Method of manufacturing semiconductor device, thin film transistor, liquid crystal panel, and projection type liquid crystal projector - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To manufacture a fine semiconductor device with high characteristics. <P>SOLUTION: A first insulation film 13 is formed on a semiconductor film 12, and a gate electrode 14 is formed on the first insulation film 13, and then a second insulation film 15 is formed at least on the side faces of the gate electrode 14. With the second insulation film 15 as a mask, dopants are introduced in a low concentration 16 into the semiconductor film 12, and a resist film 17 is formed at least on the side faces of the second insulation film 15. Thereafter, with the resist mask 17 as a mask, the dopants are introduced in a high concentration 18 into the semiconductor film 12, and then the dopants introduced into the semiconductor film 12 are diffused. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a manufacturing method of a semiconductor device such as a thin film transistor (TFT), a thin film transistor manufactured using the manufacturing method, a liquid crystal display device including the thin film transistor, and a projection type liquid crystal projector including the liquid crystal display device.

  Conventionally, in a liquid crystal panel, a TFT driving method using a thin film transistor using polycrystalline silicon (Si) arranged in correspondence with each pixel electrode has been widely used while forming a pixel electrode on a matrix on a glass substrate. ing. In addition, the polycrystalline silicon TFT has an advantage that the mobility is about two orders of magnitude higher than the amorphous silicon TFT, so that not only the pixel driving TFT but also a circuit necessary for panel driving is provided in the peripheral portion. It has the feature that it can be formed simultaneously.

  As a circuit formed in the peripheral portion of the panel, a CMOS circuit is mounted in order to reduce power consumption. It is desirable that the pixel driving TFT has an excellent holding characteristic in which the on-current is high and the off-current is low in order to hold the pixel signal for one frame period in order to write a signal in a shorter time. Also in the CMOS circuit TFT mounted in the peripheral circuit portion, it is desirable that the on-current is high and the off-current is low in order to transfer a signal at a higher speed and prevent a decrease in output.

  In recent years, there is an increasing demand for miniaturization, high definition, and high brightness in liquid crystal panels used in projection type liquid crystal projectors. In response to this requirement, forming a fine element achieves a narrow pixel pitch and a high aperture ratio, and can be said to be a very effective means.

  In the polycrystalline silicon TFT, a recombination current is generated via the crystal grain boundary at the drain end where the electric field is concentrated. In order to reduce this off current, a TFT adopting an LDD structure is known. This structure is a technique for reducing electric field concentration by reducing the impurity concentration in the vicinity of the position corresponding to the end surface on the gate electrode side of the active layer. This structure is also employed in a polycrystalline silicon TFT mounted on a small-sized, high-definition, high-brightness liquid crystal panel for projector use. In this case, it is desirable to process the LDD length as fine as possible.

  Here, a manufacturing process of a TFT adopting a conventional LDD structure will be described with reference to FIGS.

First, as shown in FIG. 8A, a patterned Si active layer 2 and a gate insulating film mainly composed of a silicon oxide film are formed on an insulating substrate 1 including an interlayer insulating film for suppressing impurity diffusion. 3. A gate electrode 4 is formed, and a low concentration ion implantation process is performed using the gate electrode 4 as a mask. In this step, an ion species 6 having an impurity concentration of 1 × 10 ¹² to 1 × 10 ¹⁴ atoms / cm ² per unit area is implanted using an ion implantation apparatus to form a low concentration N-type conductive region.

Next, as shown in FIG. 8B, a photoresist 7 is formed, and a high concentration impurity region set in a range of 1 × 10 ¹⁴ to 1 × 10 ¹⁶ atoms / cm ^{2 using} the resist 7 as a mask. Are formed by implanting ion species 8 using an ion implantation apparatus. Thereby, an LDD region and source / drain regions are formed. At this time, in the active layer 2, the distance from the position corresponding to the side end face of the gate electrode 4 to the position corresponding to the side end face of the photoresist 7 is defined as the mask LDD length.

  Next, as shown in FIG. 8C, an interlayer insulating film 9 mainly composed of a silicon oxide film is formed and heat-treated using an arc furnace or the like to diffuse impurities in the active layer 2. This diffuses by ΔL directly from the LDD region to the lower side of the gate electrode 4. The effective LDD length after impurity diffusion can be obtained by (effective LDD length) = (mask LDD length) −Δl.

  Thereafter, as shown in FIG. 8D, a contact hole is opened, a metal as an electrode material is formed, and patterning is performed using a photolithography technique to form the source / drain electrodes 10. Subsequent steps include the formation of an interlayer insulating film, hydrogenation, contact opening, formation of a common electrode, contact opening, extraction of a pixel electrode, etc., although detailed description is omitted.

  According to the conventional manufacturing method described above, in the low concentration ion implantation process, since the ion implantation is performed using the gate electrode as a mask, in the active layer, from the source / drain side to the position corresponding to the side end surface of the gate electrode, When ions are implanted and thermally diffused, the impurity concentration in the vicinity of the electrode-side end face under the gate electrode of the active layer is high (deep), and the profile (concentration distribution gradient) becomes steep, so that it is turned off. There was a problem that the current value became high and high performance could not be realized.

  The present invention has been made to solve the above problems, and provides a method for manufacturing a semiconductor device such as a thin film transistor capable of sufficiently reducing off-state current without inhibiting miniaturization. It is an object of the present invention to provide a small and high-performance semiconductor device having a holding characteristic, and a high-quality liquid crystal panel and a projection type liquid crystal projector.

  In order to solve the above-described problems, according to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, the step of forming a first insulating film on a semiconductor film, and a gate electrode on the first insulating film. Forming a second insulating film having a predetermined width on at least a side surface of the gate electrode; and implanting low concentration impurities into the semiconductor film using the gate electrode and the second insulating film as a mask A step of forming a resist film on at least a side surface of the second insulating film, and a step of implanting a high concentration impurity into the semiconductor film using the gate electrode, the second insulating film, and the resist film as a mask. And a method of manufacturing a semiconductor device, including a step of diffusing impurities implanted into the semiconductor film.

  In the method of manufacturing a semiconductor device according to the first aspect of the present invention, a second insulating film having a predetermined width is formed on at least a side surface of the gate electrode, and the semiconductor film is formed using the gate electrode and the second insulating film as a mask. Since the low concentration impurity is implanted, an offset region where the low concentration impurity is not implanted is formed in a portion corresponding to the vicinity of the side surface of the gate electrode of the semiconductor film. Therefore, when the impurity is diffused in the step of diffusing the impurity, the low concentration impurity is diffused from the position offset from the position corresponding to the side surface of the gate electrode in the semiconductor film. As a result, the impurity concentration at the position corresponding to the side surface of the semiconductor film can be made lower than before, and the profile (concentration distribution gradient) of the impurity at the side surface of the gate electrode of the semiconductor film and the portion corresponding to the vicinity thereof becomes gentle. The off-state current can be reduced, and a small and high-performance semiconductor device having excellent holding characteristics can be manufactured.

  In the semiconductor device manufacturing method according to the first aspect of the present invention, the width of the second insulating film can be set to 0.4 μm or less.

  According to a second aspect of the present invention, there is provided a thin film transistor manufactured using the method for manufacturing a semiconductor device according to the first aspect of the present invention.

  According to a third aspect of the present invention, there is provided a liquid crystal panel in which a liquid crystal is sealed between a pixel substrate having a pixel electrode and a switching element, and a counter substrate having a counter electrode. A liquid crystal panel including the thin film transistor according to the second aspect is provided.

  According to a fourth aspect of the present invention, there is provided a projection type liquid crystal projector provided with a liquid crystal panel according to the third aspect of the present invention.

  According to the present invention, impurity diffusion can be suppressed and the impurity concentration in the vicinity of the side surface of the gate electrode can be reduced. Therefore, there is an effect that a semiconductor device with a small off-current can be manufactured without hindering miniaturization.

  Further, there is an effect that it is possible to provide a semiconductor device including a small and high-performance thin film transistor having excellent holding characteristics, and a high-quality liquid crystal panel or a projection-type liquid crystal projector.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[First Embodiment]
FIGS. 1A to 1G are diagrams showing a manufacturing process of an N-channel TFT having an offset LDD structure according to the first embodiment of the present invention.

  First, as shown in FIG. 1A, a patterned Si active layer 12 and a gate insulating film mainly composed of a silicon oxide film on an insulating substrate 11 including an interlayer insulating film that suppresses impurity diffusion. 13. The gate electrode 14 is formed using a general manufacturing process.

  Here, the film thickness of the Si active layer 12 is preferably within 0.1 μm from the viewpoint of securing a sufficient write current and reducing the photosensitivity. The gate insulating film 13 is preferably formed by a thermal oxidation method at about 1000 ° C. when a quartz substrate having high heat resistance is used as the insulating substrate 11. In the case where a low-melting-point substrate such as borosilicate glass is used as the insulating substrate 11, the gate insulating film 13 is preferably formed using a plasma CVD method, an LP-CVD method, a sputtering method, or the like. After the gate insulating film 13 is formed, impurity ions are implanted for Vth adjustment. Next, a film to be the gate electrode 14 is formed by a CVD method or a sputtering method, and is patterned using a photolithography technique.

  For the formation of the gate electrode 14, P is added and a metal having a relatively high melting point such as poly-Si having an N-type conductivity type, Mo, Ta, or Cr is used. Further, a polycide such as MoSix, TaSix, CrSix, etc., which is a compound of a metal having a high melting point and Si, may be used. Further, if the insulating substrate 11 is a low-melting glass substrate, a metal such as Al or Cu protected by a barrier metal may be used.

  Next, as shown in FIG. 1B, the insulating film 15 is formed by using a film forming method such as an LP-CVD method or a Plasma-CVD method. The thickness of the insulating film 15 is less than 1 μm, preferably within the range of 0.1 to 0.4 μm. The film thickness of the insulating film 15 becomes the offset length Loff as it is. As the insulating film 15, a silicon oxide film, a silicon nitride film, or a BSG film, a PSG film, or a BPSG film in which silicon oxide is the main component and B or P is added as an impurity is used.

  When Al is used as the material for forming the gate electrode 14, an anodized film obtained by anodizing this may be used. If the insulating substrate 11 is a heat-resistant quartz substrate and poly Si is used for the gate electrode 14, a thermal oxide film obtained by thermally oxidizing the insulating substrate 11 in an oxygen atmosphere at 800 to 1,000 ° C. is used. Alternatively, the insulating film 15 may be used.

Next, as shown in FIG. 1C, a low concentration ion implantation step is performed to form an LDD region. In this step, an ion species 16 having an impurity concentration of 1 × 10 ¹² to 1 × 10 ¹⁴ atoms / cm ² per unit area is implanted using an ion implantation apparatus to form a low concentration N-type conductive region. P +, As +, etc. are used for the ion species 16. At this time, the film thickness of the insulating film 15 becomes the offset length Loff from the gate end as it is due to self-alignment.

Next, as shown in FIG. 1D, a photoresist 17 is formed, and a high concentration impurity region designed in a range of 1 × 10 ¹⁴ to 1 × 10 ¹⁶ atoms / cm ^{2 using} the resist 17 as a mask. Are formed by implanting ion species 18 such as P + and As + using an ion implantation apparatus. Thereby, an LDD region and source / drain regions are formed. At this time, the distance from the side surface of the gate electrode 14 to the corresponding side surface of the photoresist 17 is defined as the mask LDD length.

  Next, as shown in FIG. 1E, an interlayer insulating film 19 mainly composed of a silicon oxide film is formed. As this insulating film 19, a BSG film to which B or P is added, a PSG film, a BPSG film, an NSG film to which no impurities are added, or the like is used.

Next, as shown in FIG. 1F, an activation process is performed. In this activation treatment, the impurities in the active layer 12 are diffused by heat treatment. In this embodiment, a Furnace type batch furnace was used for this heat treatment, and a treatment at about 1000 ° C. was performed for several minutes to several tens of minutes in an N ₂ atmosphere. In addition to the heat treatment of the Furnace type batch furnace, heat treatment by RTA (Rapid Thermal Anneal), heat treatment by ELA (Exima Laser Anneal), or a combination thereof may be performed. After the heat treatment, impurities are diffused by a diffusion length Δl from the source / drain region to the LDD region and by a diffusion length ΔL from the end of the LDD region to the lower side of the gate electrode 14 through the offset region. The impurities pass through the offset region (Loff) and diffuse to the bottom of the gate electrode 14, and the effective LDD length after the impurity diffusion is expressed by the following equation (1).

  (Effective LDD length) = (mask LDD length) −Δl (1)

  Thereafter, as shown in FIG. 1G, contact holes are opened, a metal to be the source / drain electrodes 20 is formed, and patterning is performed using a photolithography technique to form the source / drain electrodes 20. . Subsequent steps are not described in detail, but include formation of an interlayer insulating film, hydrogenation, contact opening, formation of a common electrode, contact opening, extraction of a pixel electrode, and the like.

  Here, compared with the conventional manufacturing method shown in FIG. 8, in FIG. 8B and FIG. 1D, the mask LDD length is determined by the finished line width of the photoresists 7 and 17, Then it is the same length. In FIG. 8C and FIG. 1F, when the activation process is performed under the same conditions, impurities are diffused by substantially the same length (ΔL).

  However, in FIG. 1F of the present embodiment, since an offset region (Loff) exists in the vicinity of the side surface of the gate electrode 14, a position corresponding to the side surface of the gate electrode 14 of the active layer 12 (X1, hereinafter for convenience). Compared at the same position (X2, hereinafter referred to as the drain end for the sake of convenience) in the conventional FIG. 1C, the impurity concentration is lower (thin) and the gate electrode It turns out that the penetration to 14 side is also small. It should be noted that the effective LDD length after diffusion in the prior art is the same as the above equation (1) (mask LDD length−Δl).

  The impurity concentration at the drain end X1 in FIG. 1F becomes thinner as the length of the offset length Loff is increased, and Loff, that is, the film thickness (width) of the insulating film 15 is adjusted to lower it to a desired concentration. good. Further, since Loff is adjusted by self-alignment, the impurity concentration at the drain end X1 can be adjusted with higher accuracy than the adjustment method using the photoresist mask 17.

[Second Embodiment]
Next, a second embodiment of the present invention will be described with reference to FIG. The second embodiment is an example in the case where the offset region (Loff) is formed by a method different from the first embodiment described above. The same components as those in the first embodiment described above are denoted by the same reference numerals, and a part of the description is omitted.

  First, similarly to FIG. 1A of the first embodiment described above, a patterned Si active layer 12 and a silicon oxide film are mainly formed on an insulating substrate 11 including an interlayer insulating film for suppressing impurity diffusion. The gate insulating film 13 and the gate electrode 14 as components are formed using a general manufacturing process.

  Next, as shown in FIG. 2A, an insulating film 21 as a silicon nitride film is formed using the LP-CVD method. The thickness of the insulating film 21 is less than 1 μm, preferably within the range of 0.1 to 0.4 μm. The film thickness of the insulating film 21 becomes the offset length Loff as it is.

  Next, as shown in FIG. 2B, portions other than the portions corresponding to the side surfaces of the gate electrode 14 of the insulating film 21 are removed by anisotropic dry etching, and sidewall spacers 22 are formed on the side walls of the gate electrode 14. . This film thickness corresponds to the offset length Loff. The film thickness of the sidewall spacer 22 is substantially equal to the film thickness of the insulating film (silicon nitride film) 21 formed in FIG.

Next, as shown in FIG. 2C, a low concentration ion implantation step is performed to form an LDD region. In this step, an ion species 16 having an impurity concentration of 1 × 10 ¹² to 1 × 10 ¹⁴ atoms / cm ² per unit area is implanted using an ion implantation apparatus to form a low concentration N-type conductive region. P +, As +, etc. are used for the ion species 16. Thereafter, the same steps as those in FIGS. 1E to 1G of the first embodiment described above are performed.

[Third Embodiment]
Next, a third embodiment of the present invention will be described with reference to FIG. The third embodiment is an example in which the offset region (Loff) is self-aligned by a method different from that of the first embodiment described above, and is a case where a gate electrode having a laminated structure is used. The same components as those in the first embodiment described above are denoted by the same reference numerals, and a part of the description is omitted.

  First, similarly to FIG. 1A of the first embodiment described above, a patterned Si active layer 12 and a silicon oxide film are mainly formed on an insulating substrate 11 including an interlayer insulating film for suppressing impurity diffusion. A gate insulating film 13 as a component is formed using a general manufacturing process. Next, as shown in FIG. 3A, a first gate material 31 and a second gate material 32 on the premise that sidewall oxidation is performed are sequentially formed, and a photoresist 33 is formed. Here, the first gate material 31 is made of poly-Si having an N-type conductivity to which P is added, or a metal such as Mo, Cr, Ta or the like, and the second gate material 32 is made from the first gate material 31. Polycides such as WSix, MoSix, TiSix, and TaSi that are not easily oxidized are used.

  Next, as shown in FIG. 3B, the gate electrode 14 having a laminated structure is formed by dry etching using the photoresist 33 as a mask.

Next, as shown in FIG. 3C, thermal oxidation at around 1000 ° C. in a dry O ₂ atmosphere or pyro-oxidation at around 900 ° C. in an O ₂ atmosphere containing water vapor is performed to form a first electrode of the gate electrode 14. A side wall portion of the gate material 31 is used as an oxide film 34 for forming an offset region. The offset length Loff corresponds to the thickness of the oxide film 34, and the thickness of the oxide film 34 can be adjusted by the oxidation time.

Next, as shown in FIG. 3D, a low concentration ion implantation step is performed to form an LDD region. In this step, an ion species 16 having an impurity concentration of 1 × 10 ¹² to 1 × 10 ¹⁴ atoms / cm ² per unit area is implanted using an ion implantation apparatus to form a low concentration N-type conductive region. P +, As +, etc. are used for the ion species 16. Thereafter, the same steps as those in FIGS. 1E to 1G of the first embodiment described above are performed.

In order to analyze the effect of the present invention, the impurity concentration at the drain end (side surface on the drain side of the electrode 14) of the TFT manufactured according to the second embodiment described above was calculated using a simple numerical simulation. The results as shown in FIGS. 4 to 6 were obtained. In this simulation, P + is used as the ion species 16 in the low-concentration ion implantation step of FIG. 2C, and the condition for the subsequent activation treatment is 1000 ° C. and N ₂ atmosphere treatment for 9 minutes. This is a calculation of the impurity concentration at the drain end using a first-order approximation neglected. As the impurity concentration, a relative impurity concentration normalized by the peak concentration of the LDD region is used.

  FIG. 4 shows a conventional TFT without an offset, that is, an offset length Loff = 0, and FIG. 5 shows a TFT according to the second embodiment described above, where the offset length Loff is set to 0.2 μm. FIG. 6 shows the TFT according to the second embodiment, and shows the case where the offset length Loff is set to 0.4 μm. FIG. 6A is a cross-sectional view of the main part, and FIG. The normalized impurity concentration profile after activation processing corresponding to each offset length is shown. 4B, FIG. 5B, and FIG. 6B, the vertical axis indicates the normalized concentration, and the horizontal axis indicates the drain end (the side on the drain side of the gate electrode 14) X = 0. The measured dimensions (μm) are shown.

  4A, 5A, and 6A, 12A represents a region where the impurity P is diffused in the active layer 12, and 12B represents an intrinsic channel region where the impurity P does not diffuse. As described above, 11 represents a substrate, 12 represents an active layer, 13 represents a gate insulating film, 14 represents a gate electrode, and 22 represents a sidewall spacer formed of a silicon nitride film.

In FIG. 4B, FIG. 5B, and FIG. 6B, the impurity concentration at the drain end where the horizontal axis X = 0 is “1.00” when Loff = 0 μm, and Loff = 0.2 μm. In some cases, it is “4.62E ⁻¹ ”, and in the case where Loff = 0.4 μm, it is “4.57E ⁻² ”, and it can be seen that the impurity concentration decreases as the offset length increases. Therefore, the electric field relaxation effect at the drain end can be expected.

Next, the off-current characteristics of the TFT manufactured according to the present embodiment are shown in FIG. The dimensions of each part of the manufactured TFT are L length (gate electrode length) = 2.5 μm, offset length Loff = 0 to 0.4 μm, mask LDD length = 0.9 to 1.3 μm (including offset length). The active heat treatment condition is a heat treatment in a batch diffusion furnace at 1000 ° C. for 9 minutes in an N ₂ atmosphere. Current values at Vds = 10V and Vgs = −6V are used for the off characteristics of the TFT, and the values are shown relative to the values at the mask LDD length of 0.9 μm. From the figure, it is apparent that the TFT manufactured according to this embodiment has better off-current characteristics. That is, in a TFT manufactured according to the prior art without an offset region, the off-current is reduced only to 0.65 even if the mask LDD length is extended from 0.9 μm to 1.3 μm. On the other hand, the off current of the TFT manufactured according to the present embodiment provided with the offset region is reduced to 0.43, and the characteristics are clearly excellent.

  Further, when Loff = 0.2 μm and the mask LDD length is 1.1 μm, the off-current is 0.54, although the mask LDD length is smaller than 0.65 of the conventional mask LDD length of 1.3 μm. The characteristics are excellent. This is nothing but the effect due to the decrease in the impurity concentration at the drain end described above with reference to FIGS. Therefore, by applying the present invention, it is not necessary to make the mask LDD length longer than necessary, and a fine and high-performance TFT (semiconductor device) can be manufactured.

  The embodiment described above is described for facilitating the understanding of the present invention, and is not described for limiting the present invention. Therefore, each element disclosed in the above embodiment is intended to include all design changes and equivalents belonging to the technical scope of the present invention. For example, in the above-described embodiment, an N-channel TFT has been described as an example. However, in the case of a P-channel TFT, an ND TFT and a source / drain region other than the step of implanting an impurity corresponding to the P-type conductivity type may be used. This is the same as in the case of a channel TFT, and the present invention can be similarly applied.

FIG. 1 is a diagram showing a manufacturing process of a TFT according to the first embodiment of the present invention. FIG. 2 is a view showing a manufacturing process of a TFT according to the second embodiment of the present invention. FIG. 3 is a view showing a manufacturing process of a TFT according to the third embodiment of the present invention. FIG. 4 is a diagram showing an impurity concentration profile when the offset length is 0 μm. FIG. 5 is a diagram showing an impurity concentration profile when the offset length is 0.2 μm. FIG. 6 is a diagram showing an impurity concentration profile when the offset length is 0.4 μm. FIG. 7 is a diagram showing the off-current characteristics of a TFT manufactured according to an embodiment of the present invention in comparison with a TFT manufactured according to the prior art. FIG. 8 is a diagram showing a TFT manufacturing process according to the prior art.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 11 ... Board | substrate, 12 ... Active layer, 13 ... Insulating layer, 14 ... Gate electrode, 15 ... Insulating film, 16 ... Ion seed | species, 17 ... Resist, 18 ... Ion seed | species, 19 ... Insulating layer, 20 ... Source-drain electrode.

Claims (5)

A method for manufacturing a semiconductor device, comprising:
Forming a first insulating film on the semiconductor film;
Forming a gate electrode on the first insulating film;
Forming a second insulating film having a predetermined width on at least a side surface of the gate electrode;
Implanting low-concentration impurities into the semiconductor film using the gate electrode and the second insulating film as a mask;
Forming a resist film on at least a side surface of the second insulating film;
Implanting high-concentration impurities into the semiconductor film using the gate electrode, the second insulating film, and the resist film as a mask;
And a step of diffusing impurities implanted into the semiconductor film.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the width of the second insulating film is set to 0.4 [mu] m or less.   A thin film transistor manufactured using the method for manufacturing a semiconductor device according to claim 1. A liquid crystal panel in which liquid crystal is sealed between a pixel substrate having a pixel electrode and a switching element, and a counter substrate having a counter electrode,
A liquid crystal display device comprising the thin film transistor according to claim 3 as the switching element.   A projection type liquid crystal projector comprising the liquid crystal panel according to claim 4.

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