JP2005150148A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device being capable of easily forming a re-wiring having a required shape and a required size and having an excellent productivity and a high performance. <P>SOLUTION: The semiconductor device is composed of a plurality of first bonding pads 2, a passivation film 3 protecting a circuit forming surface 1, a first insulating film 4 formed on the film 3, and a stress relaxation layer 5 formed on the first insulating film 4. The semiconductor device is further composed of the re-wiring 6 in which one end is connected to the first bonding pad 2 and second bonding pad 8 formed at the other end is arranged on the layer 5, a second insulating film 7 protecting the re-wiring 6, and bump electrodes 9 set to the second bonding pads 8. The outer-peripheral wall surface 5a of the layer 5 is formed in an inclined plane of approximately 5 to 30°, and the directions of the routing of all the re-wiring 6 on the wall surface 5a are set in the vertical or inclined directions to the direction of the upper edge or lower edge of the wall surface 5a. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a CSP (Chip Size Package) type semiconductor device in which rewiring is performed on a circuit formation surface, and more particularly, to a stress relaxation in a CSP type semiconductor device in which a stress relaxation layer is provided under a bump electrode. The present invention relates to the layer configuration and the direction of rewiring routed on the stress relaxation layer.

  In recent years, in order to cope with the demands for smaller, lighter, faster and more advanced electrical equipment, there are increasing demands for smaller, lighter, higher integration and easier mounting of semiconductor devices mounted on electrical equipment. ing.

  Conventionally, as a semiconductor device capable of responding to each of these requirements, as shown in FIG. 5, a first bonding pad (aluminum pad) 2 arranged along the periphery and a first circuit for protecting the circuit forming surface 1 are used. A passivation film (first insulating film) 3 formed on the circuit formation surface 1 excluding the formation portion of one bonding pad 2, a stress relaxation layer 5 formed in a bump electrode array region on the passivation film 3, and a passivation A rewiring 6 formed on the film 3 and the stress relaxation layer 5 and having one end connected to the first bonding pad 2, a second insulating film 7 for protecting the rewiring 6, and the other end of the rewiring 6 A semiconductor device called CSP having a bump electrode 9 set on a second bonding pad 8 formed on the semiconductor device has been proposed (see Patent Document 1).

  In this CSP type semiconductor device, the bump electrode 9 can be disposed on almost the entire surface of the circuit formation surface 1, so that the bump electrode 9 is formed directly on the first bonding pads 2 arranged along the periphery. In comparison, the distance between the bump electrodes 9 can be increased, so that the number of terminals of the semiconductor device can be increased, so that the functionality can be improved and the mounting on the electric device can be facilitated. In addition, since the CSP type semiconductor device does not encapsulate the semiconductor element, the semiconductor device can be reduced in size and weight. Furthermore, since this CSP type semiconductor device is provided with the stress relaxation layer 5 under the bump electrode 9, when the semiconductor device is mounted on the wiring board on the electric equipment side via the bump electrode 9, the semiconductor device and the wiring Thermal stress resulting from the difference in thermal expansion coefficient with the substrate is less likely to act between the bump electrode 9 and the wiring substrate and between the bump electrode 9 and the second bonding pad 8, and the connection reliability of each part can be improved. Thus, the durability of the semiconductor device can be improved.

  As a method for forming the stress relieving layer 5, in Patent Document 1, after a photosensitive insulating material film having a uniform thickness is formed on the first bonding pad 2 and the passivation film 3, the photosensitive insulating material film is exposed. A method has been proposed in which an opening not having the stress relaxation layer 5 is formed in a portion where the first bonding pad 2 is formed by sequentially performing and development. According to this method, as shown in FIGS. 6A to 6D, the outer peripheral wall surface 5a of the stress relaxation layer 5 has a wedge shape or a wedge shape having round corners, or a round or sloped chamfer at the corner portions. Formed on a vertical surface.

  Further, as a method for forming the rewiring 6, in Patent Document 1, as shown in FIG. 7, a plating power supply comprising a titanium film on a passivation film 3 and a stress relaxation layer 5 and a copper film laminated thereon. A step of forming a film by sputtering or the like (procedure S11), a step of applying a negative photoresist layer on the plating power supply film to a uniform thickness (procedure S12), and applying a negative photoresist layer to the second bonding pad 8 A step of exposing the shape of the rewiring 6 to be included (procedure S13), a step of removing the exposed portion by development processing to expose the plating power supply film corresponding to the exposed portion (step S14), and a thickness on the exposed plating power supply film. The step of electrolytic plating the metal film layer (procedure S15), the step of removing the remaining negative photoresist layer and exposing the plating power feeding layer on which the thick metal film layer is not laminated ( In step S16), the plating power supply film and the thick metal layer are etched, and the difference in film thickness between the portion where the plating power supply film exists alone and the portion where the thick film metal layer exists on the plating power supply film is used. There has been proposed a method including a step (step S <b> 17) of selectively forming the thick film metal layer laminated on the plating power feeding film and forming the rewiring 6.

  In addition, as a method for forming the rewiring 6, as shown in FIG. 8, a step of forming a plating power supply film by uniformly sputtering chromium or copper on the passivation film 3 and the stress relaxation layer 5 (procedure S21). ), A step of forming a photoresist layer on the plating power supply film with a uniform thickness (procedure S22), a step of exposing the photoresist layer to the shape of the rewiring 6 including the second bonding pad 8 (procedure S23), The step of removing the unexposed portion by development processing to expose the plating power supply film corresponding to the unexposed portion (step S24), the step of removing the exposed plating power supply film by chemical etching (step S25), and the remaining photoresist The step of removing the layer by ashing to expose the plating power supply film corresponding to the exposed portion (step S26), and copper plating on the exposed plating power supply film Which comprises the step (Step S27) for forming a rewiring 6 including a second bonding pad 8 and have been proposed conventionally.

As described above, when the outer peripheral wall surface 5a of the stress relaxation layer 5 is formed in a wedge shape, a wedge shape having round corners, or a vertical surface having chamfered round corners or slopes, Since it is difficult to uniformly form a plating power supply film having a thickness equivalent to the planar portion of the stress relaxation layer 4, it is difficult to stack a uniform thick film metal layer on the plating power supply film. In the semiconductor device described in FIG. 5, in order to suppress the increase in wiring resistance by shortening the routing length of the rewiring 6 as much as possible, as shown in FIG. The routing direction of the rewiring 6 is designed so as to be orthogonal to each other.
JP-A-11-054649

  By the way, in this type of semiconductor device, in order to facilitate the formation of the stress relaxation layer 5 and to reduce the cost of the semiconductor device, a semiconductor device manufacturing method in which the stress relaxation layer 5 is formed by a screen printing method has been conventionally used. Proposed. The outer peripheral wall surface 5a of the stress relaxation layer 5 formed by the screen printing method causes the stress relaxation layer material to flow in a viscous manner after the metal mask is pulled up. Therefore, as shown in FIG. It will be a gentle slope of degree.

  For the outer peripheral wall surface 5a formed on a gentle slope having an inclination angle of about 5 degrees to 30 degrees, a plating power supply film having a thickness equivalent to the planar portion of the stress relaxation layer 5 can be uniformly formed by sputtering or the like. A uniform thick metal film layer can be laminated on the plating power supply film, and the rewiring 6 can be routed in the direction of the outer peripheral wall surface 5a as shown in FIG. The degree of freedom can be increased.

  However, when the rewiring 6 is routed in the formation direction of the outer peripheral wall surface, when the rewiring 6 forming method shown in FIG. 7 is adopted, after the development of the photoresist layer, as shown in FIG. The developer Ld of the photoresist layer tends to remain in the corners of the film 6a and the photoresist layer 10, and the inconvenience that the thick metal layer 6b having the required shape and the required size is not laminated on the plating power supply film 6a is likely to occur. . Further, when the method of forming the rewiring 6 of FIG. 8 is adopted, after the unnecessary plating power supply film is etched, as shown in FIG. 11B, the stress relaxation layer 5, the plating power supply film 6a, and the photoresist layer 10 are formed. The etching solution Le tends to remain in the corners of the metal film, and an undercut is generated in the plating power supply film 6a, so that the inconvenience that the rewiring 6 having a required shape and a required dimension is not formed is likely to occur.

  The present invention has been made to solve such deficiencies of the prior art, and has an object of being able to easily form rewiring of a required shape and required dimensions, and having excellent productivity and high performance. It is to provide a semiconductor device.

  In order to solve the above problems, the present invention is formed on the circuit formation surface excluding a plurality of first bonding pads arranged along the outer periphery of the circuit formation surface and a formation portion of the first bonding pad. An insulating film, a stress relaxation layer formed in a bump electrode array region on the insulating film, a rewiring formed on the insulating film and the stress relaxation layer, and having one end connected to the first bonding pad And a plurality of second bonding pads formed on the other end of the rewiring and disposed on the stress relaxation layer, and the outer peripheral wall surface of the stress relaxation layer is 5 degrees to the circuit formation surface. In a semiconductor device formed in a slope shape inclined at an angle of 30 degrees, the routing direction of all the rewirings on the outer peripheral wall surface is directed to the upper edge or the lower edge of the outer peripheral wall surface on which the rewiring is formed. Perpendicular to And the configuration that is set in a direction inclined.

  As described above, when the rewiring direction formed on the outer peripheral wall surface of the stress relaxation layer is set to a direction perpendicular to or inclined with respect to the direction of the upper edge or the lower edge of the outer peripheral wall surface on which the rewiring is formed. In addition, surplus developer and etchant are likely to flow out along the photoresist layer during manufacturing, so that retention of surplus developer and etchant can be suppressed. Therefore, it is possible to easily form a rewiring having a required shape and a required dimension, and it is possible to improve the yield of non-defective products and improve the performance of the semiconductor device.

  In the semiconductor device having the above configuration, the rewiring direction is set in a range of 45 degrees to 135 degrees with respect to the direction of the upper edge or the lower edge of the outer peripheral wall surface on which the rewiring is formed. It was configured to do.

  In this way, if the rewiring direction is set in the range of 45 degrees to 135 degrees with respect to the direction of the upper edge or the lower edge of the outer peripheral wall surface on which the rewiring is formed, excess developer or etching solution flows out. And the retention of excess developer and etchant can be further reduced, making it possible to easily form the rewiring of the required shape and required dimensions and improve the yield of non-defective products. In addition, the performance of the semiconductor device can be improved.

  Further, according to the present invention, in the semiconductor device having the above configuration, the set density of the first bonding pads at the four corners of the circuit formation surface is greater than the set density of the first bonding pads at the middle portion of the four sides of the circuit formation surface. The structure was also high.

  When the inclination angle of the outer peripheral wall surface of the stress relaxation layer is formed on a gentle slope of about 5 to 30 degrees, a plating power supply film having the same thickness as the other surface of the stress relaxation layer is uniformly formed on the outer peripheral wall surface by sputtering or the like. Since a uniform thick film metal layer can be laminated on the plating power supply film, rewiring can be routed in an arbitrary direction. Accordingly, rewiring can be formed even in a semiconductor device in which the setting density of the first bonding pads at the four corners of the circuit formation surface is higher than the setting density of the first bonding pads at the middle part of the four sides of the circuit formation surface. It is possible to make a CSP chip of a kind of semiconductor device.

  According to the present invention, in the semiconductor device having the above-described configuration, the rewiring on the outer peripheral wall surface of the stress relaxation layer is a straight line.

  Thus, if the rewiring on the outer peripheral wall surface of the stress relaxation layer is formed in a straight line, the outflow of excess developer and etching solution can be promoted, and the retention of excess developer and etching solution is further reduced. Therefore, it is possible to easily form a rewiring having a required shape and a required dimension, improve the yield of non-defective products, and improve the performance of the semiconductor device.

  In the semiconductor device of the present invention, the direction of the rewiring formed on the outer peripheral wall surface of the stress relaxation layer is perpendicular to or inclined with respect to the direction of the upper edge or the lower edge of the outer peripheral wall surface on which the rewiring is formed. Therefore, it is possible to suppress the retention of excess developer and etching solution during manufacturing, and it is possible to easily form a rewiring of a required shape and a required dimension, thereby improving the yield of non-defective products and High performance of the semiconductor device can be achieved.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, a semiconductor device according to an embodiment of the invention will be described with reference to FIGS. 1 is a plan view of the semiconductor device according to the embodiment from which the second insulating film is removed, FIG. 2 is a cross-sectional view taken along the line AA in FIG. 1, FIG. 3 is an enlarged view of a B part in FIG. It is a flowchart which shows the manufacturing method of the semiconductor device which concerns.

  As shown in FIGS. 1 and 2, the semiconductor device of the present example includes a plurality of first bonding pads 2 arranged along the outer periphery of the circuit forming surface 1 and a first for protecting the circuit forming surface 1. Passivation film 3 formed on circuit formation surface 1 excluding the formation portion of bonding pad 2, first insulating film 4 formed on passivation film 3, and bump electrode array region on first insulating film 4 In order to protect the rewiring 6, the rewiring 6 formed on the first insulating film 4 and the stress relieving layer 5 and having one end connected to the first bonding pad 2. A second insulating film 7 formed on the first insulating film 4 and the stress relaxation layer 5 and a bump electrode 9 set on the second bonding pad 8 formed on the other end of the rewiring 6 are configured. First in the four corners of the circuit forming surface 1 Setting the density of emission loading pad 2 is higher than the set density of the first bonding pads 2 at the intermediate portion of the four sides of the circuit forming surface 1. On the circuit forming surface 1, a semiconductor circuit (not shown) composed of a required semiconductor element group is formed by a wafer process.

  The first bonding pad 2 and the passivation film 3 are formed by a normal wafer process. The first insulating film 4, the stress relaxation layer 5, the rewiring 6 including the second bonding pad 8, the second insulating film 7, and the bump electrode are formed. 9 is formed in a rewiring process after the wafer process is completed.

  The first insulating film 4 is made of a photosensitive resin material such as a photosensitive polyimide resin, and is formed on the circuit forming surface 1 excluding the central portion of the first bonding pad 2 as shown in FIG. The first insulating film 4 is formed so as to cover the opening end of the first bonding pad 2 in order to prevent damage to the first bonding pad 2 when the rewiring 6 is formed. The first insulating film 4 is formed by applying a resin layer made of a photosensitive resin material to a uniform thickness on a circuit forming surface of a silicon wafer serving as a semiconductor device, and then applying the resin layer to the first insulating film. The exposed portion is exposed to the shape of the film 4 to cure the exposed portion, and then the unexposed portion is removed by development processing. If the passivation film 3 has sufficient insulation, the formation of the first insulating film 4 can be omitted and the stress relaxation layer 5 can be formed directly on the passivation film 3.

The stress relaxation layer 5 is formed on the inner peripheral portion of the first insulating film 4 excluding the setting portion of the first bonding pad 2 by screen printing a polyimide resin softer than the first insulating film 4. As shown in FIG. 1, the stress relaxation layer 5 of this example is formed in a substantially quadrangular plan shape, and on the outer peripheral portion, as shown in FIG. 2, the stress relaxation layer material after the metal mask is pulled up is formed. Due to the viscous flow, an outer peripheral wall surface 5a made of a gentle slope having an inclination angle θ of 5 degrees to 30 degrees with respect to the circuit forming surface 1 is formed. Note that the upper edge 5a ₁ of the outer peripheral wall surface 5a, not sharp-edged, as shown in FIG. 2, there is a case made of an arc shape. The stress relaxation layer is formed by positioning and arranging a metal mask having a through hole for forming the stress relaxation layer on the first insulating film 4, potting the stress relaxation layer material on the metal mask, The step of spreading the stress relaxation layer material with a squeegee and filling it into the through hole of the metal mask, the step of lifting the metal mask from the first insulating film 4, and the stress relaxation formed on the first insulating film 4 It is performed through a step of drying the layer 5.

The rewiring 6 including the second bonding pad 8 is formed of a conductor such as copper plating, and is arranged on the first insulating film 4 and the stress relaxation layer 5 as shown in FIGS. One end of the rewiring 6 is connected to the first bonding pad 2, and the second bonding pad 8 at the other end is formed on the stress relaxation layer 5 in a required arrangement. Then, on the outer peripheral wall surface 5a of the stress relaxation layer 5, in order to make it possible to easily form a rewiring having a required shape and a required dimension, as shown in FIG. but it is set in a direction perpendicular or inclined to the direction X-X of the upper edge 5a ₁ or lower edge 5a ₂ of the outer peripheral wall surface 5a of the rewiring is formed, and is formed in a linear shape. When set to a direction inclined to lead direction Y-Y of the rewiring 6 with respect to the orientation X-X of the upper edge 5a ₁ or lower edge 5a ₂ of the outer peripheral wall surface 5a, as shown in FIG. 3, the inclination It is particularly preferable to set the angle ψ in the range of 45 degrees to 135 degrees. The rewiring 6 can be formed by the above-described forming method of FIG. 10 or the forming method of FIG.

  The second insulating film 7 is made of a photosensitive resin material such as a photosensitive polyimide resin harder than the stress relaxation layer 5, and as shown in FIG. 2, the first insulating film excluding the central portion of the second bonding pad 8. 4 and on the stress relaxation layer 5. The second insulating film 7 is also formed by the same method as the first insulating film 4.

  The bump electrode 9 is formed of a solder ball formed by soldering in a ball shape, a coating solder ball obtained by coating the surface of a resin ball with solder, or other ball-like conductive material, and arranged on the stress relaxation layer 5. It is mounted on each second bonding pad 8.

  As shown in FIG. 4, in the semiconductor device according to the embodiment, the first insulating film 4 is formed on the passivation film 3 of the silicon wafer on which the required circuit formation surface 1 and the passivation film 3 are formed by the wafer process. Step of forming (procedure S1), step of forming stress relaxation layer 5 on first insulating film 4 (procedure S2), rewiring 6 including second bonding pad 8 on first insulating film 4 and stress relaxing layer 5 Forming the second insulating film 7 on the outer surface of the rewiring 6, the first insulating film 4 and the stress relaxation layer 5 (procedure S 4), and forming the bump electrode 9 on the second bonding pad 8. Is manufactured through a step of setting (step S5) and a step of dicing the silicon wafer to take out pieces of the semiconductor device (step S6). If the passivation film 3 has sufficient insulation, the step of forming the first insulating film 4 on the passivation film 3 (procedure S1) can be omitted.

The semiconductor device of this example, stress leading direction Y-Y of the re-wiring 6 is formed on the outer peripheral wall surface 5a of the relaxation layer 5, the upper edge 5a ₁ of the outer peripheral wall surface 5a of the rewiring 6 is formed or lower edge Since it is set in a direction perpendicular to or inclined with respect to the direction XX of 5a ₂ , excess developer or etching solution tends to flow out along the photoresist layer 10 at the time of manufacturing, and excess developer or etching solution is retained. Can be suppressed. Therefore, rewiring with a required shape and required dimensions can be easily formed, and the yield of non-defective products can be improved and the performance of the semiconductor device can be improved.

Further, in the semiconductor device of this example, the upper edge 5a ₁ or the lower edge 5a _{2 of the} outer peripheral wall surface 5a on which the rewiring 6 is formed in the routing direction YY of the rewiring 6 on the outer peripheral wall surface 5a of the stress relaxation layer 5. Is set in the range of 45 degrees to 135 degrees with respect to the direction, the flow of excess developer and etchant during manufacture becomes easier, and the retention of excess developer and etchant can be further reduced. Therefore, rewiring with a required shape and required dimensions can be easily formed, and the yield of non-defective products can be improved and the performance of the semiconductor device can be improved.

Furthermore, the semiconductor device of this example, stress leading direction Y-Y of the re-wiring 6 is formed on the outer peripheral wall surface 5a of the relaxation layer 5, the upper edge 5a ₁ of the outer peripheral wall surface 5a of the rewiring 6 is formed or Since the direction is set to be perpendicular or inclined with respect to the direction XX of the lower edge 5a _2, the degree of freedom of the routing pattern of the rewiring 6 can be increased, and the first bonding pads 2 at the four corners of the circuit forming surface 1 can be increased. Also, a semiconductor device having a set density higher than the set density of the first bonding pads 2 in the middle part of the four sides of the circuit forming surface 1 can be easily formed with rewiring, and this type of semiconductor device can be formed into a CSP chip. be able to.

  In addition, since the semiconductor device of this example forms the rewiring 6 on the outer peripheral wall surface 5a of the stress relaxation layer 5 in a straight line, the outflow of excess developer and etching solution can be promoted, and excess development. Since the retention of the solution and the etching solution can be further reduced, it becomes possible to easily form the rewiring 6 having the required shape and the required size, improve the yield of non-defective products, and improve the performance of the semiconductor device. Can be achieved.

It is the top view which removed the 2nd insulating film of the semiconductor device concerning an embodiment. It is an AA section sectional view of Drawing 1. It is the B section enlarged view of FIG. It is a flowchart which shows the manufacturing method of the semiconductor device which concerns on embodiment. It is a perspective view of the semiconductor device which concerns on a prior art example. It is principal part sectional drawing which shows the shape of the outer peripheral wall surface of the stress relaxation layer in the semiconductor device which concerns on a prior art example. It is a flowchart which shows the 1st example of the rewiring formation method. It is a flowchart which shows the 2nd example of the rewiring formation method. It is principal part sectional drawing which shows the shape of the outer peripheral wall surface of the stress relaxation layer formed by the screen printing method. It is the top view which removed the 2nd insulating film of the semiconductor device which concerns on a prior art example. It is principal part sectional drawing which shows the defect of the semiconductor device which concerns on a prior art example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Circuit formation surface 2 1st bonding pad 3 Passivation film 4 1st insulating film 5 Stress relaxation layer 5a Perimeter wall surface 6 Rewiring 7 2nd insulating film 8 2nd bonding pad

Claims (4)

A plurality of first bonding pads arranged along the outer periphery of the circuit forming surface, an insulating film formed on the circuit forming surface excluding a portion where the first bonding pad is formed, and a bump electrode on the insulating film A stress relieving layer formed in the arrangement region; a rewiring formed on the insulating film and the stress relieving layer; one end connected to the first bonding pad; and the other end of the rewiring formed on the other end. A plurality of second bonding pads disposed on the stress relieving layer, and an outer peripheral wall surface of the stress relieving layer is formed in a slope shape inclined at an angle of 5 degrees to 30 degrees with respect to the circuit forming surface. In semiconductor devices
A semiconductor device characterized in that a routing direction of all the rewirings on the outer peripheral wall surface is set to a direction perpendicular to or inclined with respect to the direction of the upper edge or the lower edge of the outer peripheral wall surface on which the rewiring is formed. .   2. The semiconductor according to claim 1, wherein a direction in which the rewiring is routed is set in a range of 45 degrees to 135 degrees with respect to a direction of an upper edge or a lower edge of an outer peripheral wall surface on which the rewiring is formed. apparatus.   The set density of the first bonding pads at the four corners of the circuit forming surface is higher than the set density of the first bonding pads at an intermediate portion of the four sides of the circuit forming surface. Semiconductor device.   The semiconductor device according to claim 1, wherein the rewiring on the outer peripheral wall surface of the stress relaxation layer is a straight line.

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