JP2005142749A - Optical packet head timing synchronizing method and optical packet head timing synchronizing device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a resetting method which is adaptive to an arbitrary length and asynchronous optical packet and a device therefor. <P>SOLUTION: The optical packet inputted to the optical packet head timing synchronizing device 10 is branched into two; and the optical packet of one side is guided to a heat timing synchronizing signal generating circuit 11 via an optical delay line 13 and the optical packet of the other is guided to a reset signal generating circuit 12. The output signal from the reset signal generating circuit 12 is used as a reset signal for the head timing synchronizing signal generating circuit 11. Since the fixed optical delay line 13 is interposed between the two-branches of the optical packet and the head timing synchronizing signal generating circuit 11, resetting operation is completed in a guard time between the optical packets without fail in whatever timing the optical packet reaches the head timing synchronizing signal generating circuit 11, the circuit correctly operates for not only an input of a synchronous optical packet sequence, but also an input of an asynchronous optical packet sequence. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an optical packet head timing synchronization method and an optical packet head timing synchronization device, and more particularly to an optical packet head timing synchronization method capable of handling an arbitrary length, asynchronous optical packet and an apparatus based on the method.

  As an effective method for synchronizing the switches in the nodes of the high-speed optical packet communication network, each node extracts the leading marker pulse of the incoming optical pulse (or generates a single optical pulse synchronized with the leading marker pulse) In addition, a method (self-synchronization method) for reconstructing a local clock light for switch control based on a single optical pulse for each extracted (or generated) packet is known. The effectiveness of the self-synchronization method is that instantaneous timing extraction from burst optical packets can be easily performed, and that a single optical pulse extracted (generated) has a high level of timing accuracy applicable to sequential bit processing of optical packets. By having.

  An example of a conventional single optical clock pulse generation circuit that can be applied to the self-synchronization method is a leading optical pulse extraction circuit using a SOA (Semiconductor Optical Amplifier) asymmetric arrangement ring interferometer (for example, Non-Patent Document 1). However, since this circuit uses SOA mutual gain modulation, it is difficult to achieve both high input sensitivity and high output extinction ratio. There is a problem that there are many restrictions on the optical intensity and format of an optical packet, such as the need to preamble a continuous bit of a value “1” (High level) that is zero at the beginning of the packet.

  In view of such a problem, by generating a stepped electric signal by the incidence of the head marker pulse and detecting the rising timing of the step electric signal, the head is not affected by the second and subsequent input pulses. A method for generating a single optical clock pulse for each packet synchronized in timing with only a marker pulse and a device using a photoconductive sample-hold circuit have been proposed (see Patent Document 1 and Patent Document 2). According to these methods and apparatuses, it is not necessary to insert a preamble having no information (that is, without reducing bit utilization efficiency), and both high input sensitivity and high output extinction ratio are achieved, Furthermore, it is possible to provide a method and circuit for generating a single optical clock pulse for self-synchronization that can be applied to a high-speed optical packet exceeding 40 Gbit / s.

JP 2002-148574 A JP 2002-135208 A IEEE Photon Technol. Lett., Vol.11, p.1310 (1999).

  However, when executing the packet synchronization method using such step signal generation, the step signal generated by receiving the leading marker pulse of the packet may be reset during the guard time until the next optical packet arrives. Necessary.

  An object of the present invention is to provide a step signal reset method and apparatus required for a packet synchronization method using step signal generation, and particularly when the packet length and the packet rate fluctuate with time. An object of the present invention is to provide a reset method and apparatus capable of dealing with an arbitrary-length, asynchronous optical packet that can be applied.

  In order to achieve such an object, the present invention provides an optical packet head timing synchronization method for generating a signal synchronized with a head bit of an input optical packet (finite length optical pulse train). The first optical packet is branched into two, and one optical packet is input to the reset signal generating means, and the other optical packet is input to the synchronization signal generating means at a timing delayed from the input to the reset signal generating means. And a second step of resetting the operation of the synchronization signal generating means by a reset signal generated by the reset signal generating means based on the one optical packet, and resetting in the second step The operation is performed within a guard time between the input optical packets.

  Preferably, in the second step, the response time constant (reciprocal of band) TRS of the optical receiving means included in the reset signal generating means is longer than the longest zero continuous time included in the optical packet and the guard It is set shorter than the time, and one reset signal corresponding to each of the input optical packets is generated.

  Preferably, in the second step, one step signal (rectangular wave signal) generated by the optical receiving unit and corresponding to each of the optical packets is converted by the pulsing unit included in the reset signal generating unit. The signal is converted into one pulse signal corresponding to each optical packet, and the pulse signal is used as the reset signal.

  Further preferably, in the second step, a zero signal portion of a signal sequence of a step signal (rectangular wave signal) generated by the optical receiver and corresponding to each of the optical packets is used as the reset signal.

  A second invention is an optical packet head timing synchronization method for generating a signal synchronized with a head bit of an input optical packet, the timing signal output from the synchronization signal generating means in response to the input of the input optical packet A first step of branching into two, and one of the two branched timing signals is used as an output signal, and a predetermined delay is given to the other timing signal to serve as a reset signal for the synchronization signal generating means. These steps are provided.

  A third invention is an optical packet head timing synchronization device, comprising: a branching means for branching an input optical packet into two parts; a reset signal generating means for inputting one of the two branched optical packets; and the other optical packet. An input sample hold (S / H) means, and an optical delay means provided between the branching means and the S / H means, wherein the S / H means S / H means for generating a synchronization signal in which a predetermined voltage value is sampled and held by reception of a leading optical pulse, and the reset signal generating means transmits a reset signal based on the one optical packet to the S / H means. Reset signal generating means for resetting the operation of the S / H means, and the reset operation is configured to be executed within a guard time between the input optical packets. And said that you are.

  Preferably, the reset signal generating means includes an optical receiving means, and a time constant TRS of response of the optical receiving means is set longer than the longest zero continuous time included in the optical packet and shorter than the guard time. The reset signal corresponding to each of the input optical packets is generated one by one.

  Preferably, one step signal (rectangular wave signal) generated by the optical receiving unit and corresponding to each of the optical packets is corresponded to each of the optical packets by the pulsing unit included in the reset signal generating unit. The signal is converted into one pulse signal, and the pulse signal is used as the reset signal.

  Preferably, one step signal (rectangular wave signal) generated by the optical receiving means and corresponding to each of the optical packets is used as a hold signal for the S / H means, while the signal sequence of the step signal is zero. The signal portion is used as the reset signal.

  Preferably, the pulsing means includes a two-output type voltage level identification circuit having an inverting output and a non-inverting output, a two-input type AND logic gate circuit, and two inputs to the AND logic gate circuit. Means for providing different delays.

  Further, preferably, the S / H means includes a light receiving element that performs light-current conversion of an input optical packet, a capacitor that holds a photoelectric current generated by the light receiving element as an electric charge and generates an output voltage, and the hold A photoconductive S / H circuit including a switch for discharging and resetting a charge.

  According to the present invention, a reset method (optical packet head timing synchronization method) that can be applied to an arbitrary length, asynchronous optical packet, and an apparatus (optical packet) that can be applied even when the packet length and packet rate fluctuate with time. It is possible to provide a head timing synchronization device.

Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a diagram for explaining a configuration of an optical packet head timing synchronization method of the present invention and an optical packet head timing synchronization device of the present invention based on this method. The device called “optical packet head timing synchronization device” used in this specification is a device that generates a signal synchronized with the head bit of the received optical packet. The optical packet head timing synchronization device 10 shown in FIG. The timing synchronization signal generation circuit 11 and the reset signal generation circuit 12 are provided.

  The optical packet input to the optical packet head timing synchronizer 10 is branched into two, and one of the optical packets is guided to the head timing synchronization signal generation circuit 11 via the optical delay line 13 and the other optical packet is generated as a reset signal. Lead to circuit 12. The output signal from the reset signal generation circuit 12 is used as a reset signal for the head timing synchronization signal generation circuit 11.

  The reason why the fixed optical delay line 13 is inserted between the bifurcated portion (not shown) of the input optical packet and the head timing synchronization signal generation circuit 11 is that the input timing of the optical packet to the reset signal generation circuit 12 side This is because the timing is set so as to slightly precede the input timing of the optical packet to the head timing synchronization signal generation circuit 11 side. That is, when an optical packet is input to the optical packet head timing synchronization device 10, the head timing synchronization signal generation circuit 11 is first reset by the reset signal transmitted from the reset signal generation circuit 12, and then the reset is performed. The operation is performed in the order that the timing signal is generated by the optical packet received late.

  Therefore, no matter what timing the optical packet arrives at the leading timing synchronization signal generating circuit 11, the reset operation is within the guard time between the optical packets (that is, before receiving the leading optical pulse of the optical packet, and It is always executed within the time corresponding to the last optical pulse of the optical packet input immediately before, and not only for the input of the synchronous optical packet sequence but also for the input of the asynchronous optical packet sequence. Even in this case, the circuit can be operated correctly.

  FIG. 2 is a diagram for explaining a configuration example of a photoconductive sample-and-hold (S / H) circuit that can be used as such a head timing synchronization signal generating circuit 11. The photoconductive S / H circuit 20 is a circuit that charges a hold capacitor 21 with a photocurrent generated by reception of the first bit of an optical packet and generates a stepped electric signal by holding the charge.

  The rising timing of the output signal of the photoconductive S / H circuit 20 is accurately synchronized (with an accuracy of a few picoseconds) to the first bit of the input packet. It is not affected at all by subsequent bits after 2 pulses. Therefore, as shown in FIG. 2, the photoconductive S / H circuit 20 alone can be used as the leading timing synchronization signal generating circuit 11.

  Further, a head timing synchronization signal generation circuit of an optical pulse output type can be configured by a combination of a rising edge detection type pulsing circuit and a semiconductor laser.

  FIG. 3 is a diagram for explaining an example of the leading timing synchronization signal generating circuit having such a configuration. This leading timing synchronization signal generation circuit is configured by connecting a photoconductive S / H circuit 31, a rising detection pulse circuit 32, and a semiconductor laser 33 in this order. Is input to the rising detection pulse generator 32, and the pulsed modulation signal output from the rise detection pulse converter 32 is input to the semiconductor laser 33. The semiconductor laser 33 outputs a single pulse output having the first bit of the input optical packet and a fixed time delay Td.

  The configuration example of the photoconductive S / H circuit and the application example of the photoconductive S / H circuit to the leading timing synchronization signal generation circuit shown in FIGS. 2 and 3 are disclosed in Patent Document 1 and Patent Document 2.

  By the way, in order to apply a step signal generation circuit such as a photoconductive S / H circuit to the optical packet head timing synchronization device, the step signal generated by the input of the optical packet is guarded until the next optical packet arrives. Must be reset during time. If only a synchronous packet sequence with a fixed packet rate (time interval between the first bits of each packet) is processed, for example, a single pulse signal for each optical packet generated in the configuration of FIG. A reset method that can be used as a reset signal after a predetermined time delay corresponding to a predetermined packet interval is conceivable.

  FIG. 4 is a conceptual diagram of the configuration of an optical packet head timing synchronizer for explaining such a reset method. The optical packet head timing synchronizer 40 includes a head timing synchronization signal generation circuit 41 without branching the optical packet. And the output from the head timing synchronization signal generation circuit 41 is branched into two, and one of them is fed back to the head timing synchronization signal generation circuit 41 via the delay device 42 and the reset signal of the head timing synchronization signal generation circuit 41 is received. It is supposed to be configured.

  However, this reset method cannot cope with an asynchronous optical packet sequence in which the packet rate varies with time. As described above, the optical packet head timing synchronization device 10 shown in FIG. 1 branches the input optical packet into two, and guides one of the optical packets to the head timing synchronization signal generation circuit 11 via the optical delay line 13. At the same time, the other optical packet is guided to the reset signal generation circuit 12 and the output signal from the reset signal generation circuit 12 is used as the reset signal for the head timing synchronization signal generation circuit 11. This is to make it possible to handle columns.

  FIGS. 5 and 6 are first and second conceptual diagrams of the reset signal generating circuit used in the optical packet head timing synchronization apparatus of the present invention. The reset signal generation circuit 50 having the first configuration shown in FIG. 5 includes an optical reception circuit 51 having a response time constant (reciprocal of band) having a value of TRS and a rising detection type pulse circuit 52 connected in series. The reset signal generation circuit 60 of the second configuration shown in FIG. 6 is configured by connecting an optical reception circuit 61 having a time constant TRS and a level identification circuit 62 in series.

  The rising edge detection type pulsing circuit 52 can be configured as shown in FIG. 7, for example. That is, in the rising detection type pulsing circuit 52, a level identification circuit 71 to which an input signal is input and an AND logic circuit 72 to output an output signal are connected by two signal lines, and one of the signal lines is not connected. An inverted output is transmitted, and the other signal line is configured to transmit an inverted output with an electrical delay line 73 inserted. In the case of using the pulse forming circuit having the configuration shown in FIG. 7, the circuit having the first configuration includes the circuit having the second configuration.

  If the time constant TRS is set to be longer than the longest zero continuous time included in the optical packet and shorter than any guard time provided between the optical packets, these resets are performed. The operation waveform of the signal generation circuit is as shown in FIG.

  FIG. 8A shows a waveform of an input optical packet, and here, a case where three packets having different packet lengths and packet intervals are input is illustrated. Further, the case where the longest zero bit sequence is in the first input packet and the shortest guard time is the guard time between the first and second input packets is illustrated.

  FIG. 8B shows the output of the optical receiver circuit with the time constant TRS for the input packet sequence shown in FIG. The optical receiving circuit generates a signal when receiving an optical pulse in the packet, and the generated signal is attenuated by a time constant TRS during a period in which no optical pulse is input (during zero bit input and guard time in the packet). . With the above-described TRS setting, the signal attenuation at an arbitrary guard time is greater than the signal attenuation during any packet input. In other words, the minimum level of the output signal at any guard time is smaller than the minimum level of the output signal during any packet input. Accordingly, by appropriately setting the identification level of the voltage identification circuit at the subsequent stage, one rectangular wave signal that lasts for the input period of each packet can be obtained for one input optical packet.

  FIG. 8C and FIG. 8D are diagrams showing this rectangular wave signal. These correspond to the non-inverted output (FIG. 8C) and the inverted output (FIG. 8D) from the voltage level identification circuit, respectively. As shown in the figure, the duration of this rectangular wave signal is approximately a value obtained by adding the time constant TRS to the duration of each packet. The reset signal generation circuit having the second configuration shown in FIG. 6 outputs the rectangular wave signal shown in FIG. 8C or FIG. 8D.

  FIG. 8E is a diagram illustrating a pulse signal in which the rising edge of the non-inverted output signal from the identification circuit is detected. The output pulse width is set appropriately, and is indicated as TWRS in this figure. Due to the above-described TRS setting, one pulse signal shown in FIG. 8 (e) is generated for each input optical packet to form an electric pulse train having a pulse width TWRS.

  FIG. 9 is a diagram for explaining the configuration (and input / output waveforms) of the optical packet head timing synchronization device 90 configured using the reset signal generation circuit 50 and the photoconductive S / H circuit 20 of the first configuration. FIG. 10 is a diagram for explaining a timing chart in this apparatus configuration. In this device configuration, the pulse signal having the waveform shown in FIG. 8E is used as the reset signal.

  The condition for normal operation of the optical packet head timing synchronization device 90 is that a reset signal is supplied to a reset FET (see FIG. 2) that discharges the held charges during each guard time. ) Starts and ends. In FIG. 9, ti, trs, and ts indicate the input timing of the optical packet to the photoconductive S / H circuit 20, the reset start timing, and the set timing of the photoconductive S / H circuit 20, respectively. Indicates the delay value in the fixed optical delay line 13 inserted before the photoconductive S / H circuit 20.

  At this time, the above-described TWRS and τ1 are set as follows. That is, TWRS is set to be shorter than the shortest guard time, and τ1 is set to be τ1 = TWRS + Δ (Δ is a minute positive value). With these settings, the step signal generated by the reception of the previous optical packet is reset at time trs during the guard time after reception of the final optical pulse, and ti = trs + τ1 = trs + TWRS + Δ. Ends immediately before reception of the first optical pulse of the optical packet.

  Since this reset operation is automatically executed by a signal generated based on the packet itself every time an optical packet arrives, the apparatus operates normally even when an asynchronous packet sequence is input.

  In FIG. 10, S and R represent set and reset, respectively. The S / H circuit will be described as an example. The reset state is a state in which the FET for discharging electric charges is energized (a state in which the gate of the FET is opened) as described above. Is a state in which no current flows through the FET (a state where the gate of the FET is closed and the S / H circuit can hold the charge). As shown in this figure, “end of reset operation” described above is synonymous with “start of set operation”, and the S / H circuit is reset during the guard time, further set, and immediately after that. In response to the optical packet, a step signal is generated.

  Here, the delay time of the signal in the reset signal generation circuit is ignored, but this is a substantially constant value. For example, in a reset signal generation circuit in which TRS is set to 1 nanosecond, the uncertainty of the delay time can be at most 100 picoseconds. Therefore, when the circuit is actually operated, the circuit operates normally by adding “delay time of reset signal generation circuit + indeterminate amount” to τ1.

  FIG. 11 is a diagram for explaining the configuration (and input / output waveforms) of the optical packet head timing synchronization apparatus 100 configured using the reset signal generation circuit 60 and the photoconductive S / H circuit 20 of the second configuration. FIG. 12 is a diagram for explaining a timing chart in this apparatus configuration.

  The normal operation condition of the optical packet head timing synchronization apparatus 100 is that the reset operation is started and ended during each period of each guard time. In this apparatus configuration, a rectangular wave signal having the waveform shown in FIG. 8D is used as a set signal.

  As already described, this rectangular wave signal is a signal that persists during the input period of each packet, and is a signal that automatically attenuates and disappears during a guard time when there is no packet input. Therefore, by using this rectangular wave signal (the zero level portion in FIG. 8D) as a set signal (in other words, using a portion of the rectangular wave signal that is interrupted in time as a reset signal), there is no packet input. During the guard time, the circuit always stands by in a reset state.

  In FIG. 11, τ 2 indicates a delay value in the fixed optical delay line 13 inserted before the photoconductive S / H circuit 20. At this time, τ2 is set to τ2 = Δ (Δ is a minute positive value). With this setting, when an optical packet arrives in the standby state, first, the photoconductive S / H circuit 20 receives a signal from the reset signal generation circuit 60, and from the reset state to the set state (the S / H circuit holds the charge). Can be switched). Immediately after this, the photoconductive S / H circuit 20 receives the leading optical pulse of the optical packet and generates a step signal.

  Since the time constant TRS of the optical receiving circuit is set shorter than the guard time, when the packet ends, the set signal from the optical receiving circuit is interrupted during the guard time until the next packet arrives, and the S / H circuit Automatically returns to the always reset state. This completes the operation. Thus, the reset operation in this configuration is automatically performed with the end of the optical packet, and the set operation is automatically performed using a signal based on the incoming packet itself. Therefore, the apparatus operates normally even when an asynchronous packet sequence is input.

  In this case as well, the signal delay time in the reset signal generation circuit is ignored, but this is a substantially constant value. Similarly to the above, for example, in the reset signal generation circuit in which TRS is set to 1 nanosecond, the uncertainty of the delay time can be set to 100 picoseconds or less at most. Therefore, in actual operation of the circuit, the circuit operates normally by adding “delay time of reset signal generation circuit + indeterminate amount” to τ2.

  The reset signal generation circuit having the second configuration shown in FIG. 6 is configured using a high impedance type optical receiver circuit having a time constant TRS. FIG. 13 is a diagram for explaining the configuration of this high-impedance type time constant TRS optical receiver circuit. , V1 and V2 represent power supply voltages. The time constant TRS in this circuit configuration is approximately equal to the product of R and (Cpd + Ci). However, when defining TRS with “10% / 90% transition time”, the value is approximately 2.2 times this product.

  Here, (Cpd + Ci) is set to about 0.1 pF (picofarad), R is set to about 10 kΩ (kiloohms), and the time constant TRS is set to about about an arbitrary length asynchronous packet sequence with a bit rate of 40 Gbit / s. One nanosecond was set. By setting this time constant, it is possible to handle 40 Gbit / s optical packets including continuous zero bits of about 40 bits at the longest (duration of about 1 nanosecond). Further, as described above, the rectangular wave set signal output from the reset signal generation circuit has a time width obtained by adding the time constant TRS (1 nanosecond) to the duration of each packet. If the time is given about 2 nanoseconds or more, the time width of the reset signal can be secured about 1 nanosecond or more. The time width of this reset signal is sufficient to completely reset the S / H circuit.

  As described above, a reset signal generation circuit capable of handling an arbitrary length asynchronous 40 Gbit / s packet sequence is configured. Note that a GaAs-IC (Integrated Circuit) compatible with 10 Gbit / s was used for the level identification circuit.

  On the other hand, the head timing synchronization signal generation circuit used in combination with the reset signal generation circuit is configured as follows. First, the photoconductive S / H circuit having the configuration shown in FIG. 2 is constructed from an MSM-PD (Metal-Semiconductor Metal Photodetector), a capacitor, and an FET (FET) using InGaAs having a sensitivity in the 1.55 micron band as a light absorption layer. It was fabricated as a monolithic integrated circuit on an InP substrate made of a field-effect transistor. Here, the FET is used to constitute a reset switch and an output buffer for taking out the capacitor voltage to the outside.

  By adopting “monolithic integration”, the parasitic capacitance with respect to MSM-PD can be made almost zero, and by this low capacitance, a high sensitivity value of 0.5 picojoule per pulse is obtained as the sensitivity of the S / H circuit. I was able to. That is, if the energy of the first bit is 0.5 picojoules or more, a step signal can be generated with high timing accuracy within ± 2 picoseconds regardless of the second pulse and thereafter.

  Next, using this S / H circuit, an optical pulse generation type head timing synchronization signal generation circuit shown in FIG. 3 was constructed. Here, the configuration of the rising detection type pulsing circuit is as shown in FIG. 7, and a GaAs-IC (Integrated Circuit) corresponding to 10 Gbit / s is used for both the level identification circuit and the AND logic circuit. As a result, an electric pulse having a rise time and a fall time of 40 ps or less could be generated. As the semiconductor laser diode, a DFB (Distributed Feedback) laser was used. As a result, it was possible to generate a single optical pulse having a pulse width of 10 picoseconds, timing synchronized with the accuracy of ± 2 picoseconds with respect to the first bit of the input optical packet.

  By using such a reset signal generation circuit, as long as a guard time between packets of 2 nanoseconds or more is secured, whatever the input timing of a 40 Gbit / s packet is, and what the packet length is. In addition, the timing light pulse is normally generated even if the packet includes continuous zero bits of about 40 bits.

  In the present embodiment, the configuration of the optical receiver circuit having the time constant TRS is a high impedance type circuit as shown in FIG. 13, and the TRS is set by adjusting the CR time constant of the light receiving unit. Even when the same circuit configuration is used, a receiving circuit suitable for the object of the present invention can be configured by adjusting the band of the buffer circuit in the subsequent stage. It is also possible to use a negative feedback type circuit as shown in FIG. 14 or a circuit having another configuration.

  In the above embodiment, the bit rate of the optical packet is 40 Gbit / s, but the bit rate is not limited to this. In the above embodiment, the format of the packet and the packet string is such that the number of consecutive zero bits included in the packet is about 40 or less and the guard time between packets is about 2 nanoseconds or more. The amount depends on the bit rate and also depends on each other (a shorter guard time is allowed if the number of consecutive zero bits allowed is limited), and the format is not limited to this.

  As described above, the present invention provides a step signal reset method and apparatus necessary for executing a packet synchronization method using generation of a step signal. In particular, a reset method (optical packet head timing synchronization method) and an apparatus (optical packet head timing) that can be applied to any length, asynchronous optical packet, which can be applied even when the packet length and packet rate fluctuate with time. Synchronization device) can be provided. As a result, high-speed asynchronous arbitrary length burst optical packets exceeding 40 Gbit / s can be processed, which can contribute to the construction of a large-capacity optical packet switch network.

  The present invention makes it possible to provide a reset method (optical packet head timing synchronization method) and an apparatus (optical packet head timing synchronization device) that can handle optical packets of any length and asynchronously.

It is a figure for demonstrating the structure of the optical packet head timing synchronization apparatus of this invention. It is a figure for demonstrating the structural example of a head timing synchronizing signal generation circuit. It is a figure for demonstrating the structural example of a head timing synchronizing signal generation circuit. It is a figure for demonstrating the structural example of an optical packet head timing synchronization apparatus. It is a figure for demonstrating the reset signal generation circuit of a 1st structure. It is a figure for demonstrating the reset signal generation circuit of a 2nd structure. It is a figure for demonstrating the structural example of a rise detection type | mold pulse-forming circuit. It is a figure for demonstrating the operation | movement waveform of a reset signal generation circuit. It is a figure for demonstrating the structure (and input / output waveform) of an optical packet head timing synchronizer. It is an operation | movement timing chart of an optical packet head timing synchronizer. It is a figure for demonstrating the structure (and input / output waveform) of an optical packet head timing synchronizer. It is an operation | movement timing chart of an optical packet head timing synchronizer. It is a figure for demonstrating the structural example of the optical receiver circuit of the time constant TRS. It is a figure for demonstrating the structural example of the optical receiver circuit of the time constant TRS.

Explanation of symbols

10, 40, 90, 100 Optical packet head timing synchronization device 11, 41 Head timing synchronization signal generation circuit 12, 50, 60 Reset signal generation circuit 13 Optical delay line 20 Photoconductive S / H circuit 21 Hold capacitor 31 Photoconductive type S / H circuit 32 Rising detection type pulsing circuit 33 Semiconductor laser 42 Delay devices 51, 61 Optical receiving circuit 52 Rising detection type pulsing circuit 62 Level identification circuit 71 Level identification circuit 72 AND logic circuit 73 Electrical delay line

Claims (11)

An optical packet head timing synchronization method for generating a signal synchronized with the head bit of an input optical packet (finite length optical pulse train),
The first optical packet is branched into two, one optical packet is input to the reset signal generating means, and the other optical packet is input to the synchronization signal generating means at a timing delayed from the input to the reset signal generating means. And the steps
A second step of resetting the operation of the synchronization signal generating means by a reset signal generated by the reset signal generating means based on the one optical packet;
The optical packet head timing synchronization method, wherein the reset operation in the second step is executed within a guard time between the input optical packets. In the second step,
The response time constant (reciprocal of band) TRS of the optical receiving means provided in the reset signal generating means is set longer than the longest zero continuous time included in the optical packet and shorter than the guard time, 2. The method according to claim 1, wherein one reset signal corresponding to each of the input optical packets is generated. In the second step,
One step signal (rectangular wave signal) generated by the optical receiving means and corresponding to each of the optical packets is converted into one pulse signal corresponding to each of the optical packets by the pulsing means included in the reset signal generating means. 3. The optical packet head timing synchronization method according to claim 2, wherein the pulse signal is converted and used as the reset signal. In the second step,
3. The optical packet according to claim 2, wherein a zero signal portion of a signal sequence of a step signal (rectangular wave signal) generated by the optical receiving unit and corresponding to each of the optical packets is used as the reset signal. Start timing synchronization method. An optical packet head timing synchronization method for generating a signal synchronized with the head bit of an input optical packet,
A first step of bifurcating a timing signal output from the synchronization signal generating means in response to an input of the input optical packet;
A second step of setting one of the two branched timing signals as an output signal and adding a predetermined delay to the other timing signal as a reset signal for the synchronization signal generating means. An optical packet head timing synchronization method as a feature. Branch means for bifurcating an input optical packet, reset signal generating means for inputting one of the two branched optical packets, sample hold (S / H) means for inputting the other optical packet, and the branch means And an optical delay means provided between the S / H means and
The S / H means is an S / H means for generating a synchronization signal in which a predetermined voltage value is sampled and held by reception of a leading optical pulse of the other optical packet,
The reset signal generating means is a reset signal generating means for transmitting a reset signal based on the one optical packet to the S / H means to reset the operation of the S / H means,
The optical packet head timing synchronization apparatus, wherein the reset operation is configured to be executed within a guard time between the input optical packets. The reset signal generating means includes an optical receiving means,
The response time constant TRS of the optical receiving means is set to be longer than the longest zero continuous time included in the optical packet and shorter than the guard time, and there is one reset signal corresponding to each of the input optical packets. The optical packet head timing synchronizer according to claim 6, wherein the optical packet head timing synchronizer is configured to be generated one by one.   One step signal (rectangular wave signal) generated by the optical receiving means and corresponding to each of the optical packets is converted into one pulse signal corresponding to each of the optical packets by the pulsing means included in the reset signal generating means. 8. The optical packet head timing synchronization device according to claim 7, wherein the pulse signal is converted and used as the reset signal.   One step signal (rectangular wave signal) generated by the optical receiving means and corresponding to each of the optical packets is used as the hold signal of the S / H means, while the zero signal portion of the signal sequence of the step signal is reset. 8. The optical packet head timing synchronization apparatus according to claim 7, wherein the optical packet head timing synchronization apparatus is used as a signal.   The pulsing means provides a two-output type voltage level identification circuit having an inverted output and a non-inverted output, a two-input type AND logic gate circuit, and different delays for two inputs to the AND logic gate circuit. 9. The optical packet head timing synchronization device according to claim 8, further comprising: means. The S / H means includes a light receiving element that performs photo-current conversion on an input optical packet, a capacitor that holds the photocurrent generated by the light receiving element as a charge and generates an output voltage, and discharges the held charge. 11. The optical packet head timing synchronization device according to claim 6, wherein the optical packet head timing synchronization device is a photoconductive S / H circuit including a switch for resetting.

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