JP2005141418A - Memory controller and flash memory system having the same, and control method for flash memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory controller with which data can highly reliably be written while processing time involved in writing is restrained from becoming long by using an erasure state check function that a flash memory has and to provide a flash memory system having the memory controller and a control method for the flash memory. <P>SOLUTION: When data is written into the flash memory, an erasure processing is performed on a block being a writing destination of data. An erasure status that the flash memory creates is acquired after the erasure processing is terminated. When the acquired erasure status is information showing a normal erasure state, a writing processing of data is performed on the block on which the erasure processing is performed. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a memory controller, a flash memory system including the memory controller, and a flash memory control method.

  In recent years, a flash memory is often used as a semiconductor memory used in a memory system such as a memory card or a silicon disk. This flash memory is a kind of non-volatile memory, and is required to retain data regardless of whether power is turned on.

  By the way, the NAND flash memory that is often used in the above-described devices is used when a memory cell is changed from an erased state (logical value “1”) to a written state (logical value “0”). Can be performed in units of memory cells. However, when a memory cell is changed from a written state (logical value “0”) to an erased state (logical value “1”), it must be performed in memory cells. This can only be done with a predetermined erase unit (block) consisting of a plurality of memory cells. Such a batch erase operation is generally called block erase.

Due to the above characteristics, in a memory system using a NAND flash memory, data is written in a block erased block, but the block erased block is normal due to an accidental error or defective block formation. It may not be erased. As a countermeasure against such a problem, Patent Document 1 (Japanese Patent Laid-Open No. 2001-243122) diagnoses the state of an erased block before actually writing data.
JP 2001-243122 A

  However, the countermeasure disclosed in Patent Document 1 (Japanese Patent Application Laid-Open No. 2001-243122) improves the reliability of the write data, but performs processing such as reading the data written in the memory cells of the erased block before writing. Therefore, there is a problem that the processing time associated with writing becomes long.

  Also, recently provided flash memory has a function to check the erased state of the erased block at the time of block erase and generate status information indicating whether all bits are in the erased state. There is something to prepare. Therefore, if a flash memory having such an erase state check function is used, the erase state can be checked more easily.

  Accordingly, the present invention provides a memory controller and a memory controller that can perform highly reliable data writing while suppressing an increase in processing time associated with writing by using an erase state check function provided in a flash memory. An object of the present invention is to provide a flash memory system and a flash memory control method.

An object of the present invention is to provide a writing means for writing data to a flash memory,
Reading means for reading data from the flash memory;
Erasing means for erasing data written in the flash memory;
Status acquisition means for acquiring an erase status generated by the flash memory when data written to the flash memory is erased, and
This is achieved by a memory controller configured to start writing data to an erased block related to the erase status only when the acquired erase status corresponds to a normal erase state.

  The object according to the present invention is also achieved by a flash memory system comprising the flash memory having the memory controller and the status generating means.

  Here, the erase status generated by the flash memory is information indicating whether or not the erased state is normal. If all the bits are in the erased state, the normal state is not erased even by one bit. If the bit is present, it indicates an abnormality.

  In addition, according to the present invention, it is preferable to include candidate block setting means for setting candidates for blocks to which data is written.

  According to the present invention, there is provided invalid flag setting means for setting an invalid flag indicating that the data written in the user area of the block is invalid in the redundant area, and the candidate block setting means includes the redundant flag. It is preferable that a block in which the invalid flag is set in the area is set as a data write destination candidate.

  Further, according to the present invention, it is provided with a diagnostic means for diagnosing the erased state based on the read processing for the erased block, and the normal erased state is determined by either one of the diagnostic means and the status acquisition means. Data writing may be started with respect to the determined erased block.

  That is, a process for determining whether or not the normal erase state is based on the read process for the erased block, and a process for determining whether or not the normal erase state is based on the erase status generated by the flash memory. Can be selectively used, and writing of data is started based on the determination.

Another object of the present invention is to perform an erasure process on a block to which data is written when data is written to the flash memory.
Get the erase status generated by the flash memory after the erase process ends,
When the acquired erase status is information indicating a normal erase status,
This is achieved by a flash memory control method, in which data write processing is performed on the erased block.

  Here, the erase status generated by the flash memory is information indicating whether or not the erased state is normal. If all the bits are in the erased state, the normal state is not erased even by one bit. If the bit is present, it indicates an abnormality.

  Further, according to the present invention, a data write destination is a block in which an invalid flag indicating that the erased block or the data written in the user area of the block is invalid is set in the redundant area. It is preferable.

According to the present invention, the status information generated by the flash memory (information indicating whether or not the erased state is normal. If all bits are in the erased state, the normal state is in the erased state even with one bit. If there is a non-existing bit, an error is indicated.) Is acquired, and data is written to a block that is determined to be in a normal erase state based on this status information. The determination of the erase state and the data writing are performed as a series of processes. By performing such processing, highly reliable data writing can be performed while suppressing an increase in processing time associated with writing.

  Also, if the data written in the user area of a block becomes invalid or unnecessary, if an invalid flag is set in the redundant area of that block, only the erasure process is performed immediately before the data is written. Therefore, the processing efficiency at the time of data rewriting is further improved.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[Description of flash memory system 1]
FIG. 1 is a block diagram schematically showing a flash memory system 1 according to the present invention. As shown in FIG. 1, the flash memory system 1 includes a flash memory 2 and a controller 3 that controls the flash memory 2. The flash memory system 1 is normally used by being detachably attached to the host system 4, and is used as a kind of external storage device for the host system 4.

  Examples of the host system 4 include various information processing apparatuses such as a personal computer and a digital still camera that process various information such as characters, sounds, and image information.

  The flash memory 2 is a device that executes reading or writing in units of pages and erasing in units of blocks. For example, one block is composed of 32 pages, and one page is a 512-byte user area and a 16-byte redundant area. It is configured. In addition, one block is composed of 64 pages, and one page is composed of a 2 kbyte user area and a 64-byte redundant area, and the storage capacity of the block or page tends to increase in the future.

  The controller 3 includes a host interface control block 5, a microprocessor 6, a host interface block 7, a work area 8, a buffer 9, a flash memory interface block 10, an ECC (error collection code) block 11, And a flash memory sequencer block 12. The controller 3 constituted by these functional blocks is integrated on one semiconductor chip. The function of each block will be described below.

  The microprocessor 6 is a functional block that controls the operation of the entire functional blocks constituting the controller 3.

  The host interface control block 5 is a functional block that controls the operation of the host interface block 7. Here, the host interface control block 5 includes an operation setting register (not shown) for setting the operation of the host interface block 7, and the host interface block 7 operates based on the operation setting register.

The host interface block 7 is a functional block that exchanges data, address information, status information, and external command information with the host system 4. That is, when the flash memory system 1 is attached to the host system 4, the flash memory system 1 and the host system 4 are connected to each other via the external bus 13, and in this state, the host system 4 connects to the flash memory system 1. The supplied data or the like is taken into the controller 3 using the host interface block 7 as an entrance, and the data or the like supplied from the flash memory system 1 to the host system 4 is sent to the host system 4 using the host interface block 7 as an exit. To be supplied.

  Further, the host interface block 7 includes a task file register (not shown) for temporarily storing a host address and an external command supplied from the host system 4 and an error register (not shown) set when an error occurs. ) Etc.

  The work area 8 is a work area in which data necessary for controlling the flash memory 2 is temporarily stored, and is a functional block configured by a plurality of SRAM (Static Random Access Memory) cells.

  The buffer 9 is a functional block that temporarily holds data read from the flash memory 2 and data to be written to the flash memory 2. That is, data read from the flash memory 2 is held in the buffer 9 until the host system 4 can receive the data, and data to be written to the flash memory 2 is stored in the buffer 9 until the flash memory 2 becomes writable. Retained.

  The flash memory sequencer block 12 is a functional block that controls the operation of the flash memory 2 based on internal commands. The flash memory sequencer block 12 includes a plurality of registers (not shown), and information necessary for executing an internal command is set in the plurality of registers. When information necessary for executing an internal command is set in the plurality of registers, the flash memory sequencer block 12 executes processing based on the information. Here, the “internal command” is a command given from the controller 3 to the flash memory 2 and is distinguished from an “external command” which is a command given from the host system 4 to the flash memory system 1.

  The flash memory interface block 10 is a functional block that exchanges data, address information, status information, and internal command information with the flash memory 2 via the internal bus 14.

  The ECC block 11 generates an error correction code to be added to data to be written to the flash memory 2, and detects and corrects errors included in the read data based on the error correction code added to the read data. Function block.

[Description of memory cell]
Next, a specific structure of the memory cell 16 constituting the flash memory 2 shown in FIG. 1 will be described with reference to FIGS.

  FIG. 2 is a cross-sectional view schematically showing the structure of the memory cell 16 constituting the flash memory. As shown in the figure, the memory cell 16 includes an N-type source diffusion region 18 and a drain diffusion region 19 formed in the P-type semiconductor substrate 17, and a P between the source diffusion region 18 and the drain diffusion region 19. Tunnel oxide film 20 formed to cover type semiconductor substrate 17, floating gate electrode 21 formed on tunnel oxide film 20, insulating film 22 formed on floating gate electrode 21, and insulating film 22 The control gate electrode 23 is formed on the top. A plurality of memory cells 16 having such a configuration are connected in series in the flash memory.

The memory cell 16 has either an “erased state (a state where no electrons are accumulated)” or a “written state (a state where electrons are accumulated)” depending on whether electrons are injected into the floating gate electrode 21 or not. Is shown. Here, one memory cell 16 corresponds to 1-bit data, the “erased state” of the memory cell 16 corresponds to data of “1” of the logical value, and the “written state” of the memory cell 16 corresponds to the logical value. Corresponds to “0” data.

  In the “erased state”, since electrons are not accumulated in the floating gate electrode 21, when the read voltage (high level voltage) is not applied to the control gate electrode 23, the source diffusion region 18 and the drain diffusion region 19 In the meantime, no channel is formed on the surface of the P-type semiconductor substrate 17, and the source diffusion region 18 and the drain diffusion region 19 are electrically insulated. On the other hand, when a read voltage (high level voltage) is applied to the control gate electrode 23, a channel (not shown) is formed on the surface of the P-type semiconductor substrate 17 between the source diffusion region 18 and the drain diffusion region 19. The source diffusion region 18 and the drain diffusion region 19 are electrically connected by this channel.

  That is, in the “erased state”, when the read voltage (high level voltage) is not applied to the control gate electrode 23, the source diffusion region 18 and the drain diffusion region 19 are electrically insulated, and the control gate electrode 23 In the state where the read voltage (high level voltage) is applied, the source diffusion region 18 and the drain diffusion region 19 are electrically connected.

  FIG. 3 is a cross-sectional view schematically showing the memory cell 16 in the “written state”. As shown in the figure, the “written state” refers to a state in which electrons are accumulated in the floating gate electrode 21. Since the floating gate electrode 21 is sandwiched between the tunnel oxide film 20 and the insulating film 22, the electrons once injected into the floating gate electrode 21 stay in the floating gate electrode 21 for a very long time. In this “write state”, since electrons are accumulated in the floating gate electrode 21, regardless of whether or not a read voltage (high level voltage) is applied to the control gate electrode 23, A channel 24 is formed on the surface of the P-type semiconductor substrate 17 between the drain diffusion region 19. Therefore, in the “written state”, the source diffusion region 18 and the drain diffusion region 19 are always electrically connected by the channel 24 regardless of whether or not a read voltage (high level voltage) is applied to the control gate electrode 23. Will be connected.

  Whether the memory cell 16 is in an erased state or a written state can be read as follows. A plurality of memory cells 16 are connected in series in the flash memory. A low level voltage is applied to the memory cell 16 selected in the series body, and a high level voltage is applied to the control gate electrode 23 of the other memory cells 16. In this state, it is detected whether or not the serial body of the memory cells 16 is in a conductive state. As a result, if the serial body is in a conductive state, it is determined that the selected memory cell 16 is in a written state, and if it is in an isolated state, it is determined that the selected flash memory cell 16 is in an erased state. The In this way, it is possible to read out whether the data held in any memory cell 16 included in the serial body is “0” or “1”.

  When the memory cell 16 in the erased state is changed to the written state, a high voltage is applied so that the control gate electrode 23 is on the high potential side, and electrons are injected into the floating gate electrode 21 through the tunnel oxide film 20. To do. At this time, an FN (Fowler-Nordheim) tunnel current flows and electrons are injected into the floating gate electrode 21. On the other hand, when changing the flash memory cell 16 in the written state to the erased state, a high voltage is applied to the control gate electrode 23 on the low potential side, and the voltage is stored in the floating gate electrode 21 via the tunnel oxide film 20. Discharge electrons.

[Description of flash memory structure]
Next, the memory structure of the flash memory will be described. FIG. 4 schematically shows a memory structure of the flash memory. As shown in FIG. 4, the flash memory is composed of pages, which are processing units for reading and writing data, and blocks, which are data erasing units.

  The page is composed of, for example, a user area 25 of 512 bytes and a redundant area 26 of 16 bytes. The user area 25 is an area mainly storing data supplied from the host system 4, and the redundant area 26 stores additional information such as an error collection code, a corresponding logical block address and a block status. It is an area.

  The error collection code is additional information for correcting an error included in the data stored in the user area 25, and is generated by an ECC block. Based on the error collection code, if the number of errors included in the data stored in the user area 25 is equal to or less than a predetermined number, the error is corrected.

  The corresponding logical block address indicates to which logical block address the block corresponds when data is stored in the block. If no data is stored in the block, the corresponding logical block address is not stored. Therefore, whether or not the block is an erased block depends on whether or not the corresponding logical block address is stored. Judgment can be made. That is, if the corresponding logical block address is not stored, it is determined that the block is an erased block.

  The block status is a flag indicating whether or not the block is a bad block (a block in which data cannot be normally written). If it is determined that the block is a bad block, the block status is bad. A flag indicating a block is set.

[Description of logical block address and physical block address]
Since the flash memory cannot overwrite data, when rewriting data, write new data (data after rewriting) to the erased block that has been erased, and old data (data before rewriting). The process of erasing the written block must be performed. At this time, since erasure is processed in units of blocks, the data of all pages in the block including the page in which the old data (data before rewriting) is written is erased. Therefore, when data is rewritten, it is necessary to perform processing for moving the data of other pages of the block including the page to be rewritten to the erased block.

  When rewriting data as described above, since the data after rewriting is written in a different block from before rewriting, the logical block address given from the host system side and the physical block which is the block address in the flash memory The correspondence with the address changes dynamically every time data is rewritten. Therefore, an address conversion table showing the correspondence between logical block addresses and physical block addresses is required. This address conversion table is created based on the corresponding logical block address written in the redundant area of the flash memory, and each time the data is rewritten, the correspondence relationship of the part involved in the rewriting is updated.

[Description of zone configuration]
As described above, in the flash memory system, data write processing and data read processing are performed using an address conversion table showing the correspondence between logical block addresses and physical block addresses. Many flash memory systems create an address translation table for each zone composed of a plurality of blocks in the flash memory in order to shorten the creation time of the address translation table. The number of blocks constituting the zone is not particularly limited, and can be set as appropriate according to the use of the flash memory system and the specification of the flash memory.

Next, the zone will be described with reference to the drawings. FIG. 5 shows an example in which a zone is composed of 1024 blocks. In this example, the zone is composed of 1024 blocks B0000 to B1023, and each block is composed of 32 pages P00 to P31 which are units of read and write processing. This zone is assigned to a logical block address space for 1000 blocks. Here, the block is a unit of erasing processing, and the page is a unit of reading and writing processing. Further, the reason why the blocks constituting the zone are allocated to the extra 24 blocks is that the occurrence of defective blocks is taken into consideration. However, when data is rewritten and new data is once written to another block, and then the block where the old data has been written is erased, a spare block for writing the new data is necessary. In effect, an extra 23 blocks are allocated.

[Description of address translation table]
Next, an example of an address conversion table for the zone shown in FIG. 5 will be described with reference to the drawings. FIG. 6 shows an address conversion table in the case where a zone is configured with blocks B0000 to B1023 (physical block addresses 0000 to 1023) as shown in FIG. 5 and this zone is assigned to a space of 1000 blocks of logical block addresses. Is shown. In this address conversion table, physical block addresses of blocks storing data corresponding to each logical block address are described in the order of logical block addresses. Here, for a logical block address in which the corresponding data is not stored, a flag (not a physical block address but a corresponding data is stored in a portion corresponding to the logical block address in the address conversion table ( Hereinafter, a flag indicating that the corresponding data is not stored is referred to as an unstored flag).

  Next, a method for creating this address conversion table will be described. When creating the address conversion table shown in FIG. 6, for example, an area in which physical block addresses for 1000 blocks can be described is secured on the SRAM, and an unstored flag is set as an initial setting in the area in which physical block addresses are described. . After that, the blocks (redundant area) assigned to the zone for creating the address conversion table were read sequentially, and the logical block address (logical block address described as the corresponding logical block address) was described in the redundant area. In this case, the physical block address of the block in which the logical block address is described is described in the portion corresponding to the logical block address of the address conversion table. This process is sequentially performed for the 1024 blocks constituting the zone, and when this process is completed, the address conversion table is completed. In the address conversion table creation process, the unstored flag described in the initial setting remains as it is for the part where the physical block address is not described.

[Description of erased block search table and candidate table]
Next, the erased block search table and candidate table will be described. The candidate table is a table in which erased blocks prepared as data write destinations (hereinafter, erased blocks prepared as data write destinations are referred to as write candidate blocks) are set in each zone. Created every time. The erased block search table is a table for searching for erased blocks set as candidate write blocks in the candidate table. As an example of the erased block search table, each block constituting the zone is associated with each bit on the SRAM, and data is written according to the value of each bit (“0” or “1”). Or a state in which data is not written.

  FIG. 7A is a conceptual diagram conceptually showing the erased block search table of the zone shown in FIG. Here, the bits on the erased block search table correspond to blocks B0000 to B1023 (physical block addresses 0000 to 1023) constituting the zone. With respect to this correspondence, the bits on the erased block search table are associated with each other in the order of physical block addresses from the upper row to the lower row and from the left to the right. Therefore, the upper left bit of the erased block search table corresponds to the block B0000 (physical block address 0000), and the lower right bit corresponds to the block B1023 (physical block address 1023).

The bits on the erased block search table indicate whether the block is an erased block by “0” and “1”. For example, when data is written (or a defective block) Is set to “0” in the bit, and “1” is set in the bit when data is not written (in the case of an erased block). The erased block search table can be created together with the address conversion table. For example, “0” is set in the SRAM area for creating the erased block search table, and the corresponding logical block address is not described in the redundant area of each block and the block status indicating that it is a bad block is not described. Sometimes, if the bit corresponding to the block is set to “1”, the address conversion table can be created together. In other words, if this process is performed when the data described in the redundant area of the blocks constituting the zone is read out, only “1” is set to the bit corresponding to the erased block, and this corresponds to the block that is not the erased block. The bit to be maintained remains “0” set in advance.

  For updating the erased block search table, when data is written to the erased block, the bit corresponding to the block is changed from “1” to “0” and the data is written. When a block is erased, the bit corresponding to that block is changed from “0” to “1”.

  Further, in the processing in the flash memory system according to the present invention, when writing data to the flash memory, the write destination block is erased as a block, and then the write processing is performed. Therefore, for a block in which previously written data became invalid due to data rewriting, etc., a flag indicating that the data became invalid without performing block erase when invalidated (Hereinafter, a flag indicating that data written in the user area has become invalid may be referred to as an invalid flag) may be set in the redundant area of the block. A block with an invalid flag set in the redundant area is equivalent to a block in which no data has been written, that is, erased when creating or updating the above address conversion table or erased block search table. Treat as a block.

  As a method of setting the invalid flag, for example, a specific bit in the redundant area is used as a bit indicating validity / invalidity of data written in the user area, and data written in the user area is invalidated. There is a method of overwriting the bit from “1 (erased state)” to “0 (written state)”.

  Next, a case where an erased block (or a block in which an invalid flag is set in the redundant area) is searched using this erased block search table will be described with reference to FIG. In the search for the erased block (or the block in which the invalid flag is set in the redundant area), the bit (the leftmost bit in the top row) corresponding to the block B0000 (physical block address 0000) is used. Scan up to the bit (the rightmost bit in the bottom row) corresponding to block B1023 (physical block address 1023), and an invalid flag is set in the erased block (or redundant area) The bit of “1” corresponding to the block) is searched. The scanning is performed from the upper row to the lower row and from the left to the right in each row.

  In the erased block search table shown in FIG. 7B, when scanning is started from the leftmost bit in the top row, the third bit from the left in the second row from the top is Since it is “1”, the search is terminated here, and the block B0010 (physical block address 0010) corresponding to this bit is set as a write candidate block in the candidate table. In the next search, scanning starts from the fourth bit from the left in the second row from the top, and the fifth bit from the left in the fourth row from the top is “1”. And block B0028 (physical block address 0028) corresponding to this bit is set in the candidate table as a write candidate block. Thereafter, such a search is continued, and when the scanning proceeds to the rightmost bit in the bottom row, the processing returns to the leftmost bit in the top row.

[Description of processing according to the present invention]
The processing according to the present invention will be described with reference to the flowchart shown in FIG. In the flash memory system according to the present invention, the erased state of the erased block is checked at the time of block erase, and status information indicating whether all bits are in the erased state (hereinafter, all the blocks in the erased block are erased). Status information indicating whether or not a bit is in an erased state is called an erase status. A flash memory system is configured using a flash memory having a function of generating a bit.
Step 1:
An erasure process is performed on the block set in the candidate table. In the candidate table, an erased block or a block for which an invalid flag is set in the redundant area is set. The reason why the erase process is performed on the erased block is to confirm whether all bits of the block are in the erased state based on the erase status. Further, when the erase process is performed on the block set in the candidate table, the following erase process is set in the register of the flash memory sequencer block.
1) An internal erase command is set as an internal command in a predetermined register in the flash memory sequencer block.
2) The physical block address of the block set in the candidate table is set in a predetermined register in the flash memory sequencer block.

Thereafter, the flash memory sequencer block executes the process based on the setting of the erase process. When this process is executed, command information and address information for executing an internal erase command are supplied from the flash memory interface block to the flash memory via the internal bus, and the flash memory is busy until the erase process is completed. It becomes a state (a state where processing is not accepted).
Step 2:
After the block erase is completed, an erase status is set in a register in the flash memory. This erase status is read, and it is determined whether or not all the bits of the block subjected to the erase process are in the erased state. If it is determined by this determination that the normal erasure state is set (all bits are in the erasure state), the process goes to step 3. If it is determined that the normal erasure state is not set, the process goes to step 4. move on.
Step 3:
Write processing is performed on the block that has been erased in step 1. In this write process, the following write process is set in the register of the flash memory sequencer block.
1) An internal write command is set in a predetermined register in the flash memory sequencer block as an internal command.
2) The address of the page in the block that has been erased in step 1 is set in a predetermined register in the flash memory sequencer block. Here, the address of the page is given by adding 5 bits (bits for identifying 32 pages) corresponding to the page number to the physical block address.
Thereafter, the flash memory sequencer block executes processing based on the setting of the write processing. When this process is executed, command information and address information for executing an internal write command are supplied from the flash memory interface block to the flash memory via the internal bus. The write data held in the buffer is also supplied to the flash memory via the internal bus, and is written to the page in the block that has been erased in step 1. Further, after completion of the writing process, the bit on the erased block search table corresponding to the block in which the data is written is changed from “1” to “0”.

In addition, if there is old data corresponding to the logical block address supplied from the host system side in the write process, an erase process is performed on the block in which the old data is written after the write process of the new data. Alternatively, the process of setting the invalid flag in the redundant area of the block is performed, and the bit on the erased block search table corresponding to the block for which the erase process or the process of setting the invalid flag is subsequently performed is changed from “0” to “1”. Change to
Step 4:
Use the erased block search table to search for an erased block or a block with an invalid flag set in a redundant area, and to search for a physical block of an erased block or an invalid flag set in a redundant area in the candidate table Set the address.

  In addition, for the block that is determined not to be in a normal erase state in step 2, it is diagnosed whether erasure, writing, etc. can be performed normally. Then, a flag (block status) indicating a defective block is set in the redundant area of the block, and the bit on the erased block search table corresponding to the block is changed from “1” to “0”. .

  As described above, according to the present invention, all the bits are set to the erased state based on the erase status set in the register in the flash memory after the block erase is completed without performing the read process on the erased block. It is determined whether or not. Therefore, it is possible to perform highly reliable data writing in a shorter processing time than in the case where it is determined whether or not all the bits are in the erased state based on the read processing for the erased block.

  If the storage capacity of the block is increased in the future, the process of making a determination based on the erase status becomes more effective. However, since the processing time may not be a problem, a determination based on the erase status and a determination based on a read process for the erased block may be selected according to a user request (setting).

FIG. 1 is a block diagram schematically showing a flash memory system according to the present invention. FIG. 2 is a cross-sectional view schematically showing the structure of the memory cell constituting the flash memory. FIG. 3 is a cross-sectional view schematically showing a memory cell in a written state. FIG. 4 is a diagram schematically showing the structure of the address space of the flash memory. FIG. 5 is a diagram showing an example in which a zone is composed of 1024 blocks. FIG. 6 is a diagram illustrating an example of an address conversion table. FIG. 7 is a conceptual diagram showing an example of an erased block search table. FIG. 8 is a flowchart for explaining the processing according to the present invention.

Explanation of symbols

1 Flash memory system 2, 35, 36 Flash memory 3 Controller 4 Host computer 5 Host interface control block 6 Microprocessor 7 Host interface block 8 Work area 9 Buffer 10 Flash memory interface block 11 ECC block 12 Flash memory sequencer block 13 External bus 14 Internal bus 16 Memory cell 17 P-type semiconductor substrate 18 Source diffusion region 19 Drain diffusion region 20 Tunnel oxide film 21 Floating gate electrode 22 Insulating film 23 Control gate electrode 24 Channel 25 User region 26 Redundant region

Claims (7)

A writing means for writing data to the flash memory;
Reading means for reading data from the flash memory;
Erasing means for erasing data written in the flash memory;
Status acquisition means for acquiring an erase status generated by the flash memory when data written to the flash memory is erased, and
A memory controller configured to start writing data to an erased block related to an erase status only when the acquired erase status corresponds to a normal erase state. The memory controller according to claim 1, further comprising candidate block setting means for setting a block candidate as a data write destination. An invalid flag setting means for setting an invalid flag indicating that the data written in the user area of the block is invalid is set in the redundant area, and the candidate block setting means sets the invalid flag in the redundant area. The memory controller according to claim 2, wherein the block is set as a data write destination candidate. Based on the read processing for the erased block, a diagnostic means for diagnosing the erased state is provided, and the erased block determined to be in the normal erased state by either one of the diagnostic means and the status acquisition means 4. The memory controller according to claim 1, wherein data writing is started. 5. 5. A flash memory system comprising: the memory controller according to claim 1; and a flash memory having status generation means for generating the erase status. When writing data to the flash memory, erase the block to which data is written,
Get the erase status generated by the flash memory after the erase process ends,
When the acquired erase status is information indicating a normal erase status,
A flash memory control method, comprising: performing a data write process on a block that has been erased. 7. The data write destination is an erased block or a block in which an invalid flag indicating that data written in a user area of the block is invalid is set in a redundant area. The control method of the flash memory as described in 2.

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