CN112540882A - Flash memory device detection system and flash memory device detection method - Google Patents
Flash memory device detection system and flash memory device detection method Download PDFInfo
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- CN112540882A CN112540882A CN201910901380.9A CN201910901380A CN112540882A CN 112540882 A CN112540882 A CN 112540882A CN 201910901380 A CN201910901380 A CN 201910901380A CN 112540882 A CN112540882 A CN 112540882A
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- 238000001514 detection method Methods 0.000 title claims abstract description 38
- 238000012360 testing method Methods 0.000 claims abstract description 25
- 238000012937 correction Methods 0.000 claims abstract description 14
- 238000000034 method Methods 0.000 claims description 11
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- 238000010586 diagram Methods 0.000 description 2
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- 238000007796 conventional method Methods 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2273—Test methods
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
- G06F11/106—Correcting systematically all correctable errors, i.e. scrubbing
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2268—Logging of test results
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- Techniques For Improving Reliability Of Storages (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Abstract
The invention provides a flash memory device detection system and a flash memory device detection method. The flash memory device detection system includes: a flash memory device including a plurality of blocks; and a host coupled to the flash memory device. The flash memory device records an available block table, and each of a plurality of blocks in the available block table corresponds to the first mark. The host sends an erasing command to erase the plurality of blocks in sequence. When a first block of the plurality of blocks has an erasure error, the flash memory device updates a first flag corresponding to the first block in the available block table to a second flag. After the plurality of blocks are erased, the host sends a write command to write the test data into the plurality of blocks, and sequentially reads the read data of each of the plurality of blocks after error correction by the error correction code. When the read data and the test data of a second block of the plurality of blocks are partially different, the flash memory device updates a first mark corresponding to the second block in the available block table to a second mark. Therefore, the generation of defective products can be effectively reduced when the quality of the flash memory device is not ideal.
Description
Technical Field
The present invention relates to a flash memory device detection system and a flash memory device detection method, and more particularly, to a flash memory device detection system and a flash memory device detection method for improving the quality of a flash memory device.
Background
In a conventional method for detecting a bad block of a flash memory device, the quality of the block is generally determined by detecting only the first kilobyte (1 kbyte) and the last kilobyte of each block according to the Specification on a Specification table (Specification) to determine whether the inoperable Byte exists in the last kilobyte of each block. However, such a method often results in poor quality of the produced flash memory device, and errors occur when reading and writing data, resulting in data incompleteness.
Disclosure of Invention
The invention provides a flash memory device detection system and a flash memory device detection method, which improve the quality of flash memory devices and the integrity of stored data by a perfect flash memory device detection method.
The invention provides a flash memory device detection system, comprising: a flash memory device including a plurality of blocks; and a host coupled to the flash memory device. The flash memory device records an available block table, and each of a plurality of blocks in the available block table corresponds to the first mark. The host sends an erasing command to erase the plurality of blocks in sequence. When a first block of the plurality of blocks has an erasure error, the flash memory device updates a first flag corresponding to the first block in the available block table to a second flag. After the plurality of blocks are erased and the available block table is updated according to the erased plurality of blocks, the host sends a write command to write the test data into the plurality of blocks and sequentially reads the read data of each of the plurality of blocks after error correction by the error correction code. When the read data and the test data of a second block of the plurality of blocks are partially different, the flash memory device updates a first mark corresponding to the second block in the available block table to a second mark.
The invention provides a flash memory device detection method which is suitable for a flash memory device detection system. The flash memory device detection system includes: a flash memory device including a plurality of blocks; and a host coupled to the flash memory device. The flash memory device detection method comprises the following steps: the flash memory device records an available block table, and each of a plurality of blocks in the available block table corresponds to a first mark; the host sends an erasing command to sequentially erase the plurality of blocks; when a first block of the plurality of blocks has an erasure error, the flash memory device updates a first mark corresponding to the first block in the available block table to a second mark; after the plurality of blocks are erased and the available block table is updated according to the erased plurality of blocks, the host sends a write command to write the test data into the plurality of blocks and sequentially reads the read data of each of the plurality of blocks after error correction by the error correction code; and when the read data and the test data of a second block of the plurality of blocks are partially different, the flash memory device updates the first mark corresponding to the second block in the available block table to a second mark.
Based on the above, the flash memory device detection system and the flash memory device detection method provided in the embodiments of the present invention record the available block table in the flash memory device. The method comprises the steps of firstly sequentially erasing a plurality of blocks in a detection procedure, and when an erasure error occurs in a first block, updating a first mark of the first block in an available block table into a second mark by the flash memory device to represent that the first block is a bad block. After the plurality of blocks are erased, the host writes the test data into the plurality of blocks and sequentially reads the read data corrected by the error correction code. When the read data and the test data of the second block are partially different, the flash memory device updates the first mark of the available block table of the second block to a second mark to represent that the block is a bad block. By detecting the erasure error and the write-in read error, the bad blocks of the flash memory device can be detected comprehensively, so that the generation of defective products is effectively reduced, and the reliability of data stored in the flash memory device is improved.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and together with the description serve to explain the principles of the invention.
FIG. 1 is a block diagram of a flash memory device detection system according to an embodiment of the present invention;
FIG. 2 is a flow chart of a method for detecting a flash memory device according to an embodiment of the invention.
The reference numbers illustrate:
100: a flash memory device detection system;
110: a host;
120: a flash memory device;
s201 to S212: steps of a flash memory device detection method.
Detailed Description
Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.
FIG. 1 is a block diagram of a flash memory device detection system according to an embodiment of the present invention;
referring to fig. 1, a flash memory device detection system 100 according to an embodiment of the invention includes a host 110 and a flash memory device 120. The host 110 is coupled to a flash memory device 120. The flash memory device 120 is, for example, a Solid State Drive (SSD), a flash Drive (flash Drive) or other similar devices. The flash memory device 120 includes a plurality of blocks (or referred to as blocks).
In one embodiment, the flash memory device 120 records an available block table, where each of the plurality of blocks corresponds to the first flag. That is, each block in the available block table is default to the first flag, indicating that all blocks are good blocks. When the flash memory device 120 starts to detect, the host 110 issues an erase command to sequentially erase a plurality of blocks to clear data that may exist inside the flash memory device 120. When an erasure error occurs in a first block of the plurality of blocks, the flash memory device 120 updates a first flag corresponding to the first block in the available block table to a second flag, so as to indicate that the first block in which the erasure error occurs is a bad block. After erasing the plurality of blocks and updating the available block table according to the erased plurality of blocks, the host 110 issues a write command to write test data into all storage spaces of the plurality of blocks and sequentially reads read data of each of the plurality of blocks after error correction by the error correction code. When the read data and the test data of the second block of the plurality of blocks are partially different (i.e., the read data corrected by the error correction code has abnormal bytes), the flash memory device 120 updates the first flag corresponding to the second block in the available block table to the second flag to indicate that the second block is a bad block.
It should be noted that the test data written into different blocks may be the same or different test data, and the host 110 records each block and the corresponding test data written into each block.
In one embodiment, the flash memory device stores 120 the available block table in spare blocks.
In one embodiment, when the threshold voltage of any memory cell in the first block after the erase operation is greater than the threshold value, the first block has an erase error.
In one embodiment, after the erase operation, if all the memory cells of the first block have the first bit value (e.g., 0) after the erase operation, the first block has an erase error.
In one embodiment, when the first block is erased, the flash memory device 120 does not perform a subsequent read/write operation of the test data on the first block to add the detection procedure.
FIG. 2 is a flow chart of a method for detecting a flash memory device according to an embodiment of the invention.
Referring to fig. 2, in step S201, the process is started. The bad block detection mechanism is started.
In step S202, erasing a plurality of blocks is started.
In step S203, whether the current block is successfully erased is determined.
If the current block is successfully erased, in step S204, it is determined whether the current block is the last block.
If the current block is not the last block, in step S205, the next block is accessed.
If the current block is not successfully erased, in step S206, the available block table is updated according to the current block. That is, the available block table may include information that the current block is marked with a bad block (e.g., a first mark corresponding to the current block is updated to a second mark).
If the current block is the last block, in step S207, the test data is written into all blocks.
In step S208, it is determined whether the read data of the current block matches the written test data. Specifically, when the read data and the test data of the current block are partially different, the flash memory device updates the first flag corresponding to the current block in the available block table to the second flag.
If the read data of the current block matches the written test data, in step S209, it is determined whether the current block is the last block.
If the current block is not the last block, in step S210, the next block is accessed.
If the read data of the current block does not conform to the written test data, in step S211, the available block table is updated according to the current block. That is, the available block table may include information that the current block is marked with a bad block (e.g., a first mark corresponding to the current block is updated to a second mark).
In step S212, the flow ends. The bad block detection mechanism is ended.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (10)
1. A flash memory device detection system, comprising:
a flash memory device including a plurality of blocks; and
a host coupled to the flash memory device, wherein
The flash memory device records an available block table, and each of the plurality of blocks in the available block table corresponds to a first mark;
the host sends an erasing command to sequentially erase the plurality of blocks;
when a first block of the plurality of blocks has an erasure error, the flash memory device updates the first mark corresponding to the first block in the available block table to a second mark;
after the plurality of blocks are erased and the available block table is updated according to the erased plurality of blocks, the host sends a write command to write test data into the plurality of blocks and sequentially reads the read data of each of the plurality of blocks after error correction by the error correction code; and
when the read data and the test data of a second block of the plurality of blocks are partially different, the flash memory device updates the first flag corresponding to the second block in the usable block table to the second flag.
2. The flash memory device detection system of claim 1, wherein the host issues the write command to write the test data to all of the storage spaces of the plurality of blocks.
3. The flash device detection system of claim 1, wherein the flash device stores the table of available blocks in a spare block.
4. The flash memory device detection system of claim 1, wherein the erase error occurs in the first block when a threshold voltage of any one of the memory cells of the first block after the erase operation is greater than a threshold value.
5. The system of claim 1, wherein the erase error occurs in the first block if the first block has a first bit value after the erase operation, but not all of the cells of the first block have the first bit value.
6. A flash memory device detection method is suitable for a flash memory device detection system, and the flash memory device detection system comprises: a flash memory device including a plurality of blocks; and a host coupled to the flash memory device, wherein the flash memory device detection method comprises:
the flash memory device records an available block table, and each of the plurality of blocks in the available block table corresponds to a first mark;
the host sends an erasing command to sequentially erase the plurality of blocks;
when a first block of the plurality of blocks has an erasure error, the flash memory device updates the first mark corresponding to the first block in the available block table to a second mark;
after the plurality of blocks are erased and the available block table is updated according to the erased plurality of blocks, the host sends a write command to write test data into the plurality of blocks and sequentially reads the read data of each of the plurality of blocks after error correction by the error correction code; and
when the read data and the test data of a second block of the plurality of blocks are partially different, the flash memory device updates the first flag corresponding to the second block in the usable block table to the second flag.
7. The method of claim 6, wherein the host issues the write command to write the test data into all of the storage spaces of the plurality of blocks.
8. The method of claim 6, wherein the flash memory device stores the table of available blocks in a spare block.
9. The method of claim 6, wherein the erase error occurs in the first block when a threshold voltage of any one of the memory cells in the first block after the erase operation is greater than a threshold value.
10. The method of claim 6, wherein the first block has the erase error if the first block has not all the memory cells of the first block obtained by detecting the voltage after the erase operation have the first bit value.
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| CN201910901380.9A CN112540882A (en) | 2019-09-23 | 2019-09-23 | Flash memory device detection system and flash memory device detection method |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| TWI831118B (en) * | 2022-01-21 | 2024-02-01 | 慧榮科技股份有限公司 | Data storage device and programming stress relief method thereod |
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| CN101499316A (en) * | 2008-01-30 | 2009-08-05 | 群联电子股份有限公司 | Flash memory block management method and controller employing the same |
| CN102237143A (en) * | 2010-04-21 | 2011-11-09 | 深圳市江波龙电子有限公司 | Reconstruction method, system and reconstruction device for block information provided in flash memory |
| CN102543216A (en) * | 2010-12-29 | 2012-07-04 | 中芯国际集成电路制造(上海)有限公司 | Test method for flash memory |
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Patent Citations (5)
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|---|---|---|---|---|
| US20040064636A1 (en) * | 2001-03-16 | 2004-04-01 | Takeo Yoshii | Storage device, storage device controlling method, and program |
| JP2005141418A (en) * | 2003-11-05 | 2005-06-02 | Tdk Corp | Memory controller and flash memory system having the same, and control method for flash memory |
| CN101499316A (en) * | 2008-01-30 | 2009-08-05 | 群联电子股份有限公司 | Flash memory block management method and controller employing the same |
| CN102237143A (en) * | 2010-04-21 | 2011-11-09 | 深圳市江波龙电子有限公司 | Reconstruction method, system and reconstruction device for block information provided in flash memory |
| CN102543216A (en) * | 2010-12-29 | 2012-07-04 | 中芯国际集成电路制造(上海)有限公司 | Test method for flash memory |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| TWI831118B (en) * | 2022-01-21 | 2024-02-01 | 慧榮科技股份有限公司 | Data storage device and programming stress relief method thereod |
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