JP2005129815A - Charge pump circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a charge pump circuit which can make its semiconductor substrate not carry the potential of a negative electrode output terminal but carry grounding potential. <P>SOLUTION: The charge pump circuit has a positive voltage generating circuit 210 for generating a positive voltage +2VDD twice as large as a power-supply voltage VDD and has a negative voltage generating circuit 220 for generating a negative voltage -2VDD inversely twice as large as the power supply voltage VDD. The positive voltage generating circuit 210 comprises a first boosting portion 211 so having MOS transistors T31-T34 and capacitors C31, C32 as to generate the positive voltage +2VDD by feeding the power-supply voltage VDD. The negative voltage generating circuit 220 comprises an inverting portion 221 so having MOS transistors T41-T44 and capacitors C41, C42 as to generate the negative voltage -VDD by feeding the power supply voltage VDD, and comprises a second boosting portion 222 so having MOS transistors T51-T54 and capacitors C51, C52 as to generate the negative voltage -2VDD by feeding the negative voltage -VDD from the inverting portion 221. The transistors T31, T33, T34 and T41 are p-channel type ones, and transistors T32, T42-T44 and T51-T54 are n-channel type ones. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a charge pump circuit capable of obtaining a positive voltage twice as large as a power supply voltage and a negative voltage twice as large as a power supply voltage from a single power supply.

  A charge pump circuit that can obtain a positive voltage that is twice the power supply voltage and a negative voltage that is twice the power supply voltage from a single power supply is used (see, for example, Patent Document 1). Hereinafter, a conventional charge pump circuit 100 will be described with reference to FIG. The charge pump circuit 100 includes a positive voltage generation circuit 110 and a negative voltage generation circuit 120. By connecting the power supply VDD between the input terminal 1 and the ground terminal 2 and supplying the power supply voltage VDD, the positive voltage generation circuit 110 generates a positive voltage + 2VDD that is twice the power supply voltage VDD, and the positive voltage + 2VDD is negative. The negative voltage generation circuit 120 generates a negative voltage −2VDD that is twice the power supply voltage VDD. Then, a positive voltage + 2VDD is output between the positive electrode output terminal 3 and the ground terminal 2, and a negative voltage -2VDD is output between the negative electrode output terminal 4 and the ground terminal 2.

  In the positive voltage generation circuit 110, S11 to S14 are switches, and C11 and C12 are capacitors. First, when the power supply voltage VDD is supplied to the input terminal 1 and the switches S11 and S12 are on-controlled and the switches S13 and S14 are off-controlled, the capacitor C11 is charged. Next, when the switches S11 and S12 are turned off and the switches S13 and S14 are turned on, the capacitor C11 is discharged, and the capacitor C12 is charged with a voltage obtained by superimposing the power supply voltage VDD on the voltage charged in the capacitor C11. Is done. Thereafter, by alternately switching the switches S11, S12 and S13, S14, electric charge is accumulated in the capacitor C12, and the positive voltage generation circuit 110 to the negative voltage generation circuit 120 and the positive output terminal 3 are positively doubled to the power supply voltage VDD. The voltage + 2VDD is output.

  In the negative voltage generation circuit 120, S21 to S24 are switches, and C21 and C22 are capacitors. First, when the positive voltage + 2VDD is supplied from the positive voltage generation circuit 110 and the switches S21 and S22 are turned on and the switches S23 and S24 are turned off, the capacitor C21 is charged. Next, when the switches S21 and S22 are turned off and the switches S23 and S24 are turned on, the charge charged in the capacitor C21 is discharged and the capacitor C22 is charged. Thereafter, by alternately switching the switches S21, S22 and S23, S24, electric charges are accumulated in the capacitor C22, and a negative voltage −2VDD that is twice the power supply voltage VDD is output from the negative voltage generation circuit 120 to the negative output terminal 4. The

  FIG. 7 shows an example in which the switches S11 to S14 and S21 to S24 of the charge pump circuit 100 are composed of MOS transistors. In the figure, T11, T13, T14 and T21 are enhancement type P-channel MOS transistors as switches S11, S13, S14 and S21, respectively, and T12 and T22 to T24 are enhancement type N-channel MOS transistors as switches S12 and S22 to S24. is there. Accordingly, in the positive voltage generation circuit 110, the MOS transistor T11, T12 is turned on, and the MOS transistor T13, T14 is turned off, so that the capacitor C11 is charged by the power supply voltage VDD. Further, when the MOS transistors T13 and T14 are turned on and the MOS transistors T11 and T12 are turned off, the charge charged in the capacitor C11 is discharged, and the power supply voltage VDD is superimposed on the voltage charged in the capacitor C11. The capacitor C12 is charged with the voltage. In the negative voltage generation circuit 120, the MOS transistor T21, T22 is turned on and the MOS transistor T23, T24 is turned off to charge the capacitor C21, and the MOS transistors T23, T24 are turned on, and By turning off the MOS transistors T21 and T22, the charge charged in the capacitor C21 is discharged and charged in the capacitor C22. As will be described later, the MOS transistors T12, T22 to T24 are exemplified by a case where a P-type semiconductor substrate is used as a back gate. The back gates of the MOS transistors T12, T22 to T24 are common to the negative output terminal 4. It is connected. An electrostatic protection diode Di is connected between the input terminal 1 and the positive output terminal 3.

  Next, regarding the operation of the charge pump circuit 100 shown in FIG. 7 in the steady state, the power supply voltage VDD = 3v is supplied to the input terminal 1, and the positive voltage + 2VDD double the power supply voltage VDD = 3v from the positive output terminal 3 = 6v is output, and a case where a negative voltage −2VDD = −6v, which is twice the power supply voltage VDD = 3v, is output from the negative output terminal 4 will be described with reference to FIGS. The potentials Vg11 to Vg14 and Vg21 to Vg24 of the gates G11 to G14 and G21 to G24 of the MOS transistors T11 to T14 and T21 to T24 are controlled as shown in FIG. Thereby, the gate-source voltages Vgs11 to Vgs14 and Vgs21 to Vgs24 (absolute value) and the gate-back gate voltages Vgb11 to Vgb14 and Vgb21 to Vgb24 (absolute value) of the MOS transistors T11 to T14 and T21 to T24. Is as shown in FIG. 9 and FIG. As shown in FIGS. 9 and 10, a maximum voltage of 12 V is applied to each of the MOS transistors T11 to T14 and T21 to T24 of the charge pump circuit 100. Therefore, the MOS transistors T11 to T14 and T21 to T24 are applied. Requires a breakdown voltage of 12v or higher. For example, a low voltage transistor with a breakdown voltage of 7v cannot be used. For example, a high voltage transistor with a breakdown voltage of 42v is used.

  First, at time t1, the MOS transistors T11, T12, T21, and T22 are on-controlled, and the MOS transistors T13, T14, T23, and T24 are off-controlled. At time t2, MOS transistors T11, T12, T21, and T22 are turned off, and after time Δt from time t2, MOS transistors T13, T14, T23, and T24 are turned on. At time t3, the MOS transistors T13, T14, T23, and T24 are turned off, and after the time Δt from time t3, the MOS transistors T11, T12, T21, and T22 are turned on.

  Thereafter, by repeatedly applying the above-described potential to the gates of the MOS transistors T11 to T14 and T21 to T24, charges are accumulated in the capacitors C12 and C22, and the positive output terminal 3 is twice the power supply voltage VDD = 3v. A positive voltage + 2VDD = 6v is output, and a negative voltage −2VDD = −6v that is twice the power supply voltage VDD = 3v is output to the negative output terminal 4.

FIG. 11 shows an example in which the charge pump circuit 100 in which each of the above-described switches is configured by a MOS transistor composed of a high voltage transistor is configured as a semiconductor integrated circuit. P-channel MOS transistors T 11, T 13, T 14, and T 21 are formed as high-voltage transistors on deep N well 12 formed in P-type semiconductor substrate 11. On the other hand, the N-channel MOS transistors T12 and T22 to T24 are formed on the P-type semiconductor substrate 11 as high-voltage transistors. Accordingly, the back gates of the MOS transistors T12, T22 to T24 are the P-type semiconductor substrate 11, and the potential of the P-type semiconductor substrate 11 is set to the lowest potential at which the negative voltage −2VDD = −6v which is twice the power supply voltage VDD = 3v. There must be. The electrostatic protection diode Di is formed on the N well 13 formed in the P-type semiconductor substrate 11.
JP-A-6-165482 (page 2 to page 3, FIG. 13)

In the semiconductor integrated charge pump circuit 100, the forward current flows through the electrostatic protection diode Di at the moment when the power supply voltage VDD is applied to the input terminal 1, and the potential of the positive output terminal 3 is raised in the VDD direction. It is done. At this time, since the potential of the P-type semiconductor substrate 11 is floating, the parasitic PNP transistor T1 including the diode Di and the P-type semiconductor substrate 11 is turned on, and the potential of the P-type semiconductor substrate 11 is raised in the VDD direction. By this lifting, the parasitic NPN transistor T2 including the N well 13 forming the electrostatic protection diode Di, the P type semiconductor substrate 11, and the N region of the ground potential formed in the P type semiconductor substrate 11 is turned on. . As a result, the parasitic transistors T1 and T2 perform a thyristor operation, a large current flows between the input terminal 1 and the ground terminal 2, and the charge pump circuit 100 does not start. In order to normally start the charge pump circuit 100, a Schottky having Vf smaller than the forward voltage Vf of the electrostatic protection diode Di between the input terminal 1 and the positive output terminal 3 so that the parasitic transistor T1 is not turned on. A diode must be connected. For this reason, when a Schottky diode is connected, there are problems such that the number of external parts increases and the mounting area increases. In addition, noise may occur due to fluctuations in the substrate potential due to the floating potential of the semiconductor substrate.
The present invention has been made to solve the above problem, and an object of the present invention is to provide a charge pump circuit capable of setting a semiconductor substrate to a ground potential without setting the potential of the negative electrode output terminal.

A charge pump circuit according to the present invention includes a positive voltage generation circuit that generates a positive voltage that is twice the power supply voltage, and a negative voltage generation circuit that generates a negative voltage that is twice the power supply voltage, and a plurality of switch elements. In the charge pump circuit configured with a capacitor, the positive voltage generation circuit is configured with a first booster that generates the positive voltage by supplying the power supply voltage, and the negative voltage generation circuit is configured by supplying the power supply voltage. The inverter includes: an inverting unit that generates a negative voltage having the same voltage as the power supply voltage; and a second boosting unit that generates a negative voltage twice the negative voltage by supplying the negative voltage from the inverting unit. And
In the above charge pump circuit, each of the first booster and the second booster includes a first switch element, a first capacitor and a second switch element connected in series between the input terminal and the ground terminal, an input terminal, and a second switch element. A third switch element connected between the series connection points of one capacitor and the second switch element, a fourth switch element connected between the series connection point of the first switch element and the first capacitor and the output terminal, and an output terminal And a second capacitor connected between the ground terminal, and the inverting unit includes a first switch element, a first capacitor and a second switch element connected in series between the input terminal and the ground terminal, and a first switch. A third switch element connected between the series connection point of the element and the first capacitor and the ground terminal, and a fourth switch connected between the series connection point of the first capacitor and the second switch element and the output terminal. Characterized in that it has a switch element and a second capacitor connected between the output terminal and the ground terminal.
Further, in the above charge pump circuit, each of the switch elements is composed of a MOS transistor.
Further, in the above charge pump circuit, the double well formed in each semiconductor transistor on the semiconductor substrate is used as a back gate.
According to this means, when the switch element of the charge pump circuit is configured by a MOS transistor, the double well formed in the semiconductor substrate can be used as the back gate, so that the potential of the negative output terminal is set to the potential of the semiconductor substrate. Thus, the semiconductor substrate can be set to the ground potential. As a result, even if the Schottky diode is not connected between the input terminal and the positive output terminal, the thyristor operation due to the parasitic transistor at the start-up does not occur.

  According to the present invention, the semiconductor substrate does not have to be at the potential of the negative output terminal and can be set to the ground potential, so that it is not necessary to connect a Schottky diode. In addition, noise due to fluctuations in the substrate potential due to the floating potential of the semiconductor substrate can be reduced.

  A charge pump circuit 200 according to an embodiment of the present invention will be described below with reference to FIG. The charge pump circuit 200 includes a positive voltage generation circuit 210 and a negative voltage generation circuit 220. By connecting the power supply VDD between the input terminal 1 and the ground terminal 2 and supplying the power supply voltage VDD, the power supply voltage VDD is supplied to the positive voltage generation circuit 210 and the negative voltage generation circuit 220. A positive voltage + 2VDD that is twice the power supply voltage VDD is generated, and a negative voltage −2VDD that is twice the power supply voltage VDD is generated by the negative voltage generation circuit 220. Then, a positive voltage + 2VDD is output between the positive electrode output terminal 3 and the ground terminal 2, and a negative voltage -2VDD is output between the negative electrode output terminal 4 and the ground terminal 2.

  The positive voltage generation circuit 210 includes a first booster 211. In the first booster 211, S31 to S34 are switches, and C31 and C32 are capacitors. A switch S31, a capacitor C31, and a switch S32 are connected in series between the input terminal 1 and the ground terminal 2. The switch S33 is connected between the input terminal 1 and the series connection point of the capacitor C31 and the switch S32, and the switch S34 is connected between the series connection point of the switch S31 and the capacitor C31 and the positive output terminal 3, so that the positive output A capacitor C32 is connected between the terminal 3 and the ground terminal 2. First, when the power supply voltage VDD is supplied to the input terminal 1 and the switches S31 and S32 are turned on and the switches S33 and S34 are turned off, the capacitor C31 is charged. Next, when the switches S31 and S32 are turned off and the switches S33 and S34 are turned on, the capacitor C31 is discharged, and the capacitor C32 is charged with a voltage obtained by superimposing the power supply voltage VDD on the voltage charged in the capacitor C31. Is done. Thereafter, by alternately switching the switches S31, S32 and S33, S34, charges are accumulated in the capacitor C32, and a positive voltage + 2VDD that is twice the power supply voltage VDD is output from the first booster 211 to the positive output terminal 3. .

  The negative voltage generation circuit 220 includes an inversion unit 221 and a second boosting unit 222. In the inverting unit 221, S41 to S44 are switches, and C41 to C42 are capacitors. A switch S41, a capacitor C41, and a switch S42 are connected in series between the input terminal 1 and the ground terminal 2. The switch S43 is connected between the series connection point of the switch S41 and the capacitor C41 and the ground terminal 2, and the switch S44 is connected between the series connection point of the capacitor C41 and the switch S42 and the output terminal of the inverting unit 221. A capacitor C <b> 42 is connected between the output terminal of the inverting unit 221 and the ground terminal 2. First, when the power supply voltage VDD is supplied to the input terminal 1 and the switches S41 and S42 are turned on and the switches S43 and S44 are turned off, the capacitor C41 is charged by the power supply voltage VDD. Next, when the switches S41 and S42 are turned off and the switches S43 and S44 are turned on, the charge charged in the capacitor C41 is discharged and the capacitor C42 is charged. Thereafter, by alternately switching the switches S41, S42 and S43, S44, charges are accumulated in the capacitor C42, and the negative voltage −VDD having the same voltage as the power supply voltage VDD is output from the inverting unit 221 to the second boosting unit 222. .

  In the second booster 222, S51 to S54 are switches, and C51 and C52 are capacitors. A switch S51, a capacitor C51, and a switch S52 are connected in series between the input terminal of the second booster 222 and the ground terminal 2. The switch S53 is connected between the input terminal of the second booster 222 and the series connection point of the capacitor C51 and the switch S52, and the switch S54 is connected between the series connection point of the switch S51 and the capacitor C51 and the negative output terminal 4. A capacitor C52 is connected between the negative output terminal 4 and the ground terminal 2. First, when the negative voltage −VDD is supplied from the inversion unit 221 and the switches S51 and S52 are turned on and the switches S53 and S54 are turned off, the capacitor C51 is charged. Next, when the switches S51 and S52 are turned off and the switches S53 and S54 are turned on, the capacitor C51 is discharged, and the capacitor C52 is discharged with a voltage in which the negative voltage −VDD is superimposed on the voltage charged in the capacitor C51. Charged. Thereafter, by alternately switching the switches S51, S52 and S53, S54, charges are accumulated in the capacitor C52, and a negative voltage -2VDD that is twice the negative voltage -VDD is output from the second booster 222 to the negative output terminal 4. Is done.

  FIG. 2 shows an example in which the switches S31 to S34, S41 to S44, and S51 to S54 of the charge pump circuit 200 are composed of MOS transistors. In the figure, T31, T33, T34, and T41 are enhancement-type P-channel MOS transistors as switches S31, S33, S34, and S41, and T32, T42 to T44, and T51 to T54 are switches S32, S42 to S44, and S51 to 54, respectively. This is an enhancement type N-channel MOS transistor. Accordingly, in the first booster 211 of the positive voltage generation circuit 210, the MOS transistors T31 and T32 are turned on and the MOS transistors T33 and T34 are turned off, so that the capacitor C31 is charged by the power supply voltage VDD. Further, when the MOS transistors T33 and T34 are turned on and the MOS transistors T31 and T32 are turned off, the charge charged in the capacitor C31 is discharged, and the power supply voltage VDD is superimposed on the voltage charged in the capacitor C31. The capacitor C32 is charged with the voltage.

  In the inversion unit 221 of the negative voltage generation circuit 220, the MOS transistors T41 and T42 are turned on and the MOS transistors T43 and T44 are turned off, so that the capacitor C41 is charged by the power supply voltage VDD. Further, when the MOS transistors T43 and T44 are turned on and the MOS transistors T41 and T42 are turned off, the charge charged in the capacitor C41 is discharged and charged in the capacitor C42. Further, in the second boosting unit 222 of the negative voltage generation circuit 220, the MOS transistors T51 and T52 are turned on and the MOS transistors T53 and T54 are turned off, so that the capacitor C51 is fed by the negative voltage −VDD from the inverting unit 221. Is charged. Further, when the MOS transistors T53 and T54 are turned on and the MOS transistors T51 and T52 are turned off, the charge charged in the capacitor C51 is discharged, and the voltage charged in the capacitor C51 is changed to the negative voltage from the inverting unit 221. The capacitor C52 is charged with a voltage on which −VDD is superimposed. The back gate of the MOS transistor T31 is connected in common to the back gate of the MOS transistor T34, and the back gates of the MOS transistors T32 to T34, T41 to T44, and T51 to T54 are connected to their sources. An electrostatic protection diode Di is connected between the input terminal 1 and the positive output terminal 3.

  Next, regarding the operation in the steady state of the charge pump circuit 200 shown in FIG. 2, the power supply voltage VDD = 3v is supplied to the input terminal 1 and the positive voltage + 2VDD that is twice the power supply voltage VDD = 3v from the positive output terminal 3 = 6v is output, and a case where a negative voltage −2VDD = −6v that is twice the power supply voltage VDD = 3v is output from the negative output terminal 4 will be described with reference to FIGS. The potentials Vg31 to Vg34, Vg41 to Vg44 and Vg51 to Vg54 of the gates G31 to G34, G41 to G44 and G51 to G54 of the MOS transistors T31 to T34, T41 to T44 and T51 to T54 are controlled as shown in FIG. The Thereby, the gate-source (back gate) voltages Vgs (b) 31 to Vgs (b) 34, Vgs (b) 41 to Vgs (b) of the MOS transistors T31 to T34, T41 to T44 and T51 to T54. ) 44 and Vgs (b) 51 to Vgs (b) 54 (absolute values) are as shown in FIG. As shown in FIG. 4, only a maximum voltage of 6v is applied to each of the MOS transistors T31 to T34, T41 to T44, and T51 to T54 of the charge pump circuit 200. For example, a low voltage transistor with a withstand voltage of 7v is used. Can do.

  First, at time t1, the MOS transistors T31, T32, T41, T42, T53, T54 are on-controlled, and the MOS transistors T33, T34, T43, T44, T51, T52 are off-controlled. At time t2, MOS transistors T31, T32, T41, T42, T53, and T54 are turned off, and after time Δt from time t2, MOS transistors T33, T34, T43, T44, T51, and T52 are turned on. At time t3, the MOS transistors T33, T34, T43, T44, T51, and T52 are turned off, and after time Δt from time t3, the MOS transistors T31, T32, T41, T42, T53, and T54 are turned on.

  Thereafter, by repeatedly applying the above potential to the gates of the MOS transistors T31 to T34, T41 to T44, and T51 to T54, charges are accumulated in the capacitors C32 and C52, and the power supply voltage VDD = 3v is applied to the positive output terminal 3. Of the positive voltage + 2VDD = 6v, and the negative output terminal 4 outputs the negative voltage −2VDD = −6v which is twice the power supply voltage VDD = 3v.

  FIG. 5 shows an example in which the charge pump circuit 200 in which each of the switches described above is configured by a MOS transistor is configured as a semiconductor integrated circuit. As described above, each of the MOS transistors T31 to T34, T41 to T44, and T51 to T54 of the charge pump circuit 200 can be configured by a low voltage transistor having a withstand voltage of 7v. Therefore, the P-channel MOS transistors T31, T33, T34, and T41 are provided with an N-well 23 in a deep N-well 22 formed in the P-type semiconductor substrate 21 and a low-voltage transistor on the N-well 23, as shown in FIG. It is formed as. In contrast, N channel MOS transistors T32, T42 to T44, T51 to T54 are provided with a P well 24 in a deep N well 22 formed on a P type semiconductor substrate 21, as shown in FIG. A low voltage transistor is formed on the well 24. Therefore, the back gates of the MOS transistors T32, T42 to T44, T51 to T54 serve as the P well 24, and the potential of the P-type semiconductor substrate 21 can be set to the ground potential. The electrostatic protection diode Di is formed on the N well 25 formed in the P-type semiconductor substrate 21.

  As described above, since the negative voltage generation circuit 220 of the charge pump circuit 200 is configured by the inversion unit 221 and the second boosting unit 222, when each switch is configured by a MOS transistor, the MOS transistor has an absolute value. No voltage greater than 2VDD is applied. Therefore, when the charge pump circuit 200 is used to generate, for example, the positive voltage + 2VDD = 6V and the negative voltage −2VDD = −6v from the power supply voltage VDD = 3V, a low voltage transistor process in which each MOS transistor is formed in a double well. Can be formed. As a result, the P-type semiconductor substrate 21 does not have to be set at the potential of the negative output terminal 4 and can be set to the ground potential, so that it is not necessary to connect a Schottky diode that causes a thyristor operation by a parasitic transistor. In addition, since the potential of the P-type semiconductor substrate 21 can be set to the ground potential, noise due to fluctuations in the substrate potential due to the floating potential of the semiconductor substrate can be reduced.

1 is a circuit diagram of a charge pump circuit 200 according to an embodiment of the present invention. FIG. 2 is a circuit diagram using MOS transistors as switches of the charge pump circuit 200 shown in FIG. 3 is a timing chart showing the gate potential of the MOS transistor of the charge pump circuit 200 shown in FIG. 3 is a timing chart showing a gate-source (back gate) voltage of a MOS transistor of the charge pump circuit 200 shown in FIG. FIG. 3 is a schematic cross-sectional view when the charge pump circuit 200 shown in FIG. 2 is formed on a semiconductor substrate as a semiconductor integrated circuit. 1 is a circuit diagram of a conventional charge pump circuit 100. FIG. FIG. 7 is a circuit diagram using MOS transistors as switches of the charge pump circuit 100 shown in FIG. 6. 7 is a timing chart showing the gate potential of the MOS transistor of the charge pump circuit 100 shown in FIG. 7 is a timing chart showing the gate-source voltage of the MOS transistor of the charge pump circuit 100 shown in FIG. 7 is a timing chart showing the gate-back gate voltage of the MOS transistor of the charge pump circuit 100 shown in FIG. FIG. 7 is a schematic cross-sectional view when the charge pump circuit 100 shown in FIG. 6 is formed on a semiconductor substrate as a semiconductor integrated circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Input terminal 2 Ground terminal 3 Positive output terminal 4 Negative output terminal 21 P type semiconductor substrate 22 Deep N well 23 N well 24 P well 25 N well 200 Charge pump circuit 210 Positive voltage generation circuit 211 1st voltage booster 220 Negative voltage generation Circuit 221 Inverting unit 222 Second boosting unit S31-34, S41-S44, S51-S54 Switches C31, C32, C41, C42, C51, C52 Capacitors T31, T33, T34, T41 P-channel MOS transistors T32, T42-T44, T51 to T54 N-channel MOS transistor Di Static protection diode

Claims (4)

A charge pump circuit in which a positive voltage generation circuit that generates a positive voltage twice the power supply voltage and a negative voltage generation circuit that generates a negative voltage twice the power supply voltage are configured by a plurality of switch elements and capacitors. In
The positive voltage generation circuit is configured by a first booster that generates the positive voltage by supplying the power supply voltage;
The negative voltage generation circuit generates a negative voltage having the same voltage as the power supply voltage by supplying the power supply voltage, and generates a negative voltage twice the negative voltage by supplying the negative voltage from the inversion unit. A charge pump circuit comprising: a second boosting unit configured to Each of the first booster and the second booster includes a first switch element, a first capacitor and a second switch element, and an input terminal, a first capacitor, and a second switch element connected in series between the input terminal and the ground terminal. A third switch element connected between the series connection points, a fourth switch element connected between the series connection point of the first switch element and the first capacitor and the output terminal, and connected between the output terminal and the ground terminal. A second capacitor,
The inverting unit is connected between the first switch element, the first capacitor, and the second switch element that are connected in series between the input terminal and the ground terminal, and between the series connection point of the first switch element and the first capacitor and the ground terminal. A third switch element, a fourth switch element connected between the series connection point of the first capacitor and the second switch element and the output terminal, and a second capacitor connected between the output terminal and the ground terminal. The charge pump circuit according to claim 1.   3. The charge pump circuit according to claim 1, wherein each of the switch elements comprises a MOS transistor.   4. The charge pump circuit according to claim 3, wherein each MOS transistor has a double well formed on a semiconductor substrate as a back gate.

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