JP2005129567A - Manufacturing method for semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method for a semiconductor device capable of protecting a wafer from a shock and safely carrying the wafer by a simple method, the cost of which is reduced, when the wafer to which an element-circuit forming process is completed is carried to the next process. <P>SOLUTION: The wafer to which the element-circuit forming process is completed is divided into two or more of wafer pieces containing a plurality of chips, and the wafer pieces are packed up. Moment by the deforming stress of a load in a packing is reduced by carrying the packed-up wafer pieces to a place in the next process, and the wafer is protected from the shock and carried safely. It is desirable that the wafer is cut once or more in the vertical direction and once or more in the horizontal direction on scribing lines. Non-defective chips are picked up and die-bonded easily in an assembly process by transmitting the positional informations of the wafer pieces in the wafer for the assembly process. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a technique that is effective when applied to a method for transporting a semiconductor wafer that has completed an element circuit formation step to the next step.

  For example, as a technique studied by the present inventor, the following technique is conceivable in a method for transporting a semiconductor wafer (hereinafter simply referred to as “wafer”) after the element circuit formation process to the next process.

  After the completion of the element circuit forming process using the large-diameter wafer, the wafer is transferred to the assembly process through a wafer level test process. The destination can be domestic or overseas. During the transfer process, temporary or steady stress is applied to the wafer. The technology for protecting wafers from impacts caused by transport and transporting wafers safely is to attach a protective ring with a diameter larger than that of the wafer around the adhesive sheet material, and then attach the wafer inside the protective ring. There is a method in which a lid is closely attached to the upper surface, a lower surface protective body having a recess is applied to the lower surface side, and the lid, the protective ring, and the lower surface protective body are integrated with an adhesive tape or the like (see, for example, Patent Document 1) .

  Also, when transporting using a pellet case, a wafer on which the element circuit formation process has been completed is pasted on a dicing tape affixed to a dicing carrier jig, the wafer is diced, a good chip is picked up, and a pellet case Store in a container. In the next assembly process, the chip stored in the pellet case is taken out, and the chip is die-bonded on the lead frame.

Moreover, when conveying the wafer cut | disconnected by dicing, the wafer which the element circuit formation process completed is affixed on the dicing tape affixed on the dicing carrier jig | tool, and the said wafer is diced. And the wafer cut | disconnected in the state affixed on the dicing tape as it is is conveyed. In the next assembly process, a good chip on the dicing tape is picked up and the chip is die-bonded on the lead frame.
JP-A-10-261701

  By the way, as a result of examination of the technique of the semiconductor device manufacturing method as described above by the present inventor, the following has been clarified.

  For example, while a large-diameter wafer is being transferred to the next assembly process, an external impact is applied to the wafer itself through the form of wafer packaging. Depending on the degree of impact, temporary or steady stress can cause cracks in the periphery of the wafer, crystal transition inside the wafer, or the wafer itself split into multiple clusters. . In a dicing process in which a shape that can be started is determined in advance, a wafer having a crack cannot be started. Along with the change in the shape of these wafers, the start of the back grinding process and the dicing process in the assembly process is hindered. In some cases, the start of the process becomes impossible and disposal is performed. As the diameter of the wafer being transferred increases, the moment due to the deformation stress of the load in the package increases and the wafer is damaged. And the largest passivation distortion and crystal transition occur in the weakest part of the wafer which finished the element circuit formation process, and it becomes weak in terms of quality reliability. In small-lot, high-mix product groups, wafer scrap (disposal) before the assembly process is directly related to the delivery date issue.

  Further, as a technique for protecting a wafer from an impact in a wafer transfer process, there is a technique described in Patent Document 1, but this technique requires a special packaging material, which leads to an increase in cost.

  Moreover, when conveying using a pellet case, there are various types of pellet cases depending on the chip size, and the cost of the case itself is not negligible particularly for small-volume products having a rectangular chip shape.

  Further, when a wafer cut by dicing is transported, the size of the dicing carrier jig becomes larger as the diameter becomes larger, and the transportation cost increases as the volume and weight increase.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a method for manufacturing a semiconductor device in which a wafer can be safely transported while protecting the wafer from impact by a simple and low-cost method when transporting a wafer that has completed an element circuit formation process to the next process. Is to provide.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  That is, in the method for manufacturing a semiconductor device according to the present invention, the wafer after the element circuit forming step is divided into two or more wafer pieces including a plurality of chips, the wafer pieces are packed, and the packed wafer pieces Is transferred to the place of the next process, the moment due to the deformation stress of the load in the package is reduced, and the wafer is safely transferred while being protected from impact.

  The wafer is preferably divided on the scribe line at least once in the vertical direction and at least once in the horizontal direction.

  In addition, by transmitting the position information of the wafer piece in the wafer for the assembly process, it becomes easy to pick up non-defective chips and die-bond in the assembly process.

  Of the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  (1) Since the bending moment applied to the wafer being transferred is reduced, a damage accident due to wafer impact during wafer transfer is avoided.

  (2) It is possible to avoid deterioration in quality reliability due to stress applied to the wafer.

  (3) Since the actual weight of the dicing carrier jig required for conveyance after dicing is reduced and the volume and weight are reduced, the conveyance cost is reduced.

  (4) It is not necessary to manage the time from sticking the wafer to the dicing tape until the chip is picked up, and the in-process inventory in the start plan management of the assembly process is reduced.

  (5) The cost of transport to destinations including overseas is greatly reduced.

  (6) Quality safety of high-quality wafers is ensured.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

  FIG. 1 is a flowchart showing a method for manufacturing a semiconductor device according to an embodiment of the present invention, and FIG. 2 is an explanatory diagram showing a flow of the method for manufacturing a semiconductor device according to the present embodiment.

  First, an example of a method for manufacturing a semiconductor device according to the present embodiment will be described with reference to FIGS. The semiconductor device manufacturing method according to the present embodiment uses, for example, a large-diameter wafer, and the semiconductor device is manufactured by the following steps.

  In step S101 (element circuit formation process), an unprocessed wafer (bare wafer 13) is put into a wafer fabrication, and wafer processing such as thin film formation, doping, diffusion, and etching is performed to form an element circuit on the wafer.

  In step S102, a TEG (Test Element Group) on the scribe line of the wafer 14 on which the element circuit is formed is measured to determine whether the wafer 14 is good or bad. In the case of a pass (non-defective product), the process proceeds to step S103. In the case of a fail (defective product), a treatment such as discarding is performed on the wafer.

  In step S103, a probe test is performed on each chip 15 in the wafer. The pass (failed product) / fail (defective product) of the chip 15 is determined from the test result, and the pass / fail data 11 is stored in the pickup data 12. The pickup data 12 is chip information for extracting (picking up) non-defective chips in the assembly process. Then, the chip information in the pickup data 12 is transmitted from the wafer fabrication process (including the test) to the die bonding process in the assembly process. The pickup data 12 includes wafer piece position information in addition to lot ID, wafer ID, chip coordinates, and probe test pass / failure information as chip information. The wafer piece position information is information indicating the position of the wafer piece divided in step S104 described later in the wafer.

  In step S104, the wafer 14 is diced in the wafer fabrication and divided into two or more wafer pieces 16 including a plurality of chips 15 (hereinafter referred to as “pre-dicing”). Pre-dicing cuts the scribe line of the wafer 14 at least once in the vertical direction and at least once in the horizontal direction. FIG. 2 shows a case where the wafer 14 is divided into four parts by cutting once in the vertical direction and once in the horizontal direction. As another cutting method, for example, a method of cutting the wafer on the scribe line once in the vertical direction, twice in the horizontal direction, or twice in the vertical direction and once in the horizontal direction to divide the wafer into six can be considered.

  In step S105, the divided wafer pieces 16 are packaged. In step S106, the wafer pieces 16 are packed. In step S107, the wafer pieces 16 are transported to a place for the next process (such as an assembly process).

  Subsequently, in the assembly process, in step S108, unpacking is performed and the wafer piece 16 is taken out. In step S109, the wafer piece 16 is back-ground (back-wrapped), and in step S110, the wafer piece 16 is diced to obtain a plurality of chips 15. Divide into

  In step S111, the chip information of the pickup data 12 transmitted from the wafer fabrication is used to pick up a non-defective chip from the wafer piece 16, and in step S112, the non-defective chip is die bonded (adhered) to the lead frame 17. To do.

  In step S113, wire bonding is performed using a metal wire, and in step S114, molding (sealing) is performed and naming is performed.

  In step S115, the lead of the lead frame is cut and molded.

  In step S116, a final test is performed to select non-defective semiconductor devices. In the case of a pass, the completed semiconductor device is packed and shipped in step S117. In the case of failure, take measures such as disposal.

  Next, how the maximum bending moment is applied and its size when the wafer is divided into wafer pieces including a plurality of chips in this embodiment (four divisions in FIG. 3) will be described with reference to FIG. FIG. 3 is an explanatory view showing a comparison of the maximum bending moment between the wafer 14 and the wafer piece 16 in the present embodiment. In the following, although not limited to this, a case where the wafer 14 is divided into four wafer pieces 16 will be described as an example.

  3A shows the maximum bending moment when the wafer 14 is not divided, and FIG. 3B shows the maximum bending moment applied to the wafer piece 16 when the wafer 14 is divided into four.

  As shown in FIG. 3A, when the diameter of the wafer 14 is L and the force applied to the wafer 14 is F, the maximum bending moment M is M = F · L. On the other hand, as shown in FIG. 3B, when the wafer 14 is divided into four, the maximum bending moment M applied to the wafer piece 16 is M = F · L / √2. Therefore, for example, the maximum bending moment applied to the wafer piece 16 due to the foreign matter being conveyed has a difference of 1 / √2 times between when it is divided into four and when it is not divided.

  Therefore, when the wafer 14 is divided into two or more wafer pieces 16 including a plurality of chips and then transferred, the bending moment applied to the wafer 14 being transferred is reduced, so that the wafer is damaged by the wafer impact during the wafer transfer. Accidents are avoided. That is, it is possible to avoid the occurrence of cracks in the wafer or the wafer piece due to the bending moment leading to plastic deformation, and the start of the assembly process becoming impossible.

  In addition, it is possible to avoid deterioration in quality reliability due to stress applied to the wafer. That is, even if the wafer itself does not undergo plastic deformation, it can be avoided that the passivation pattern formed on the wafer is distorted and the quality is deteriorated.

  Next, referring to FIG. 4, the wafer shipping merit by shipping by wafer in-plane branching specification will be described. FIG. 4 is an explanatory diagram showing a method for shipping by wafer in-plane branching specification according to the present embodiment.

  FIG. 4A shows divided conveyance by device specification when the wafer fabrication specification is divided in the wafer plane. In FIG. 4A, the surface of the wafer 14 is divided into four parts, element circuits are formed under different process conditions, and A, B, C, and D regions including a plurality of chips with different device specifications are created. To do. A boundary portion (invalid region 18) between A, B, C, and D is a region where the process condition is changed, and thus the device specification is uncertain. Next, the wafer 14 is pre-diced and divided into wafer pieces 16 having device specifications A, B, C, and D. Each wafer piece is then transported and shipped by device specification. By doing so, it becomes possible to ship a plurality of wafer pieces having different device specifications from one wafer, and it is possible to cope with a small quantity and a variety of production.

  FIG. 4B shows divided conveyance for each customer when the wafer conveyance / shipping destination is divided in the wafer plane. In FIG. 4B, the surface of the wafer 14 is divided into four parts for different customers A, B, C, and D, respectively. The wafer 14 is pre-diced and conveyed and shipped to customers A, B, C, and D, respectively. The transportation / shipping destination is not limited to each customer, but may be any different location. By doing so, it becomes possible to transport and ship a plurality of wafer pieces divided from one wafer to different places, and it is possible to cope with a small quantity and a variety of production.

  FIG. 4C shows divided conveyance when only a part of the wafer is shipped. In FIG. 4C, the wafer 14 is pre-diced and divided into four wafer pieces 16. Then, only a part of the wafer pieces 16 including the necessary number of chips are transported and shipped to a place where they are needed. The remaining wafer pieces 16 are transported / shipped when necessary at a later time or discarded. By doing so, it becomes possible to carry and ship a necessary amount, and the carrying cost is reduced.

  Next, the back surface grinding according to the in-wafer surface shunt specification will be described with reference to FIG. FIG. 5 is an explanatory view showing back surface grinding according to the in-wafer surface shunt specification in the present embodiment. As shown in FIG. 5, the wafer 14 is divided into four wafer pieces 16 by pre-dicing, and then transported and shipped. In the assembly process, the wafer pieces 16 are back-ground to different thicknesses. In the case of FIG. 5, the chip thickness at the wafer piece position A is 400 μm, the chip thickness at the wafer piece position B is 280 μm, the chip thickness at the wafer piece position C is 140 μm, and the chip thickness at the wafer piece position D is 90 μm. By doing so, the back surface grinding (back lapping) specification, that is, the chip thickness specification can be changed for each wafer piece within the same wafer.

  Next, a flow from wafer fabrication (element circuit formation process) to chip die bonding in the case where the wafer piece 16 cut and divided in the present embodiment is conveyed in the present embodiment will be described with reference to FIG. FIG. 6 is an explanatory diagram showing a flow from wafer fabrication to die bonding of chips in the present embodiment.

  First, the wafer 14 for which the element circuit forming process has been completed is cut by pre-dicing and divided into four wafer pieces 16. Next, the wafer piece 16 is conveyed. In the assembly process, the wafer piece 16 is ground on the back surface. Next, the dicing tape 19 is attached to the dicing carrier jig 21, and the wafer piece 16 is attached thereon. Then, the wafer piece 16 is diced and divided into a plurality of chips 15. Using the chip information of the pickup data 12, a good chip on the dicing tape 19 is picked up, and the chip 15 is die-bonded on the lead frame 17. The defective chip 20 is left on the dicing tape 19.

  Therefore, since the wafer is conveyed in the state of wafer pieces from the fabrication process to the assembly process, the packing form is small and light. Therefore, the conveyance cost is reduced.

  Further, since dicing can be performed in the assembly process, the dicing process can be started in accordance with the die bonding start plan, and time management of the dicing tape becomes unnecessary. That is, conventionally, since the wafer was transported in a state where the wafer was attached to the dicing tape on the dicing carrier jig, time management from the time when the wafer was attached to the dicing tape until the chip was picked up was necessary. According to the present embodiment, such time management becomes unnecessary.

  Furthermore, since the dicing carrier jig can be re-used with a small-diameter jig and a construction specification, it is highly effective in reducing assembly investment costs.

  In particular, the effect of the present invention becomes greater as the semiconductor device uses a large-diameter wafer or the product is a small quantity, multi-product product using the most advanced process.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the above-described embodiment, the case where the wafer is mainly transported in four parts has been described. However, the present invention is not limited to this, and the case where the wafer is transported in two parts, three parts, five parts or more is also described. Applicable.

It is a flowchart which shows the manufacturing method of the semiconductor device which is one embodiment of this invention. It is explanatory drawing which shows the flow of the manufacturing method of the semiconductor device which is one embodiment of this invention. (A), (b) is explanatory drawing which shows the maximum bending moment comparison of the wafer and wafer piece in one embodiment of this invention. (A), (b), (c) is explanatory drawing which shows the method of shipment according to the in-plane shunt specification in one Embodiment of this invention. It is explanatory drawing which shows the method of the back surface grinding classified by wafer in-plane shunt specification in one embodiment of this invention. It is explanatory drawing which shows the flow from the wafer fabrication in one embodiment of this invention to the die bonding of a chip | tip.

Explanation of symbols

11 Pass / Fail Data 12 Pickup Data 13 Bare Wafer 14 Wafer 15 Chip 16 Wafer Piece 17 Lead Frame 18 Invalid Area 19 Dicing Tape 20 Defective Chip 21 Dicing Carrier Jig

Claims (10)

Dividing the semiconductor wafer that has completed the element circuit formation step into two or more wafer pieces including a plurality of chips;
Packing the wafer pieces;
A step of transporting the packed wafer pieces to a place for the next step;
A method for manufacturing a semiconductor device, comprising: Receiving a wafer piece including a plurality of chips divided from a semiconductor wafer on which an element circuit is formed, which has been packed and transported;
Dicing the wafer piece and dividing it into a plurality of the chips;
A step of die bonding the chip;
A method for manufacturing a semiconductor device, comprising: Dividing the semiconductor wafer that has completed the element circuit formation step into two or more wafer pieces including a plurality of chips;
Packing the wafer pieces;
A step of transporting the packed wafer pieces to a place for the next step;
Receiving the packed wafer pieces;
Dicing the wafer piece and dividing it into a plurality of the chips;
A step of die bonding the chip;
A method for manufacturing a semiconductor device, comprising: In the manufacturing method of the semiconductor device of Claim 1 or 3,
The step of dividing the semiconductor wafer into the wafer pieces includes cutting the scribe line one or more times in the vertical direction and one or more times in the horizontal direction. In the manufacturing method of the semiconductor device of Claim 1 or 3,
A method of manufacturing a semiconductor device, wherein the element circuit is formed under different process conditions in a region to be the two or more wafer pieces of the semiconductor wafer. In the manufacturing method of the semiconductor device of Claim 1 or 3,
The method of manufacturing a semiconductor device, wherein the two or more wafer pieces are respectively transferred to different places. In the manufacturing method of the semiconductor device of Claim 2 or 3,
The semiconductor device manufacturing method, wherein the transporting step transports a part of the wafer piece including a necessary number of chips to a required place. In the manufacturing method of the semiconductor device of Claim 2 or 3,
A method of manufacturing a semiconductor device, wherein the received wafer piece is back-ground to a predetermined thickness before the dicing step. In the manufacturing method of the semiconductor device of Claim 1 or 3,
A method of manufacturing a semiconductor device, wherein when the wafer piece is transported, position information of the wafer piece within the semiconductor wafer is transmitted for an assembly process. In the manufacturing method of the semiconductor device of Claim 2 or 3,
When the wafer piece is received, the position information of the wafer piece in the semiconductor wafer is received, and the position information is used when the chip is picked up in the die bonding process. Method.

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