JP2005128907A - Method for controlling arithmetic unit, arithmetic unit, its program, and recording medium - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an arithmetic unit that can compute floating point numbers in such a way as to provide computation results precisely rounded off in a shorter time as a whole. <P>SOLUTION: The mantissa parts of first and second registers 11, 12 are capable of storing floating point numbers whose mantissa parts are one digit greater than those floating point numbers which are given as operands. An arithmetic circuit 21 aligns the values of the mantissa parts of the second register 12 in which floating point numbers with fewer digits are stored, by shifting the values to the right by the digits of the difference between the exponent parts of the first and second registers 11, 12. Further, prior to adding the mantissa parts of the registers 11, 12 together, a transfer control circuit 22 stores a value for a rounding process ("1" for binary operation) in the lowest digit of the mantissa part of the first register 11. Thereafter, the arithmetic circuit 21 adds the mantissa parts of the registers 11, 12 together to calculate the mantissa parts of computation results. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a control method for an arithmetic device, an arithmetic device, a program, and a recording medium for obtaining a correct rounded operation result in a shorter time as a whole when calculating a floating point number.

Traditionally, when floating-point numbers are calculated, such as floating operations and operations with simple decimal points such as calculators, the calculation accuracy is improved and the apparent difference between binary and decimal numbers is corrected. Therefore, for example, as in Patent Document 1 to be described later, one or more digits are calculated more than the number of digits required as the calculation result, and after the calculation, the value is set to a predetermined number (binary calculation). In the case of “1” and “5” in the case of a decimal operation, it is determined whether or not it exceeds. It has been broken.
JP 2000-174624 A (publication date: June 23, 2000)

  However, in the above-described conventional configuration, the calculation is time-consuming because the rounding process is performed after calculating one or more extra digits.

  The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a control method for an arithmetic device and an arithmetic device capable of obtaining a correctly rounded arithmetic result as a whole in a shorter time. It is to be realized.

  In order to solve the above problems, the control method of the arithmetic unit according to the present invention can store a floating-point number whose mantissa part is one digit larger than the operand given as a floating-point number including a mantissa part and an exponent part. And a control circuit for controlling each of the registers and the arithmetic circuit, the control method for the arithmetic device comprising: a plurality of registers; When two operands are given, to the two of the plurality of registers, the value of the least significant digit of each mantissa is 0, and the remaining value is the corresponding operand. When the control circuit has a write step of writing an operand to each register and a register storing each of the operands, if the value of the exponent part is different, the larger one is If the value of the exponent part of the register is the same, when one of these registers is the first register and the one that is not the first register among the registers storing the operands is the second register, An alignment step in which the arithmetic circuit shifts the value of the mantissa part of the second register to the right by the digit of the difference between the two exponent parts and stores it in one of the plurality of registers; and the mantissa of the first register A calculation step of calculating an addition result or a subtraction result of a value of a part and a value of a mantissa part of a register in which a shift result is stored in the alignment step to obtain a mantissa part of the calculation result; And the control circuit includes a setting step for setting a predetermined number for rounding to the least significant digit of the mantissa part of the first register. .

  In order to solve the above problem, the arithmetic unit according to the present invention can store a floating-point number whose number of digits in the mantissa part is one digit larger than an operand given as a floating-point number including a mantissa part and an exponent part. An arithmetic device having a plurality of registers, an arithmetic circuit that performs an operation with reference to the value of each register, and a control circuit that controls the registers and the arithmetic circuit, wherein the control circuit is used for addition or subtraction. When the two operands are given, the value of the least significant digit of each mantissa becomes 0 and the remaining value becomes the corresponding operand to two of the plurality of registers. The operands are written to the respective registers, and the arithmetic circuit selects the larger one of the registers storing the respective operands when the value of the exponent part of the registers is different. If the value of the exponent part is the same, one of these registers is the first register, and the one that is not the first register among the registers storing the operands is the second register. The value of the mantissa part of the second register is right-shifted by the digit of the difference between the exponent parts of both, and is stored in one of the plurality of registers, and the value of the mantissa part of the first register and the shift The result of addition or subtraction with the value of the mantissa part of the register in which the result is stored is calculated to obtain the mantissa part of the operation result, and the control circuit further includes a mantissa part of the operation result. Before obtaining the value, a predetermined number is set for rounding to the least significant digit of the mantissa part of the first register.

  Furthermore, the program according to the present invention includes a plurality of registers capable of storing a floating-point number whose number of digits in the mantissa part is one digit larger than an operand given as a floating-point number including a mantissa part and an exponent part, This is a program that causes a computer having an arithmetic circuit that performs an operation with reference to values and a control circuit that controls the registers and the arithmetic circuit to execute the writing step, the alignment step, the calculating step, and the setting step.

  On the other hand, in order to solve the above-described problem, the control method of the arithmetic unit according to the present invention provides a floating-point number in which the number of digits of the mantissa part is one digit larger than the operand given as a floating-point number including a mantissa part and an exponent part. Arithmetic apparatus having a plurality of storable registers, a specific register capable of storing the operand, an arithmetic circuit that performs an operation with reference to the value of each register, and a control circuit that controls the registers and the arithmetic circuit When two operands for multiplication are given, the value of the least significant digit of each mantissa is set to 0 and the remainder is set to one of the plurality of registers. A writing step in which the control circuit writes the operand to the register and writes the other operand to the specific register so that the operand becomes one of the operands; The control circuit performs the acquisition step of acquiring the value of each digit of the mantissa part of the specific register in order from the least significant digit, and corresponding to each digit acquired in the acquisition step, the calculation In response to an instruction from the control circuit, the circuit changes the value of the mantissa part of the register in which the current operation result is stored among the plurality of registers to the register in which the operand is written. The mantissa value is added corresponding to the number of times of the corresponding digit, and the addition result is written to one of the plurality of registers, and each digit obtained in the acquisition step is performed. The arithmetic circuit shifts the mantissa value of the register in which the addition result is written in the addition step corresponding to the same digit to the right by one digit, and uses the shift result as a new calculation result. Write to one of the registers And the control circuit rounds to the least significant digit of the mantissa part of the register in which the operand is written out of the plurality of registers. And a setting step for setting a predetermined number for processing.

  In order to solve the above problem, the arithmetic unit according to the present invention can store a floating-point number whose number of digits in the mantissa part is one digit larger than an operand given as a floating-point number including a mantissa part and an exponent part. An arithmetic device having a plurality of registers, a specific register capable of storing the operand, an arithmetic circuit that performs an operation by referring to a value of each register, and a control circuit that controls the registers and the arithmetic circuit When the two operands for multiplication are given, the control circuit sets the least significant digit value of each mantissa part to one of the plurality of registers, and the remainder is the operand. And writing the operand to the register, writing the other operand to the specific register, and the mantissa part of the specific register. The value of each digit is obtained in order from the least significant digit, and the arithmetic circuit, based on an instruction from the control circuit, for each digit obtained by the control circuit, among the plurality of registers, The mantissa value of the register in which the operand is written out of the plurality of registers is added to the value of the mantissa part of the register storing the operation result by the number of times of the corresponding digit, and the addition result is obtained. Write to one of the plurality of registers, shift the mantissa value of the register to the right by one digit, and write the shift result to one of the plurality of registers as a new operation result. The control circuit is further configured in advance to perform rounding to the least significant digit of the mantissa part of the register in which the operand is written out of the plurality of registers before the final addition by the arithmetic circuit. It is characterized in that to set the number was fit.

  Furthermore, in order to solve the above-described problem, the program according to the present invention is capable of storing a plurality of floating-point numbers in which the number of digits of the mantissa part is one digit larger than the operand given as a floating-point number including a mantissa part and an exponent part. The writing step in a computer having a register of the above, a specific register capable of storing the operand, an arithmetic circuit that performs an operation with reference to a value of each register, and a control circuit that controls the registers and the arithmetic circuit The acquisition step, the addition step, the shift step, and the setting step are executed.

  On the other hand, in order to solve the above problems, the control method of the arithmetic device according to the present invention includes a plurality of registers capable of storing operands given as floating point numbers including a mantissa part and an exponent part, and values of the respective registers. A control method of an arithmetic unit having an arithmetic circuit that performs an arithmetic operation with reference, and a control circuit that controls each of the registers and the arithmetic circuit. When two operands for division are given, the control circuit A writing step of writing corresponding operands to two of the plurality of registers, a register storing the number of operands of the operand among the plurality of registers, a register of the number of operands, When the register storing the ordinal number is the ordinal register and the register storing the operation result is the operation result register, the above arithmetic circuit is The value of the mantissa part of the ordinal register is subtracted from the value of the mantissa part of the operand register by how many times the value of the mantissa part of the ordinal register is shifted right by one digit by the number of digits of the mantissa part. By calculating whether each digit of the operation result is obtained and determining each digit in the corresponding digit of the mantissa part of the operation result register, the arithmetic circuit determines the number of digits of the mantissa part. If the mantissa value of the ordinal register can be subtracted from the value of the mantissa part of the ordinal register after being shifted right by a predetermined number of times for rounding, the mantissa of the operation result register And a rounding process step of increasing the number by one.

  In order to solve the above problem, the arithmetic device according to the present invention refers to a plurality of registers capable of storing operands given as floating-point numbers including a mantissa part and an exponent part, and values of the respective registers. An arithmetic unit having an arithmetic circuit for calculating, and a control circuit for controlling each of the registers and the arithmetic circuit, wherein the control circuit, when two operands for division are given, An operand corresponding to each of the plurality of registers is written to two of the plurality of registers, and the arithmetic circuit selects a register in which the operand number of the operand is stored among the plurality of registers as an operand register, When the ordinal register of the operand is stored in the ordinal register and the register in which the operation result is stored is the operation result register, the above-mentioned ordinal number How many times can the value of the mantissa part of the ordinal register be subtracted from the value of the mantissa part of the ordinal register while shifting the right side of the mantissa part of the register by the number of digits of the mantissa part? To determine each digit of the operation result, store each in the corresponding digit of the mantissa part of the operation result register, and shift the right after the number of digits of the mantissa part. When the mantissa part value of the ordinal register can be subtracted from the value of the mantissa part of the register by a predetermined number of times for rounding, the mantissa part of the operation result register is incremented by 1. It is characterized by.

  Further, in order to solve the above-described problem, the program according to the present invention calculates a plurality of registers capable of storing operands given as floating-point numbers including a mantissa part and an exponent part, and the values of the respective registers. And a computer having a control circuit that controls each of the registers and the arithmetic circuit are caused to execute a writing step, an arithmetic step, and a rounding step.

  In addition, the recording medium according to the present invention is characterized in that any one of the above programs is recorded in order to solve the above problems.

  As described above, the control method and the arithmetic device of the arithmetic device according to the present invention perform rounding processing on the least significant digit of the mantissa part of the first register before the arithmetic circuit obtains the mantissa part of the arithmetic result. For this purpose, a predetermined number is set.

  In the configuration and the subsequent configuration, the number for rounding is a number obtained by subtracting the minimum value from the numbers raised by the rounding from the radix of the operation. “1” is “5” when a decimal operation is performed. Further, the second register and the register storing the shift result may be the same register or different registers. In the case of the same register, the number of registers necessary for the arithmetic unit is set. Can be reduced. Further, in the configuration and the subsequent configuration, a right shift means a shift to a smaller digit.

  Here, the first register can store a floating-point number whose mantissa part is one digit larger than the operand, and, among the registers storing the operands, when the values of the exponent parts are different from each other, If the larger value or the value of the exponent part is the same, it is one of these registers. Therefore, the least significant digit of the mantissa part of the first register is always “0” unless a number for rounding is set.

  In the above configuration, calculation is performed after setting the number for rounding processing to the least significant digit. Unlike the conventional configuration in which rounding processing is performed after the calculation, carry-up processing after calculation is performed. Therefore, a correctly rounded operation result can be obtained.

  Further, in this configuration, compared with the above-described conventional configuration, the setting processing for the least significant digit is increased, but the carry processing after calculation is decreased. Here, the setting process for a specific digit is different from the process in which the calculation result of one digit affects the calculation result of another digit, such as the carry-up process after the calculation. Does not affect. Therefore, calculation can be performed in a shorter time. As a result, a correctly rounded addition or subtraction result can be obtained in a shorter time as a whole.

  In addition, as described above, the control method and the arithmetic device of the arithmetic device according to the present invention add the other of the operands to the arithmetic result for each digit of one mantissa part of the operand as many times as the number indicated by the digit and the arithmetic result. Is shifted by one digit to the right, the multiplication result is calculated, but at the time prior to the last addition, the mantissa part of the register in which the operand is stored is similar to the control method and arithmetic unit of the arithmetic unit described above. The number for rounding is set in the least significant digit.

  Note that the least significant digit of the mantissa part of the register is always “0” unless a number for rounding is set. Also in this case, the register for storing the operand, the register for writing the addition result, and the register for writing the operation result may be always the same register or different for each digit calculation.

  Therefore, similarly to the control method and the arithmetic device of the arithmetic device, as a whole, the multiplication result that is correctly rounded can be obtained in a shorter time as compared with the configuration in which the rounding process is performed after the final addition.

  In addition, as described above, the control method and the arithmetic device of the arithmetic device according to the present invention are based on the value of the mantissa part of the ordinal register after the arithmetic circuit is right-shifted by the number of digits of the mantissa part. When the value of the mantissa part of the ordinal register can be subtracted a predetermined number of times for rounding processing, the mantissa part of the arithmetic result register is incremented by one.

  In the case of division, unlike the case of addition / subtraction and multiplication, the number of times determined in advance for the rounding process is the minimum value (threshold value) among the numbers raised by the rounding process. “1” is used for calculation, and “5” is used for decimal calculation. Also in this case, the ordinal number register, the ordinal number register, and the operation result register may always be the same register, or different registers may be used at each time point, for example, every shift.

  Therefore, as in the conventional configuration, the calculation result register obtains a value that is one digit lower than the required digit, and then determines whether it is necessary to carry it forward according to whether the value exceeds the threshold value. If necessary, the mantissa part of the operation result register can be reduced as compared with the configuration for performing the operation for carry-up, and the processing for setting the value one digit lower than the required digit and the number of subtractions can be reduced. Can reduce the number of digits required. As a result, a correctly rounded division result can be obtained in a shorter time as a whole.

  Here, although the said arithmetic unit may be implement | achieved only by hardware, you may implement | achieve using software. Specifically, by causing each computer according to the present invention to be executed by each computer, or by causing the computer to read and execute each program recorded on the recording medium according to the present invention, the computer is executed. It can be operated as each of the above arithmetic devices. Therefore, as with the above arithmetic devices, a correct rounded calculation result can be obtained in a shorter time as a whole.

[First Embodiment]
An embodiment of the present invention will be described below with reference to FIGS. In other words, the control method of the arithmetic device according to the present embodiment can calculate at a higher speed than the case of performing rounding after calculation, even though rounding is performed when calculating a numerical value having a decimal part. It is a method, for example, and can be used suitably for the calculation with a simple decimal point used with a calculator, and the calculation of a floating point number.

  Specifically, the arithmetic device 1 according to the present embodiment is a device that performs addition or subtraction of floating point, and, as shown in FIG. 1, calculates a floating-point displayed number of a predetermined number of digits. The first and second registers 11 and 12 to be stored are operated with reference to the values of the registers 11 and 12 according to instructions, and the operation results are sent to the registers 11 and 12 according to instructions. The write operation circuit 21, the transfer control circuit 22 for controlling the data transfer to or from the registers 11 and 12, and the registers 11 and 12 and the operation according to a predetermined algorithm. And a control circuit 23 for controlling the circuit 21 and the transfer control circuit 22.

  A floating point number (floating point number) calculated by the arithmetic device 1 of the present embodiment is expressed by, for example, 1 bit as shown in FIG. 2 when n and m are predetermined natural numbers. , A m-digit exponent part, and an n-digit mantissa part. In the floating-point number according to the present embodiment, the value of the mantissa part is expressed as an absolute value. Further, both the registers 11 and 12 can store a floating point number obtained by adding one digit lower than the least significant digit to the mantissa part of the floating point number shown in FIG. 2 for rounding processing. As shown in FIG. 3, an area AS for storing a sign, an area AE for storing an exponent part of m digits, and an area AM for storing a mantissa part of n + 1 digits are provided.

  On the other hand, the arithmetic circuit 21 according to the present embodiment is realized by a logic circuit such as a combinational logic circuit and a sequential logic circuit, for example, an ALU (Arithmetic Logical Unit). That is, it is configured such that addition and subtraction of the mantissa part, comparison of absolute values, comparison of signs, calculation of a difference in value of the exponent part, and digit shift (right) are possible.

  More specifically, when the addition of the mantissa part is instructed from the control circuit 23, the arithmetic circuit 21 determines the mantissa part of the instructed two registers (first and second registers 11 and 12 in this embodiment). Values read from the area AM are added together, and the addition result can be stored in the area AM of the mantissa part of the designated register (for example, the first register 11). Similarly, when subtraction of the mantissa part is instructed from the control circuit 23, the designated register (for example, for example, from the value read from the area AM of the mantissa part of the instructed register (for example, the first register 11)). The value read from the mantissa area AM of the second register 12) can be subtracted, and the subtraction result can be stored in the mantissa area AM of the designated register (for example, the first register 11).

  When the control circuit 23 is instructed to compare the absolute values, the arithmetic circuit 21 compares the absolute values of the floating-point numbers output from the areas AE and AM of the two instructed registers, The comparison result can be transmitted to the control circuit 23. Similarly, when a sign comparison is instructed from the control circuit 23, the arithmetic circuit 21 compares the signs of the floating-point numbers output from the instructed areas AS of the two registers, and the control circuit 23. The comparison result can be communicated to.

  Further, when the calculation of the difference between the exponent values is instructed from the control circuit 23, the arithmetic circuit 21 calculates the difference between the values read from the exponent area AE of the two designated registers. The result can be output to the control circuit 23. When the control circuit 23 instructs the right shift of the mantissa part, the arithmetic circuit 21 reads from the mantissa part area AM of the indicated register (for example, the second register 12) of the registers 11 and 12 above. The output value can be shifted to the right by the indicated digit, and the shifted value can be written in the mantissa area AM of the register. This right shift is an arithmetic right shift. As a result of the shift, the value of the upper digit newly inserted is set to “0”.

  Further, the transfer control circuit 22 according to the present embodiment is a circuit configured by, for example, a logic circuit, and exchanges values between registers and the least significant digit of the mantissa part according to an instruction from the control circuit 23 It is configured so that the value of can be set.

  More specifically, when the transfer control circuit 22 receives a content exchange instruction from the control circuit 23, the arithmetic circuit 21 can exchange the values of the two designated registers. For example, in the present embodiment, the value output from the first register 11 can be written to the second register 12 and the value output from the second register 12 can be written to the first register 11.

  Further, when the setting of the least significant digit is instructed from the control circuit 23, the transfer control circuit 22 moves to the storage area of the least significant digit (n + 1st digit) of the instructed register (for example, the first register 11). The indicated value can be written.

  Here, in the setting process for the least significant digit, there is a possibility that a carry or a borrow from the upper digit may occur like an addition or subtraction process. Unlike the process that affects the calculation of, the process is completed only by the process of the digit (lowest digit). Therefore, the transfer control circuit 22 according to the present embodiment can set the least significant digit in a shorter time than the addition process and the subtraction process performed by the arithmetic circuit 21.

  Further, the control circuit 23 indicates the processing to be performed to the arithmetic circuit 21 and the transfer control circuit 22 by giving a control signal indicating an instruction code for specifying the processing to the arithmetic circuit 21 or the transfer control circuit 22, for example. Each can be controlled by applying a control signal. Further, the control circuit 23 not only controls each of the registers 11 and 12, the arithmetic circuit 21 and the transfer control circuit 22 in a predetermined order, but also includes the result of the arithmetic circuit 21 according to a predetermined algorithm. By receiving the difference between the comparison result and the value of the exponent part, the control of each of the registers 11 and 12, the arithmetic circuit 21, and the transfer control circuit 22 can be changed accordingly. The details of the algorithm will be described later together with the overall operation of the arithmetic device 1.

  For example, if the control circuit 23 can control the registers 11 and 12, the arithmetic circuit 21 and the transfer control circuit 22 with the algorithm, the control circuit 23 outputs each control signal to each at a predetermined timing and order. Alternatively, it may be realized by a logic circuit that reads the output of the arithmetic circuit 21 at a predetermined timing and applies the control signal, and changes the timing and order of the application of the control signal. Further, for example, it is realized by a calculation means such as a CPU executing a program stored in a storage means such as a ROM or a RAM and controlling the registers 11 and 12, the calculation circuit 21 and the transfer control circuit 22. Also good. In this case, one or a plurality of computers having these means reads the recording medium (for example, a CD-ROM) on which the program is recorded, and executes the program, whereby the arithmetic device 1 according to the present embodiment is executed. Can be realized.

  The arithmetic device 1 is also provided with a memory 31 in which operands to be operated are stored and in which the operation results are written. The transfer control circuit 22 is responsive to instructions from the control circuit 23. The operand read from 31 is stored in the designated register (for example, both registers 11 and 12) or stored in the designated register (for example, the first register 11) based on the instruction of the control circuit 23. The calculation result can be stored in the memory 31 for use in later processing such as calculation result display processing, for example.

  In the above configuration, for example, two operands are stored in a predetermined storage area of the memory 31, and a command indicating an instruction to start addition is written to a predetermined address of the control circuit 23. When addition to (X + Y) is instructed, in step 1 shown in FIG. 4 (hereinafter abbreviated as S1), the control circuit 23 instructs the transfer control circuit 22 to perform the above calculation. Both operands X and Y are stored in both registers 11 and 12. Hereinafter, regardless of the order of both operands when instructed, the operand stored in the first register 11 is referred to as X, and the operand stored in the second register 12 is referred to as Y.

  Here, as shown in FIG. 2, the floating point numbers indicating both operands are m + n digits excluding the sign, whereas, as shown in FIG. Since digits for rounding are added, the number of digits is m + n + 1 digits excluding the sign. As described above, the number of operand digits (excluding the sign) is less than the number of floating-point numbers (excluding the sign) that can be stored in both the registers 11 and 12. In S1, the transfer control circuit 22 In accordance with an instruction from the control circuit 23, when operands X and Y are stored in both registers 11 and 12, "0" is set in the least significant digit of both registers 11 and 12.

  When operands are stored in both registers 11 and 12 in S1, the control circuit 23 instructs the arithmetic circuit 21 to compare the absolute values of both registers 11 and 12 in S2, and receives the comparison result. When the comparison result indicates that the absolute value of the floating point number X stored in the first register 11 is smaller than the absolute value of the floating point number Y stored in the second register 12, the control circuit In step S3, 23 instructs the arithmetic circuit 21 to exchange the floating point numbers X and Y stored in both the registers 11 and 12, and then performs the processing in step S4 and subsequent steps. On the other hand, if it is determined in S2 that the absolute value of the floating point number X is larger or the same, the processing from S4 is performed without performing S3.

  That is, in S4, the control circuit 23 instructs the arithmetic circuit 21 to calculate the difference between the exponents of both the registers 11 and 12, receives the calculation result, and further, only the digit indicated by the calculation result (difference of the difference). The mantissa part (Y mantissa part) of the second register 12 is instructed to shift right, and the operation result is written to the mantissa part of the second register 12. As a result, the significand part of the second register 12 is aligned with the mantissa digit (exponent part value) of the first register 11, and each mantissa part changes the value of the exponent part to the exponent of the first register 11. This is the value when the floating-point notation is aligned with the value of the part.

  In this state, the value of the least significant digit (n + 1 digit) of the mantissa part of the second register 12 is the value of the operand whose exponent part is smaller among the operands instructed to the arithmetic unit 1. It is set according to. On the other hand, the value of the least significant digit of the mantissa part of the first register 11 is “0”.

  In S5, the control circuit 23 according to the present embodiment further instructs the transfer control circuit 22 before adding or subtracting the mantissa part in S5, so that the least significant digit of the first register 11 (the least significant digit of X) To a value set in advance as a rounding value. Note that the rounding value is the minimum value among the values that are raised by the rounding process. For example, when a floating-point number is expressed in binary, it is expressed in “1” or decimal. If it is, it is “5”.

  Further, after the rounding value is set in S5, the control circuit 23 considers the sign area AS of both the registers 11 and 12 to the arithmetic circuit 21, and takes the mantissa of both the registers 11 and 12 into consideration. The value of the part area AM is added, and the addition result is stored in the mantissa part area AM of the first register 11 (S6). Specifically, the control circuit 23 instructs addition or subtraction according to the value of the sign area AS of both registers 11 and 12. More specifically, the control circuit 23 instructs the arithmetic circuit 21 to compare the signs of both the registers 11 and 12, and if the comparison result from the arithmetic circuit 21 indicates that the signs of the two coincide, The circuit 21 is instructed to add. On the other hand, when indicating a mismatch, the control circuit 23 instructs the arithmetic circuit 21 to subtract the mantissa part of the second register 12 from the mantissa part of the first register 11. In any case, the calculation result is stored in the mantissa area AM of the first register 11. Here, in S2 and S3, since the larger absolute value is stored in the first register 11, the sign area AS of the first register 11 is determined regardless of the values stored in both the registers 11 and 12. It is not necessary to change the value of.

  In S6, the addition result of the mantissa parts (X and Y mantissa parts) of both registers 11 and 12 is written in the mantissa part (X mantissa part) of the first register 11, and when the calculation is completed, the control circuit In S 7, 23 instructs the transfer control circuit 22 to output the calculation result, and causes the memory 31 to store the floating point number X stored in the first register 11. Here, as described above, the number of digits (excluding the sign) of the floating-point number as the operation result is one digit smaller than the number of digits (excluding the sign) of the first register 11. The part of the first register 11 excluding the least significant digit is stored in the memory 31.

  In the above configuration, before performing the addition process in S6, in S5, the least significant digit of the mantissa part of the first register 11 that should be 0 is set to a rounding value. Therefore, after addition processing, if the least significant digit is greater than or equal to the rounding value, 1 is added to the value on the least significant digit (the least significant digit of the floating-point number as the addition result). Similarly, a correct rounding result can be obtained.

  Further, unlike the case of rounding after addition, although the correct rounding result is obtained, the comparison processing after addition and the processing of adding 1 are not required. Here, in the addition method according to the present embodiment, instead of the comparison process after addition and the process of adding 1, in S5, a rounding value setting process is added. Unlike the process where the operation result in one digit affects the value of the other digit as in the process, it does not affect the value of the other digit, and the process is completed only by setting the lowest digit. . Therefore, calculation can be performed in a shorter time. Therefore, when viewed as a whole, the rounded addition result can be obtained in a shorter time compared to the method of rounding after addition.

  In the above description, the case where addition is instructed to the arithmetic device 1 has been described as an example. However, when subtraction (XY) is instructed, the processing shown in FIG. . That is, in FIG. 5, instead of the addition process of S6, a step (S6a) of performing a subtraction process in consideration of the sign of the floating-point number stored in both registers 11 and 12 is provided. The control circuit 23 instructs the arithmetic circuit 21 to perform addition or subtraction according to the value of the sign area AS of both the registers 11 and 12, and stores the operation result in the mantissa area AM of the first register 11. Let More specifically, the control circuit 23 instructs the arithmetic circuit 21 to compare the signs of the two registers 11 and 12. When the comparison result from the arithmetic circuit 21 indicates that the two signs do not match, the control circuit 23 In this case, the subtraction is instructed to the arithmetic circuit 21 instead of the addition, and if the match is indicated, the addition is instructed to the arithmetic circuit 21 instead of the subtraction. As a result, as in the case of addition, when viewed as a whole, the rounded subtraction result can be obtained in a shorter time compared to the method of rounding after subtraction.

  In the above description, the case where the mantissa part is expressed by an absolute value has been described as an example. However, the arithmetic circuit 21 in accordance with the instruction of the control circuit 23 performs addition or subtraction in consideration of the sign of the values of both registers 11 and 12. If possible, addition or calculation can be performed without any problem even if the data is expressed in complement, and the calculation result can be stored in the first register 11.

[Second Embodiment]
By the way, in the first embodiment, the case of adding or subtracting a floating point number has been described. Even in the case of multiplication, the last shift and addition of digits are repeated to obtain a multiplication result. By setting a rounding value before the addition, a similar effect can be obtained.

  That is, as shown in FIG. 6, the arithmetic device 1b according to the present embodiment is substantially the same as the configuration of the arithmetic device 1 shown in FIG. 1, except that the number of digits in the mantissa area AM is n digits. Except for this, a third register 13b having the same configuration as each of the registers 11 and 12 is provided, and an algorithm used when the control circuit 23 controls each of the members 11 to 13b, 21b, and 22b is changed.

  In the present embodiment, the arithmetic circuit 21b provided in place of the arithmetic circuit 21 according to the first embodiment adds the values of the exponent part, and adds the codes between the arithmetic circuits 21 in addition to the operations that the arithmetic circuit 21 can perform. An exclusive OR operation and a test of a specific digit of the mantissa are possible. If addition / subtraction is not required, unlike the arithmetic circuit 21, processing that is not used in the description of the operation of the present embodiment (for example, absolute value comparison processing) may not be performed.

  More specifically, the arithmetic circuit 21b according to the present embodiment, when instructed to add the exponent part from the control circuit 23, the exponents of the instructed two registers (for example, the second and third registers 12, 13b). The values read from the part area AE can be added together, and the addition result can be stored in the exponent part area AE of the indicated register (for example, the first register 11). Similarly, when an exclusive OR operation of a sign is instructed from the control circuit 23, a value read from the sign area AS of the instructed two registers (for example, the second and third registers 12 and 13b) An exclusive OR between them is calculated, and the calculation result can be stored in the sign area AS of the designated register (for example, the first register 11). In addition, when the control circuit 23 instructs the test of the designated digit (for example, the least significant digit) of the designated register (for example, the third register 13b) from the control circuit 23, the arithmetic circuit 21b sets the value of the digit. Can be transmitted to the control circuit 23.

  Further, in the present embodiment, the transfer control circuit 22b provided in place of the transfer control circuit 22 of the first embodiment has a register instructed by the control circuit 23 in addition to the processing that can be performed by the transfer control circuit 22. , A floating point number indicating “0” can be stored.

  In the above configuration, for example, two operands are stored in a predetermined storage area of the memory 31, and an instruction indicating an instruction to start multiplication is written to a predetermined address of the control circuit 23. When the multiplication (Y * Z → X) is instructed, in S11 shown in FIG. 7, the control circuit 23 instructs the transfer control circuit 22b to select one of the two operands to be multiplied as the second operand. While storing in the register 12, the other is stored in the third register 13b. Hereinafter, regardless of the order of both operands when instructed, the operand stored in the second register 12 is referred to as Y, and the operand stored in the third register 13b is referred to as Z. Further, when storing in the second register 12, the transfer control circuit 22 b sets “0” to the least significant digit (the least significant digit of Y) of the second register 12 as in S <b> 1 shown in FIG. 4. .

  When the operands are stored in both the registers 12 and 13b in S11, the control circuit 23 instructs the transfer control circuit 22b in S12 to set the floating point number X of the first register 11 used for storing the multiplication result. Set to “0”.

  Further, in S13, the control circuit 23 instructs the arithmetic circuit 21b to add the values of the exponent parts of the second and third registers 12 and 13b, and to give the calculation result to the area of the exponent part of the first register 11. Store in AE (exponential part of Y + exponential part of Z → exponential part of X). In S14, the control circuit 23 instructs the arithmetic circuit 21b to calculate the exclusive logical sum of the signs of the second and third registers 12 and 13b, and displays the calculation result in the sign area of the first register 11. The data is stored in the AS (the Y code EX-OR Z code → X code).

  Further, the control circuit 23 repeats the following processes of S21 to S24 (n-1) times, where n is the number of digits of the mantissa part. As an example, the case where the arithmetic circuit 21b performs binary calculation will be described. In S21, the control circuit 23 instructs the arithmetic circuit 21b to output the value of the least significant digit (the least significant digit of Z) of the third register 13b. ) And read the value. If the value is “1” (YES in S21), the control circuit 23 instructs the arithmetic circuit 21b in S22 to set the mantissa of the second register 12 to the value of the mantissa part of the first register 11. After the value obtained by adding the values of the parts is stored in the mantissa part area AM of the first register 11, the processing after S23 is executed (the mantissa part of X + the mantissa part of Y → the mantissa part of X). On the other hand, if the value is “0” (NO in S21), the control circuit 23 performs the processing after S23 without performing the processing in S22.

  That is, in S23, the control circuit 23 instructs the arithmetic circuit 21b to shift the value of the mantissa part (the mantissa part of X) of the first register 11 to the right by one digit. Further, in S24, the control circuit 23 instructs the arithmetic circuit 21b to shift the value of the mantissa part (the mantissa part of Z) of the third register 13b to the right by one digit.

  When the processes of S21 to S24 are repeated (n-1) times, the control circuit 23 causes the arithmetic circuit 21b to read the value of the least significant digit of the third register 13b and receives the value in S31. If the value is “0” (NO in S31), the control circuit 23 instructs the transfer control circuit 22b in S32 and stores “0” in the second register 12 (Y). , S5 to S7 are executed. On the other hand, if the value is “1” (YES in S31), the control circuit 23 performs the processing of S5 to S7 without performing the processing of S22.

  Here, S5 to S7 of this embodiment are substantially the same as S5 to S7 shown in FIG. 4, but in S6b provided in place of S6, unlike S6, the significand part is not considered without considering the sign. The values of are added together. Specifically, in S6b, the control circuit 23 instructs the arithmetic circuit 21b to add the value of the mantissa part of the first register 11 and the value of the mantissa part of the second register 12, and to add the addition result to the first The data is stored in the mantissa area AM of the register 11.

  In the above description, as an example, the case of binary calculation has been described as an example, but more generally, when a natural number of 2 or more is x and x-ary calculation is performed, the processing of S21 and S22, that is, Instead of the process of determining whether or not to perform the process of S22 according to the value of the least significant digit, a process of repeating the process of S22 as many times as the value of the least significant digit of the third register 13b is performed. . Further, after S24, the same processing as S24 is performed for the number of times of the least significant digit of the third register 13b, that is, the addition processing to the mantissa part of the second register 12 to the mantissa part of the first register 11 is performed. The processes of S31 to S32 and S5 to S7 are performed instead of the addition process at the time of the last repetition.

  Further, in the above description, the case where the processing of S31 and S32 is performed has been described as an example. However, the method of expressing the floating-point number stored in the third register 13b is except when the whole is “0”. If it is expressed by an expression method in which the most significant digit is not “0”, that is, if the determination of S31 is always YES, the processing of S31 and S32 is unnecessary. In this case, when the operand stored in the third register 13b is “0”, the operation result does not become “0”. However, after S11, the control circuit 23 instructs the operation circuit 21b to execute both operands. That is, the portion excluding the least significant digit of the second register 12 and the value of the third register 12) are tested to see if they are "0". Instead of executing the subsequent processing, the transfer control circuit 22b may be instructed to output “0” as the calculation result. The prior confirmation that both operands are not “0” is effective in improving the calculation speed regardless of whether or not S31 and S32 are omitted.

  As described above, when multiplying the floating-point number, the arithmetic device 1b according to the present embodiment repeatedly obtains the multiplication result by repeating the shift and addition of digits, and the last addition among these repeated shift and addition processes. Before the process, after the rounding value is set, the final addition process is performed. Therefore, similarly to the first embodiment, when viewed as a whole, the rounded multiplication result can be obtained in a shorter time compared to the method of performing the rounding process after the calculation.

[Third Embodiment]
In the present embodiment, a configuration capable of calculating a correctly rounded division result at high speed will be described. That is, the arithmetic device 1c according to the present embodiment repeats the right shift of the operand number, the left shift of the operator result, and the lowest digit setting of the operator result according to the comparison between the operand number and the ordinal number. The result is calculated, but instead of rounding digit setting processing and rounding processing, processing for determining whether or not to add the rounding value is performed according to the comparison result between the ordinal number and the ordinal number. Yes.

  Specifically, the arithmetic device 1c according to the present embodiment has substantially the same configuration as the arithmetic device 1b according to the second embodiment, but instead of the first and second registers 11 and 12, a third register 13b, the first and second registers 11b and 12b having n digits in the mantissa are provided, and the control circuit 23 controls each member 11c to 13b, 21c and 22b. The algorithm has changed.

  In this embodiment, the arithmetic circuit 21c provided in place of the arithmetic circuit 21b according to the second embodiment includes subtraction of the exponent part, comparison of the mantissa parts, It is configured so that the mantissa part can be increased by 1 and the mantissa part can be shifted (left). If addition / subtraction and multiplication are not necessary, unlike the arithmetic circuits 21 and 21b, processing (for example, absolute value comparison processing) not used in the description of the operation of the present embodiment may not be performed.

  More specifically, when the subtraction of the exponent part is instructed from the control circuit 23, the arithmetic circuit 21c according to the present embodiment reads out from the exponent part area AE of the instructed register (for example, the second register 12c). The value read from the exponent part area AE of the designated register (for example, the third register 13b) is subtracted from the designated value, and the subtraction result is subtracted from the designated register (for example, the first register 11c). It can be stored in the area AE of the exponent part.

  When the comparison of the mantissa is instructed from the control circuit 23, the values read from the mantissa area AM of the two instructed registers (for example, the second and third registers 12c and 13b) are compared. Then, the comparison result can be transmitted to the control circuit 23. Further, when an instruction to increase the mantissa part by 1 is instructed from the control circuit 23, the value of the mantissa part of the instructed register (for example, the first register 11c) is incremented by 1 and stored in the area AM of the mantissa part of the register. it can. Similarly, when a left shift is instructed, the value of the mantissa part of the instructed register (for example, the first register 11c) is shifted one digit to the left, and the shift result is transferred to the mantissa part area AM of the register. Can be stored. Note that the left shift is also an arithmetic left shift in the same way as the right shift. As a result of the shift, the value of the newly inserted lower digit is set to “0”.

  In the above configuration, for example, two operands are stored in a predetermined storage area of the memory 31, and an instruction indicating a division start instruction is written to a predetermined address of the control circuit 23. When division to Y (Z / X → X) is instructed, in S41 shown in FIG. 8, the control circuit 23 instructs the transfer control circuit 22b to store the ordinal number Y in the second register 12c and the ordinal number. Z is stored in the third register 13b.

  When the operand is stored in both registers 12c and 13b in S41, the control circuit 23 instructs the transfer control circuit 22b in S42 to use the floating point of the first register 11 used for storing the division result (quotient). The number X is set to “0”.

  Further, in S43, the control circuit 23 instructs the arithmetic circuit 21c to subtract the value of the exponent part of the third register 13b from the value of the exponent part of the second register 12c, and the operation result is obtained from the first register 11c. (Exponential part of Y−exponential part of Z → exponential part of X). In S44, the control circuit 23 instructs the arithmetic circuit 21b to calculate the exclusive OR of the signs of the second and third registers 12c and 13b, and displays the calculation result in the sign area of the first register 11c. The data is stored in the AS (the Y code EX-OR Z code → X code).

  Further, the control circuit 23 repeats the following processes of S51 to S55 by the number of digits of the mantissa part (only n times). As an example, the case where the arithmetic circuit 21c performs binary calculation will be described. In S51, the control circuit 23 instructs the arithmetic circuit 21c so that the values of the mantissa parts of the second register 12c and the third register 13b (Y Are compared with each other and a comparison result is received. When the value of the mantissa part of the second register 12c is greater than or equal to that of the third register 13b (when S ≧ Y in Z51), the control circuit 23 instructs the arithmetic circuit 21c to instruct the second register 12c. The value of the mantissa part of the third register 13b is subtracted from the value of the mantissa part of the second register 12b, and the subtraction result is stored in the area AM of the mantissa part of the second register 12c (the mantissa part of Y−the mantissa part of Z → the mantissa of Y) Part). Further, in S53, the control circuit 23 instructs the arithmetic circuit 21c to write “1” in the least significant digit (the least significant digit of X) of the mantissa part of the first register 11c, and then the processing after S54 I do. On the other hand, when the value of the mantissa part of second register 12c is smaller (in S51, if Y <Z), the processes in and after S54 are performed without performing the processes in S52 and S53.

  That is, in S54, the control circuit 23 instructs the arithmetic circuit 21c to shift the value of the mantissa part (the mantissa part of X) of the first register 11c to the left by one digit. In S55, the control circuit 23 instructs the arithmetic circuit 21c to shift the value of the mantissa part (Y mantissa part) of the second register 12c to the right by one digit, and the mantissa part area AM of the second register 12c. To store.

  When the processes of S51 to S55 are repeated n times, the control circuit 23 causes the arithmetic circuit 21c to send the values of the mantissa parts of the second register 12c and the third register 13b (Y mantissa part and Z mantissa in S61). Part) and receive the comparison result. When the comparison result indicates that the second register 12c is larger or the same (when Y ≧ Z in S61), the control circuit 23 determines the value of the mantissa part of the first register 11c (S62) The mantissa part of X) is incremented by 1, and then the processing from S63 is performed. On the other hand, if the comparison result indicates that the second register 12c is smaller (in the case of Y <Z in S61), the processes in and after S63 are performed without performing the process in S62. That is, in S63, the control circuit 23 instructs the transfer control circuit 22b to output the operation result, and causes the memory 31 to store the floating point number X stored in the first register 11c.

  In the above description, as an example, a case where binary calculation is performed has been described as an example. However, in a case where x-ary calculation is performed more generally, instead of the processes of S51 to S53, the processes of S51 and S52 are as follows. The processing is repeated until it is determined in S51 that the mantissa part of the third register 13b is smaller, and then the number of repetitions is written in the least significant digit of the first register 11c. Further, instead of the processing of S61 and S62, it is determined that the processing of S51 and S52 is smaller in the mantissa part of the third register 13b, or the number of repetitions is the rounding value (for example, decimal). In the case of (5), the process is repeated until it reaches 5). If the number of repetitions reaches the rounding value, the process of S62 is performed after the process of S62. On the other hand, if the repetition is completed before the number of repetitions reaches the rounding value, the control circuit 23 performs the process of S63 without performing the process of S62.

  In the above configuration, after calculating the least significant digit of the quotient, it is determined whether or not 1 is added to the quotient depending on whether the number of times the ordinal number can be subtracted from the ordinal number exceeds the rounding value. Yes. Accordingly, the number of digits and the amount of calculation required for the calculation can be reduced as compared with the configuration in which the rounding process is performed after determining the value one digit lower than the least significant bit of the quotient (the value of the rounding digit).

  The arithmetic device control method and arithmetic device according to the present invention, when calculating a floating-point number, can obtain a correctly rounded operation result as a whole in a shorter time. Widely applicable to.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1, showing an embodiment of the present invention, is a block diagram illustrating a main configuration of an arithmetic device. It is a figure which shows the floating-point number used as the operand of a calculation, or a calculation result. It is drawing which shows the register | resistor provided in the said arithmetic unit. It is operation | movement of the said arithmetic unit, Comprising: It is a flowchart which shows the operation | movement at the time of addition. It is operation | movement of the said arithmetic unit, Comprising: It is a flowchart which shows the operation | movement at the time of subtraction. FIG. 10 is a block diagram illustrating another embodiment of the present invention and illustrating a configuration of a main part of an arithmetic device. It is a flowchart which shows operation | movement of the said arithmetic unit, and shows the operation | movement at the time of multiplication. It is a flowchart which shows further another embodiment of this invention, Comprising: The operation | movement at the time of a division | segmentation.

Explanation of symbols

1, 1b, 1c Arithmetic unit 11, 11c First register (register; operation result register)
12.12c Second register (register; ordinal number register)
13b Third register (specific register; ordinal register)
21, 21b, 21c Arithmetic circuits 22, 22b Transfer control circuit (control circuit)
23 Control circuit

Claims (10)

A plurality of registers capable of storing a floating-point number whose number of digits in the mantissa part is one digit larger than an operand given as a floating-point number including a mantissa part and an exponent part, and an arithmetic circuit for performing an operation with reference to the value of each register And a control method of an arithmetic unit having a control circuit for controlling each of the registers and the arithmetic circuit,
When two operands for addition or subtraction are given, the value of the least significant digit of each mantissa becomes 0 and the remaining value corresponds to each of two of the plurality of registers. A writing step in which the control circuit writes an operand to each of the registers so as to be an operand;
Of the registers storing the above operands, when the values of the exponents of the two are different, the larger one is the first register, and when the values of the exponents of both are the same, one of these registers is the first register, Of the registers storing the operands, when the second register is not the first register, the arithmetic circuit calculates the mantissa value of the second register by the difference between the exponents of the two registers. An alignment step of shifting right and storing in any of the plurality of registers;
An operation for calculating the mantissa part of the operation result by calculating an addition result or a subtraction result between the value of the mantissa part of the first register and the value of the mantissa part of the register storing the shift result in the alignment step. Process,
Executed before the operation step, and the control circuit includes a setting step for setting a predetermined number for rounding to the least significant digit of the mantissa part of the first register. A control method for an arithmetic device. A plurality of registers capable of storing a floating-point number whose number of digits in the mantissa part is one digit larger than an operand given as a floating-point number including a mantissa part and an exponent part, and an arithmetic circuit for performing an operation by referring to the value of each register And a control circuit that controls each of the registers and the arithmetic circuit,
When two operands for addition or subtraction are given to the control circuit, the least significant digit value of each mantissa is set to 0 and the remaining value is set to two of the plurality of registers. , The operands are written to the registers so that the corresponding operands are
In the arithmetic circuit, when the values of the exponent parts of the operands are different from each other, the larger one is the first register, and when the values of the exponent parts are the same, one of these registers is assigned. When the second register is the first register and the one that stores each of the operands is not the first register, the value of the mantissa part of the second register is the digit of the difference between the exponents of the two registers. And right-shifted and stored in one of the plurality of registers, and the addition result or subtraction result of the value of the mantissa part of the first register and the value of the mantissa part of the register storing the shift result is To calculate the mantissa part of the operation result,
Further, the control circuit sets a predetermined number for rounding to the least significant digit of the mantissa part of the first register before the arithmetic circuit obtains the mantissa part of the operation result. An arithmetic device characterized by that.   A plurality of registers capable of storing a floating-point number whose number of digits in the mantissa part is one digit larger than an operand given as a floating-point number including a mantissa part and an exponent part, and an arithmetic circuit for performing an operation with reference to the value of each register A program that causes a computer having a control circuit that controls each of the registers and the arithmetic circuit to execute each step according to claim 1. A plurality of registers capable of storing a floating point number whose number of digits in the mantissa part is one digit larger than an operand given as a floating point number including a mantissa part and an exponent part; a specific register capable of storing the operand; A control method for an arithmetic device having an arithmetic circuit that performs an operation with reference to a register value, and a control circuit that controls each of the registers and the arithmetic circuit,
When two operands for multiplication are given, the value of the least significant digit of each mantissa part becomes 0 and the remainder becomes one of the operands to one of the plurality of registers. The control circuit writes the operand to the register and writes the other of the operands to the specific register;
An acquisition step in which the control circuit acquires the value of each digit of the mantissa part of the specific register in order from the least significant digit;
The mantissa of the register in which the operation result is stored among the plurality of registers according to an instruction from the control circuit is performed corresponding to each digit acquired in the acquisition step. The value of the mantissa of the register in which the operand is written is added by the number of times of the corresponding digit, and the addition result is written to one of the plurality of registers. Process,
The arithmetic circuit shifts the value of the mantissa part of the register in which the addition result is written in the addition step corresponding to the same digit to the right by one digit. A shift step of writing the shift result into one of the plurality of registers as a new operation result;
Of the above addition steps, the control circuit is executed before the final addition step, and the control circuit performs a rounding process in advance on the least significant digit of the mantissa part of the register in which the operand is written out of the plurality of registers. And a setting step for setting a predetermined number. A plurality of registers capable of storing a floating point number whose number of digits in the mantissa part is one digit larger than an operand given as a floating point number including a mantissa part and an exponent part; a specific register capable of storing the operand; An arithmetic device having an arithmetic circuit that performs an operation referring to a value of a register, and a control circuit that controls each of the registers and the arithmetic circuit,
When two operands for multiplication are given, the control circuit sets the value of the least significant digit of each mantissa part to one of the plurality of registers to be 0, and the remainder is the value of the operand. Write the operand to the register so that it becomes one, write the other operand to the specific register, and obtain the value of each digit of the mantissa part of the specific register in order from the lowest digit Is what
The arithmetic circuit, based on an instruction from the control circuit, for each digit acquired by the control circuit, to the value of the mantissa part of the register in which the current arithmetic result is stored among the plurality of registers. Among the registers, the value of the mantissa part of the register in which the operand is written is added by the number of times of the corresponding digit, the addition result is written to one of the plurality of registers, and the value of the mantissa part of the register Is shifted one digit to the right, and the shift result is written to one of the plurality of registers as a new operation result.
The control circuit further includes a number predetermined for rounding to the least significant digit of the mantissa part of the register in which the operand is written out of the plurality of registers before the final addition by the arithmetic circuit. An arithmetic device characterized in that it is set.   A plurality of registers capable of storing a floating point number whose number of digits in the mantissa part is one digit larger than an operand given as a floating point number including a mantissa part and an exponent part; a specific register capable of storing the operand; The program which makes a computer which has the arithmetic circuit which calculates with reference to the value of a register, and the control circuit which controls each said register | resistor and arithmetic circuit to perform each process of Claim 4. A plurality of registers capable of storing an operand given as a floating-point number including a mantissa part and an exponent part; an arithmetic circuit for performing an operation by referring to the value of each register; and a control circuit for controlling the registers and the arithmetic circuit. A method of controlling an arithmetic unit having
When two operands for division are given, the control circuit writes a corresponding operand to each of two of the plurality of registers;
Of the plurality of registers, a register storing the ordinal number of the operands is an ordinal register, a register storing the ordinal number of the operands is an ordinal register, and a register storing the operation result is an operation result register. When the arithmetic circuit shifts the value of the mantissa part of the mantissa register rightward by one digit by the number of digits of the mantissa part, the ordinal number from the value of the mantissa part of the mantissa register By determining how many times the value of the mantissa part of the register can be subtracted, each operation result is obtained, and each is stored in the corresponding digit of the mantissa part of the operation result register; and
A predetermined number of times for rounding the mantissa value of the ordinal register from the value of the mantissa part of the ordinal register after the arithmetic circuit is right-shifted by the number of digits of the mantissa part. And a rounding process for incrementing the mantissa part of the calculation result register by 1 when the calculation result register is subtracted. A plurality of registers capable of storing an operand given as a floating-point number including a mantissa part and an exponent part; an arithmetic circuit for performing an operation by referring to the value of each register; and a control circuit for controlling the registers and the arithmetic circuit. An arithmetic unit having
In the control circuit, when two operands for division are given, the control circuit writes corresponding operands to two of the plurality of registers,
The arithmetic circuit stores a result of an operation in which a register in which an ordinal number of the operands is stored is an ordinal register, a register in which the ordinal number of the operands is stored, and an ordinal register. When the register is an arithmetic result register, the value of the mantissa part of the mantissa register is shifted right by one digit by the number of digits of the mantissa part, and the ordinal number is calculated from the value of the mantissa part of the mantissa register. By determining how many times the value of the mantissa part of the register can be subtracted, each digit of the operation result is obtained and stored in the corresponding digit of the mantissa part of the operation result register. The mantissa value of the ordinal register after being shifted right by the number of times could be subtracted a predetermined number of times for rounding from the mantissa value of the ordinal register. If the arithmetic unit, characterized in that in which increased by one mantissa of the operation result register.   A plurality of registers capable of storing operands given as floating-point numbers including a mantissa part and an exponent part; an arithmetic circuit for performing an operation with reference to the value of each register; and a control circuit for controlling the registers and the arithmetic circuit. The program which makes a computer which has these execute each process of Claim 7.   A recording medium on which the program according to claim 3, 6 or 9 is recorded.

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