JP4271589B2 - Control method of arithmetic device, program thereof and recording medium - Google Patents

Description

  The present invention is preferably used for, for example, scaling processing, and the remainder obtained by dividing the dividend given as a floating-point number by the divisor and, if necessary, the quotient (arrangement) in a shorter time. The present invention relates to an arithmetic device control method, an arithmetic device, a program thereof, and a recording medium.

  Conventionally, for example, when calculating a function whose value periodically changes, such as a trigonometric function, a value corresponding to an argument in a certain range is stored, and the value is deviated from the above range by referring to it. A method for calculating a value corresponding to the argument is widely used.

  For example, taking the case of trigonometric function y = sin (x) as an example, y corresponding to −π / 2 ≦ x ≦ + π / 2 is stored, and when the absolute value of input x is large, x (dividend) ) Is divided by π / 2 (divisor) and the remainder is obtained, and then the value of the function is calculated from y stored correspondingly after entering the range of −π / 2 to π / 2. is doing.

On the other hand, when dividing an integer instead of a floating-point number, Patent Document 1 described later includes an approximate digit alignment circuit that calculates a shift amount based on the number of invalid bits of 0 following the most significant digit of the dividend and the divisor. A left shifter that shifts the dividend to the left by the shift amount, a divisor conversion unit that converts the divisor so that a partial remainder and a partial quotient can be obtained simultaneously when the divisor is subtracted from the dividend, and the left-shifted dividend is 1 bit By providing a division processing unit that repeatedly subtracts the divisor while shifting leftward one by one, the partial remainder and partial quotient can be obtained simultaneously, saving the division processing step, and the redundant circuit of the division circuit for dividing the upper invalid bits of the dividend A configuration is disclosed in which the number of iterations in the division circuit is reduced without reducing the operation and increasing the circuit scale.
JP 2002-175179 A (publication date: June 21, 2002)

  However, when the divisor and the dividend are expressed as floating-point numbers, the method of Patent Document 1 cannot be adopted as it is. On the other hand, when calculating the remainder, if the remainder x2 and the quotient q are calculated by q = INT (x / y) and x2 = x−q * y, there arises a problem that it takes time for the floating point calculation.

  The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a control method and a calculation method for an arithmetic device capable of calculating an integer division result and a remainder with a smaller calculation amount and calculation time. It is to provide an apparatus, a program thereof, and a recording medium.

  In order to solve the above problems, a control method for an arithmetic unit according to the present invention includes a dividend and a divisor register for storing a dividend and a divisor given as floating point numbers including a mantissa part and an exponent part, respectively, and a quotient for storing a quotient. A control method for an arithmetic unit comprising a register, an arithmetic circuit that performs an operation with reference to values of the registers, and a control circuit that controls the registers and the arithmetic circuit, wherein the arithmetic circuit includes the control circuit The subtraction step for subtracting the exponent part of the divisor register from the exponent part of the dividend register based on the instruction of the divisor register, and when shifted left, from the mantissa part of the dividend register including the digit, the divisor register When the mantissa part of the quotient register can be subtracted, 1 is set to the least significant digit of the quotient register, and when the subtraction cannot be performed, 0 is set to the least significant digit of the quotient register. And repeating the process of shifting the mantissa part of the dividend register and the quotient register one digit at a time, based on an instruction from the control circuit, by the number of subtraction results of the subtraction process. It is characterized by including.

  In the above configuration, since the number of repetitions of both processes in the repetition process is set to the number of subtraction results in the subtraction process, the value of the quotient register at the end of the repetition process is an integerized division result, The value of the dividend register at the time is the remainder.

  Therefore, as in normal division, both processes of the iteration process are repeated by the number of significant digits to obtain a division result, and the division result is converted to an integer, and the integer value and the divisor are calculated from the dividend. Compared with the case where the multiplication result is subtracted, the number of repetitions of both processes can be reduced.

  As a result, it is possible to calculate the integer division result and the remainder with a smaller calculation amount and calculation time.

  In order to solve the above problems, an arithmetic unit according to the present invention includes a dividend and divisor register for storing a dividend and a divisor given as floating point numbers including a mantissa part and an exponent part, and a quotient register for storing a quotient. And an arithmetic circuit that performs an operation by referring to the values of the registers, and a control circuit that controls the registers and the arithmetic circuit. The arithmetic circuit is based on an instruction from the control circuit. The exponent part of the divisor register can be subtracted from the exponent part of the dividend register, and when shifted left, the mantissa part of the divisor register can be subtracted from the mantissa part of the dividend register including the digit. If the least significant digit of the quotient register is set to 1 and subtraction is not possible, the process of setting 0 to the least significant digit of the quotient register and the dividend Mantissa registers and a process of left-shifting the quotient register by one order of magnitude, and wherein the number of times of subtraction result of the subtraction step is to repeat.

  Since the arithmetic device can execute the control method of the arithmetic device, as in the control method of the arithmetic device, the arithmetic result and the remainder can be calculated with a smaller arithmetic amount and arithmetic time.

  By the way, although the said arithmetic unit may be implement | achieved only with hardware, you may implement | achieve combining software and hardware. Specifically, the program according to the present invention includes a dividend and divisor register for storing a dividend and a divisor given as floating point numbers including a mantissa part and an exponent part, a quotient register for storing a quotient, and each of these registers Is a program that causes a computer having an arithmetic circuit that performs an operation with reference to the value of the above and a control circuit that controls the registers and the arithmetic circuit to execute the processes. The program is recorded on the recording medium according to the present invention.

  When these programs are executed by the computer, the computer executes each step of the control method of the arithmetic device. Therefore, as in the control method of the arithmetic unit, the integer division result and the remainder can be calculated with a smaller calculation amount and calculation time.

  According to the present invention, it is possible to reduce the number of iterations compared to the case of calculating the remainder after normalization by dividing into integers. Therefore, the division result and the remainder converted to integers can be obtained with less calculation amount and calculation time. It is possible to calculate and to achieve an effect that a scaling process and the like can be executed at high speed.

  An embodiment of the present invention will be described below with reference to FIGS. That is, the control method of the arithmetic unit according to the present embodiment uses a floating-point number subtraction to obtain a floating-point number division result (strictly, quotient), but relatively quickly. This is a method capable of calculating the remainder and can be suitably used for scaling processing and the like. Here, for example, when the absolute value of the input x of the trigonometric function sin (x) is large, the scaling process is performed by dividing x by π / 2 to obtain the remainder, thereby obtaining −π / 2 to π / 2 is a process for obtaining a remainder when dividing a given dividend x by a divisor y and a quotient (an adjusted quotient) as needed, such as a process of entering a range of 2, where the remainder is x2 and the quotient is q. Q = INT (x / y) and x2 = x−q * y.

  Specifically, the arithmetic device 1 according to the present embodiment is a device that performs the above-described scaling processing by floating-point arithmetic, and displays a floating-point value with a predetermined bit width as shown in FIG. First and second registers 11 and 12 for storing a predetermined number (floating point number), third and fourth registers 13 and 14 for storing a signed or unsigned integer of a predetermined bit width, and instructions Accordingly, an operation is performed with reference to the values of the registers 11 to 14, and an operation circuit 21 that can write the operation result to the registers 11 to 14 and an instruction to the registers 11 to 14 according to an instruction. Or the transfer control circuit 22 for controlling the data transfer from the registers 11 to 14 and the registers 11 to 14 and the arithmetic circuit 2 according to a predetermined algorithm. And a control circuit 23 for controlling the transfer control circuit 22 stores the dividend x and divisor y to be calculated of the subject, and a memory 31 that the operation result is written. The arithmetic circuit 21 and the transfer control circuit 22 correspond to the arithmetic circuit described in the claims.

  The floating-point numbers x and y to be calculated by the calculation device 1 according to the present embodiment are, for example, a code represented by 1 bit, an m-bit exponent part, and n and m, when n and m are predetermined natural numbers. , And an n-bit mantissa part. In the floating-point number according to the present embodiment, the value of the mantissa part is expressed as an absolute value.

  On the other hand, the first and second registers 11 and 12 are registers (floating point registers) capable of storing floating-point numbers, and store a sign, an exponent part, and a mantissa part, respectively, as shown in FIG. Regions AS1, AE1 and AM1, or AS2, AE2 and AM2 are provided. The first register (dividend register) 11 is used for storing a dividend and a remainder, and the second register 12 (divisor register) is used for storing a divisor. In the present embodiment, the bit widths of these areas AS1 (AS2), AE1 (AE2), and AM1 (AM2) are 1 bit, m bits, and n bits, respectively.

  The third register 13 is a register (quotient register) for storing a quotient, and its bit width is set to a bit width capable of storing the quotient as a signed integer. In the example of FIG. 3, the bit width of the third register 13 is set to L + 1 bits, and a quotient expressed as a combination of a 1-bit code and an L-bit unsigned integer (absolute value) is represented. I can remember. Further, the fourth register 14 is a working register, and its bit width is set to at least m bits (L + 1 bits as in the third register 13 in the example of FIG. 2).

  On the other hand, the arithmetic circuit 21 according to the present embodiment is realized by a logic circuit such as a combinational logic circuit and a sequential logic circuit, for example, an ALU (Arithmetic Logical Unit). That is, subtraction between exponent parts, subtraction between mantissa parts, exclusive OR operation between sign parts, arithmetic shift of mantissa part or integer part (left), increment of mantissa part or integer part, exponent part or integer part The decrement, the mantissa part or the comparison operation between the register and the indicated value, and the evaluation of a specific bit of the register are possible.

  More specifically, when the subtraction between the exponent parts is instructed from the control circuit 23, the arithmetic circuit 21 uses the exponent parts of the instructed two registers (first and second registers 11 and 12 in this embodiment). The values read from the area AE (AE1 and AE2 in this example) are subtracted from each other, and the subtraction result (for example, Xe−Ye) is subtracted from the specified area (for example, the fourth register 14). ) Can be stored. Similarly, when the subtraction between the mantissa parts is instructed, it is read out from the mantissa area AM (eg, AM1 · AM2) of the two instructed registers (eg, the first and second registers 11 and 12). The subtracted values can be subtracted from each other, and the subtraction result (for example, Xm−Ym) can be stored in the designated area of the designated register (for example, the mantissa area AM1 of the first register 11).

  In addition, when an exclusive OR operation between the code parts is instructed from the control circuit 23, the arithmetic circuit 21 is a code area of the instructed two registers (for example, the first and second registers 11 and 12). The exclusive OR of the values read from (for example, AS1 and AS2) is calculated, and the operation result (Xs EOR Ys) is calculated in the designated area of the designated register (for example, the sign of the first register 11). In the area AS1).

  Further, when the control circuit 23 instructs the left shift of the mantissa part or the integer part, the arithmetic circuit 21 reads the indicated area of the indicated register (for example, the mantissa part AM1 of the first register 11, The value read from the integer part AM3 of the third register 13 and the like can be shifted to the left by the designated digit, and the shifted value can be written in the read area. This left shift is an arithmetic left shift. As a result of the shift, the value of the newly inserted lower digit is set to “0”. Furthermore, the arithmetic circuit 21 can notify the control circuit 23 of the occurrence of an overflow when, for example, a left overflow occurs as a result of the left shift, for example, when the most significant bit is “1”. .

  In addition, when the decrement or increment is instructed from the control circuit 23, the arithmetic circuit 21 indicates the designated area (the exponent part AE1 of the first register 11, the integer part AM3 of the third register 13, the second register 13). The value read from the 4 register 14 or the like can be decremented or incremented, and the calculation result can be stored in the area where the value is read.

  Further, when the control circuit 23 instructs the mantissa parts to be compared with each other, the arithmetic circuit 21 has a mantissa part area of the two designated registers (for example, the mantissa part AM1 of the first and second registers 11 and 12). A value can be read from AM2) and compared, and the comparison result can be returned to the control circuit 23. Similarly, when a comparison with a predetermined value is instructed from the control circuit 23, an instructed area (for example, the fourth register 14) of one instructed register and an instructed value (for example, , 0, n, or L-1) and the comparison result can be returned.

  In addition, when an evaluation of a certain bit is instructed from the control circuit 23, the arithmetic circuit 21 selects the indicated bit (for example, the top of the area AM 1 of the first register 11) out of the indicated area of the indicated register. Evaluating the higher order bits), it is possible to return to the control circuit 23 whether the bit is “0” or “1”.

  On the other hand, the transfer control circuit 22 according to the present embodiment is, for example, a circuit configured by a logic circuit, and can store predetermined values in each register in accordance with an instruction from the control circuit 23. . Further, the transfer control circuit 22 stores the dividend x or divisor y read from the memory 31 in the designated register (for example, the first and second registers 11 and 12) in accordance with an instruction from the control circuit 23. Or the operation results X and Q stored in the instructed registers (for example, the first and third registers 11 and 13) based on the instruction of the control circuit 23, for example, a display process of the operation results, etc. It can be stored in the memory 31 for use in processing.

  Further, the control circuit 23 indicates the processing to be performed to the arithmetic circuit 21 and the transfer control circuit 22 by giving a control signal indicating an instruction code for specifying the processing to the arithmetic circuit 21 or the transfer control circuit 22, for example. Each can be controlled by applying a control signal. Further, the control circuit 23 not only controls each of the registers 11 and 12, the arithmetic circuit 21 and the transfer control circuit 22 in a predetermined order, but also includes the result of the arithmetic circuit 21 according to a predetermined algorithm. By receiving the difference between the comparison result and the value of the exponent part, the control of each of the registers 11 and 12, the arithmetic circuit 21, and the transfer control circuit 22 can be changed accordingly. The details of the algorithm will be described later together with the overall operation of the arithmetic device 1.

  For example, if the control circuit 23 can control the registers 11 and 12, the arithmetic circuit 21 and the transfer control circuit 22 with the algorithm, the control circuit 23 outputs each control signal to each at a predetermined timing and order. Alternatively, it may be realized by a logic circuit that reads the output of the arithmetic circuit 21 at a predetermined timing and applies the control signal, and changes the timing and order of the application of the control signal. Further, for example, an arithmetic means such as a CPU executes a program stored in a storage device such as a ROM or a RAM (none of which is shown), and the registers 11 and 12, the arithmetic circuit 21 and the transfer control circuit 22 are connected. You may implement | achieve by controlling. In this case, one or a plurality of computers having these means reads the recording medium (for example, CD-ROM) on which the program is recorded, and executes the program, whereby the arithmetic device 1 according to the present embodiment is executed. Can be realized.

  In the above configuration, for example, the dividend and the divisor are stored in a predetermined storage area of the memory 31, and a command indicating an instruction to start the operation is written to a predetermined address of the control circuit 23. When the start of the scaling process by the divisor y of the dividend x is instructed to 1, the arithmetic unit 1 in step 1 shown in FIG. 3 (hereinafter abbreviated as S1), as will be described in detail later. The first to fourth registers 11 to 14 are initialized, the dividend x and the divisor y are set in the first and second registers 11 and 12, 0 is stored in the third register 13, and the fourth register 14 is stored. The value obtained by subtracting the exponent part of the divisor y from the exponent part of the dividend x is set. Note that the arithmetic device 1 according to the present embodiment also determines whether or not the scaling process is necessary or not (described later) in the initialization process in S1.

  Hereinafter, the values stored in the first to fourth registers 11 to 14 are referred to as X, Y, Q, and Z, respectively. Further, each code is referred to by adding s to the end of the reference code, for example, the code of X is Xs, and the mantissa part or the absolute value of the integer is added with m at the end of the reference code. refer. Furthermore, the exponent parts of X and Y are referred to as Xe and Ye, respectively. In addition, in the arithmetic device 1 according to the present embodiment, as an example, x when the trigonometric function Sin (x) is calculated is scaled by π / 2, and is put in a range of −π / 2 to + π / 2. Therefore, x is stored in the first register 11 and y = π / 2 is stored in the second register 12 by the initialization process of S1.

  When the initialization process is completed in S1, the control circuit 23 of the arithmetic device 1 instructs the arithmetic circuit 21 in S2, and the sign parts of the values stored in the first and second registers 11 and 12 are exchanged. The exclusive OR is calculated, and the calculation result is stored in the area AS1 of the sign part of the first register 11 (Xs EOR Ys → Xs).

  Further, the control circuit 23 repeats the following processes of S3 to S9 as many times as the value Z stored in the fourth register 14 in S1. Specifically, in S3, the control circuit 23 instructs the arithmetic circuit 21 to compare the mantissa parts Xm and Ym of the values stored in the first and second registers 11 and 12, and receives the comparison result.

  When the mantissa part Xm is greater than or equal to the mantissa part Ym (in the case of YES in S3), the control circuit 23 instructs the arithmetic circuit 21 in S4 to change from the mantissa part Xm of the first register 11 to the second register. The value of 12 mantissa part Ym is subtracted, and the subtraction result is stored in the mantissa part area AM 1 of the first register 11. Further, the arithmetic circuit 21 increments the mantissa part Qm of the value stored in the third register 13 by 1 according to the instruction of the control circuit 23, and stores the arithmetic result in the mantissa part area AM 1 of the third register 13. (S5).

  When the processes of S4 and S5 are completed, or when the mantissa part Xm is smaller than the mantissa part Ym (NO in S3), the control circuit 23 instructs the arithmetic circuit 21 in S6. Then, the value stored in the fourth register 14 is compared with “0”, and the comparison result is received. If the two match (YES in S6), as will be described in detail later, in S21, the arithmetic unit 1 converts the format of the value X stored in the first register 11 to obtain the value. Normalization is performed so that the most significant bit of the mantissa part of X becomes 1, and in S22, the control circuit 23 instructs the transfer control circuit 22 to specify the floating point number X stored in the first register 11 and the third number. The quotient Q stored in the register 13 is stored in the memory 31, and the result of the scaling process is output.

On the other hand, if the value stored in the fourth register 14 is not 0 (NO in S6), the control circuit 23 instructs the arithmetic circuit 21 in S7 and stores it in the first register 11. 1 is subtracted from the exponent part Xe of the obtained value, the subtraction result is stored in the area AE1 of the exponent part of the first register 11 , and 1 is subtracted from the value Z stored in the fourth register 14, and the operation result is given as the fourth. It is stored in the register 14. In addition, the arithmetic circuit 21 shifts the mantissa part Xm of the value stored in the first register 11 to the left by 1 bit according to the instruction of the control circuit 23 and stores the arithmetic result in the mantissa part area AM1 of the first register 11. At the same time, the absolute value Qm of the value stored in the third register 13 is shifted one bit to the left, and the calculation result is stored in the absolute value area AM3 of the third register 13 (S8).

  Further, in S9, the control circuit 23 determines whether or not an overflow has occurred due to the left shift of the mantissa part Xm in S8. If no overflow has occurred (YES in S9). ), The above-described processing after S3 is repeated. On the other hand, when the digit overflow has occurred, the processing after S4 is repeated.

  In the above configuration, the number of repetitions of S3 to S5 and S7 to S9 is set to the value stored in the fourth register 14 in S1, that is, the value obtained by subtracting the exponent part of the divisor y from the exponent part of the dividend x. ing. Accordingly, the value Q of the third register 13 at the end of the repetition (YES at S6) is the integer division result, and the value X of the first register 11 at that time becomes the remainder.

  Therefore, as in normal division, the processes of S3 to S5 and S7 to S9 are repeated by the number of significant digits to obtain a division result, the division result is converted to an integer, and the integer is converted from the dividend. Compared to the case where the multiplication result of the value and the divisor is subtracted, the number of repetitions of the above process can be reduced. As a result, it is possible to calculate the integer division result and the remainder with a smaller calculation amount and calculation time.

In the above, in order to repeat the processing of S3 to S9 by the value Z stored in the fourth register 14 in S1, Z is subtracted in S7, and whether or not Z is 0 in S6. However, the present invention is not limited to this. For example, the control circuit 23 may instruct the arithmetic circuit 21 to determine whether or not Z <0, and the Z subtraction process may be moved before the determination. In any case, the same effect can be obtained if the number of repetitions of S3 to S5 and S7 to S9 is a value obtained by subtracting the exponent part of the divisor y from the exponent part of the dividend x.

  In the above description, in S5, 1 is set to the least significant bit of the value Qm of the integer part of the third register 13 by adding 1, but the third register 13 in S1 is cleared to 0 or Since the least significant bit is “0” by the left shift in S8, the same effect can be obtained even if the arithmetic circuit 21 sets “1” in the least significant bit in accordance with an instruction from the control circuit 23.

  Hereinafter, the initialization process of S1 and the normalization process of S21 will be described in some detail. That is, in S1, the steps S31 to S36 shown in FIG. 4 are performed. In other words, when the arithmetic device 1 receives an instruction to start scaling processing by the divisor y of the dividend x, the control circuit 23 of the arithmetic device 1 instructs the transfer control circuit 22 to become the dividend to the first register 11 in S31. A floating point number x is stored, and a floating point number y as a divisor is stored in the second register 12. In S32, the transfer control circuit 22 sets the value of the third register 13 to 0 in accordance with an instruction from the control circuit 23.

  Further, in S33, the arithmetic circuit 21 subtracts the exponent part Ye of the value stored in the second register 12 from the exponent part Xe of the value stored in the first register 11 according to the instruction of the control circuit 23, The subtraction result is stored in the 4 register 14.

  In S34 and S35, the arithmetic unit 1 instructs the arithmetic circuit 21 so that the value Z stored in the fourth register 14 is in the range of 0 or more and a predetermined value (L-1) or less. It is judged whether it is in or not. Note that L is the bit width of an area provided for storing the absolute value of an integer in the third register 13.

  In the present embodiment, whether the value Z is in the above range is determined based on whether the value Z is negative and whether it exceeds (L-1). More specifically, in S34, the control circuit 23 instructs the arithmetic circuit 21 to determine whether or not the value Z stored in the fourth register 14 is negative, and receives the determination result. When the determination result indicates negative (in the case of YES in S34 above), this indicates that the dividend X is smaller than the divisor Y, and the quotient is 0 without performing scaling processing. The dividend X indicates that there is a remainder. Therefore, in this case, the control circuit 23 skips S2 to S21 shown in FIG. 3, performs the process of S22, and sets the value (Q = 0) set in the third register 13 in S32 and the above S31. The value (X = x) set in the first register 11 is output as a scaling result.

  On the other hand, when the value Z stored in the fourth register 14 is not negative (NO in S34), the control circuit 23 instructs the arithmetic circuit 21 in S35 and is stored in the fourth register 14. A comparison result is received by comparing the obtained value Z with the value (L-1). When the comparison result indicates that it is greater than L-1 (YES in S35), this indicates that the quotient becomes so large that it cannot be stored in the third register 13. Therefore, in this case, the control circuit 23 instructs the transfer control circuit 22, for example, to clear the first register 11 to 0 in S36, and then stores the operation result of the memory 31 in the first register area. 11 is stored, and for example, the abnormal end process is performed by storing a value indicating the occurrence of an abnormality in an area of the memory 31 indicating the presence or absence of an abnormality.

  On the other hand, when the arithmetic unit 1 determines that the value Z stored in the fourth register 14 is in the range of 0 or more and not more than a predetermined value (L-1) (S34 described above). In the case of NO in both S35 and S35), the control circuit 23 ends the initialization process and executes the processes after S2 shown in FIG.

  In the above configuration, before starting the scaling process after S2, the arithmetic unit 1 makes the value Z stored in the fourth register 14 be in a range not less than 0 and not more than a predetermined value (L-1). It is determined whether or not it is entered. If it is not entered, the processing after S2 is skipped. As a result, when the process after S2 is not performed and the remainder and the quotient are known, or when it is determined that the correct quotient cannot be calculated by the process after S2 without performing the process. The processing can be skipped, and unnecessary processing can be prevented. As a result, it is possible to shorten the time until all the processes are completed, compared with the case where the above determination is not performed.

  On the other hand, in the normalization process of S21 shown in FIG. 3, the processes of S41 to S51 are performed as shown in FIG. Specifically, in S41, the control circuit 23 instructs the arithmetic circuit 21 to compare the value Z of the fourth register 14 with n, and receives the comparison result. Note that n is the bit width of the mantissa part of the first and second registers 11 and 12 as described above.

  If they do not match (NO in S41), the control circuit 23 instructs the arithmetic circuit 21 in S42 to evaluate the value of the most significant bit of the mantissa part of the first register 11, and the evaluation result Receive.

  If the most significant bit indicates “1” (YES in S42), the value X of the first register 11 indicates that it has already been normalized. Therefore, in this case, the control circuit 23 ends the normalization process, and executes the processes after S22 shown in FIG.

  On the other hand, when the most significant bit is not “1” (NO in S42), the control circuit 23 instructs the arithmetic circuit 21 in S43 to indicate the value of the exponent part of the first register 11. Xe is decremented by 1 and stored in the exponent part area AE1 of the first register 11. Further, the arithmetic circuit 21 shifts the value Xm of the mantissa part of the first register 11 to the left by 1 bit based on the instruction of the control circuit 23 and stores the result in the area AM1 of the mantissa part of the first register 11. . In addition, the control circuit 23 instructs the arithmetic circuit 21 to increase the value of the fourth register 14 by one. Further, the control circuit 23 repeats the processes after S41.

  Here, the processing of S41 to S43 is repeated until the most significant bit of the mantissa part of the first register 11 becomes “1”. If the remainder is 0, the number of times of the bit width of the mantissa part Even if it is repeated (n times), the most significant bit does not become “1”. In this case, in S41, the value Z of the loop counter coincides with n (YES in S41). Therefore, the control circuit 23 instructs the transfer control circuit 22 in S51 to store 0 in the first register 11, and then ends the normalization process. Execute the process.

  In the above configuration, the remainder exponent part is adjusted by the normalization process of S41 to S51 so that the most significant bit of the remainder mantissa part becomes 1 unless the remainder is 0. Therefore, even if the remainder after the scaling process is required to be normalized, the calculation can be continued without any trouble.

  In the above, in order to repeat the processing of S42 and S43 n times, the fourth register 14 is set as a loop counter, and it is determined whether or not the end condition (Z == n) is satisfied in S41. However, the present invention is not limited to this as long as these processes can be repeated n times. For example, another register may be provided and the register may be a loop counter. In this case, if the value of the register is cleared to 0 before S41, the end condition of S41 can be made the same (== n). The number of repetitions is determined by the bit width of the mantissa part of the first and second registers 11 and 12, so that the program code for the processing of S42 and S43 may be repeated n times in the program. Good. In any case, the same effect can be obtained if the processes of S42 and S43 can be repeated n times.

  According to the present invention, it is possible to obtain a remainder when dividing a dividend given as a floating-point number by a divisor and a quotient (an integer quotient) if necessary in a shorter time. It can be suitably used for an arithmetic device that performs processing or the like.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1, showing an embodiment of the present invention, is a block diagram illustrating a main configuration of an arithmetic device. It is drawing which shows the register | resistor provided in the said arithmetic unit. It is a schematic flowchart which shows operation | movement of the said arithmetic unit. It is a flowchart which shows an initialization process in more detail among the said operation | movement. It is a flowchart which shows the remainder normalization process in more detail among the said operation | movement.

Explanation of symbols

1 arithmetic unit 11 first register (dividend register)
12 Second register (divisor register)
13 Third register (quotient register)
21 arithmetic circuit 22 transfer control circuit (arithmetic circuit)
23 Control circuit

Claims (3)

A dividend register and a divisor register for storing a dividend and a divisor given as floating point numbers including a mantissa part and an exponent part, respectively, a quotient register for storing a quotient, an integer register for storing an integer, and values of these registers A control method for an arithmetic device having an arithmetic circuit that performs a reference and a control circuit that controls each of the registers and the arithmetic circuit ,
From the exponent portion of the upper Symbol dividend register, and exponent subtraction step of subtracting the exponent of the divisor register,
An integer register value initial setting step of setting the subtraction result of the exponent part subtraction step to the value of the integer register;
A quotient register value initial setting step for setting the value of the quotient register to 0;
Only after the exponent subtraction step, integer register value initialization step, and quotient register value initialization step, the mantissa part of the dividend register is greater than or equal to the mantissa part of the divisor register. A mantissa subtraction step of subtracting the mantissa of the divisor register from the mantissa to increase the value of the quotient register by 1 ;
A determination step of determining whether the value of the integer register is 0 after the mantissa subtraction step;
In the determining step, when the value of the integer register is not 0, the exponent part of the dividend register and the value of the integer register are each subtracted, and the mantissa part of the dividend register and the quotient register are shifted to the left by one digit. And an integer register value subtraction step for shifting to the mantissa part subtraction step
And an output step of outputting the floating point number of the dividend register and the value of the quotient register as an operation result when the value of the integer register is 0 in the determination step. Control method. A dividend register and a divisor register for storing a dividend and a divisor given as floating point numbers including a mantissa part and an exponent part, respectively, a quotient register for storing a quotient, an integer register for storing an integer, and values of these registers A program for causing a computer having an arithmetic circuit to perform a reference and a control circuit for controlling each of the registers and the arithmetic circuit to execute each step according to claim 1. A computer-readable recording medium on which the program according to claim 2 is recorded.

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