JP2005123392A - Method for manufacturing ferroelectric capacitor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a ferroelectric capacitor which thins a film of a hard mask formed on an upper electrode film. <P>SOLUTION: An interlayer insulating film 20 is formed on a silicon substrate 10, and a lower electrode film 31', a ferroelectric film 33', and an upper electrode film 35' for the ferroelectric capacitor are sequentially formed on the interlayer insulating film 20. Next, a barrier film 41' is formed on the upper electrode film 35', and a resist mask 43 of a specific shape is formed on the barrier film 41'. The resist mask 43 is used as a mask, and the barrier film 41' and the upper electrode film 35' are etched for removing, and a hard mask 41 and an upper electrode 35 are formed, respectively. Next, this resist mask 43 is removed. The hard mask 41 is used as a mask, the ferroelectric film 33' and the lower electrode film 31' are etched for removing, and a ferroelectric of the ferroelectric capacitor and a lower electrode are formed, respectively. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a ferroelectric capacitor.

  Conventionally, a ferroelectric memory (FeRAM: ferroelectric memory) has been widely known as a nonvolatile memory utilizing the polarization hysteresis characteristic of a ferroelectric. The demand for this ferroelectric memory is increasing because of its low power consumption and high-speed operation. Such a ferroelectric memory is generally composed of a plurality of memory cells each composed of a ferroelectric capacitor and a switching MOS transistor. The ferroelectric capacitor is composed of an upper electrode and a lower electrode, and a ferroelectric substance sandwiched between the two electrodes.

The upper electrode and the lower electrode are made of noble metals such as platinum (Pt) and iridium (Ir), and the ferroelectric film is made of SBT (SrBi ₂ Ta ₂ O ₉ ) or PZT (PbZr _1-X Ti _X O ₃ ) Or the like is often used. Such noble metals, SBT, and the like have poor reactivity with the etching gas, and a sufficient etching selectivity cannot be obtained with the resist film.

That is, when a ferroelectric capacitor is formed by etching a top electrode film, a ferroelectric film, a bottom electrode film, etc. using a resist film having a predetermined pattern (that is, a resist mask) as a mask, this series of etching is performed. In this process, the surface of the resist mask is greatly shaved, and the resist mask is retracted to the substrate side. Therefore, as a method for delaying such mask recession, a method using a hard mask made of SiO ₂ , SiO, SiN, SiON, TiN, TiO ₂ or the like instead of a resist mask is known (for example, Patent Documents). 1 and 2).

According to such a method, since the hard mask is harder to etch than the resist mask, the upper electrode film, the ferroelectric film, and the lower electrode film are sequentially dry etched while suppressing the recession of the mask to some extent. Thus, a ferroelectric capacitor can be formed. Further, in this series of etching processes, the gas type and mixing ratio of the etching gas are devised in order to suppress the amount of hard mask scraping as much as possible.
JP 2002-280524 A JP 2002-94019 A

  By the way, according to the method for forming a ferroelectric capacitor described in Patent Document 1 and the like, the upper electrode film, the ferroelectric film, and the lower electrode film are sequentially dry-etched using one hard mask. Therefore, the amount of scraping of the hard mask reaches a considerable amount when the etching of the lower electrode film is completed. In addition, since this hard mask reflects all the etching variations of the upper electrode film, the ferroelectric film, and the lower electrode film, the amount of abrasion within the wafer surface of the hard mask and between lots can be reduced. The variation is large.

  For this reason, in the method described in the above-mentioned Patent Document 1 and the like, it is necessary to form the hard mask particularly thick in consideration of the amount of shaving of the hard mask and the magnitude of the variation thereof. In addition, when the hard mask is formed thick in this way, the hard mask is often left thick in a state where the thickness of the hard mask is large when the etching of the lower electrode film is completed. Therefore, in the process of removing the hard mask, the hard mask must be over-etched excessively for the purpose of complete removal of the hard mask, and the interlayer insulating film around the ferroelectric capacitor is greatly shaved by the over-etching. There was a risk of it.

  SUMMARY OF THE INVENTION Accordingly, the present invention has been made to solve such problems, and an object thereof is to provide a method for manufacturing a ferroelectric capacitor in which a hard mask formed on an upper electrode film can be thinned.

  In order to solve the above-described problems, a first method for manufacturing a ferroelectric capacitor according to the present invention is a method for forming a ferroelectric capacitor, wherein an insulating film is formed on a substrate, and the insulating film is formed on the insulating film. Sequentially forming a lower electrode film, a ferroelectric film and an upper electrode film for the ferroelectric capacitor, forming a barrier film on the upper electrode film, and forming a predetermined shape on the barrier film. A resist mask is formed, and the barrier film and the upper electrode film are removed by etching using the resist mask as a mask to form a hard mask made of the barrier film and an upper electrode of the ferroelectric capacitor, respectively. Removing the resist mask after forming the upper electrode, and sequentially removing the ferroelectric film and the lower electrode film by etching using the hard mask as a mask. Forming ferroelectric collector capacitor and the lower electrode, respectively, it is characterized in that comprises a.

Here, the upper electrode film and the lower electrode film are made of a noble metal having high corrosion resistance such as platinum (Pt) or iridium (Ir). The ferroelectric film is made of, for example, SBT (SrBi ₂ Ta ₂ O ₉ ) or PZT (PbZr _1-X Ti _X O ₃ ).
According to the first ferroelectric capacitor manufacturing method of the present invention, the resist mask is used as an etching mask for the upper electrode film, and the hard mask is used as an etching mask for the ferroelectric film and the lower electrode film. Therefore, the hard mask formed on the upper electrode film can be made thinner than in the conventional method. Thereby, the etching conditions (for example, etching time etc.) at the time of removing this hard mask can be eased.

  A second method of manufacturing a ferroelectric capacitor according to the present invention is a method of forming a ferroelectric capacitor, wherein an insulating film is formed on a substrate, and a lower portion for the ferroelectric capacitor is formed on the insulating film. A step of sequentially forming an electrode film, a ferroelectric film, and an upper electrode film; a step of forming a barrier film on the upper electrode film; and forming a resist mask having a predetermined shape on the barrier film; The barrier film, the upper electrode film, and the ferroelectric film are removed by etching using the mask as a mask, and the hard mask made of the barrier film, and the upper electrode and the ferroelectric substance of the ferroelectric capacitor are respectively removed. Forming a resist, removing the resist mask after forming the ferroelectric, etching the lower electrode film using the hard mask as a mask, and removing the lower electrode of the ferroelectric capacitor. A step of forming and is characterized in that it comprises a.

According to the second method for manufacturing a ferroelectric capacitor according to the present invention, since the hard mask is used as an etching mask for only the lower electrode film, the hard mask is compared with the method for manufacturing the first ferroelectric capacitor. The etching conditions (for example, etching time) when removing the hard mask can be further relaxed.
The third ferroelectric capacitor manufacturing method according to the present invention is the above-described first and second ferroelectric capacitor manufacturing methods, wherein the insulating film is formed on the substrate after the insulating film is formed. Forming an adhesion layer on the insulating film to enhance adhesion to the lower electrode film, and then sequentially forming the lower electrode film, the ferroelectric film, and the upper electrode film on the adhesion layer; It is a feature.

According to the third method of manufacturing a ferroelectric capacitor according to the present invention, when the lower electrode film is formed by etching the lower electrode film using the hard mask as a mask, the interlayer insulation of the lower electrode is formed. Peeling from the film can be prevented.
According to a fourth method for manufacturing a ferroelectric capacitor according to the present invention, in the first to third methods for manufacturing a ferroelectric capacitor, the barrier film is made of titanium aluminum nitride (TiAlN). It is what.

The fifth ferroelectric capacitor manufacturing method according to the present invention is the above-described fourth ferroelectric capacitor manufacturing method, wherein the lower electrode film is removed by etching using the hard mask as a mask. When forming the lower electrode of the ferroelectric capacitor, a mixed gas composed of chlorine (Cl ₂ ), oxygen (O ₂ ), and argon (Ar) is used as an etching gas.

Here, the adhesion layer is made of a titanium-based compound such as titanium oxide (TiO _x ) or titanium aluminum nitride (TiAlN). In dry etching using a mixed gas composed of chlorine (Cl ₂ ), oxygen (O ₂ ), and argon (Ar), a high etching selection is made between such an adhesion layer and a hard mask and the lower electrode. It is possible to obtain a ratio.

  According to the fourth and fifth methods for manufacturing a ferroelectric capacitor according to the present invention, when the lower electrode film is formed by etching the lower electrode film, the amount of abrasion of the hard mask can be suppressed low. Therefore, it is possible to form the lower electrode in a predetermined shape with good reproducibility. Moreover, the amount of abrasion of the adhesion layer can be kept low by configuring the adhesion layer with the titanium-based compound as described above. This eliminates the need to expose the underlying insulating film to the etching atmosphere when forming the lower electrode.

A sixth method for manufacturing a ferroelectric capacitor according to the present invention uses chlorine (Cl ₂ ) gas after forming the lower electrode in the above-described fourth and fifth methods for manufacturing a ferroelectric capacitor. And a step of etching and removing the hard mask.
According to the sixth method for manufacturing a ferroelectric capacitor according to the present invention, since the hard mask and the adhesion layer can be etched at the same time, for example, the amount of abrasion of the interlayer insulating film under the lower electrode can be reduced.

Hereinafter, a method for manufacturing a ferroelectric capacitor according to an embodiment of the present invention will be described with reference to the drawings.
FIG. 1A to FIG. 3C are process diagrams (parts 1 to 3) showing a method of manufacturing the ferroelectric memory 100 according to the embodiment of the present invention. This process diagram shows a method of forming a ferroelectric capacitor 30 on the interlayer insulating film 20 on the silicon substrate 10 along the procedure.

In FIG. 1A, first, an interlayer insulating film 20 is formed on a silicon substrate 10 on which a MOS transistor or the like (not shown) is formed. The interlayer insulating film 20 is, for example, a silicon oxide film or the like, and is formed by, for example, a CVD (Chemical Vapor Deposition) method. Next, an adhesion layer 23 is formed on the interlayer insulating film 20. The adhesion layer 23 is a film for enhancing adhesion between a lower electrode 31 and an interlayer insulating film 20 described later. The adhesion layer 23 is made of a titanium-based compound such as titanium oxide (TiO _x ) or titanium aluminum nitride (TiAlN), and has a film thickness of about several hundreds [Å], for example. The adhesion layer 23 is formed by, for example, (sputtering method).

  Next, as shown in FIG. 1B, a lower electrode film 31 ′ made of platinum or the like is formed on the adhesion layer 23. The lower electrode film 31 ′ is formed by, for example, a sputtering method. Then, a ferroelectric film 33 ′ made of, for example, SBT or the like is formed on the lower electrode film 31 ′. The formation of the ferroelectric film 33 'is performed by, for example, a well-known sol-gel method. Further, an upper electrode film 35 ′ made of, for example, platinum is formed on the ferroelectric film 33 ′. The upper electrode film 35 'is formed by, for example, a sputtering method.

  Next, as shown in FIG. 1C, a titanium aluminum nitride (TiAlN) film 41 'is formed on the upper electrode film 35'. The film thickness of the TiAlN film 41 ′ is, for example, about 2000 [Å]. The TiAlN film 41 ′ is formed by, for example, (sputtering method). Next, as shown in FIG. 2A, a resist mask 43 having a predetermined shape is formed on the TiAlN film 41 'so as to cover the region where the ferroelectric capacitor is to be formed and to expose the other regions. . The resist mask 43 is formed using, for example, a photolithography technique.

Next, as shown in FIG. 2B, the TiAlN film is removed by etching using the resist mask 43 as a mask to form a hard mask 41 made of TiAlN. The hard mask 41 is formed by plasma etching using, for example, chlorine (Cl ₂ ). Subsequently, as shown in FIG. 2C, the upper electrode film is removed by etching using the resist mask 43 as a mask to form the upper electrode 35. The upper electrode 35 is formed by plasma using a mixed gas (hereinafter referred to as Cl ₂ / O ₂ / Ar gas) composed of, for example, chlorine (Cl ₂ ), oxygen (O ₂ ), and argon (Ar). Etching is performed.

By the way, the above-described plasma etching using Cl ₂ / O ₂ / Ar gas cannot provide a sufficient etching selectivity between the upper electrode 35 made of platinum or the like and the resist mask 43. For this reason, as shown in FIG. 2C, the resist mask 43 is etched from the upper surface and side surfaces thereof, and retracts toward the silicon substrate 10 side. Further, since the plasma etching using the Cl ₂ / O ₂ / Ar gas is anisotropic, the resist mask 43 is etched larger from the upper surface than the side surface.

  For this reason, as shown in FIG. 2C, the resist mask 43 after the upper electrode 35 is formed has a substantially trapezoidal shape in a sectional view (hereinafter referred to as a sectional shape). Further, since the hard mask 41 made of TiAlN and the upper electrode 35 are formed using the resist mask 43 as a mask, the cross-sectional shapes of the hard mask 41 and the upper electrode 35 are also substantially trapezoidal.

Further, in the above-described plasma etching using Cl ₂ / O ₂ / Ar gas, the upper electrode film made of platinum or the like is over-etched to some extent to remove all the upper electrode films exposed from under the resist mask 43. For this reason, in the region exposed from below the resist mask 43, the ferroelectric film 33 ′ which is the base of the upper electrode film is also etched to some extent. Therefore, after the formation of the upper electrode 35, as shown in FIG. 2C, the ferroelectric film 33 ′ exposed from the bottom of the resist mask 43 is also etched to some extent to reduce the film.

Next, as shown in FIG. 3A, the resist mask 43 is removed by ashing. Then, the ferroelectric film 33 ′ is removed by etching using the hard mask 41 exposed from below the resist mask as a mask. As a result, a ferroelectric 33 is formed as shown in FIG. The ferroelectric 33 is formed by plasma etching using CF ₄ / Ar gas, for example.

Subsequently, the lower electrode film is removed by etching using the hard mask 41 as a mask to form the lower electrode 31. The lower electrode 31 is formed by plasma etching using, for example, Cl ₂ / O ₂ / Ar gas. As described above, since the adhesion layer 23 made of a titanium-based compound is formed between the lower electrode 31 and the interlayer insulating film 20, the etching ratio using the gas system is high. Etching can be prevented on the adhesion layer. In this way, the ferroelectric capacitor 30 including the lower electrode 31, the ferroelectric 33, and the upper electrode 35 is formed on the interlayer insulating film 20.

Next, the adhesion layer 23 is etched using the hard mask 41 as a mask, and the adhesion layer 23 is removed from the interlayer insulating film 20 other than the region where the ferroelectric capacitor 30 is formed. The adhesion layer 23 is etched by plasma etching using a gas such as Cl ₂ . Thereby, the hard mask made of TiAlN is removed from the upper electrode 35 as shown in FIG. In this plasma etching using Cl ₂ gas, the interlayer insulating film made of SiO ₂ is hardly etched, whereas the hard mask made of TiAlN is etched well. Therefore, it is possible to remove only the hard mask without almost etching the interlayer insulating film 20.

  Thus, according to the method of manufacturing the ferroelectric memory 100 according to the present invention, the resist mask 43 is used as an etching mask for the upper electrode film 35 ', and the hard mask 41 is used for the ferroelectric film 33' and the lower electrode. Since it is used as an etching mask for the film 31 ', the hard mask 41 formed on the upper electrode film 35' can be made thinner than in the conventional method. Thereby, the etching conditions (for example, etching time) when removing the hard mask 41 can be relaxed, and the amount of abrasion of the interlayer insulating film 20 can be reduced.

The hard mask 41 may be made of SiO ₂ or the like. However, the hard mask 41 is made of TiAlN instead of SiO ₂ or the like, so that the etching selectivity between the hard mask 41 and the interlayer insulating film 20 is increased. Can be made high enough. Thus, the etching of the interlayer insulating film 20 can be suppressed when the hard mask 41 is removed by plasma etching using Cl ₂ / O ₂ gas, so that the hard mask 41 is made of SiO ₂ or the like. In addition, the amount of abrasion of the interlayer insulating film 20 can be further reduced.

  In this embodiment, the ferroelectric capacitor 30 corresponds to the ferroelectric capacitor of the present invention, and the silicon substrate 10 corresponds to the substrate of the present invention. The interlayer insulating film 20 corresponds to the insulating film of the present invention, and the resist mask 43 corresponds to the resist mask of the present invention. Further, the lower electrode film 31 'corresponds to the lower electrode film of the present invention, and the lower electrode 31 corresponds to the lower electrode of the present invention. Further, the ferroelectric film 33 ′ corresponds to the ferroelectric film of the present invention, and the ferroelectric 33 corresponds to the ferroelectric film of the present invention. Further, the upper electrode film 35 'corresponds to the upper electrode film of the present invention, and the upper electrode 35 corresponds to the upper electrode of the present invention. Further, the TiAlN film 41 ′ corresponds to the barrier film of the present invention, and the hard mask 41 corresponds to the hard mask of the present invention. Furthermore, the adhesion layer 23 corresponds to the adhesion layer of the present invention.

  In this embodiment, the ferroelectric film 33 ′ and the lower electrode film 31 ′ are sequentially etched using the hard mask 41 as a mask to form the ferroelectric 33 and the lower electrode 31, respectively. However, according to the present invention, the TiAlN film 41 ′, the upper electrode film 35 ′, and the ferroelectric film 33 ′ are sequentially etched and removed using the resist mask 43 as a mask, so that the upper electrode 35 and the hard mask 41 are removed. And the ferroelectric 33, and after the resist mask 43 is removed, the lower electrode 31 is formed by etching and removing the lower electrode film 31 'using the hard mask 41 as a mask. good. According to such a configuration, since the hard mask 41 is used as an etching mask for only the lower electrode film 31 ′, the thickness of the hard mask 41 is further reduced as compared with the above-described embodiment. Can do.

  In this embodiment, the case where a silicon substrate is used as an example of the substrate has been described. However, the substrate of the present invention is not limited to this, and may be, for example, an SOI (silicon on insulator) substrate. When an SOI substrate is used as the substrate of the present invention, a MOS transistor (not shown) is formed on the top silicon layer of the SOI substrate. The interlayer insulating film 20 is formed on this top silicon layer.

FIG. 5 is a process diagram showing a manufacturing method (part 1) of the ferroelectric memory 100; FIG. 5 is a process diagram showing a manufacturing method (part 2) of the ferroelectric memory 100; FIG. 5 is a process diagram showing a method (part 3) for manufacturing the ferroelectric memory 100;

Explanation of symbols

  10 silicon substrate, 20 interlayer insulation film, 23 adhesion layer, 31 lower electrode, 31 ′ lower electrode film, 33 ferroelectric, 33 ′ ferroelectric film, 35 upper electrode, 35 ′ upper electrode film, 41 hard mask, 41 'Barrier film, 43 resist mask, 30 ferroelectric capacitor, 100 ferroelectric memory

Claims (6)

A method of forming a ferroelectric capacitor, comprising:
Forming an insulating film on the substrate and sequentially forming a lower electrode film, a ferroelectric film and an upper electrode film for the ferroelectric capacitor on the insulating film;
Forming a barrier film on the upper electrode film;
A resist mask having a predetermined shape is formed on the barrier film, the barrier film and the upper electrode film are removed by etching using the resist mask as a mask, a hard mask made of the barrier film, and the ferroelectric Forming each of the upper electrodes of the capacitors;
Removing the resist mask after forming the upper electrode;
Using the hard mask as a mask to sequentially remove the ferroelectric film and the lower electrode film by etching to form the ferroelectric capacitor and the lower electrode of the ferroelectric capacitor, respectively. A method for manufacturing a ferroelectric capacitor. A method of forming a ferroelectric capacitor, comprising:
Forming an insulating film on the substrate and sequentially forming a lower electrode film, a ferroelectric film and an upper electrode film for the ferroelectric capacitor on the insulating film;
Forming a barrier film on the upper electrode film;
A resist mask having a predetermined shape is formed on the barrier film, and the barrier film, the upper electrode film, and the ferroelectric film are removed by etching using the resist mask as a mask, and a hard mask made of the barrier film And forming each of the upper electrode and the ferroelectric of the ferroelectric capacitor,
Removing the resist mask after forming the ferroelectric;
Etching the lower electrode film by using the hard mask as a mask to form a lower electrode of the ferroelectric capacitor, and a method for manufacturing the ferroelectric capacitor.   After forming the insulating film on the substrate, an adhesion layer for improving adhesion between the insulating film and the lower electrode film is formed on the insulating film, and then the lower electrode film and the lower electrode film are formed on the adhesion layer. 3. The method of manufacturing a ferroelectric capacitor according to claim 1, wherein the ferroelectric film and the upper electrode film are sequentially formed.   4. The method for manufacturing a ferroelectric capacitor according to claim 1, wherein the barrier film is made of titanium aluminum nitride (TiAlN). 5. The lower electrode film is removed by etching using the hard mask as a mask, and when forming the lower electrode of the ferroelectric capacitor, chlorine (Cl ₂ ), oxygen (O ₂ ), argon (Ar), 5. The method of manufacturing a ferroelectric capacitor according to claim 4, wherein a mixed gas comprising: is used as an etching gas. 6. The method of manufacturing a ferroelectric capacitor according to claim 4, further comprising a step of etching and removing the hard mask using chlorine (Cl ₂ ) gas after forming the lower electrode. Method.

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