JPH11354505A - Manufacture of dielectric thin film element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a dielectric thin film element whose fine working precision is improved. SOLUTION: A method for manufacturing a dielectric thin film element includes a process for forming a multi-layer thin film 20 including a lower electrode layer 24 on a substrate 10, a process for forming the pattern of a first nitride layer 40 including a metallic element to be oxidized on the multilayer thin film 20, a process for patterning the lower electrode layer 20 into a desired shape by selectively etching the multilayer thin film 20 by using mixed gas including oxidized gas by using the pattern of the first nitride layer 40 as a mask, and a process for removing the pattern of the first nitride layer 40.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a dielectric thin film element used for a semiconductor device such as a semiconductor integrated circuit, and more particularly to a method of etching a high melting point metal film and a dielectric thin film contained in a dielectric thin film element. About.

[0002]

2. Description of the Related Art In recent years, ferroelectric nonvolatile memory devices using a ferroelectric film having spontaneous polarization for a capacitor have been actively developed. Also, devices such as DRAMs using a high dielectric constant film as a memory capacitor have been developed. An oxide crystal is mainly used as a dielectric material such as a ferroelectric thin film or a high dielectric thin film used for these devices. Since a high-temperature oxygen atmosphere is required to form such a crystal film, a high-melting point metal (Pt and Ir) that is resistant to the high-temperature oxygen atmosphere is used as a material for the electrodes used in the electronic device. Etc.) or an oxide material having conductivity. Further, in order to manufacture a device using such a material as a high melting point metal, an etching step for fine processing is indispensable.

Conventionally, as fine processing of a refractory metal film, for example, in Pt etching, ion milling with Ar or reactive etching using chlorine gas or the like has been performed. As a mask for etching, a resist film, a silicon oxide film, an Au film, or the like has been used.

[0004] Also, Extended Abstracts of the 1994 I
nternational Conference on SSDM, Yokohama, 1994, pp
According to 721-723, in the etching of Pt, SOG
Using a (Spin on Glass) mask, etching is performed with a mixed gas of chlorine and oxygen. According to the 58th Annual Meeting of the Japan Society of Applied Physics, 2p-PA-19, a 1 μm-thick CVDSiO ₂ film is used as a mask for etching Ir and IrO ₂ . In Japanese Patent Application No. 9-266200, Pt is etched with a mixed gas of chlorine and oxygen using a Ti film as a mask.

[0005]

When a ferroelectric or high dielectric material is used for a dielectric thin film element such as a capacitor,
In many cases, the electrodes of the element are formed of a high melting point metal or a high melting point metal compound. For this reason, there is a problem that etching is difficult, or even if etching is possible, the etch rate is slow. With the conventional mask as described above, it is difficult to perform high-precision fine processing of an element including formation of an electrode. This will be described in more detail below.

[0006] When etching is performed using a resist mask as in the conventional case, the resist film thickness (about 2 times or more) of the normal thickness is used.
500 nm). For this reason, fine processing was difficult. Further, even when a silicon oxide film mask such as an SOG mask is used, a thick mask is required because the selectivity with respect to a dielectric, a high melting point metal or a high melting point metal compound is poor. Further, deposits are generated on the side walls of the thick mask due to a reaction between the mask material or the material to be etched and the etching gas. This causes a reduction in processing accuracy, and also requires extra processing of removing extraneous matter.

In the case of a silicon oxide mask such as an SOG mask, the mask cannot be completely removed even after the mask removing step, so that a residue is left. If the etching selectivity between the base and the mask after etching is insufficient, it is difficult to remove only the mask. Even in the case of a metal mask made of Ti or the like, as in the case of the SOG mask, it is difficult to remove the mask using the difference in the etching rates between the base material after etching and the material of the mask. is there. For this reason, it is necessary to narrow down the etching conditions strictly.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a dielectric thin film including a layer made of a high melting point metal or a high melting point metal compound having high accuracy and simple steps. An object of the present invention is to provide a device manufacturing method and a dielectric thin film device manufactured by the method.

[0009]

According to the present invention, there is provided a method of manufacturing a dielectric thin film device, comprising the steps of: forming a multilayer thin film including a lower electrode layer on a substrate; and forming an oxidizable film on the multilayer thin film. Forming a pattern of a first nitride layer containing a metal element, and selectively using the mixed gas containing an oxidizing gas with the pattern of the first nitride layer as a mask. The method includes a step of patterning the lower electrode layer into a desired shape by etching, and a step of removing the pattern of the first nitride layer, whereby the object is achieved.

In one embodiment, the first nitride layer contains, as a composition thereof, an element selected from the group including Ta, Hf, and Si.

[0011] In one embodiment, the thickness of the first nitride layer is in a range of about 20-500 nm.

In one embodiment, the first nitride layer is
The step of forming a pattern includes a first step including a halogen group element.
Gas, the second gas containing a halogen group element, or the second gas
Etching a mixed gas of the first gas and the second gas with an etching gas
And the first gas is HCl, BCl_Three, C
l_Two, CCl_Four, CH_xCl_4-X, COCl_Two, S_TwoCl_Two,
PCl_Three, CCl_xBr_4-x, NOCl and SiCl_FourIncluding
And the second gas is CF 2_Four, C_TwoF_Four,
CHF_Three, C_TwoF₆, C_ThreeF₈, C_FourF_Ten, SF₆, S_TwoF_Two,
CHFCl_2,BrF_Three, BrF_Five,HBr, HF, BF_Three,
COF_Two, NF_Three, SiF_Four, XeF_Two, CF_xCl_4-x, C
HFCl_Two, ClF_Three, BBr_Three, CBr_Four, CF _xB
r_4-X, CHFBr_TwoAnd S_TwoBr_TwoSelected from the group containing
(Where x is an integer of 4 or less), the second gas in the mixed gas.
The ratio of the metal is about 20% or more and 50% or less.

[0013] In one embodiment, the oxidizing gas is N
_It contains at least one gas selected from the group comprising ₂ O gas, O ₃ gas and O ₂ gas.

[0014] In one embodiment, a ratio of the oxidizing gas in the mixed gas is about 20% or more and 70% or less.

[0015] In one embodiment, a ratio of the oxidizing gas in the mixed gas is about 20% or more and 50% or less.

In one embodiment, the mixed gas further contains a halogen gas or a compound gas containing a halogen group element.

In one embodiment, the halogen gas or the compound gas containing a halogen group element is HC1, BC
_{1 3, Cl 2, CC1 4} , CH x Cl 4-x, COC1 2, S 2
Cl ₂ , PCl ₃ , CCl _x Br ₄ , NOCl, SiCl _4,
CF ₄ , C ₂ F ₄ , CHF ₃ , C ₂ F ₆ , C ₃ F ₈ , C ₄ F ₁₀ ,
SF ₆ , S ₂ F ₂ , CHFCl ₂ , BrF ₃ , BrF ₅ , HB
r, HF, BF ₃ , COF ₂ , NF ₃ , SiF ₄ , Xe
_{F 2, CF x Cl 4-} x, CHFCl 2, ClF 3, BBr 3,
It is selected from a group including CBr ₄ , CF _x Br _4-x , CHFBr ₂ and S ₂ Br ₂ (where x is an integer of 4 or less).

In one embodiment, the multilayer thin film further includes a dielectric layer formed on the lower electrode layer, and a diffusion barrier layer formed between the substrate and the lower electrode layer. Wherein the diffusion barrier layer prevents interdiffusion of elements between the substrate and the dielectric layer, and the step of removing the pattern of the first nitride layer selectively removes the diffusion barrier layer. Patterning into the desired shape by removing.

In one embodiment, the first nitride layer has the same composition as the diffusion barrier layer.

In one embodiment, the first nitride layer has a thickness greater than the diffusion barrier layer.

In one embodiment, a step of forming an upper electrode layer on the dielectric layer, and a step of forming a second nitride layer containing a metal element, which is oxidizable, on the upper electrode layer And a step of patterning the upper electrode into a desired shape by selectively etching the upper electrode using a mixed gas containing an oxidizing gas using the pattern of the second nitride layer as a mask. Are further included.

In one embodiment, the lower electrode layer is formed of I
It is formed of a metal element selected from the group including r, Pt, Ru, Rh, Os, and Re.

In one embodiment, the upper electrode layer is formed of I
It is formed of a metal element selected from the group including r, Pt, Ru, Rh, Os, and Re.

In one embodiment, a buffer layer is formed on a surface of the substrate.

In one embodiment, the buffer layer is formed of T
It is formed of an element selected from the group including i, Ta, Co, Ni, Hf, Mo and W, or a compound containing at least one of them.

In one embodiment, the multilayer thin film includes an interlayer insulating film formed between the dielectric layer and the first nitride layer, and includes a pattern of the first nitride layer. The step of forming includes patterning the interlayer insulating film.

Another method for manufacturing a dielectric thin film element according to the present invention includes a step of forming a diffusion barrier layer on a substrate, a step of forming a multilayer thin film including a lower electrode layer on the diffusion barrier layer, Forming a pattern of an oxidizable first nitride layer containing at least one element constituting the diffusion barrier layer on the multilayer thin film; and forming the first nitride layer. Patterning the lower electrode layer into a desired shape by selectively etching the multilayer thin film using a mixed gas containing an oxidizing gas with the pattern of (a) as a mask; And a step of removing the pattern described above, whereby the object is achieved.

In one embodiment, the diffusion barrier layer comprises:
It is formed of TaSiN, HfSiN, TiN or TiAlN.

In one embodiment, the ratio of the oxidizing gas in the mixed gas is about 20% or more and 70% or less.

The ferroelectric thin film device according to the present invention includes a dielectric thin film device manufactured by the above manufacturing method. Further, a high dielectric thin film device according to the present invention includes a dielectric thin film device manufactured by the above manufacturing method. Further, a semiconductor device according to the present invention has a dielectric thin film element provided in a circuit portion of an integrated circuit on an integrated circuit wafer and manufactured by the above manufacturing method.

[0031]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The most basic features of the present invention will be described below with reference to FIG.

FIG. 1 shows a cross section of a main part of a basic structure of a dielectric thin film element. This dielectric thin film element is
And a buffer layer (adhesion layer) formed on the surface of the substrate 10
12, a diffusion barrier layer 22 on the buffer layer 12, a lower electrode layer 24, a dielectric layer 25, and an upper electrode layer 28. The buffer layer 12 is for preventing the diffusion barrier layer 22 from being oxidized and improving the adhesion to the substrate 10. The diffusion barrier layer 22 includes the substrate 10 and the dielectric layer 25.
The purpose is to prevent mutual diffusion of elements between these elements.

In the present invention, as a mask used in an etching step for finely processing an electrode layer or the like, a nitride layer containing a metal element (a first nitride layer and a second nitride Layer). Using such a mask, only the electrode layer or the dielectric layer and the electrode layer are continuously etched. Such a nitride layer mask is oxidized by a mixed gas containing an oxidizing gas during the etching step, so that the etching resistance is significantly increased. Therefore, the oxidized mask is not etched. By using such a mask having high etching resistance, the thickness can be reduced to 20 to 50.
Since the thickness can be reduced to about 0 nm, the above-described problems associated with the conventional thick mask can be avoided. Hereinafter, the above-mentioned nitride layer is also referred to as an “etching-resistant film”.

With respect to the preferable thickness of the above-mentioned etching resistant film, the lower limit of 20 nm is a thickness that can exist as a film. When the thickness of the film is 20 nm or less, the effect of the present invention cannot be obtained because stripe-like grains grow in the film, and even if the film becomes a film, the effect is caused by pinholes and the like. On the other hand, the upper limit of 500 nm is
The thickness is such that peeling due to stress does not occur during film formation. If the thickness of the film is 500 nm or more, peeling or cracking may occur due to the stress of the film when the film is formed. Due to this, the above effects of the present invention may not be obtained. Further, in consideration of the ease of film formation, the thickness of the etching resistant film is set to about 20 to 250.
nm is more preferable.

The etching resistant film is, for example, TaSiN, H
It may be formed of a nitride such as fSiN, TiN or TiAlN. These compounds are easily oxidized by the oxidizing gas. In the specification of the present application, the fact that the etching-resistant film is “easy to be oxidized” means, for example, that it is easily oxidized than a noble metal such as Pt, Au, or Ir, and is also easily oxidized as compared with Si. Means that. Elements such as Si are hardly oxidized at room temperature and oxidized in high-temperature oxygen (for example, at a temperature of about 600 ° C. or higher), but their progress is slow, and the same applies in an oxygen plasma atmosphere. However, the etching resistant film of the present invention is easily oxidized under these conditions.

When the etching resistant film is formed of, for example, TaSiN, Ta is converted to Ta ₂ O ₅ by oxidation.
And a strong film of Ta ₂ O ₅ is formed on the surface of the TaSiN layer. With this coating, TaSiN becomes
Etching is stopped by the chemical action of the halogen gas. Ta ₂ O _{5 due to} sputtering during the process
Even if there is no more, new Ta is immediately oxidized to Ta ₂ O ₅ to prevent TaSiN from being etched.

The mixed gas used for etching contains an oxidizing gas and a halogen gas. As the oxidizing gas, O _2, O ₃ or N ₂ O or the like is used, the chlorine gas or the like is used as the halogen gas.

Further, by forming the diffusion barrier layer 22 and the etching resistant film 40 with the same compound, the electrode layer,
Alternatively, after the etching of the dielectric layer and the electrode layer is completed, the removal of the etching resistant film 40 can be performed simultaneously with the etching of the diffusion barrier layer 22. If the diffusion barrier group and the etching-resistant group are not formed of the same compound, after the etching of the electrode layer or the dielectric layer and the electrode layer is completed, a gas capable of obtaining a difference between the base and the etching rate is used. The etching film 40 is removed.

The ferroelectric element of the present invention includes a ferroelectric capacitor, and further includes an element mounted on a wafer for an integrated circuit as a part of a semiconductor device.
Further, the forming method of the present invention includes the steps of:
Alternatively, the present invention can be applied to the manufacture of a dielectric thin film element included in a gate portion of an FET (field effect transistor), and includes an MFMIS-FET (Metal Ferr
oelectric Metal Insulator Semiconductor FET)), M
FS-FET (Metal Ferroelectric Semiconductor FE
It can also be used as a method for forming a thin film element such as T).

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(First Embodiment) FIGS. 2A to 2E
1 shows a first embodiment of a method for manufacturing a dielectric thin film element according to the present invention. In the present embodiment, an etching method for patterning the lower electrode layer 24 will be described.

First, as shown in FIG. 2A, a silicon oxide film 11 having a thickness of about 600 nm is formed on the surface of the silicon substrate 10 by using the CVD method. Next, a diffusion barrier layer 22 is formed by forming an amorphous tantalum silicon nitride (TaSiN) layer having a thickness of about 100 nm by a DC magnetron reactive sputtering method.
Thereafter, a heat treatment is performed in a nitrogen atmosphere to stabilize the tantalum silicon nitride film. This heat treatment may not be particularly necessary depending on the film forming conditions. The conditions for forming the tantalum silicon nitride film are as follows. The element molar ratio of the alloy target is about Ta: Si = 10: 3, and the substrate temperature is about 5
The sputtering power is about 2000 W, the sputtering gas pressure is about 0.7 Pa, and the Ar / N ₂ flow rate ratio is about 3/2. Regarding the heat treatment conditions, the rate of temperature rise in a pure nitrogen atmosphere is about 5 ° C./min, the holding temperature is about 600 ° C., and the holding time is about 1 hour.

The tantalum silicon formed under the above conditions
Con nitride film is Ta_0.85Si_0.15N _0.41Has the composition
And has an amorphous structure. These things are
Confirmed by Auger spectroscopy and X-ray diffraction analysis respectively
You.

Next, on the diffusion barrier layer 22 made of a tantalum silicon nitride film, a DC magnetron sputtering method is used.
An iridium (Ir) layer (thickness: about 150 nm) is formed as the lower electrode layer 24. The formation conditions are DC power of 0.
5 kW, substrate temperature 500 ° C., gas pressure 0.6 Pa.
Only Ar gas is used as a sputtering gas. Thereafter, a tantalum silicon nitride layer having the same composition as the diffusion barrier layer 22 (thickness: about 120 n
m) is formed in the same manner as in the case of the diffusion barrier layer 22. Further, a resist pattern 50 having a thickness of 1 μm is formed on the etching resistant film 40, and is patterned into a square of about 800 to 2500 nm by a usual photolithography technique.

As described above, the configuration shown in FIG. 2A is obtained. The layer structure including the diffusion barrier layer 22 and the lower electrode layer 24 is called a “multilayer thin film”.

An etching method for patterning the etching resistant film 40 and the lower electrode layer 24 will be described below. The etching is performed using an ECR (Electron Cyclotron Resonance) plasma etching apparatus as shown in FIG. This device includes a solenoid coil 80, a wafer 8
1, electrode 82, O ₂ gas inlet 83, halogen gas inlet 84, 2.45 GHz microwave 88 and 13.56
MHz high frequency 89. The basic conditions for the etching are a pressure of about 1.4 mTorr and a microwave output of about 1000 W.

First, as shown in FIG.
The etching resistant film 40 of N
Using a mask as a mask, chlorine gas about 50 SCCM, RFPow
is patterned into a desired shape by etching at about 100W. The etching gas at this time is not limited to chlorine gas, and when a silicon-based residue remains, a fluorine-based halogen gas or a mixed gas thereof may be used.

Thereafter, as shown in FIG. 2C, the resist pattern 50 is removed. Ashing using ozone or a stripping agent can be used for removing the resist pattern 50.

Thereafter, as shown in FIG. 2D, using the etching resistant film 40 as a mask, the lower electrode layer 24, which is an Ir film, is patterned into a desired shape by etching. As the etching gas at this time, chlorine gas (Cl ₂ ) was used as a halogen gas, oxygen (O ₂ ) was used as an oxidizing gas, and the gas flow rate was Cl ₂ / O ₂ = 64/16.
It is set to about SCCM. RFPower is about 10
It is set to 0W. The relationship between the flow ratio of the etching gas and the etch rates of the Ir film (the lower electrode layer 24) and the TaSiN layer (the etching resistant film 40 and the diffusion barrier layer 22) is shown in FIG. 4 (the square marks indicate the Ir film 24). data from,
Circles indicate data of the TaSiN layer 40). As shown in FIG. 4, when the oxygen flow rate is about 20% or more of the total flow rate, TaS
The etching rate of the etching of the iN layer is reduced to about 8 nm / min, and the progress of the etching of the TaSiN layer is substantially stopped. The progress of the etching is stopped because the TaSiN film is oxidized by the oxygen gas, and as a result, the etching resistance is improved. The TaSiN film thus oxidized (the etching resistant film 40 ′ and the diffusion barrier layer 22 ′) is constituted by a TaSiN layer protected by a thin Ta ₂ O ₅ film.

From the results shown in FIG. 4, as the etching gas,
It is necessary to perform the etching at an oxygen flow rate of about 20% or more. Further, when the oxygen flow rate is about 80% or more of the total flow rate, the etch rate of the Ir film is reduced. Therefore, the oxygen flow rate is preferably about 70% or less of the total flow rate.

Next, the etching for removing the etching resistant film 40 'and the etching for patterning the diffusion barrier layer 22' are simultaneously performed. The etching conditions at this time are as follows: in this embodiment, chlorine is about 50 SCCM and RF Power is about 100 W.
It is. Note that the etching gas is not limited to chlorine, and a fluorine-based halogen gas or a mixed gas thereof may be used. Etching resistant film 40 'and diffusion barrier layer 2
Since 2 ′ has the same composition, the etching resistant film 40 ′
Removal and selective etching of the diffusion barrier layer 22 'proceed simultaneously. For this reason, there is no need to set the etching conditions in consideration of the difference in the etch rates of these layers, and the etching is simplified.

In this embodiment, Ir is used as the metal constituting the electrode layer, but Pt, Rh, Os, Rc or Ru is used.
May be used. Each of these metals,
Used as a material for electrodes in high dielectric and ferroelectric devices.

In the above description, the lower electrode layer 24 is etched.
Cling gas is Cl_TwoChlorine gas and O_TwoTo
However, the present invention is not limited to this.
Not. HCl, BCl as chlorine-based gas_Three, Cl_Two, C
Cl_Four, CH_xCl_4-x, COCl_Two, S_TwoCl_Two, PC
l_Three, CCl_xBr_4-x, NOCl, SiCl_FourEtc., haloge
CF_Four,C_TwoF_Four, CHF_Three, C_TwoF₆, C_ThreeF
₈, C_FourF_Ten,SF₆, S _TwoF_Two, CHFCl_Two, BrF_Three, B
rF_Five, HBr, HF, BF_Three, COF_2,NF_Three, Si
F_Four, XeF_Two, CF_xCl_4-x, CHFCl_Two, ClF_Three,
BBr_Three, CBr_Four, CF_xBr_4-x, CHFBr_Two, S_TwoB
r_Two(Where x is an integer of 4 or less)_Two
And O_ThreeAnd N_TwoUsing a gas such as O or a mixed gas thereof
Dry etching may be performed.

[0054] Further, as the etching resistant film 40 and the diffusion barrier layer 22 in this embodiment uses the Ta _{0. 85} Si _0.15 N _0.41 layer, which is different from the composition ratio of TaSiN or HrSiN, TiN, oxides such as TiA1N, A film that is easy to use may be used. It is not necessary to limit the composition of these compounds in consideration of the effect of etching, and any composition can be etched by the etching method of the present invention. However, in consideration of electrical characteristics or heat resistance, for example, in the case of a Ta _x Si _1-x N _y film as the diffusion barrier layer 22, 0.75 <x <0.95 and 0.3 <y <0.5 It is more preferable if it is within the range.

When removing the mask (etching resistant film 40) made of TaSiN, HfSiN, TiN or TiAlN and etching the diffusion barrier layer,
HCl, BCl ₃ , Cl ₂ , CCl ₄ , CH _x Cl _4-x , C
OCl ₂ , S ₂ Cl ₂ , PCl ₃ , CCl _x Br _4-x , NOC
1, SiCl ₄ , CF ₄ , C ₂ F ₄ , CHF ₃ , C ₂ F ₆ , C ₃
F ₈ , C ₄ F ₁₀ , SF _6, S ₂ F ₂ , CHFCl ₂ , BrF ₃ ,
BrF ₅ , HBr, HF, BF ₃ , COF ₂ , NF ₃ , Si
F ₄ , XeF ₂ , CF _x Cl _4-x , CHFCl ₂ , ClF ₃ ,
_{BBr 3, CBr 4, CF x} Br 4-x, CHFBr 2, and S ₂ Br ₂ (where x is an integer of 4 or less) complete the etching by using one or more gases selected from the group comprising can do. Further, when these oxidizable nitrogen compounds are used as a mask, O ₂ , O ₃ , N ₂
An oxidizing gas such as O is added to a halogen gas or a halogenated gas to perform etching.
% Or more may be added.

The substrate 10 is not particularly limited to a silicon substrate as long as it can be used as a substrate for a semiconductor device, an integrated circuit, or the like.
compound semiconductor substrate such as s, oxide crystal substrate such as MgO,
It can be selected depending on the type of the element to be formed, such as a glass substrate, the use, and the like. Of the above substrates, a silicon substrate is most preferred.

Further, a material containing at least one element selected from the group consisting of Ti, Ta, Co, Ni, Hf, Mo and W is provided between the silicon oxide film 11 and the diffusion barrier layer 22. A buffer layer (adhesion layer) may be formed.

The above buffer layer and diffusion barrier layer 2
2, and a structure including the lower electrode layer 24 is referred to as a lower electrode structure. In the present specification, the lower electrode structure means a part of the dielectric element, that is, a capacitor electrode. The lower electrode structure may be formed directly on the substrate by a known method such as a sputtering method or a vapor deposition method, or may include an insulating film, a lower wiring, a desired element, an interlayer insulating film, or a plurality thereof. It may be formed on a substrate.

The electrode processed by etching as described above has a very thin mask as compared with a conventional resist or a silicon oxide film mask, so that there is no residue attached to the side wall. Loading is also greatly reduced.

The patterning accuracy of the electrode depends on the accuracy of the TaSiN mask, and the accuracy of the TaSiN mask depends on the accuracy of the resist pattern for forming the mask. Since the resist pattern is for forming only the TaSiN mask, the thickness of the resist itself can be reduced. For this reason, miniaturization can be easily performed as compared with the case where a conventional thick resist is used to improve the depth of focus and the resolution.

Further, the etching resistant film 40 as a mask
And the composition of the underlying diffusion barrier layer 22 are the same,
The removal of the mask and the etching of the diffusion barrier layer can be performed simultaneously. This means that conventional SOG, CVD SiO
_2. Unlike the case of using a Ti mask, the mask can be easily removed because there is no need to consider the selection ratio between the mask and the base. From these facts, it is possible to perform highly accurate etching for forming a fine capacitor by the method of the present invention.

Second Embodiment In the first embodiment, the multilayer thin film 20 to be etched includes only the lower electrode layer 24, but in the second embodiment, the multilayer thin film including the dielectric layer is etched. Will be described.

First, as shown in FIG. 5A, a silicon oxide film 11 having a thickness of about 600 nm is formed on the surface of a silicon substrate 10 by using a CVD method. Next, a diffusion barrier layer 22 is formed by forming an amorphous tantalum silicon nitride (TaSiN) layer having a thickness of about 100 nm by a DC magnetron reactive sputtering method.
Thereafter, a heat treatment is performed in a nitrogen atmosphere to stabilize the tantalum silicon nitride film. Next, an iridium (Ir) layer is formed as the lower electrode layer 24 on the diffusion barrier layer 22 by DC magnetron sputtering. Diffusion barrier layer 2
2 and the lower electrode layer 24 are formed under the following conditions:
This is the same as in the first embodiment.

Next, the dielectric layer 25 is formed on the lower electrode layer 24 by using ferroelectric SrBi ₂ Ta ₂ O ₉ (SBT).
To form As a forming method, the following spin-on method is used. First, a precursor solution in which constituent elements are dispersed in a solvent is prepared, and the precursor solution is applied to a substrate at a rotation speed of 3000 rpm using a spinner. 1 in the atmosphere
After drying at 50 ° C. for 10 minutes, calcination is performed in air at 400 ° C. for 30 minutes. Thereafter, crystallization was performed at 700 ° C. for 1 hour. These steps are repeated three times to form an SBT thin film of about 200 nm as the dielectric layer 25.

Next, on the dielectric layer 25 (SBT thin film),
50 interlayer insulating films (NSG) 27 made of silicon oxide
It is formed on the order of nm. CVD is used to form the interlayer insulating film 27.
Method. The interlayer insulating film 27 is provided to prevent the surface of the SBT from being directly exposed to the plasma during the removal of the mask, thereby preventing the SBT surface from being damaged and deteriorating the characteristics. In addition,
This layer may not be necessary if a property recovery process is performed after the etching. When the upper electrode is formed first, after forming the dielectric layer 25, the upper electrode may be formed thereon, and then the interlayer insulating film 27 may be formed.

Thereafter, in the same manner as in the first embodiment,
An etching resistant film 40 (tantalum silicon nitride layer) having the same composition as the diffusion barrier layer 22 is formed on the interlayer insulating film 27. Further, a film thickness of 1 μm
Is formed. As described above, the configuration shown in FIG. 5A is obtained. The multilayer thin film 20
It includes a diffusion barrier layer 22, a lower electrode layer 24, a dielectric layer 25, and an interlayer insulating film 27.

After that, similarly to the first embodiment, the etching-resistant film 40 is patterned. At this time, FIG.
As shown in (b), the interlayer insulating film 27 is etched into the same shape as the etching resistant film 40. At this time, the etching of the interlayer insulating film 27 uses Cl ₂ gas and C ₂ F ₆ gas. Here, if the etching rate of the interlayer insulating film 27 is higher than that of the TaSiN layer 40, it may cause film roughness.
As shown in FIG. 6, when the flow rate ratio of C ₂ F ₆ is about 50% or less of the total flow rate, the etching rate of the TaSiN layer 40 becomes faster than that of the silicon oxide film (interlayer insulating film 27). However, when the flow rate ratio of C ₂ F ₆ is smaller than 30%, there is a residue, so the flow rate ratio of C ₂ F ₆ is preferably about 30% or more and 50% or less.

Next, a TaSiN film (etching resistant film) 4
0 mask, the SBT thin film 2 as the dielectric layer 25 is used.
5, and the Ir film 24 serving as the lower electrode layer 24 is etched.

As shown in FIG. 4, the etching rate of the SBT thin film 25 (triangular mark) is such that the oxygen addition amount is 50% of the total flow rate.
To the extent it falls slowly, above which it drops sharply. Therefore, at the time of etching, it is desirable that the flow rate of oxygen with respect to the total flow rate is about 20% to 50%. In this embodiment, the SBT thin film 25 and the Ir thin film 24
Are both about Cl ₂ / O ₂ = 61/16 SCCM, RF =
Etching is performed under the condition of about 100 W to etch into the shape shown in FIG. In this etching step, the TaSiN film is oxidized by oxygen gas, and as a result, the etching resistance is improved. The TaSiN film thus oxidized (the etching resistant film 40 ′ and the diffusion barrier layer 22 ′) is constituted by a TaSiN layer protected by a thin Ta ₂ O ₅ film.

Next, as shown in FIG. 5D, the etching resistant film 40 'and the underlying diffusion barrier layer 22' are simultaneously etched. The etching conditions at this time are, as in the first embodiment, about Cl ₂ / O ₂ = 61/16 SCCM.
RF was performed at about 100 W. The etching gas at this time is not limited to chlorine, and a fluorine-based halogen gas or a mixed gas thereof may be used.

Hereinafter, the dielectric layer 25 will be described in more detail. As the dielectric layer 25, a Bi-based ferroelectric (S
A ferroelectric thin film such as rBi _2, Ta ₂ O ₉ , Bi ₄ Ti ₃ O ₁₂ ), an oxide ferroelectric PZT (lead zirconate titanate), or the like can be used.

[0072] When the Bi-based ferroelectric, strong ferroelectric thin film is not particularly limited as long as it is a dielectric having a layered perovskite _{structure, Bi 2 A m-1 B} m O 3m + 3 (A Is Na, K, Pb, Ca, S
r, Ba or Bi; B is preferably a ferroelectric material represented by Fe, Ti, Nb, Ta, W or Mo), and more preferably a compound in which m is a natural number. Specifically, Bi ₄ Ti ₃ O _12,
SrBi ₂ Ta ₂ O ₉ , SrBi ₂ Nb ₂ O ₉ , BaBi ₂ N
b ₂ O ₉ , BaBi ₂ Ta ₂ O ₉ , PbBi ₂ Nb ₂ O ₉ , Pb
Bi ₂ Ta ₂ O ₉ , PbBi ₄ Ti ₄ O _15, SrBi ₄ Ti ₄ O
_15, Sr ₂ Bi ₄ Ti ₄ O ₁₅ , Pb ₂ Bi ₄ Ti ₄ O ₁₅ , Sr ₂
Bi ₄ Ti ₄ O ₁₈ , Ba ₂ Bi ₄ Ti ₅ O ₁₈ , Pb ₂ Bi ₄ T
_{i 5 O 18, Na 0.5 Bi} 4.5 Ti 4 O 15, K 0.5 Bi 4.5 Ti 4
O ₁₅ , Sr ₂ Bi ₄ Ti ₅ O ₁₈ , Ba ₂ Bi ₄ Ti ₅ O ₁₈ , P
b ₂ Bi ₄ Ti ₅ O _{18 and the} like, among which SrBi ₂ Ta
₂ O ₉ is preferred.

The above ferroelectric thin film can be formed by a known method, for example, a spin-on method, a reactive evaporation method, an EB evaporation method, a sputtering method, a laser ablation method or the like. For example, in the spin-on method, generally, a raw material containing a part or all of the elements constituting the thin film is dispersed in an organic solvent, and the resultant is applied to an electrode layer by a spinner and dried. Thereafter, the carbon component present in the film is removed by sintering (temporary sintering),
Thereafter, firing is performed in a gas containing oxygen or an oxygen compound for crystallization to form a ferroelectric thin film.

In this embodiment, Ir is used as the metal constituting the electrode layer, but Pt, Rh, Os, Rc or Ru is used.
May be used. Each of these metals,
Used as a material for electrodes in high dielectric and ferroelectric devices.

In the above description, a chlorine gas of Cl ₂ and an oxidizing gas of O ₂ are used as a gas for etching the lower electrode layer 24 and the dielectric layer 25, but the present invention is not limited to this. HCl as a chlorine-based gas,
BCl ₃ , Cl ₂ , CCl ₄ , CH _x Cl _4-x , COCl ₂ ,
S ₂ Cl ₂ , PCl ₃ , CCl _x Br _4-x , NOCl, Si
CF _4, C ₂ F ₄ , CH as halogenated gas such as Cl _{4
F 3, C 2 F 6,} C 3 F 8, C 4 F 10, SF 6, S 2 F 2, CHF
Cl ₂ , BrF ₃ , BrF ₅ , HBr, HF, BF ₃ , CO
F _2, NF ₃ , SiF ₄ , XeF ₂ , CF _x Cl _4-x , CHF
_{Cl 2, ClF 3, BBr 3} , CBr 4, CF x Br 4-x, C
Dry etching may be performed using HFBr ₂ , S ₂ Br ₂ or the like (where x is an integer of 4 or less), a gas such as O ₂ , O ₃ or N ₂ O as an oxidizing gas, or a mixed gas thereof. .

As the etching resistant film 40 and the diffusion barrier layer 22, in addition to TaSiN, HrSiN, Ti
A film that is easily oxidized such as N or TiA1N may be used.
It is not necessary to limit the composition of these compounds in consideration of the effect of etching, and any composition can be etched by the etching method of the present invention. However, in consideration of the electrical characteristics or heat resistance, the diffusion barrier layer 22 is, for example, 0.7% in the case of a Ta _x Si _1-x N _y film.
It is more preferable that 5 <x <0.95 and 0.3 <y <0.5.

When removing the mask (etching-resistant film 40) made of TaSiN, HfSiN, TiN or TiAlN and etching the diffusion barrier layer,
HCl, BCl ₃ , Cl ₂ , CCl ₄ , CH _x Cl _4-x , C
OCl ₂ , S ₂ Cl ₂ , PCl ₃ , CCl _x Br _4-x , NOC
1, SiCl ₄ , CF ₄ , C ₂ F ₄ , CHF ₃ , C ₂ F ₆ , C ₃
F ₈ , C ₄ F ₁₀ , SF _6, S ₂ F ₂ , CHFCl ₂ , BrF ₃ ,
BrF ₅ , HBr, HF, BF ₃ , COF ₂ , NF ₃ , Si
F ₄ , XeF ₂ , CF _x Cl _4-x , CHFCl ₂ , ClF ₃ ,
_{BBr 3, CBr 4, CF x} Br 4-x, CHFBr 2, and S ₂ Br ₂ (where x is an integer of 4 or less) complete the etching by using one or more gases selected from the group comprising can do. Further, when these oxidizable nitrogen compounds are used as a mask, O ₂ , O ₃ , N ₂
An oxidizing gas such as O is added to a halogen gas or a halogenated gas to perform etching.
What is necessary is just to add 0% or more.

Further, a material containing at least one element selected from the group consisting of Ti, Ta, Co, Ni, Hf, Mo, and W is provided between the silicon oxide film 11 and the diffusion barrier layer 22. The buffer layer (adhesion layer) may be formed as in the case of the first embodiment.

As described above, according to the present invention, high-precision etching for forming a fine capacitor can be performed.

(Third Embodiment) Hereinafter, FIGS.
A third embodiment of the method for manufacturing a dielectric thin film element of the present invention will be described with reference to FIG. In the above-described second embodiment, the upper surface of the dielectric layer 25 is covered with the interlayer insulating film 27 (FIG. 5D). In the present embodiment, the dielectric layer has a configuration in which not only the upper surface but also the side surfaces are covered with the interlayer insulating film.

First, as shown in FIG. 7A, a silicon oxide film 11 having a thickness of about 600 nm is formed on the surface of the silicon substrate 10 by using the CVD method. Next, a diffusion barrier layer 22 is formed by forming an amorphous tantalum silicon nitride (TaSiN) layer having a thickness of about 100 nm by a DC magnetron reactive sputtering method.
Thereafter, a heat treatment is performed in a nitrogen atmosphere to stabilize the tantalum silicon nitride film. Next, an iridium (Ir) layer is formed as the lower electrode layer 24 on the diffusion barrier layer 22 by DC magnetron sputtering. Diffusion barrier layer 2
2 and the lower electrode layer 24 are formed under the following conditions:
This is the same as in the first embodiment.

Next, a dielectric layer 32 is formed on the lower electrode layer 24 using ferroelectric SrBi ₂ Ta ₂ O ₉ (SBT).
5 (thickness: about 200 nm) is formed. The formation method is
As in the second embodiment, a spin-on method is used. Thereafter, the dielectric layer 325 is processed into a desired capacitor size by dry etching using a resist or the TaSiN layer 40 described above (FIG. 7A). Next, R
TA (Rapid Thermal Annealin)
By using the g) method, damage due to etching of the dielectric layer 325 is recovered by a heat treatment at about 700 ° C. and about 30 seconds.

Thereafter, an interlayer insulating film 327 is formed, and the interlayer insulating film 327 is reflowed or CMP (Chemical Mech.
The surface is flattened by anical polishing. The flattening of the surface is for improving the processing accuracy of the TaSiN mask formed on the upper portion. If sufficient processing accuracy can be obtained, it is not necessary to perform the flattening step.

Next, a TaSiN layer (etching-resistant film) 40 serving as an etching mask is formed on the interlayer insulating film 327.
The diffusion barrier layer 22 is formed under the same conditions. Further Embodiment 1
Similarly to FIGS. 2 and 3, a resist pattern 50 is formed on the etching resistant film 40, and the TaSiN layer 40 and the interlayer insulating film 327 are etched (FIG. 2B). The etching of the etching resistant film 40 and the interlayer insulating film 327 is performed by using a gas system of about Cl ₂ / O ₂ = 61/16 SCCM and RF = 1.
It is performed at about 00W. By making the flow rates of the chlorine-based gas and the fluorine-based gas equal, the anti-etching film 40 and the interlayer insulating film 3 are formed.
27 have almost the same etch rate.

Next, as shown in FIG. 7C, the lower electrode layer 24 is formed using the TaSiN layer 40 formed as described above.
Is performed in the same manner as in the first and second embodiments. In this step, the exposed surfaces of the etching resistant film 40 and the diffusion barrier layer 22 are oxidized by the oxidizing gas, so that the etching resistant film 40 ′ and the diffusion barrier layer 22 ′ are formed.
become. Finally, as shown in FIG.
In the same manner as in the steps 2 and 3, the removal of the etching resistant film 40 'and the patterning of the underlying diffusion barrier layer 22' were simultaneously performed.

In this embodiment, Ir is used as the metal constituting the electrode layer, but Pt, Rh, Os, Rc or Ru is used.
May be used. Each of these metals,
Used as a material for electrodes in high dielectric and ferroelectric devices.

In the above description, the lower electrode layer 24 and
As a gas for etching the dielectric layer 325, Cl is used._TwoTo
Chlorine gas and O_TwoOxidizing gas was used, but this book
The invention is not so limited. HC as chlorine-based gas
1, BCl_Three, Cl_Two, CCl_Four, CH_xCl_4-x, COC
l_Two, S_TwoCl_Two, PCl_Three, CCl_XBr_4-x, NOCl,
SiCl_FourSuch as CF_Four,C_TwoF_Four, C
HF_Three, C_TwoF₆, C_ThreeF₈, C _FourF_Ten,SF₆, S_TwoF_Two, CH
FCl_Two, BrF_Three, BrF_Five, HBr, HF, BF_Three, C
OF_2,NF_Three, SiF_Four, XeF_Two, CF_xCl_4-x, CH
FCl_Two, ClF_Three, BBr_Three, CBr_Four, CF_xBr_4-x,
CHFBr_Two, S_TwoBr_TwoEtc. (where x is an integer of 4 or less),
O as oxidizing gas_TwoAnd O_ThreeAnd N_TwoGas such as O
Dry etching may be performed using these mixed gases.
No.

As the etching resistant film 40 and the diffusion barrier layer 22, in addition to TaSiN, HfSiN, Ti
A film that is easily oxidized such as N or TiAlN may be used.
It is not necessary to limit the composition of these compounds in consideration of the effect of etching, and any composition can be etched by the etching method of the present invention. However, in consideration of the electrical characteristics or heat resistance, the diffusion barrier layer 22 is, for example, 0.7% in the case of a Ta _x Si _1-x N _y film.
It is more preferable that 5 <x <0.95 and 0.3 <y <0.5.

In removing the mask (etching-resistant film 40) made of TaSiN, HfSiN, TiN or TiAlN and etching the diffusion barrier layer,
HCl, BCl ₃ , Cl ₂ , CCl ₄ , CH _x Cl _4-x , C
OCl ₂ , S ₂ Cl ₂ , PCl ₃ , CCl _x Br _4-x , NOC
1, SiCl ₄ , CF ₄ , C ₂ F ₄ , CHF ₃ , C ₂ F ₆ , C ₃
F ₈ , C ₄ F ₁₀ , SF _6, S ₂ F ₂ , CHFCl ₂ , BrF ₃ ,
BrF ₅ , HBr, HF, BF ₃ , COF ₂ , NF ₃ , Si
F ₄ , XeF ₂ , CF _x Cl _4-x , CHFCl ₂ , ClF ₃ ,
_{BBr 3, CBr 4, CF x} Br 4-x, CHFBr 2, and S ₂ Br ₂ (where x is an integer of 4 or less) complete the etching by using one or more gases selected from the group comprising can do. Further, when these oxidizable nitrogen compounds are used as a mask, O ₂ , O ₃ , N ₂
An oxidizing gas such as O is added to a halogen gas or a halogenated gas to perform etching.
What is necessary is just to add 0% or more.

Further, a material containing at least one element selected from the group containing Ti, Ta, Co, Ni, Hf, Mo and W is provided between the silicon oxide film 11 and the diffusion barrier layer 22. A buffer layer (adhesion layer) may be formed as in the case of the first embodiment.

As described above, the SBT layer, which is the dielectric layer 325, is processed into a desired shape in advance, and after plasma damage recovery, the SBT layer is covered with the interlayer insulating film 327. Plasma damage to the ferroelectric can be prevented.

According to the present invention, a dielectric thin film device having good characteristics can be manufactured.

(Fourth Embodiment) Hereinafter, FIGS.
A fourth embodiment of the method for manufacturing a dielectric thin film element of the present invention will be described with reference to FIG. The dielectric thin-film element of this embodiment further includes an upper electrode layer as compared with the dielectric thin-film element of the third embodiment.

First, as shown in FIG. 8A, a silicon oxide film 11 having a thickness of about 600 nm is formed on the surface of the silicon substrate 10 by using the CVD method. Next, a diffusion barrier layer 22 is formed by forming an amorphous tantalum silicon nitride (TaSiN) layer having a thickness of about 100 nm by a DC magnetron reactive sputtering method.
Thereafter, a heat treatment is performed in a nitrogen atmosphere to stabilize the tantalum silicon nitride film. This heat treatment can be omitted depending on the film forming conditions. Next, the diffusion barrier layer 22
On the lower electrode layer 2 by DC magnetron sputtering.
As No. 4, an iridium (Ir) layer is formed. The film forming conditions and the heat treatment conditions for the diffusion barrier layer 22 and the lower electrode layer 24 are the same as those in the first and second embodiments.

Next, a dielectric layer 25 is formed on the lower electrode layer 24 using ferroelectric SrBi ₂ Ta ₂ O ₉ (SBT).
(Thickness: about 200 nm). The spin-on method is used as the formation method as in the second embodiment. next,
On the dielectric layer 25, an interlayer insulating film 27 and a TaSiN film as an etching resistant film 40 are formed. Further, a resist pattern 50 is formed on the etching resistant film 40. In the above steps, a method similar to the method of the second embodiment is used.

Thereafter, similarly to the second embodiment, the etching resistant film 40 and the interlayer insulating film 27 are patterned using the resist pattern 50, and the dielectric layer 25 is patterned using the patterned etching resistant film 40. The etching of the lower electrode layer 24 is performed in the same manner as in the second embodiment. Further, the removal of the etching-resistant film 40 'and the patterning of the underlying diffusion barrier layer 22' are simultaneously performed to obtain the structure shown in FIG.
Is obtained.

Next, as shown in FIG. 8C, the interlayer insulating film 47 is covered with CV so as to cover the structure obtained as described above.
It is formed to a thickness of about 700 nm by Method D. Further, the dielectric layer 25 in the interlayer insulating film 47 is formed using a normal resist process.
A contact hole is formed in the upper region of.

Next, as shown in FIG. 8D, the upper electrode layer 28 is formed so as to cover the dielectric layer 25 and the interlayer insulating film 47.
To form The upper electrode layer 28 uses Ir in the present embodiment. Next, the etching resistant film 4 is formed on the upper electrode layer 28.
40 (second nitride layer) as a TaSiN film (thickness, 2
(About 0 to 500 nm) is formed in the same manner as in the first and second embodiments, and is used as a mask for processing the upper electrode layer 28.

Next, as shown in FIG. 8 (e), the upper electrode layer 28 is formed so that Cl ₂ / O ₂ = 64/16 SCCM.
Etching is selectively performed at about RF = 100 W. Under these conditions, as can be seen from the results of the graphs of FIGS. 4 and 9, the etching selectivity between the upper electrode layer 28 (Ir film) and the interlayer insulating film 47 (silicon oxide film) is about 1.5,
The upper electrode layer 28 and the etching resistant film 440 (TaSiN
Selectivity with the film) is about 6 or more. By using the above etching conditions, the upper electrode layer 28 with good uniformity can be processed, and the overetch amount of the interlayer insulating film 47 can be minimized.

According to the present embodiment, the etching resistant film 44
Since the 0 mask is very thin, there is no residue attached to the side walls, and microloading is greatly reduced. Further, as in the previous embodiments, the patterning accuracy is a TaSiN film (etching resistant films 40 and 440).
And the accuracy of the TaSiN film depends on the accuracy of the resist pattern for forming it. The resist pattern is for forming only the TaSiN film,
The thickness of the film itself can be reduced. For this reason, miniaturization can be easily performed as compared with the case where a conventional thick resist is used to improve the depth of focus and the resolution. According to the present embodiment, highly accurate etching for forming a fine capacitor can be performed.

(Fifth Embodiment) FIG. 10 (a)
(H), another method of forming the dielectric thin film element of the present invention will be described.

First, as shown in FIG. 10A, a LOCOS oxide film 516 having a thickness of about 500 nm is formed on the surface of the silicon substrate 10 to form an element isolation region, and then a gate electrode 517 is formed. , A selection transistor including the source / drain region 518 and the like is formed. After that, a first silicon oxide film 519 is formed as an interlayer insulating film by the CVD method.
A film having a diameter of about 0 nm is formed. A 5 μm contact hole is formed. Next, after polysilicon is buried in the contact hole by the CVD method, the surface is flattened by the CMP method to form a polysilicon plug 520.

Next, as shown in FIG. 10B, an amorphous tantalum silicon nitride film (about 100 nm thick) is formed on the polysilicon plug 520 as a diffusion barrier layer 22 by DC magnetron reactive sputtering. TaS
iN film). A heat treatment is performed in a nitrogen atmosphere to stabilize the tantalum silicon nitride film. This heat treatment may not be particularly necessary depending on the film forming conditions.

The TaSiN film used in this embodiment is formed under the following conditions: an alloy target having an elemental molar ratio of about Ta: Si = 10: 3; a substrate temperature of 500 ° C .; a sputtering power of 2000 W; 0.7 Pa, and the ratio of Ar flow rate / N ₂ flow rate is 3/2. The heat treatment was performed in a pure nitrogen atmosphere at a temperature rising rate of 5 ° C./min and a holding temperature of 6 ° C.
00 ° C., holding time 1 hour. The tantalum silicon nitride film formed under the above conditions was confirmed to have an amorphous structure by X-ray diffraction, and further, it was confirmed by Auger spectroscopy that the composition ratio was Ta _0.85 Si _0.15 N _0.41 . .

An iridium layer was formed on the diffusion barrier layer 22 as a lower electrode layer 24 by DC magnetron sputtering.
DC power 0.5kW, substrate temperature 500 ° C, gas pressure 0.
6 Pa and a film thickness of 150 nm were formed. The sputtering gas is A
Only r gas is used. Next, as shown in FIG.
SrBi ₂ which is a ferroelectric as a dielectric film 25 on a substrate
A Ta ₂ O ₉ thin film (SBT thin film) is formed. As a forming method, a spin-on method is used. First, a precursor solution in which constituent elements are dispersed in a solvent is prepared, and the precursor solution is applied to a substrate at a rotation speed of 3000 rpm using a spinner, and dried at 150 ° C. for 10 minutes in the atmosphere.
Then, after calcination is performed at 400 ° C. for 30 minutes in the air, crystallization is performed at 700 ° C. for 1 hour. These steps are repeated three times, and an SBT thin film is
It is formed on the order of nm.

Thereafter, as shown in FIG. 10D, a resist mask 550 is formed and patterned by photolithography into 0.8 to 2.5 μm square. Using the formed resist pattern, the dielectric film 25 is dry-etched using, for example, a halogen-based gas to pattern the dielectric layer 25 (FIG. 10E). After that, the resist mask 550 is removed.

Next, as shown in FIG. 10E, the same tantalum silicon nitride as the diffusion barrier layer 22 is formed on the patterned dielectric film 25 as the etching resistant film 540 by the same method as described above. It is formed to a thickness of 120 nm. Further, a resist mask 50 having a thickness of 1 μm is formed thereon, and patterned by photolithography into 0.8 to 2.5 μm square. Further formed resist pattern 5
Using 0, the etching resistant film 540 is patterned by etching with, for example, 50 SCCM of chlorine gas and RFPower = 100 W. The etching gas at this time is not limited to chlorine, and when a silicon-based residue remains, a fluorine-based halogen gas or a mixed gas thereof may be used. After that, the resist pattern 50 is removed.
Ashing using ozone or a release agent is used for the removal.

Next, TaS which is the etching resistant film 540 is used.
The etching of the Ir thin film that is the lower electrode layer 24 using the iN mask will be described. Etching is
1.4 mT pressure using ECR plasma etching equipment
The operation is performed as follows under the conditions that the orr and the microwave output are set to 1000 W.

First, as shown in FIG. 10F, the Ir thin film is etched. Chlorine gas (C1 ₂₎ etching gas as halogen gas during this, using oxygen (0 ₂₎ as the oxidizing gas, the gas flow ratio C1 ₂ / O ₂ = 6
Etching was performed at 4/16 SCCM at RFPower = 100 W. At this time, the flow rate ratio of the etching gas is such that the oxygen flow rate is 20% or more of the total flow rate as shown in FIG.
In consideration of the fact that the etching of TaSiN (diffusion barrier layer 22) used as a mask (etching-resistant film 540) and Ir is stopped, it is necessary to perform etching at an oxygen flow rate of 20% or more. When the oxygen flow rate is 80% or more, the etch rate of Ir decreases. Therefore, the oxygen flow rate is preferably 70% or less of the total flow rate.

Next, as shown in FIG.
Etching of the iN mask and TaSiN which is the underlying diffusion barrier layer is performed simultaneously. The etching conditions at this time are as follows: in this embodiment, chlorine is 50 SCCM, and RFPower = 1.
00W. The etching gas at this time is not limited to chlorine, but may be a fluorine-based halogen gas or a mixed gas thereof. During this etching, the removal of the mask and the etching of the diffusion barrier proceed simultaneously. Since the mask and the diffusion barrier are composed of the same element, it is not necessary to set the etching conditions in consideration of the difference in etch rate, and the etching of the diffusion barrier layer 22 and the removal of the mask 540 can be easily performed.

Next, as shown in FIG. 10H, after forming the second silicon oxide film 521, a contact hole is formed. After that, the upper electrode 28 is formed, and further, the first aluminum extraction electrode 522 is formed.

In this embodiment, Ir is used as the metal constituting the electrode layer, but Pt, Rh, Os, Rc or Ru is used.
May be used. Each of these metals,
Used as a material for electrodes in high dielectric and ferroelectric devices.

In the above description, a chlorine gas of Cl ₂ and an oxidizing gas of O ₂ are used as a gas for etching the lower electrode layer 24 and the dielectric layer 25, but the present invention is not limited to this. HCl as a chlorine-based gas,
BCl ₃ , Cl ₂ , CCl ₄ , CH _x Cl _4-x , COCl ₂ ,
S ₂ Cl ₂ , PCl ₃ , CCl _x Br _4-x , NOCl, Si
CF _4, C ₂ F ₄ , CH as halogenated gas such as Cl _{4
F 3, C 2 F 6,} C 3 F 8, C 4 F 10, SF 6, S 2 F 2, CHF
Cl ₂ , BrF ₃ , BrF ₅ , HBr, HF, BF ₃ , CO
F _2, NF ₃ , SiF ₄ , XeF ₂ , CF _x Cl _4-x , CHF
_{Cl 2, ClF 3, BBr 3} , CBr 4, CF x Br 4-x, C
Dry etching may be performed using HFBr ₂ , S ₂ Br ₂ or the like (where x is an integer of 4 or less), a gas such as O ₂ , O ₃ or N ₂ O as an oxidizing gas, or a mixed gas thereof. .

Further, the etching resistant film 540 and the diffusion burr
As the layer 22, in addition to TaSiN, HfSiN, Ti
A film that is easily oxidized such as N or TiAlN may be used.
The composition of these compounds depends on the effect of etching.
It is not necessary to limit, and the present invention
Can be etched by the above etching method. However
In consideration of electrical characteristics or heat resistance, the diffusion barrier layer
22, for example, Ta _xSi_1-xN_y0.7 for membrane
If 5 <x <0.95 and 0.3 <y <0.5
More preferred.

Further, TaSiN, HfSiN, TiN, etc.
Or a mask (etching-resistant film) formed of TiAlN
540) and during etching of the diffusion barrier layer 22
Include HCl, BCl_Three, Cl_Two, CCl_Four, CH_xCl
_4-x, COCl_Two, S_TwoCl_Two, PCl_Three, CCl_xB
r_4-x, NOCl, SiCl_Four, CF_Four, C_TwoF_Four, CH
F_Three, C_TwoF₆, C_ThreeF₈, C_FourF_Ten, SF_6,S_TwoF_Two, CHF
Cl_Two, BrF_Three, BrF_Five, HBr, HF, BF_Three, CO
F_Two, NF_Three, SiF_Four, XeF_Two, CF_xCl_4-x, CHF
Cl_Two, ClF_Three, BBr_Three, CBr_Four, CF_xBr_4-x, C
HFBr_Two, And S_TwoBr _Two(Where x is an integer of 4 or less)
By using one or more gases selected from the group comprising
The etching can be completed. In addition, these
When using easily oxidizable nitrogen compounds as masks
Is O_TwoAnd O_ThreeAnd N_TwoOxidizing gas such as O is converted to halogen gas or
Performs etching by adding to a halogenated gas, for example,
Oxygen may be added at about 20% or more of the total amount.

Further, between the silicon oxide film 519 and the diffusion barrier layer 22, a compound containing at least one element selected from the group containing Ti, Ta, Co, Ni, Hf, Mo, and W is formed. A buffer layer (adhesion layer) may be formed.

The electrode processed by the above etching has a very thin mask thickness as compared with the case of using a conventional resist or a silicon oxide film mask, so that there is no residue attached to the side wall. Loading is also greatly reduced.

The patterning accuracy depends on the TaSiN mask accuracy, and the accuracy of the TaSiN mask depends on the resist pattern accuracy for forming the same. Since the resist pattern is for forming only the TaSiN mask, the thickness of the resist itself can be reduced. As a result, since the depth of focus and the resolution are improved, miniaturization can be performed more easily than in the case where a conventional thick resist is used.

Further, by making the constituent elements of the mask and the underlying barrier layer the same, removal of the mask and etching of the diffusion barrier layer can be performed simultaneously. This is similar to the conventional S
Unlike the case of OG, CVDSiO ₂ , Ti mask, etc., it is not necessary to consider the selection ratio between the mask and the base, so that the mask can be easily removed. From these facts, according to the method of the present invention, highly accurate etching for forming a fine capacitor can be performed, and a high-density dielectric element can be formed.

(Sixth Embodiment) FIG. 11 (a)
Still another method for forming the dielectric thin film element of the present invention will be described with reference to FIGS.

First, as shown in FIG. 11A, a LOCOS oxide film 516 having a thickness of about 500 nm is formed on the surface of the silicon substrate 10 to form an element isolation region, and then a gate electrode 517 is formed. , A selection transistor including the source / drain region 518 and the like is formed. After that, a first silicon oxide film 519 is formed as an interlayer insulating film by the CVD method.
A film is formed to a thickness of about 0 nm, and then a contact hole having a diameter of 0.5 μm is formed. Next, after polysilicon is buried in the contact hole by the CVD method, the surface is flattened by the CMP method to form a polysilicon plug 520.

Next, as shown in FIG. 11B, an amorphous tantalum silicon nitride film (about 100 nm thick) is formed on the polysilicon plug 520 as a diffusion barrier layer 22 by DC magnetron reactive sputtering. TaS
iN film). A heat treatment is performed in a nitrogen atmosphere to stabilize the tantalum silicon nitride film. This heat treatment may not be particularly necessary depending on the film forming conditions.

The TaSiN film used in the present embodiment is formed under the following conditions: an alloy target having an elemental molar ratio of about Ta: Si = 10: 3; a substrate temperature of 500 ° C .; a sputtering power of 2000 W; 0.7 Pa, and the ratio of Ar flow rate / N ₂ flow rate is 3/2. The heat treatment was performed in a pure nitrogen atmosphere at a temperature rising rate of 5 ° C./min and a holding temperature of 6 ° C.
00 ° C., holding time 1 hour. The tantalum silicon nitride film formed under the above conditions was confirmed to have an amorphous structure by X-ray diffraction, and further, it was confirmed by Auger spectroscopy that the composition ratio was Ta _0.85 Si _0.15 N _0.41 . .

An iridium layer is formed on the diffusion barrier layer 22 as the lower electrode layer 24 by DC magnetron sputtering.
DC power 0.5kW, substrate temperature 500 ° C, gas pressure 0.
6 Pa and a film thickness of 150 nm were formed. The sputtering gas is A
Only r gas is used. Next, as shown in FIG.
SrBi which is a ferroelectric as a dielectric film 625 on the substrate
_{A 2} Ta ₂ O ₉ thin film (SBT thin film) is formed. As a forming method, a spin-on method is used. First, a precursor solution in which constituent elements are dispersed in a solvent is prepared, and the precursor solution is applied to a substrate at a rotation speed of 3000 rpm using a spinner, and dried at 150 ° C. for 10 minutes in the atmosphere.
Then, after calcination is performed at 400 ° C. for 30 minutes in the air, crystallization is performed at 700 ° C. for 1 hour. These steps are repeated three times, and an SBT thin film is used as the dielectric film 625.
It is formed to a thickness of about 0 nm.

Further, on the dielectric film 625, the interlayer insulating film 2
7 is formed to a thickness of about 50 nm using a CVD method. The interlayer insulating film 27 is for preventing the SBT surface from being directly exposed to the plasma during the removal of the mask, causing damage such as deterioration of the characteristics. Note that this layer may not be provided when performing the property recovery process after the etching. When the upper electrode layer is formed first, after forming the dielectric film 625, the upper electrode may be formed thereon and then the insulating film 27 may be formed.

Next, a TaSiN film is formed on the interlayer insulating film 27 as the etching-resistant film 40 serving as a mask under the same conditions as the diffusion barrier layer 22 described above. A resist mask 550 is formed in the same manner as in the fifth embodiment, and is patterned to 0.8 to 2.5 μm square by photolithography. The etching resistant film 40 is etched using the formed resist pattern. At this time, the interlayer insulating film 2
7 is also etched into the same shape. The etching of the interlayer insulating film 27 uses Cl ₂ gas and C ₂ F ₆ gas. Here, the etching rate of the interlayer insulating film 27 is lower than that of the TaSiN layer 4.
If it is faster than 0, it may cause film roughness. As shown in FIG. 6, when the flow rate ratio of C ₂ F ₆ is about 50% or less of the total flow rate, the etching rate of the TaSiN layer 40 becomes faster than that of the silicon oxide film (interlayer insulating film 27). However, since the flow rate ratio of C ₂ F ₆ exits are left in the case of less than 20%, C ₂
It is preferable that the flow ratio of F _{6 be} about 20% or more and 50% or less.

After patterning the etching resistant film 40 and the interlayer insulating film 27, the resist pattern 550 is removed (FIG. 11D).

Next, a TaSiN film (etching-resistant film) 4
The SBT thin film 625 serving as the dielectric layer 625 and the Ir film 24 serving as the lower electrode layer 24 are etched using a mask of zero.

As shown in FIG. 4, the etch rate of the SBT thin film 25 gradually decreases until the oxygen addition amount reaches about 50% of the total flow rate, and rapidly decreases when the oxygen addition amount exceeds 50%. For that reason,
During etching, the flow rate of oxygen to the total flow rate is 20
% Is desirably about 50% or less. In the present embodiment, both the SBT thin film 625 and the Ir thin film 24
Etching is performed under the conditions of about l ₂ / O ₂ = 61/16 SCCM and RF = about 100 W, and is etched into the shape shown in FIG. In this etching step, the TaSiN film is oxidized by oxygen gas, and as a result, the etching resistance is improved. The TaSiN film thus oxidized (the etching resistant film 40 'and the diffusion barrier layer 22') is made of Ta protected by the thin Ta ₂ O ₅ film.
It is composed of a SiN layer.

Next, as shown in FIG. 11F, the etching resistant film 40 'and the underlying diffusion barrier layer 22' are simultaneously etched. The etching conditions at this time are, as in the fifth embodiment, a Cl ₂ flow rate of about 50 SCCM, an RF
The power is set at about 100 W. The etching gas at this time is not limited to chlorine, but may be a fluorine-based halogen gas,
Alternatively, a mixed gas thereof may be used.

Next, as shown in FIG. 11G, after a second silicon oxide film 521 is formed, a contact hole is formed. After that, the upper electrode 28 is formed, and further, the first aluminum extraction electrode 522 is formed.

In this embodiment, Ir is used as the metal constituting the electrode layer. However, Pt, Rh, Os, Rc or Ru is used.
May be used. Each of these metals,
Used as a material for electrodes in high dielectric and ferroelectric devices.

In the above description, a chlorine gas of Cl ₂ and an oxidizing gas of O ₂ are used as a gas for etching the lower electrode layer 24 and the dielectric layer 25, but the present invention is not limited to this. HCl as a chlorine-based gas,
BCl ₃ , Cl ₂ , CCl ₄ , CH _x Cl _4-x , COCl ₂ ,
S ₂ Cl ₂ , PCl ₃ , CCl _x Br _4-x , NOCl, Si
CF _4, C ₂ F ₄ , CH as halogenated gas such as Cl _{4
F 3, C 2 F 6,} C 3 F 8, C 4 F 10, SF 6, S 2 F 2, CHF
Cl ₂ , BrF ₃ , BrF ₅ , HBr, HF, BF ₃ , CO
F _2, NF ₃ , SiF ₄ , XeF ₂ , CF _x Cl _4-x , CHF
_{Cl 2, ClF 3, BBr 3} , CBr 4, CF x Br 4-x, C
Dry etching may be performed using HFBr ₂ , S ₂ Br ₂ or the like (where x is an integer of 4 or less), a gas such as O ₂ , O ₃ or N ₂ O as an oxidizing gas, or a mixed gas thereof. .

As the etching resistant film 40 and the diffusion barrier layer 22, in addition to TaSiN, HfSiN, Ti
A film that is easily oxidized such as N or TiAlN may be used.
It is not necessary to limit the composition of these compounds in consideration of the effect of etching, and any composition can be etched by the etching method of the present invention. However, in consideration of the electrical characteristics or heat resistance, the diffusion barrier layer 22 is, for example, 0.7% in the case of a Ta _x Si _1-x N _y film.
It is more preferable that 5 <x <0.95 and 0.3 <y <0.5.

Further, TaSiN, HfSiN, TiN, etc.
Or a mask (etching-resistant film) formed of TiAlN
540) and during etching of the diffusion barrier layer 22
Include HCl, BCl_Three, Cl_Two, CCl_Four, CH_xCl
_4-x, COCl_Two, S_TwoCl_Two, PCl_Three, CCl_xB
r_4-x, NOCl, SiCl_Four, CF_Four, C_TwoF_Four, CH
F_Three, C_TwoF₆, C_ThreeF₈, C_FourF_Ten, SF_6,S_TwoF_Two, CHF
Cl_Two, BrF_Three, BrF_Five, HBr, HF, BF_Three, CO
F_Two, NF_Three, SiF_Four, XeF_Two, CF_xCl_4-x, CHF
Cl_Two, ClF_Three, BBr_Three, CBr_Four, CF_xBr_4-x, C
HFBr_Two, And S_TwoBr _Two(Where x is an integer of 4 or less)
By using one or more gases selected from the group comprising
The etching can be completed. In addition, these
When using easily oxidizable nitrogen compounds as masks
Is O_TwoAnd O_ThreeAnd N_TwoOxidizing gas such as O is converted to halogen gas or
Performs etching by adding to a halogenated gas, for example,
Oxygen may be added at about 20% or more of the total amount.

Further, between the silicon oxide film 519 and the diffusion barrier layer 22, a compound containing at least one element selected from the group including Ti, Ta, Co, Ni, Hf, Mo, and W is formed. A buffer layer (adhesion layer) may be formed.

By using the formation method described above, the fifth
The same effect as that of the embodiment can be obtained. Also, the number of steps can be significantly reduced by performing the etching on the dielectric and the electrode at once. From these facts, according to the method of the present invention, it is possible to perform high-precision etching for forming a fine capacitor, and to form a high-density dielectric element.

(Seventh Embodiment) Hereinafter, FIG.
Still another method for forming the dielectric thin film element of the present invention will be described with reference to FIGS.

First, as shown in FIG. 12A, a LOCOS oxide film 516 having a thickness of about 500 nm is formed on the surface of the silicon substrate 10 to form an element isolation region, and then a gate electrode 517 is formed. , A selection transistor including the source / drain region 518 and the like is formed. After that, a first silicon oxide film 519 is formed as an interlayer insulating film by the CVD method.
A film is formed to a thickness of about 0 nm, and then a contact hole having a diameter of 0.5 μm is formed. Next, after polysilicon is buried in the contact hole by the CVD method, the surface is flattened by the CMP method to form a polysilicon plug 520.

Next, as shown in FIG. 12B, an amorphous tantalum silicon nitride film (about 100 nm thick) is formed on the polysilicon plug 520 as a diffusion barrier layer 22 by DC magnetron reactive sputtering. TaS
iN film). A heat treatment is performed in a nitrogen atmosphere to stabilize the tantalum silicon nitride film. This heat treatment may not be particularly necessary depending on the film forming conditions.

The conditions for forming the TaSiN film in this embodiment are as follows: an alloy target having an elemental molar ratio of about Ta: Si = 10: 3; a substrate temperature of 500 ° C .; a sputtering power of 2000 W; 0.7 Pa, and the ratio of Ar flow rate / N ₂ flow rate is 3/2. The heat treatment was performed in a pure nitrogen atmosphere at a temperature rising rate of 5 ° C./min and a holding temperature of 6 ° C.
00 ° C., holding time 1 hour. The tantalum silicon nitride film formed under the above conditions was confirmed to have an amorphous structure by X-ray diffraction, and further, it was confirmed by Auger spectroscopy that the composition ratio was Ta _0.85 Si _0.15 N _0.41 . .

On the diffusion barrier layer 22, an iridium layer was formed as a lower electrode layer 24 by DC magnetron sputtering.
DC power 0.5kW, substrate temperature 500 ° C, gas pressure 0.
6 Pa and a film thickness of 150 nm were formed. The sputtering gas is A
Only r gas is used. Next, as shown in FIG.
SrBi which is a ferroelectric as a dielectric film 725 on the substrate
_{A 2} Ta ₂ O ₉ thin film (SBT thin film) is formed. As a forming method, a spin-on method is used on a substrate.

After that, as described in the fifth embodiment,
A resist mask is formed on the dielectric layer 725, and is patterned to 0.8 to 2.5 μm square by photolithography. Using the formed resist pattern, the dielectric film 725 is dry-etched using, for example, a halogen-based gas to pattern the dielectric layer 725 (FIG. 12C). After that, the resist mask is removed. Then, RTA (Rapid Themal an)
A heat treatment of 700 ° C. × 30 sec is applied by using the nearing method to recover the damage caused by the SBT etching.

After that, as shown in FIG. 12D, an interlayer insulating film 727 is formed, and the surface of the interlayer insulating film 727 is planarized by reflow or CMP. This flattening of the surface is for improving the processing accuracy of the TaSiN mask formed on the upper portion, and if sufficient processing accuracy can be obtained,
There is no need for a planarization step.

Next, a TaSiN layer 40 serving as a mask is formed on the interlayer insulating film 727 under the same conditions as the diffusion barrier layer 22. Next, a resist mask 50 is formed, and TaSiN
And etching of the interlayer insulating film was performed (FIG. 12).
(E)). TaSiN layer C1 as a gas system in the etching of the interlayer insulating film _{2 / C 2 F 6 = 40} / 40SCCM, R
The operation is performed at FPower = 100 W. By making the chlorine-based gas and the fluorine-based gas equal, the etch rates of TaSiN and the interlayer insulating film become substantially the same. After each film is etched under the conditions, the resist mask 50 is removed.

Next, as shown in FIG. 12F, the Ir layer serving as the electrode layer 24 is etched in the same manner as in the fifth and sixth embodiments using the TaSiN mask 40 formed as described above.

Next, as shown in FIG. 12 (g), etching of the mask 40 and TaSiN which is the underlying diffusion barrier layer 22 is performed simultaneously as in the fifth and sixth embodiments.

Next, as shown in FIG. 12H, after forming a second silicon oxide film 521, a contact hole is formed. After that, the upper electrode 28 is formed, and further, the first aluminum extraction electrode 522 is formed.

In this embodiment, Ir was used as the metal constituting the electrode layer, but Pt, Rh, Os, Rc or Ru was used.
May be used. Each of these metals,
Used as a material for electrodes in high dielectric and ferroelectric devices.

In the above description, a chlorine gas of Cl ₂ and an oxidizing gas of O ₂ are used as a gas for etching the lower electrode layer 24 and the dielectric layer 25, but the present invention is not limited to this. HCl as a chlorine-based gas,
BCl ₃ , Cl ₂ , CCl ₄ , CH _x Cl _4-x , COCl ₂ ,
S ₂ Cl ₂ , PCl ₃ , CCl _x Br _4-x , NOCl, Si
CF _4, C ₂ F ₄ , CH as halogenated gas such as Cl _{4
F 3, C 2 F 6,} C 3 F 8, C 4 F 10, SF 6, S 2 F 2, CHF
Cl ₂ , BrF ₃ , BrF ₅ , HBr, HF, BF ₃ , CO
F _2, NF ₃ , SiF ₄ , XeF ₂ , CF _x Cl _4-x , CHF
_{Cl 2, ClF 3, BBr 3} , CBr 4, CF x Br 4-x, C
Dry etching may be performed using HFBr ₂ , S ₂ Br ₂ or the like (where x is an integer of 4 or less), a gas such as O ₂ , O ₃ or N ₂ O as an oxidizing gas, or a mixed gas thereof. .

As the etching resistant film 40 and the diffusion barrier layer 22, in addition to TaSiN, HfSiN, Ti
A film that is easily oxidized such as N or TiAlN may be used.
It is not necessary to limit the composition of these compounds in consideration of the effect of etching, and any composition can be etched by the etching method of the present invention. However, in consideration of the electrical characteristics or heat resistance, the diffusion barrier layer 22 is, for example, 0.7% in the case of a Ta _x Si _1-x N _y film.
It is more preferable that 5 <x <0.95 and 0.3 <y <0.5.

When removing the mask (etching-resistant film 40) made of TaSiN, HfSiN, TiN or TiAlN and etching the diffusion barrier layer 22, HCl, BCl ₃ , Cl ₂ , CCl ₄ , CH _{x are used.} C
l _4-x , COCl ₂ , S ₂ Cl ₂ , PCl ₃ , CCl _x Br
_{4-x, NOCl, SiCl 4} , CF 4, C 2 F 4, CHF 3,
_{C 2 F 6, C 3 F} 8, C 4 F 10, SF 6, S 2 F 2, CHFC
l ₂ , BrF ₃ , BrF ₅ , HBr, HF, BF ₃ , COF
_{2, NF 3, SiF 4,} XeF 2, CF x Cl 4-x, CHFC
_{l 2, ClF 3, BBr 3} , CBr 4, CF x Br 4-x, CH
The etching can be completed by using one or more gases selected from the group including FBr ₂ and S ₂ Br ₂ (where x is an integer of 4 or less). Further, when these easily oxidizable nitrogen compounds are used as a mask, an oxidizing gas such as O ₂ , O _3, or N ₂ O is added to a halogen gas or a halogenated gas to perform etching. About 20% or more of the above may be added.

In addition, between the silicon oxide film 519 and the diffusion barrier layer 22, a compound containing at least one element selected from the group including Ti, Ta, Co, Ni, Hf, Mo, and W is formed. A buffer layer (adhesion layer) may be formed.

According to the method of this embodiment, the same effects as those of the previous embodiment can be obtained. As described above, by processing the SBT layer which is a dielectric layer in advance and recovering the plasma damage, and covering the SBT layer with the interlayer insulating film, it is possible to reduce the plasma damage to the ferroelectric from the side wall in the subsequent process. From these facts, it is possible to form a highly-processed element included in a fine capacitor by the method of the present invention.

(Eighth Embodiment) Hereinafter, FIG.
The method for forming the upper electrode layer 28 in the above embodiment will be described with reference to FIGS.

The structure of FIG. 11F is manufactured by the method of the sixth embodiment. Then, as shown in FIG.
A second silicon oxide film 521 is formed to a thickness of about 700 nm by a CVD method. A contact hole is formed in the second silicon oxide film 521 so as to reach the dielectric layer 625.

Next, as shown in FIG. 13B, an upper electrode layer 28 is formed. The upper electrode layer 28 uses Ir in the present embodiment. Next, on the upper electrode layer 28, a TaSiN mask (thickness: 20 to 50) as an etching resistant film 840 is formed.
0 nm) is formed in the same manner as in the previous embodiment,
This is used as a mask for processing the upper electrode layer 28.

Next, as shown in FIG. 13 (c), the upper electrode layer 28 is formed of Cl ₂ / O ₂ = 64/16 SCCM and RF =
Etching is performed at about 100 W. Under these conditions, as can be seen from the results of the graphs of FIGS. 4 and 9, the upper electrode layer 28 (Ir film) and the interlayer insulating film 521 (silicon oxide film)
Is about 1.5, and the upper electrode layer 2
8 and the etching resistance film 840 (TaSiN film) have a selectivity of about 6 or more. By using the above etching conditions, the upper electrode layer 28 with good uniformity can be processed, and the amount of overetch of the interlayer insulating film 521 can be minimized. Next, the etching resistant film 84
Remove 0. Finally, as shown in FIG. 13D, a first aluminum electrode 522 is formed.

In this embodiment, since the mask 840 is very thin, there is no residue attached to the side wall, and microloading is greatly reduced. Further, as described in the previous embodiment, the patterning accuracy depends on the accuracy of the TaSiN film (etching-resistant film 840).
The precision of the film depends on the precision of the resist pattern for forming it. The resist pattern is for forming only the TaSiN film, and the thickness of the resist pattern itself can be reduced. For this reason, miniaturization can be easily performed as compared with the case where a conventional thick resist is used to improve the depth of focus and the resolution. According to the present embodiment, highly accurate etching for forming a fine capacitor can be performed.

(Ninth Embodiment) A method for forming a ferroelectric memory cell according to the present invention will be described below with reference to FIG. This embodiment differs from the fifth to eighth embodiments in the configuration of the upper electrode layer. As shown in FIG. 14, the upper electrode layer 928 is formed on the dielectric layer 25,
Through a contact hole in the silicon oxide film 521,
It is connected to a lead electrode 922 on the silicon oxide film 521.

The method of forming each layer of the ferroelectric memory cell of this embodiment is basically the same as the method of the fifth to eighth embodiments. Hereinafter, the formation method will be schematically described. First, a LOCOS oxide film 516 having a thickness of about 500 nm is formed on the surface of the silicon substrate 10 to form an element isolation region. Next, the gate electrode 517 and the source / drain region 51
A selection transistor including 8 and the like is formed. Thereafter, a first silicon oxide film 519 is formed as an interlayer insulating film by the CVD method.
Is formed to a thickness of about 500 nm, and then a contact hole having a diameter of 0.5 μm is formed. Next, after polysilicon is buried in the contact hole by the CVD method, the surface is flattened by the CMP method to form a polysilicon plug 520.

Next, on the polysilicon plug 520, D
The diffusion barrier layer 22 is formed by the C magnetron reactive sputtering method.
As an example, an amorphous tantalum silicon nitride film (TaSiN film) having a thickness of about 100 nm is formed. A heat treatment is performed in a nitrogen atmosphere to stabilize the tantalum silicon nitride film. This heat treatment may not be particularly necessary depending on the film forming conditions. The TaSiN film was formed using an alloy target having an elemental molar ratio of about Ta: Si = 10: 3.
A substrate temperature of 500 ° C., a sputtering power of 2000 W, a sputtering gas pressure of 0.7 Pa, and an Ar flow rate / N ₂ flow rate ratio of 3
/ 2. The heat treatment conditions are as follows: a temperature rising rate is 5 ° C./min, a holding temperature is 600 ° C., and a holding time is 1 hour in a pure nitrogen atmosphere.

An iridium layer was formed on the diffusion barrier layer 22 as the lower electrode layer 24 by DC magnetron sputtering.
DC power 0.5kW, substrate temperature 500 ° C, gas pressure 0.
6 Pa and a film thickness of 150 nm were formed. The sputtering gas is A
Only r gas is used. Next, a ferroelectric SrBi ₂ Ta ₂ O ₉ thin film (SBT thin film) is formed on the substrate as the dielectric film 25.
To form

Then, by DC magnetron sputtering,
After the upper electrode 928 having a thickness of about 50 nm is formed, etching is performed by the electrode processing method according to the present invention. After the ferroelectric film 25 is etched, the lower electrode layer 24 and the diffusion barrier layer 22 are further etched by the above-described method.

After that, a second silicon oxide film 521 is formed as an interlayer insulating film by using the CVD method, a contact hole is formed, and an upper electrode 928 of the ferroelectric capacitor is formed.
Is formed by a DC magnetron sputtering method.

In the above embodiment, as a method of forming the dielectric film, in addition to the spin-on method, MOD (Metal Organ
ic deposition) method, vacuum evaporation method, reactive magnetron sputtering method, MOCVD (organic metal CVD) method, or the like. Although SBT is used as a dielectric thin film, SrBi ₂ Nb ₂ O is used as another ferroelectric thin film.
_{9, Bi 4 Ti 3 O 12} , BaBi 2 Nb 2 O 9, BaBi 2 Ta
₂ O _9, PbBi ₂ Nb ₂ O _9, PbBi ₂ Ta ₂ O _9, SrBi ₄
Ti ₃ O ₁₅ , PbBi ₄ Ta ₄ O ₁₅ , Na _0.5 Bi _4.5 Ti ₄
O ₁₅ , K _0.5 Bi _4.5 Ti ₄ O ₁₅ , Sr ₂ Bi ₄ Ti ₅ O ₁₈ ,
Ba ₂ Bi ₄ Ti ₅ O _18, Pb ₂ Bi ₄ Ti ₅ O _18, etc.
(Ba _x, Sr _1-x ) TiO ₃ or the like can also be used as the high dielectric thin film. Further, tungsten or the like may be used as the contact plug material in addition to polysilicon.

According to the etching method of the electrode layer and the like of the present invention,
High-precision processing becomes possible. According to the present invention, a high-density ferroelectric memory cell can be manufactured.

[0168]

By using an etching resistant film which is easily oxidized as a mask for selectively etching an electrode layer or the like, the mask at the time of etching can be reduced to about 1/20 as compared with the conventional method. It becomes possible. Therefore, there is no influence of the generation of the residue on the side wall of the mask and the microloading. As a result, the in-plane uniformity of the processing accuracy is dramatically improved.

Further, since the mask can be easily formed, miniaturization can be easily performed. By using such a method of forming a dielectric element, high-precision processing can be performed, and a high-density ferroelectric memory can be realized.

[Brief description of the drawings]

FIG. 1 is a sectional view of a main part of a basic configuration of a dielectric thin film element according to the present invention.

2 (a) to 2 (e) are cross-sectional views showing steps of manufacturing a dielectric thin film element according to the present invention.

FIG. 3 is a schematic view of an ECR etching apparatus used in the present invention.

FIG. 4 shows an oxygen flow ratio according to the present invention, an SBT thin film, and TaSi.
5 is a graph showing the relationship between the etch rate of an N film and an Ir film.

5 (a) to 5 (d) are cross-sectional views showing another manufacturing process of the dielectric thin film element according to the present invention.

FIG. 6 shows C ₂ F ₆ / C ₁₂ flow ratio and Ta in the present invention.
5 is a graph showing a relationship between SiN and an etch rate of an interlayer insulating film.

FIGS. 7A to 7D are cross-sectional views showing still another manufacturing process of the dielectric thin film element according to the present invention.

FIGS. 8A to 8E are cross-sectional views showing still another manufacturing process of the dielectric thin film element according to the present invention.

FIG. 9 is a graph showing a relationship between an oxygen flow rate ratio and an etch rate of a silicon oxide film in the present invention.

10 (a) to 10 (h) are cross-sectional views showing still another manufacturing process of the dielectric thin film element according to the present invention.

FIGS. 11A to 11G are cross-sectional views showing still another manufacturing process of the dielectric thin film element according to the present invention.

12 (a) to 12 (h) are cross-sectional views showing still another manufacturing process of the dielectric thin film element according to the present invention.

13 (a) to 13 (d) are cross-sectional views showing still another manufacturing process of the dielectric thin film element according to the present invention.

FIG. 14 is a diagram showing a cross section of a ferroelectric memory cell formed by the present invention.

[Explanation of symbols]

Reference Signs List 10 substrate 11 silicon oxide film 20 multilayer thin film 22 diffusion barrier layer 24 lower electrode layer 25, 325, 625, 725 dielectric layer 27, 327, 727 interlayer insulating film 28, 928 upper electrode layer 40, 440, 540, 840 Etching film (Ta
SiN film) 50, 550 Resist pattern 80 Solenoid coil 81 Wafer 82 Electrode 83 O ₂ gas inlet 84 Halogen gas inlet 88 2.45 GHz microwave 89 13.56 MHz high frequency 516 Locos oxide layer 517 Gate electrode 518 Source / drain region 519 First silicon oxide film 520 Polysilicon plug 521 Second silicon oxide film 522 First aluminum extraction electrode

Claims (15)

[Claims] 1. A step of forming a multilayer thin film including a lower electrode layer on a substrate, and forming a pattern of a first nitride layer containing a metal element, which is oxidizable, on the multilayer thin film. And a step of patterning the lower electrode layer into a desired shape by selectively etching the multilayer thin film using a mixed gas containing an oxidizing gas using the pattern of the first nitride layer as a mask. A method for manufacturing a dielectric thin film element, comprising: a step of removing a pattern of the first nitride layer. 2. The multilayer thin film further includes: a dielectric layer formed on the lower electrode layer; and a diffusion barrier layer formed between the substrate and the lower electrode layer. The diffusion barrier layer prevents interdiffusion of elements between the substrate and the dielectric layer, and the step of removing the pattern of the first nitride layer includes selectively removing the diffusion barrier layer. 2. The method for manufacturing a dielectric thin film element according to claim 1, comprising a step of patterning the dielectric thin film element into the desired shape. 3. The step of forming a pattern of the first nitride layer, wherein the multilayer thin film includes an interlayer insulating film formed between the dielectric layer and the first nitride layer. Is
3. The method according to claim 2, further comprising patterning the interlayer insulating film. 4. A step of forming a diffusion barrier layer on a substrate; a step of forming a multilayer thin film including a lower electrode layer on the diffusion barrier layer; and forming the diffusion barrier layer on the multilayer thin film. Forming a pattern of an oxidizable first nitride layer containing at least one of the constituent elements; and mixing the first nitride layer with an oxidizing gas using the first nitride layer pattern as a mask. A step of patterning the lower electrode layer into a desired shape by selectively etching the multilayer thin film using a gas; and a step of removing the pattern of the first nitride layer. Manufacturing method of a body thin film element. 5. The method of claim 4, wherein removing the pattern of the first nitride layer comprises patterning the diffusion barrier layer into the desired shape by selectively removing the diffusion barrier layer. A method for manufacturing a dielectric thin film element. 6. The method according to claim 2, wherein the first nitride layer has the same composition as the diffusion barrier layer. 7. The diffusion barrier layer is made of TaSiN, Hf.
The method according to claim 6, wherein the dielectric thin film element is formed of SiN, TiN, or TiAlN. 8. The method according to claim 2, wherein the first nitride layer has a thickness greater than that of the diffusion barrier layer. 9. A step of forming an upper electrode layer on the dielectric layer, and forming a pattern of a second nitride layer containing a metal element, which is oxidizable, on the upper electrode layer. And a step of patterning the upper electrode into a desired shape by selectively etching the upper electrode using a mixed gas containing an oxidizing gas using the pattern of the second nitride layer as a mask. The method for manufacturing a dielectric thin film device according to claim 1, further comprising: 10. The dielectric according to claim 1, wherein the first nitride layer contains, as a composition thereof, an element selected from a group including Ta, Hf, and Si. A method for manufacturing a thin film element. 11. The thickness of the first nitride layer is about 20
The method for manufacturing a dielectric thin film device according to claim 1, wherein the thickness is in a range of from 500 nm to 500 nm. 12. The step of forming a pattern of the first nitride layer includes the step of forming a first gas containing a halogen group element, a second gas containing a halogen group element, or the first gas and the second gas. The first gas is HCl, BCl ₃ , Cl ₂ , CCl ₄ ,
CH _x Cl _4-x , COCl ₂ , S ₂ Cl ₂ , PCl ₃ , CCl
_x Br _4-x, is selected from the group comprising NOCl and SiCl _4, the gas said _{second, CF 4, C 2 F 4} , CHF 3, C 2 F 6, C
_{3 F 8, C 4 F 10} , SF 6, S 2 F 2, CHFCl 2, Br
F ₃ , BrF _5, HBr, HF, BF ₃ , COF ₂ , NF ₃ ,
SiF ₄ , XeF ₂ , CF _x Cl _4-x , CHFCl ₂ , Cl
Selected from the group comprising F ₃ , BBr ₃ , CBr ₄ , CF _x Br _4-x , CHFBr ₂ and S ₂ Br ₂ (where x is an integer of 4 or less); The ratio is about 20% or more 5
The method for manufacturing a dielectric thin film device according to claim 1, wherein the content is 0% or less. 13. The oxidizing gas according to claim 1, wherein the oxidizing gas is at least one selected from the group including N ₂ O gas, O ₃ gas and O ₂ gas.
The method for manufacturing a dielectric thin film element according to claim 1, wherein the method includes a kind of gas. 14. The method according to claim 1, wherein a ratio of the oxidizing gas in the mixed gas is about 20% or more and 70% or less.
3. The method for manufacturing a dielectric thin film element according to any one of 3. 15. The method according to claim 1, wherein the mixed gas further contains a halogen gas or a compound gas containing a halogen group element.