JP3367600B2 - Method of manufacturing dielectric thin film element - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a dielectric thin film element used for a semiconductor device such as a semiconductor integrated circuit, and more particularly to a method for etching a refractory metal film and a dielectric thin film contained in the dielectric thin film element. Regarding

[0002]

2. Description of the Related Art In recent years, a ferroelectric non-volatile memory device using a ferroelectric film having spontaneous polarization for a capacitor has been actively developed. Further, devices such as DRAM using a high dielectric constant film as a memory capacitor have been developed. Oxide crystals are mainly used as a dielectric material such as a ferroelectric thin film or a high dielectric thin film used in these devices. Since a high-temperature oxygen atmosphere is required to form such a crystal film, a high melting point metal (Pt and Ir) resistant to the high-temperature oxygen atmosphere is used as a material for the electrodes used in the above electronic device. Etc.) or an oxide material having conductivity is used. Further, in order to manufacture a device using such a material as a refractory metal, an etching process for microfabrication is indispensable.

As fine processing of a refractory metal film, for example, in Pt etching, ion etching by Ar or reactive etching using chlorine gas has been conventionally performed. A resist film, a silicon oxide film, an Au film, or the like was used as a mask for etching.

Also, Extended Abstracts of the 1994 I
nternational Conference on SSDM, Yokohama, 1994, pp
According to 721-723, in etching Pt, SOG
Etching is performed with a mixed gas of chlorine and oxygen using a (Spin on Glass) mask. According to the Proceedings of the 58th Annual Meeting of the Society of Applied Physics, 2p-PA-19, a CVDSiO ₂ film with a thickness of 1 μm is used as a mask for etching Ir and IrO ₂ . In Japanese Patent Application No. 9-266200, Pt is etched with a mixed gas of chlorine and oxygen using the Ti film as a mask.

[0005]

When a ferroelectric or high dielectric material is used for a dielectric thin film element such as a capacitor,
In many cases, the electrodes of the element are formed of a high melting point metal or a high melting point metal compound. Therefore, there is a problem that etching is difficult, or the etching rate is slow even if etching is possible. With the conventional mask as described above, it has been difficult to perform microfabrication of an element including formation of electrodes with high accuracy. This will be described in more detail below.

When etching is performed using a resist mask as in the conventional case, the resist film thickness (about 2
500 nm) is required. Therefore, fine processing has been difficult. Even when a silicon oxide film mask such as an SOG mask is used, a thick mask is required because the selection ratio with respect to the dielectric, the refractory metal or the refractory metal compound is poor. Further, due to a reaction between the mask material or the material to be etched and the etching gas, deposits are generated on the side wall of the thick mask. This causes a decrease in processing accuracy and requires an extra process of removing the adhered matter.

In the case of a silicon oxide mask such as an SOG mask, the mask cannot be completely removed even in the mask removing step, and a residue is left. Further, if the etching selectivity between the underlying layer and the mask after etching is insufficient, it becomes difficult to remove only the mask. Even in the case of a metal mask made of Ti or the like, as in the case of the SOG mask, it is difficult to remove the mask by utilizing the difference in the etching rate between the underlying material and the mask material after etching. is there. Therefore, it is necessary to strictly narrow down the etching conditions.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a dielectric thin film including a layer made of a refractory metal or a refractory metal compound, which has a high precision and a simple process. An object of the present invention is to provide an element manufacturing method and a dielectric thin film element manufactured by the method.

[0009]

A method of manufacturing a dielectric thin film element according to the present invention comprises a step of forming a multi-layer thin film including a lower electrode layer on a substrate, and an oxidizing property on the multi-layer thin film. A step of forming a pattern of the first nitride layer containing a metal element, and using the mixed gas containing an oxidizing gas as a mask with the pattern of the first nitride layer as a mask, selectively forming the multilayer thin film. The multilayer thin film including the steps of patterning the lower electrode layer into a desired shape by etching and removing the pattern of the first nitride layer.
Is a dielectric layer formed on the lower electrode layer and the substrate,
A diffusion barrier layer formed between the lower electrode layer and
The diffusion barrier layer and the substrate and the dielectric layer.
Mutual diffusion of elements with the electric conductor layer is prevented, and the first nitrogen
The step of removing the pattern of the oxide layer is performed on the diffusion barrier layer.
To the desired shape by selectively removing
The method includes a heating step, whereby the above object is achieved.

In one embodiment, the first nitride layer contains, as its composition, an element selected from the group consisting of Ta, Hf and Si.

In one embodiment, the thickness of the first nitride layer is in the range of 20 to 500 nm.

[0012] In one embodiment, the step of forming the pattern of the first nitride layer includes the step of forming a first halogen group element-containing first layer.
Gas, a second gas containing a halogen group element, or a mixed gas of the first gas and the second gas is used as an etching gas, and the first gas is HCl, BCl ₃ , C
l ₂ , CCl ₄ , CH _x Cl _4-X , COCl ₂ , S ₂ Cl ₂ ,
_{PCl 3, CCl x Br 4-} x, from NOCl and SiCl ₄
And the second gas is CF ₄ , C
₂ F ₄ , CHF ₃ , C ₂ F ₆ , C ₃ F ₈ , C ₄ F ₁₀ , SF ₆ , S ₂
F ₂ , CHFCl ₂ , BrF ₃ , BrF 5, HBr, HF, B
F ₃ , COF ₂ , NF ₃ , SiF ₄ , XeF ₂ , CF _x Cl
_4-x , CHFCl ₂ , ClF ₃ , BBr ₃ , CBr ₄ , CF _x
Br _4-x , CHFBr ₂ and S ₂ Br ₂ (where x is an integer of 4 or less) selected from the group consisting of
The ratio of the gas is 20 % or more and 50% or less.

In one embodiment, the oxidizing gas is N 2.
_It contains at least one gas selected from the group consisting of ₂ O gas, O ₃ gas and O ₂ gas.

In one embodiment, a ratio of the oxidizing gas in the mixed gas is 20 % or more and 70% or less.

In one embodiment, a ratio of the oxidizing gas in the mixed gas is 20 % or more and 50% or less.

In one embodiment, the mixed gas further contains a halogen gas or a compound gas containing a halogen group element.

In one embodiment, the halogen gas or the compound gas containing a halogen group element is HC1, BC
_{1 3, Cl 2, CC1 4} , CH x Cl 4-x, COC1 2, S 2
Cl ₂ , PCl ₃ , CCl _x Br ₄ , NOCl, SiCl ₄ ,
CF ₄ , C ₂ F ₄ , CHF ₃ , C ₂ F ₆ , C ₃ F ₈ , C ₄ F ₁₀ ,
SF ₆ , S ₂ F ₂ , CHFCl ₂ , BrF ₃ , BrF ₅ , HB
r, HF, BF ₃ , COF ₂ , NF ₃ , SiF ₄ , Xe
F ₂ , CF _x Cl _4-x , CHFCl ₂ , ClF ₃ , BBr ₃ ,
It is selected from the group consisting of CBr ₄ , CF _x Br _4-x , CHFBr ₂ and S ₂ Br ₂ (where x is an integer of 4 or less).

[0018]

In one embodiment, the first nitride layer has the same composition as the diffusion barrier layer.

In one embodiment, the first nitride layer has a greater thickness than the diffusion barrier layer.

In one embodiment, a step of forming an upper electrode layer on the dielectric layer, and a pattern of a second nitride layer containing a metal element having an oxidizable property on the upper electrode layer. And a step of patterning the upper electrode into a desired shape by selectively etching the upper electrode with a mixed gas containing an oxidizing gas using the pattern of the second nitride layer as a mask. And are further included.

In one embodiment, the lower electrode layer is I
It is formed of a metal element selected from the group consisting of r, Pt, Ru, Rh, Os and Re.

In one embodiment, the upper electrode layer is I
It is formed of a metal element selected from the group consisting of r, Pt, Ru, Rh, Os and Re.

In one embodiment, a buffer layer is formed on the surface of the substrate.

In one embodiment, the buffer layer is T
It is formed of an element selected from the group consisting of i, Ta, Co, Ni, Hf, Mo and W, or a compound containing at least one thereof.

In one embodiment, the multilayer thin film includes an interlayer insulating film formed between the dielectric layer and the first nitride layer, and has a pattern of the first nitride layer. The step of forming includes patterning the interlayer insulating film.

Another method of manufacturing a dielectric thin film element according to the present invention is a step of forming a diffusion barrier layer on a substrate, and forming a multilayer thin film including a lower electrode layer and a dielectric layer on the diffusion barrier layer. And a step of forming, on the multilayer thin film, a pattern of a oxidizable first nitride layer containing at least one kind of an element constituting the diffusion barrier layer, and the first step. Patterning the lower electrode layer into a desired shape by selectively etching the multilayer thin film with a mixed gas containing an oxidizing gas using the pattern of the nitride layer as a mask. And removing the pattern of the nitride layer, thereby achieving the above object.

In one embodiment, the diffusion barrier layer is
It is formed of TaSiN, HfSiN, TiN or TiAlN.

In one embodiment, the ratio of the oxidizing gas in the mixed gas is 20 % or more and 70% or less.

The ferroelectric thin film element according to the present invention includes the dielectric thin film element manufactured by the above manufacturing method. The high dielectric thin film element according to the present invention includes the dielectric thin film element manufactured by the above manufacturing method. Further, the semiconductor device according to the present invention has the dielectric thin film element manufactured by the above manufacturing method, which is provided in the circuit portion of the integrated circuit on the integrated circuit wafer.

[0031]

BEST MODE FOR CARRYING OUT THE INVENTION The most basic features of the present invention will be described below with reference to FIG.

FIG. 1 shows a cross section of the essential part of the basic structure of a dielectric thin film element. This dielectric thin film element is used for the substrate 10
And a buffer layer (adhesion layer) formed on the surface of the substrate 10.
12, a diffusion barrier layer 22 on the buffer layer 12, a lower electrode layer 24, a dielectric layer 25, and an upper electrode layer 28. The buffer layer 12 is for preventing oxidation of the diffusion barrier layer 22 and improving adhesion with the substrate 10. The diffusion barrier layer 22 includes the substrate 10 and the dielectric layer 25.
It is for preventing mutual diffusion of elements between and.

In the present invention, as a mask used in an etching process for finely processing an electrode layer and the like, a nitride layer (first nitride layer and second nitride layer) containing a metal element, which is oxidizable, is used. Layer) is used. Using such a mask, only the electrode layer or the dielectric layer and the electrode layer are continuously etched. Since the mask made of such a nitride layer is oxidized by the mixed gas containing the oxidizing gas during the etching process, the etching resistance is significantly increased. Therefore, the oxidized mask is not etched. By using such a mask having high etching resistance, the thickness of the mask is set to 20 to 50.
Since the thickness can be reduced to about 0 nm, the problems associated with the conventional thick mask described above can be avoided. In addition, below, the above-mentioned nitride layer is also called an "etching resistant film".

Regarding the preferred thickness of the etching resistant film, the lower limit of 20 nm is the thinness that can exist as a film. When the thickness of the film is 20 nm or less, stripe-shaped grains grow on the film, and even if it becomes a film, it is affected by pinholes and the like, so that the above effect of the present invention cannot be obtained. On the other hand, the upper limit of 500 nm is
The thickness is such that peeling due to stress does not occur during film formation. When the thickness of the film is 500 nm or more, peeling or cracks due to the stress of the film may occur during the formation of the film. This may also prevent the above effects of the present invention from being obtained. Further, in consideration of the ease of film formation, the thickness of the etching resistant film is set to about 20 to 250.
nm is more preferable.

The etching resistant film is, for example, TaSiN or H.
It may be formed of a nitride such as fSiN, TiN or TiAlN. These compounds are easily oxidized by an oxidizing gas. In the specification of the present application, the fact that the etching resistant film is “easily oxidized” means that it is more easily oxidized than a noble metal such as Pt, Au, or Ir, and easily oxidized even compared with Si. Means that. An element such as Si is hardly oxidized at normal temperature and is oxidized in high temperature oxygen (for example, a temperature of about 600 ° C. or higher), but its progress is slow and the same is true in an oxygen plasma atmosphere. However, the etching resistant film of the present invention is easily oxidized under such conditions.

When the etching resistant film is formed of, for example, TaSiN, Ta is converted into Ta ₂ O ₅ by oxidation.
And a strong coating film of Ta ₂ O ₅ is formed on the surface of the TaSiN layer. This coating allows TaSiN to
It is not etched by the chemical action of the halogen gas. Ta ₂ O ₅ may be generated due to the sputtering action during the process.
Even if it disappears, new Ta is immediately oxidized to Ta ₂ O ₅ and TaSiN is prevented from being etched.

The mixed gas used for etching contains an oxidizing gas and a halogen gas. O ₂ , O _3, N ₂ O or the like is used as the oxidizing gas, and chlorine gas or the like is used as the halogen gas.

Further, by forming the diffusion barrier layer 22 and the etching resistant film 40 with the same compound, the electrode layer,
Alternatively, the etching resistant film 40 can be removed simultaneously with the etching of the diffusion barrier layer 22 after the etching of the dielectric layer and the electrode layer is completed. When the diffusion barrier group and the etching resistant group are not formed of the same compound, after the etching of the electrode layer, or the dielectric layer and the electrode layer is completed, a gas that has a difference in etching rate from the underlying layer is used to resist the etching. The etching film 40 is removed.

The ferroelectric element of the present invention includes a ferroelectric capacitor, and further includes one mounted on a wafer for an integrated circuit as a part of the components of the semiconductor device.
In addition, the forming method of the present invention, the capacity portion of the non-volatile memory,
Alternatively, it can be applied to manufacture of a dielectric thin film element included in a gate portion of an FET (field effect transistor), and includes an MFMIS-FET (Metal Ferrite) including a source / drain region.
oelectric Metal Insulator Semiconductor FET)), M
FS-FET (Metal Ferroelectric Semiconductor FE
It can also be used as a method for forming a thin film element such as T).

Embodiments of the present invention will be described in detail below with reference to the drawings.

(First Embodiment) FIGS. 2A to 2E.
1 shows a first embodiment of a method for manufacturing a dielectric thin film element according to the present invention. In this embodiment, an etching method for patterning the lower electrode layer 24 will be described.

First, as shown in FIG. 2A, a silicon oxide film 11 having a thickness of about 600 nm is formed on the surface of the silicon substrate 10 by the CVD method. Next, the diffusion barrier layer 22 is formed by depositing an amorphous tantalum silicon nitride (TaSiN) layer with a film thickness of about 100 nm by DC magnetron reactive sputtering.
After that, heat treatment is performed in a nitrogen atmosphere to stabilize the tantalum silicon nitride film. This heat treatment may not be necessary depending on the film forming conditions. The conditions for forming the tantalum silicon nitride film are as follows. The element target has an elemental molar ratio of Ta: Si = 10: 3 and a substrate temperature of about 5
The temperature is 00 ° C., the sputtering power is about 2000 W, the sputtering gas pressure is about 0.7 Pa, and the Ar / N ₂ flow rate ratio is about 3/2. Regarding the heat treatment conditions, the temperature rising rate in a pure nitrogen atmosphere is about 5 ° C./min, the holding temperature is about 600 ° C., and the holding time is about 1 hour.

Tantalum silli formed under the above conditions
Connitride film is Ta_0.85Si_0.15N _0.41Having a composition
And has an amorphous structure. These things are that
Confirmed by Auger spectroscopic analysis and X-ray diffraction analysis, respectively
It

Next, on the diffusion barrier layer 22 made of a tantalum silicon nitride film, by a DC magnetron sputtering method,
An iridium (Ir) layer (thickness, about 150 nm) is formed as the lower electrode layer 24. The formation conditions are DC power 0.
The temperature is 5 kW, the substrate temperature is 500 ° C., and the gas pressure is 0.6 Pa.
Only Ar gas is used as the sputtering gas. After that, as the etching resistant film 40, a tantalum silicon nitride layer (film thickness, about 120 n) having the same composition as the diffusion barrier layer 22 is formed.
m) is formed in the same way as for the diffusion barrier layer 22. Further, a resist pattern 50 having a film thickness of 1 μm is formed on the etching resistant film 40 and is patterned into a corner of about 800 to 2500 nm by a normal photolithography technique.

As described above, the structure shown in FIG. 2A is obtained. A layered structure including the diffusion barrier layer 22 and the lower electrode layer 24 is referred to as a “multilayer thin film”.

An etching method for patterning the etching resistant film 40 and the lower electrode layer 24 will be described below. Etching is performed using an ECR (electron cyclotron resonance) plasma etching apparatus as shown in FIG. This device includes a solenoid coil 80 and a wafer 8.
1, electrode 82, O ₂ gas inlet 83, halogen gas inlet 84, 2.45 GHz microwave 88 and 13.56
It is constituted by a high frequency 89 of MHz. As basic conditions for etching, the pressure is about 1.4 mTorr and the microwave output is about 1000 W.

First, as shown in FIG. 2B, TaSi
The N-resistant etching film 40 is replaced with the resist pattern 50.
Approximately 50 SCCM of chlorine gas, RFPow as a mask
Patterning into a desired shape is performed by etching at about 100 W. The etching gas at this time is not limited to chlorine gas, and if a silicon-based residue remains, a fluorine-based halogen gas or a mixed gas thereof may be used.

After that, as shown in FIG. 2C, the resist pattern 50 is removed. For removing the resist pattern 50, ashing using ozone or a stripping agent can be used.

Then, as shown in FIG. 2D, the lower electrode layer 24, which is an Ir film, is patterned into a desired shape by etching using the etching resistant film 40 as a mask. As the etching gas at this time, chlorine gas (Cl ₂ ) was used as a halogen gas, oxygen (O ₂ ) was used as an oxidizing gas, and the gas flow rate was Cl ₂ / O ₂ = 64/16.
It is set to about SCCM. RFPower is about 10
It is set to 0W. The relationship between the flow rate ratio of the etching gas and the etching rates of the Ir film (lower electrode layer 24) and the TaSiN layer (the etching resistant film 40 and the diffusion barrier layer 22) is shown in FIG. 4 (square marks indicate the Ir film 24). data from,
The circle mark is the data of the TaSiN layer 40). As shown in FIG. 4, when the oxygen flow rate is about 20% or more of the total flow rate, TaS
The etching rate of the iN layer is reduced to about 8 nm / min, and the progress of the etching of the TaSiN layer is substantially stopped. The reason why the progress of etching is stopped is that the TaSiN film is oxidized by oxygen gas, and as a result, the etching resistance is improved. Such oxidized TaSiN film (anti-etching film 40 'and the diffusion barrier layer 22') is constituted by a TaSiN layer protected by a thin Ta ₂ O ₅ film.

From the results of FIG. 4, as the etching gas,
It is necessary to perform etching at an oxygen flow rate of about 20% or more. Further, when the oxygen flow rate is about 80% or more of the total flow rate, the etching rate of the Ir film decreases, so the oxygen flow rate is preferably about 70% or less of the total flow rate.

Next, etching for removing the etching resistant film 40 'and patterning the diffusion barrier layer 22' is performed at the same time. In this embodiment, the etching conditions are chlorine of about 50 SCCM and RF power of about 100 W in this embodiment.
Is. The etching gas is not limited to chlorine, and a fluorine-based halogen gas or a mixed gas thereof may be used. Etching resistant film 40 'and diffusion barrier layer 2
Since 2'has the same composition, the etching resistant film 40 '
And the selective etching of the diffusion barrier layer 22 'proceed simultaneously. Therefore, it is not necessary to set the etching conditions in consideration of the difference in the etching rates of these layers, and the etching becomes simple.

In this embodiment, Ir is used as the metal forming the electrode layer, but Pt, Rh, Os, Rc or Ru is used.
You may use metals, such as. All of these metals are
Used as a material for electrodes in high-dielectric and ferroelectric devices.

Further, in the above description, the lower electrode layer 24 is omitted.
Cl as a gas for etching₂Chlorine gas and O₂To
However, the present invention is not limited to this.
I can't. HCl, BCl as chlorine-based gas₃, Cl₂, C
Cl_Four, CH_xCl_4-x, COCl₂, S₂Cl₂, PC
l₃, CCl_xBr_4-x, NOCl, SiCl_FourEtc.
CF as gas_Four,C₂F_Four, CHF₃, C₂F₆, C₃F
₈, C_FourF_Ten,SF₆, S ₂F₂, CHFCl₂, BrF₃, B
rF_Five, HBr, HF, BF₃, COF_2,NF₃, Si
F_Four, XeF₂, CF_xCl_4-x, CHFCl₂, ClF₃,
BBr₃, CBr_Four, CF_xBr_4-x, CHFBr₂, S₂B
r₂Etc. (however, x is an integer of 4 or less), O as the oxidizing gas₂
And O₃And N₂Using a gas such as O or a mixed gas of them
Dry etching may be performed.

[0054] Further, as the etching resistant film 40 and the diffusion barrier layer 22 in this embodiment uses the Ta _{0. 85} Si _0.15 N _0.41 layer, which is different from the composition ratio of TaSiN or HrSiN, TiN, oxides such as TiA1N, A membrane that is easy to handle may be used. It is not necessary to limit the composition of these compounds in consideration of the effect of etching, and any composition can be etched by the etching method of the present invention. However, in consideration of electrical characteristics or heat resistance, when the diffusion barrier layer 22 is, for example, a Ta _x Si _1-x N _y film, 0.75 <x <0.95 and 0.3 <y <0.5 are satisfied. The range is more preferable.

When removing the mask (etching resistant film 40) formed of TaSiN, HfSiN, TiN or TiAlN and etching the diffusion barrier layer,
HCl, BCl ₃ , Cl ₂ , CCl ₄ , CH _x Cl _4-x , C
OCl ₂ , S ₂ Cl ₂ , PCl ₃ , CCl _x Br _4-x , NOC
1, SiCl ₄ , CF ₄ , C ₂ F ₄ , CHF ₃ , C ₂ F ₆ , C _{3
F 8, C 4 F 10,} SF 6, S 2 F 2, CHFCl 2, BrF 3,
BrF ₅ , HBr, HF, BF ₃ , COF ₂ , NF ₃ , Si
F ₄ , XeF ₂ , CF _x Cl _4-x , CHFCl ₂ , ClF ₃ ,
Etching is completed by using at least one gas selected from the group including BBr ₃ , CBr ₄ , CF _x Br _4-x , CHFBr ₂ and S ₂ Br ₂ (where x is an integer of 4 or less). can do. Furthermore, when using these oxidizable nitrogen compounds as a mask, O ₂ , O ₃ and N _{2 are used.}
An oxidizing gas such as O is added to a halogen gas or a halogenated gas to perform etching, and oxygen is added to a total amount of 20
% Or more may be added.

The substrate 10 is not particularly limited to a silicon substrate as long as it can be used as a substrate for semiconductor devices, integrated circuits, etc.
compound semiconductor substrate such as s, oxide crystal substrate such as MgO,
It can be selected according to the type of element to be formed, application, etc., such as a glass substrate. Of the above substrates, silicon substrates are most preferred.

Further, between the silicon oxide film 11 and the diffusion barrier layer 22, a compound containing one or more elements selected from the group containing Ti, Ta, Co, Ni, Hf, Mo, and W was formed. A buffer layer (adhesion layer) may be formed.

The above-mentioned buffer layer and diffusion barrier layer 2
The structure including 2 and the lower electrode layer 24 is referred to as a lower electrode structure. In the present specification, the lower electrode structure means a part of the dielectric element, that is, a capacitor electrode. The lower electrode structure may be formed directly on the substrate by a known method such as a sputtering method or a vapor deposition method, or may be provided with an insulating film, a lower layer wiring, a desired element, an interlayer insulating film, or the like or a plurality of these. It may be formed on the substrate.

Compared with the case of the conventional resist or silicon oxide film mask, the electrode processed by etching as described above has a very thin mask and there is no residue attached to the side wall. Loading is also greatly reduced.

The patterning accuracy of the electrode depends on the accuracy of the TaSiN mask, and the accuracy of the TaSiN mask depends on the accuracy of the resist pattern for forming it. Since the resist pattern is for forming only the TaSiN mask, the film thickness of the resist itself can be reduced. Therefore, in order to improve the depth of focus and the resolution, miniaturization can be easily performed as compared with the case of using a conventional thick resist.

Further, the etching resistant film 40 as a mask
By making the composition of the underlying diffusion barrier layer 22 the same,
The mask removal and the diffusion barrier layer etching can be performed simultaneously. This means that conventional SOG and CVD SiO
_2. Unlike the case of the Ti mask and the like, it is not necessary to consider the selection ratio between the mask and the base, so that the mask can be easily removed. For these reasons, the method of the present invention enables highly accurate etching for forming a fine capacitor.

(Second Embodiment) In the first embodiment, the multilayer thin film 20 to be etched includes only the lower electrode layer 24, but in the second embodiment, the multilayer thin film including the dielectric layer is etched. Will be described.

First, as shown in FIG. 5A, a silicon oxide film 11 having a thickness of about 600 nm is formed on the surface of the silicon substrate 10 by the CVD method. Next, the diffusion barrier layer 22 is formed by depositing an amorphous tantalum silicon nitride (TaSiN) layer with a film thickness of about 100 nm by DC magnetron reactive sputtering.
After that, heat treatment is performed in a nitrogen atmosphere to stabilize the tantalum silicon nitride film. Next, an iridium (Ir) layer is formed as the lower electrode layer 24 on the diffusion barrier layer 22 by the DC magnetron sputtering method. Diffusion barrier layer 2
2 and the film formation conditions of the lower electrode layer 24 and the heat treatment conditions are
It is similar to the first embodiment.

Next, a dielectric layer 25 is formed on the lower electrode layer 24 by using SrBi ₂ Ta ₂ O ₉ (SBT) which is a ferroelectric substance.
To form. As a forming method, the following spin-on method is used. First, a precursor solution in which constituent elements are dispersed in a solvent is prepared, and the precursor solution is applied to a substrate using a spinner at a rotation speed of 3000 rpm. In the atmosphere 1
After drying at 50 ° C. for 10 minutes, pre-baking is performed at 400 ° C. for 30 minutes in the air. Then, crystallization was performed at 700 ° C. for 1 hour. These steps are repeated three times to form the SBT thin film as the dielectric layer 25 to a thickness of about 200 nm.

Next, on the dielectric layer 25 (SBT thin film),
50 between interlayer insulation film (NSG) 27 made of silicon oxide film
about nm. CVD is used to form the interlayer insulating film 27.
Use the method. The interlayer insulating film 27 is provided to prevent the SBT surface from being directly exposed to plasma and being damaged when the mask is removed, thereby deteriorating the characteristics. In addition,
This layer may be omitted when the property recovery process is performed after etching. If the upper electrode is formed first, the interlayer insulating film 27 may be formed after forming the dielectric layer 25 and then forming the upper electrode thereon.

Then, in the same manner as in the first embodiment,
An etching resistant film 40 (tantalum silicon nitride layer) having the same composition as that of the diffusion barrier layer 22 is formed on the interlayer insulating film 27. Furthermore, a film thickness of 1 μm is formed on the etching resistant film 40.
Forming a resist pattern 50. As described above, the configuration shown in FIG. 5A is obtained. The multilayer thin film 20 is
The diffusion barrier layer 22, the lower electrode layer 24, the dielectric layer 25, and the interlayer insulating film 27 are included.

After that, as in the first embodiment, the etching resistant film 40 is patterned. At this time, FIG.
As shown in (b), the interlayer insulating film 27 is etched into the same shape as the etching resistant film 40. At this time, the interlayer insulating film 27 is etched using Cl ₂ gas and C ₂ F ₆ gas. Here, if the etching rate of the interlayer insulating film 27 is higher than that of the TaSiN layer 40, it causes film roughness.
As shown in FIG. 6, when the flow rate ratio of C ₂ F ₆ is about 50% or less with respect to the total flow rate, the etching rate of the TaSiN layer 40 becomes faster than that of the silicon oxide film (interlayer insulating film 27). However, when the flow rate ratio of C ₂ F ₆ is smaller than 30%, a residue is left. Therefore, it is preferable that the flow rate ratio of C ₂ F ₆ is about 30% or more and 50% or less.

Next, TaSiN film (etching resistant film) 4
SBT thin film 2 which is a dielectric layer 25 using a mask of 0
5, and the Ir film 24 that is the lower electrode layer 24 is etched.

As shown in FIG. 4, the etching rate of the SBT thin film 25 (marked with triangles) is such that the amount of oxygen added is 50% of the total flow rate.
It gradually decreases to a certain degree, and becomes sharply slower than that. Therefore, it is desirable that the flow rate of oxygen is about 20% or more and 50% or less with respect to the total flow rate during etching. In the present embodiment, the SBT thin film 25 and the Ir thin film 24
Are both Cl ₂ / O ₂ = 61/16 SCCM, RF =
The etching is performed under the condition of about 100 W, and the shape shown in FIG. In this etching process, the TaSiN film is oxidized by oxygen gas, and as a result, the etching resistance is improved. Such oxidized TaSiN film (anti-etching film 40 'and the diffusion barrier layer 22') is constituted by a TaSiN layer protected by a thin Ta ₂ O ₅ film.

Next, as shown in FIG. 5D, the etching resistant film 40 'and the underlying diffusion barrier layer 22' are simultaneously etched. The etching conditions at this time are Cl ₂ / O ₂ = 61/16 SCCM, as in the first embodiment.
It was performed at RF = about 100 W. The etching gas at this time is not limited to chlorine, and a fluorine-based halogen gas or a mixed gas thereof may be used.

The dielectric layer 25 will be described in more detail below. As the dielectric layer 25, a Bi-based ferroelectric (S
A ferroelectric thin film such as rBi _2, Ta ₂ O ₉ , Bi ₄ Ti ₃ O ₁₂ ) or an oxide ferroelectric PZT (lead zirconate titanate) can be used.

[0072] When the Bi-based ferroelectric, strong ferroelectric thin film is not particularly limited as long as it is a dielectric having a layered perovskite _{structure, Bi 2 A m-1 B} m O 3m + 3 (A Is Na, K, Pb, Ca, S
r, Ba or Bi; B is preferably a ferroelectric material represented by Fe, Ti, Nb, Ta, W or Mo), and more preferably a compound in which m is a natural number. Specifically, Bi ₄ Ti ₃ O _12,
SrBi ₂ Ta ₂ O ₉ , SrBi ₂ Nb ₂ O ₉ , BaBi ₂ N
b ₂ O ₉ , BaBi ₂ Ta ₂ O ₉ , PbBi ₂ Nb ₂ O ₉ , Pb
Bi ₂ Ta ₂ O ₉ , PbBi ₄ Ti ₄ O _15, SrBi ₄ Ti ₄ O
_15, Sr ₂ Bi ₄ Ti ₄ O ₁₅ , Pb ₂ Bi ₄ Ti ₄ O ₁₅ , Sr ₂
Bi ₄ Ti ₄ O ₁₈ , Ba ₂ Bi ₄ Ti ₅ O ₁₈ , Pb ₂ Bi ₄ T
i ₅ O ₁₈ , Na _0.5 Bi _4.5 Ti ₄ O _15, K _0.5 Bi _4.5 Ti ₄
O ₁₅ , Sr ₂ Bi ₄ Ti ₅ O ₁₈ , Ba ₂ Bi ₄ Ti ₅ O ₁₈ , P
b ₂ Bi ₄ Ti ₅ O _{18 and the} like, among which SrBi ₂ Ta
₂ O ₉ is preferred.

The ferroelectric thin film as described above can be formed by a known method such as spin-on method, reactive vapor deposition method, EB vapor deposition method, sputtering method, laser ablation method and the like. For example, in the spin-on method, generally, a raw material containing a part or all of the elements constituting the above thin film is dispersed in an organic solvent, which is applied onto the electrode layer by a spinner and dried. After that, the carbon component existing in the film is removed by sintering (temporary sintering),
After that, firing is performed in a gas containing oxygen or an oxygen compound for crystallization to form a ferroelectric thin film.

In this embodiment, Ir is used as the metal forming the electrode layer, but Pt, Rh, Os, Rc or Ru is used.
You may use metals, such as. All of these metals are
Used as a material for electrodes in high-dielectric and ferroelectric devices.

In the above description, chlorine gas of Cl ₂ and oxidizing gas of O ₂ are used as the gas for etching the lower electrode layer 24 and the dielectric layer 25, but the present invention is not limited to this. HCl as chlorine-based gas,
BCl ₃ , Cl ₂ , CCl ₄ , CH _x Cl _4-x , COCl ₂ ,
S ₂ Cl ₂ , PCl ₃ , CCl _x Br _4-x , NOCl, Si
Cl _4, etc., CF _4, C ₂ F ₄ , CH as halogenated gas
_{F 3, C 2 F 6,} C 3 F 8, C 4 F 10, SF 6, S 2 F 2, CHF
Cl ₂ , BrF ₃ , BrF ₅ , HBr, HF, BF ₃ , CO
F _2, NF ₃ , SiF ₄ , XeF ₂ , CF _x Cl _4-x , CHF
Cl ₂ , ClF ₃ , BBr ₃ , CBr ₄ , CF _x Br _4-x , C
Dry etching may be performed using HFBr ₂ , S ₂ Br ₂ or the like (where x is an integer of 4 or less), a gas such as O ₂ or O ₃ or N ₂ O, or a mixed gas thereof as the oxidizing gas. .

As the etching resistant film 40 and the diffusion barrier layer 22, in addition to TaSiN, HrSiN and Ti are used.
A film that easily oxidizes such as N or TiA1N may be used.
It is not necessary to limit the composition of these compounds in consideration of the effect of etching, and any composition can be etched by the etching method of the present invention. However, in consideration of the electrical characteristics or heat resistance, the diffusion barrier layer 22 is, for example, 0.7 in the case of a Ta _x Si _1-x N _y film.
More preferably, it is in the range of 5 <x <0.95 and 0.3 <y <0.5.

When removing the mask (etching resistant film 40) formed of TaSiN, HfSiN, TiN or TiAlN and etching the diffusion barrier layer,
HCl, BCl ₃ , Cl ₂ , CCl ₄ , CH _x Cl _4-x , C
OCl ₂ , S ₂ Cl ₂ , PCl ₃ , CCl _x Br _4-x , NOC
1, SiCl ₄ , CF ₄ , C ₂ F ₄ , CHF ₃ , C ₂ F ₆ , C _{3
F 8, C 4 F 10,} SF 6, S 2 F 2, CHFCl 2, BrF 3,
BrF ₅ , HBr, HF, BF ₃ , COF ₂ , NF ₃ , Si
F ₄ , XeF ₂ , CF _x Cl _4-x , CHFCl ₂ , ClF ₃ ,
Etching is completed by using at least one gas selected from the group including BBr ₃ , CBr ₄ , CF _x Br _4-x , CHFBr ₂ and S ₂ Br ₂ (where x is an integer of 4 or less). can do. Furthermore, when using these oxidizable nitrogen compounds as a mask, O ₂ , O ₃ and N _{2 are used.}
Oxidizing gas such as O is added to halogen gas or halogenated gas for etching, and oxygen is added to about 2% of the total amount, for example.
It may be added at 0% or more.

Further, between the silicon oxide film 11 and the diffusion barrier layer 22, a compound containing one or more elements selected from the group containing Ti, Ta, Co, Ni, Hf, Mo, and W was formed. The buffer layer (adhesion layer) may be formed as in the case of the first embodiment.

As described above, according to the present invention, highly precise etching for forming a fine capacitor can be performed.

(Third Embodiment) Below, FIG.
A third embodiment of the method for manufacturing a dielectric thin film element of the present invention will be described with reference to (d). In the above-described second embodiment, the upper surface of the dielectric layer 25 is covered with the interlayer insulation film 27 (FIG. 5 (d)). In the present embodiment, the dielectric layer has a structure in which not only the upper surface but also the side surfaces thereof are covered with the interlayer insulating film.

First, as shown in FIG. 7A, a silicon oxide film 11 having a thickness of about 600 nm is formed on the surface of the silicon substrate 10 by the CVD method. Next, the diffusion barrier layer 22 is formed by depositing an amorphous tantalum silicon nitride (TaSiN) layer with a film thickness of about 100 nm by DC magnetron reactive sputtering.
After that, heat treatment is performed in a nitrogen atmosphere to stabilize the tantalum silicon nitride film. Next, an iridium (Ir) layer is formed as the lower electrode layer 24 on the diffusion barrier layer 22 by the DC magnetron sputtering method. Diffusion barrier layer 2
2 and the film formation conditions of the lower electrode layer 24 and the heat treatment conditions are
It is similar to the first embodiment.

Next, a dielectric layer 32 is formed on the lower electrode layer 24 by using SrBi ₂ Ta ₂ O ₉ (SBT) which is a ferroelectric substance.
5 (thickness, about 200 nm) is formed. The formation method is
The spin-on method is used as in the second embodiment. After that, the dielectric layer 325 is processed into a desired capacitor size by dry etching using a resist or the TaSiN layer 40 described above (FIG. 7A). Then R
TA (Rapid Thermal annealin
Using the method g), the damage due to the etching of the dielectric layer 325 is recovered by heat treatment at about 700 ° C. for about 30 seconds.

After that, an interlayer insulating film 327 is formed, and reflow of the interlayer insulating film 327 or CMP (Chemical Mech) is performed.
The surface is flattened by anical polishing. This surface flattening is for improving the processing accuracy of the TaSiN mask formed on the upper surface, and if the sufficient processing accuracy is obtained, the flattening step is not necessary.

Next, a TaSiN layer (etching resistant film) 40 serving as an etching mask is formed on the interlayer insulating film 327.
It is formed under the same conditions as the diffusion barrier layer 22. Furthermore, the first embodiment
Similarly to 2 and 2, a resist pattern 50 is formed on the etching resistant film 40, and the TaSiN layer 40 and the interlayer insulating film 327 are etched (FIG. (B)). For etching the etching resistant film 40 and the interlayer insulating film 327, Cl ₂ / O ₂ = 61/16 SCCM as a gas system and RF = 1
Perform at about 00W. By setting the flow rates of the chlorine-based gas and the fluorine-based gas to be equal, the etching resistant film 40 and the interlayer insulation film 3
The etch rates of 27 are almost the same.

Next, as shown in FIG. 7C, the lower electrode layer 24 is formed by using the TaSiN layer 40 formed as described above.
The etching of the Ir layer is performed in the same manner as in the first and second embodiments. In this step, the exposed surface of the etching resistant film 40 and the diffusion barrier layer 22 is oxidized by the oxidizing gas, and the etching resistant film 40 ′ and the diffusion barrier layer 22 ′ are formed.
become. Finally, as shown in FIG.
In the same manner as in Steps 2 and 2, the etching resistant film 40 ′ was removed and the underlying diffusion barrier layer 22 ′ was patterned at the same time.

In this embodiment, Ir is used as the metal forming the electrode layer, but Pt, Rh, Os, Rc or Ru is used.
You may use metals, such as. All of these metals are
Used as a material for electrodes in high-dielectric and ferroelectric devices.

In the above description, the lower electrode layer 24 and
Cl is used as a gas for etching the dielectric layer 325.₂To
By chlorine gas and O₂I used an oxidizing gas according to
The invention is not limited to this. HC as chlorine-based gas
l, BCl₃, Cl₂, CCl_Four, CH_xCl_4-x, COC
l₂, S₂Cl₂, PCl₃, CCl_XBr_4-x, NOCl,
SiCl_FourCF as halogenated gas_Four,C₂F_Four, C
HF₃, C₂F₆, C₃F₈, C _FourF_Ten,SF₆, S₂F₂, CH
FCl₂, BrF₃, BrF_Five, HBr, HF, BF₃, C
OF_2,NF₃, SiF_Four, XeF₂, CF_xCl_4-x, CH
FCl₂, ClF₃, BBr₃, CBr_Four, CF_xBr_4-x,
CHFBr₂, S₂Br₂Etc. (however, x is an integer of 4 or less),
O as oxidizing gas₂And O₃And N₂Gas such as O, or
Dry etching may be performed using these mixed gases.
Yes.

As the etching resistant film 40 and the diffusion barrier layer 22, in addition to TaSiN, HfSiN and Ti are used.
A film that easily oxidizes such as N or TiAlN may be used.
It is not necessary to limit the composition of these compounds in consideration of the effect of etching, and any composition can be etched by the etching method of the present invention. However, in consideration of the electrical characteristics or heat resistance, the diffusion barrier layer 22 is, for example, 0.7 in the case of a Ta _x Si _1-x N _y film.
More preferably, it is in the range of 5 <x <0.95 and 0.3 <y <0.5.

When removing the mask (etching resistant film 40) formed of TaSiN, HfSiN, TiN or TiAlN and etching the diffusion barrier layer,
HCl, BCl ₃ , Cl ₂ , CCl ₄ , CH _x Cl _4-x , C
OCl ₂ , S ₂ Cl ₂ , PCl ₃ , CCl _x Br _4-x , NOC
1, SiCl ₄ , CF ₄ , C ₂ F ₄ , CHF ₃ , C ₂ F ₆ , C _{3
F 8, C 4 F 10,} SF 6, S 2 F 2, CHFCl 2, BrF 3,
BrF ₅ , HBr, HF, BF ₃ , COF ₂ , NF ₃ , Si
F ₄ , XeF ₂ , CF _x Cl _4-x , CHFCl ₂ , ClF ₃ ,
Etching is completed by using at least one gas selected from the group including BBr ₃ , CBr ₄ , CF _x Br _4-x , CHFBr ₂ and S ₂ Br ₂ (where x is an integer of 4 or less). can do. Furthermore, when using these oxidizable nitrogen compounds as a mask, O ₂ , O ₃ and N _{2 are used.}
Oxidizing gas such as O is added to halogen gas or halogenated gas for etching, and oxygen is added to about 2% of the total amount, for example.
It may be added at 0% or more.

Further, between the silicon oxide film 11 and the diffusion barrier layer 22, a compound containing one or more elements selected from the group containing Ti, Ta, Co, Ni, Hf, Mo and W was formed. The buffer layer (adhesion layer) may be formed as in the case of the first embodiment.

In this way, the SBT layer, which is the dielectric layer 325, is processed into a desired shape in advance, and after the plasma damage is recovered, it is covered with the interlayer insulation film 327, so that the sidewall of the dielectric layer 325 can be removed in the subsequent process. It is possible to prevent plasma damage to the ferroelectric substance.

According to the present invention, a dielectric thin film element having good characteristics can be manufactured.

(Fourth Embodiment) Below, FIG.
A fourth embodiment of the method for manufacturing a dielectric thin film element of the present invention will be described with reference to (e). The dielectric thin film element according to this embodiment further includes an upper electrode layer as compared with the dielectric thin film element according to the third embodiment.

First, as shown in FIG. 8A, a silicon oxide film 11 having a thickness of about 600 nm is formed on the surface of the silicon substrate 10 by the CVD method. Next, the diffusion barrier layer 22 is formed by depositing an amorphous tantalum silicon nitride (TaSiN) layer with a film thickness of about 100 nm by DC magnetron reactive sputtering.
After that, heat treatment is performed in a nitrogen atmosphere to stabilize the tantalum silicon nitride film. This heat treatment can be omitted depending on the film forming conditions. Next, the diffusion barrier layer 22
On top of the lower electrode layer 2 by DC magnetron sputtering.
An iridium (Ir) layer is formed as 4. The film formation conditions and heat treatment conditions for the diffusion barrier layer 22 and the lower electrode layer 24 are the same as those in the first and second embodiments.

Next, a dielectric layer 25 is formed on the lower electrode layer 24 by using SrBi ₂ Ta ₂ O ₉ (SBT) which is a ferroelectric substance.
(Thickness, about 200 nm) is formed. As the forming method, a spin-on method is used as in the second embodiment. next,
An interlayer insulating film 27 and a TaSiN film as an etching resistant film 40 are formed on the dielectric layer 25. Further, a resist pattern 50 is formed on the etching resistant film 40. For the above steps, the same method as that of the second embodiment is used.

After that, as in the second embodiment, the resist pattern 50 is used to pattern the etching resistant film 40 and the interlayer insulating film 27, and the patterned etching resistant film 40 is used to dielectric layer 25. The lower electrode layer 24 is etched as in the second embodiment. Further, the etching resistant film 40 'is removed and the underlying diffusion barrier layer 22' is patterned at the same time, so that FIG.
The structure shown in is obtained.

Next, as shown in FIG. 8C, the interlayer insulating film 47 is covered with CV so as to cover the structure obtained as described above.
It is formed to about 700 nm by the D method. Further, the dielectric layer 25 in the interlayer insulation film 47 is formed by using a normal resist process.
A contact hole is formed in the upper region of.

Next, as shown in FIG. 8D, the upper electrode layer 28 is formed so as to cover the dielectric layer 25 and the interlayer insulation film 47.
To form. Ir is used for the upper electrode layer 28 in the present embodiment. Next, the etching resistant film 4 is formed on the upper electrode layer 28.
40 (second nitride layer) TaSiN film (thickness, 2
(About 0 to 500 nm) is formed by the same method as in Embodiments 1 and 2, and is used as a mask for processing the upper electrode layer 28.

Next, as shown in FIG. 8E, the upper electrode layer 28 is formed with Cl ₂ / O ₂ = 64/16 SCCM,
Selective etching is performed at RF = about 100 W. As can be seen from the results of the graphs of FIGS. 4 and 9 under this condition, the etching selection ratio between the upper electrode layer 28 (Ir film) and the interlayer insulation film 47 (silicon oxide film) is about 1.5,
The upper electrode layer 28 and the etching resistant film 440 (TaSiN
The selection ratio with the membrane is about 6 or more. By using the above etching conditions, it is possible to process the upper electrode layer 28 with good uniformity, and it is also possible to minimize the amount of overetching of the interlayer insulating film 47.

According to this embodiment, the etching resistant film 44 is formed.
Since the mask of 0 is very thin, there is no residue attached to the side wall, and the microloading is also greatly reduced. Further, the patterning accuracy is the TaSiN film (the etching resistant films 40 and 440) as in the previous embodiments.
The accuracy of the TaSiN film depends on the accuracy of the resist pattern for forming it. The resist pattern is for forming only the TaSiN film,
The film thickness of itself can be reduced. Therefore, in order to improve the depth of focus and the resolution, miniaturization can be easily performed as compared with the case of using a conventional thick resist. According to this embodiment, it is possible to perform highly accurate etching for forming a fine capacitor.

(Fifth Embodiment) Below, FIG.
Other methods of forming the dielectric thin film element of the present invention will be described with reference to (h).

First, as shown in FIG. 10A, a locos oxide film 516 having a film thickness of about 500 nm is formed on the surface of the silicon substrate 10 to form an element isolation region, and then a gate electrode 517 is formed. A select transistor including the source / drain regions 518 and the like is formed. After that, the first silicon oxide film 519 is formed as an interlayer insulating film by a CVD method to form 50
A film having a diameter of O. A contact hole of 5 μm is formed. Next, after filling the contact hole with polysilicon by the CVD method, the surface is flattened by the CMP method to form a polysilicon plug 520.

Next, as shown in FIG. 10B, an amorphous tantalum silicon nitride film (about 100 nm thick) is formed on the polysilicon plug 520 as a diffusion barrier layer 22 by a DC magnetron reactive sputtering method. TaS
iN film) is formed. Heat treatment is performed in a nitrogen atmosphere to stabilize the tantalum silicon nitride film. This heat treatment may not be necessary depending on the film forming conditions.

The TaSiN film used in this embodiment was formed under the following conditions: an alloy target having an elemental molar ratio of Ta: Si = 10: 3, a substrate temperature of 500 ° C., a sputtering power of 2000 W, and a sputtering gas pressure. 0.7 Pa, Ar flow rate / N ₂ flow rate ratio is 3/2. The heat treatment conditions are as follows: a temperature rising rate of 5 ° C./min and a holding temperature of 6 in a pure nitrogen atmosphere
The temperature is 00 ° C. and the holding time is 1 hour. The tantalum silicon nitride film formed under the above conditions was confirmed to have an amorphous structure by X-ray diffraction, and further, the composition ratio was confirmed to be Ta _0.85 Si _0.15 N _0.41 by Auger spectroscopy. .

An iridium layer is formed as the lower electrode layer 24 on the diffusion barrier layer 22 by the DC magnetron sputtering method.
DC power 0.5 kW, substrate temperature 500 ° C., gas pressure 0.
The film thickness was 6 nm and the film thickness was 150 nm. Sputter gas is A
Only r gas is used. Next, as shown in FIG.
A ferroelectric film SrBi ₂ which is a ferroelectric substance is formed on the substrate.
A Ta ₂ O ₉ thin film (SBT thin film) is formed. A spin-on method is used as the forming method. First, a precursor solution in which constituent elements are dispersed in a solvent is prepared, the precursor solution is applied to a substrate using a spinner at a rotation speed of 3000 rpm, and dried in air at 150 ° C. for 10 minutes.
Then, after calcination is performed in the air at 400 ° C. for 30 minutes, crystallization is performed at 700 ° C. for 1 hour. These steps are repeated 3 times to form an SBT thin film as the dielectric film 25.
about nm.

After that, as shown in FIG. 10D, a resist mask 550 is formed and patterned into 0.8 to 2.5 μm square by photolithography. Using the formed resist pattern, the dielectric film 25 is dry-etched using, for example, a halogen-based gas to pattern the dielectric layer 25 (FIG. 10E). After that, the resist mask 550 is removed.

Next, as shown in FIG. 10E, the same tantalum silicon nitride as the diffusion barrier layer 22 is formed on the patterned dielectric film 25 as an etching resistant film 540 by the same forming method as described above. A film thickness of 120 nm is formed. Further, a resist mask 50 having a film thickness of 1 μm is formed thereon, and is patterned into 0.8 to 2.5 μm square by photolithography. Further formed resist pattern 5
0, the etching resistant film 540 is patterned by performing etching with chlorine gas 50 SCCM and RFPower = 100 W, for example. The etching gas at this time is not limited to chlorine, and when a silicon-based residue remains, a fluorine-based halogen gas or a mixed gas thereof may be used. Then, the resist pattern 50 is removed.
For removal, ashing using ozone or a stripping agent is used.

Next, TaS which is the etching resistant film 540 is formed.
The etching of the Ir thin film that is the lower electrode layer 24 using the iN mask will be described. Etching
Using ECR plasma etching equipment, pressure 1.4mT
The following is performed under the condition that the orr and μ wave output is 1000 W.

First, as shown in FIG. 10F, the Ir thin film is etched. At this time, chlorine gas (C1 ₂ ) was used as the halogen gas and oxygen (0 ₂ ) was used as the oxidizing gas, and the gas flow ratio was C1 ₂ / O ₂ = 6.
Etching was performed at 4/16 SCCM and RFPower = 100W. As for the flow rate ratio of the etching gas at this time, the oxygen flow rate is 20% or more of the total flow rate as shown in FIG.
Considering that the progress of the etching of TaSiN (diffusion barrier layer 22) used as the mask (etching resistant film 540) and the base of Ir is stopped, it is necessary to perform the etching at an oxygen flow rate of 20% or more. Further, since the Ir etching rate decreases when the oxygen flow rate is 80% or more, the oxygen flow rate is preferably 70% or less of the total flow rate.

Next, as shown in FIG.
The iN mask and the underlying diffusion barrier layer TaSiN are etched at the same time. In this embodiment, the etching conditions are chlorine of 50 SCCM and RFPower = 1.
It is 00W. The etching gas at this time is not limited to chlorine, and a fluorine-based halogen gas or a mixed gas thereof may be used. During this etching, mask removal and diffusion barrier etching proceed simultaneously. Since the mask and the diffusion barrier are composed of the same element, it is not necessary to set the etching conditions in consideration of the difference in etch rate, and the diffusion barrier layer 22 can be easily etched and the mask 540 can be removed.

Next, as shown in FIG. 10H, after forming the second silicon oxide film 521, a contact hole is formed. After that, the upper electrode 28 is formed, and further the first aluminum lead electrode 522 is formed.

In this embodiment, Ir is used as the metal forming the electrode layer, but Pt, Rh, Os, Rc or Ru is used.
You may use metals, such as. All of these metals are
Used as a material for electrodes in high-dielectric and ferroelectric devices.

In the above description, chlorine gas of Cl ₂ and oxidizing gas of O ₂ are used as the gas for etching the lower electrode layer 24 and the dielectric layer 25, but the present invention is not limited to this. HCl as chlorine-based gas,
BCl ₃ , Cl ₂ , CCl ₄ , CH _x Cl _4-x , COCl ₂ ,
S ₂ Cl ₂ , PCl ₃ , CCl _x Br _4-x , NOCl, Si
Cl _4, etc., CF _4, C ₂ F ₄ , CH as halogenated gas
_{F 3, C 2 F 6,} C 3 F 8, C 4 F 10, SF 6, S 2 F 2, CHF
Cl ₂ , BrF ₃ , BrF ₅ , HBr, HF, BF ₃ , CO
F _2, NF ₃ , SiF ₄ , XeF ₂ , CF _x Cl _4-x , CHF
Cl ₂ , ClF ₃ , BBr ₃ , CBr ₄ , CF _x Br _4-x , C
Dry etching may be performed using HFBr ₂ , S ₂ Br ₂ or the like (where x is an integer of 4 or less), a gas such as O ₂ or O ₃ or N ₂ O, or a mixed gas thereof as the oxidizing gas. .

Further, the etching resistant film 540 and the diffusion burr are formed.
As the layer 22, in addition to TaSiN, HfSiN, Ti
A film that easily oxidizes such as N or TiAlN may be used.
The composition of these compounds takes into consideration the effect of etching.
It is not necessary to limit the present invention, and the present invention can be used in any composition.
Etching can be performed by the above etching method. However
However, considering the electrical characteristics or heat resistance, the diffusion barrier layer
22 is, for example, Ta _xSi_1-xN_yFor membranes, 0.7
If 5 <x <0.95 and 0.3 <y <0.5,
More preferable.

In addition, TaSiN, HfSiN, TiN or the like.
Or a mask formed of TiAlN (etching resistant film)
540) and etching the diffusion barrier layer 22
HCl, BCl₃, Cl₂, CCl_Four, CH_xCl
_4-x, COCl₂, S₂Cl₂, PCl₃, CCl_xB
r_4-x, NOCl, SiCl_Four, CF_Four, C₂F_Four, CH
F₃, C₂F₆, C₃F₈, C_FourF_Ten, SF_6,S₂F₂, CHF
Cl₂, BrF₃, BrF_Five, HBr, HF, BF₃, CO
F₂, NF₃, SiF_Four, XeF₂, CF_xCl_4-x, CHF
Cl₂, ClF₃, BBr₃, CBr_Four, CF_xBr_4-x, C
HFBr₂, And S₂Br ₂(However, x is an integer of 4 or less)
By using one or more gases selected from the group comprising
The etching can be completed. In addition, these
When using a oxidizable nitrogen compound as a mask
Is O₂And O₃And N₂Oxidizing gas such as O is halogen gas or
Is added to halogenated gas for etching,
About 20% or more of the total amount of oxygen may be added.

Further, between the silicon oxide film 519 and the diffusion barrier layer 22, a compound containing one or more elements selected from the group containing Ti, Ta, Co, Ni, Hf, Mo, and W was formed. A buffer layer (adhesion layer) may be formed.

Compared with the case where a conventional resist or silicon oxide film mask is used, the electrode processed and subjected to the above etching has a very small mask thickness, and there is no residue attached to the side wall. Loading is also greatly reduced.

The patterning accuracy depends on the TaSiN mask accuracy, and the TaSiN mask accuracy depends on the resist pattern accuracy for forming the TaSiN mask. Since the resist pattern is for forming only the TaSiN mask, the film thickness of the resist itself can be reduced. As a result, the depth of focus and the resolution are improved, so that miniaturization can be easily performed as compared with the case of using a conventional thick resist.

Further, by making the constituent elements of the mask and the underlying barrier layer the same, the mask can be removed and the diffusion barrier layer can be etched at the same time. This is the conventional S
Unlike the case of OG, CVD SiO ₂ , Ti mask, etc., it is not necessary to consider the selection ratio of the mask and the underlying layer, and therefore the mask can be easily removed. From these facts, the method of the present invention makes it possible to perform highly accurate etching for forming a fine capacitor and form a high-density dielectric element.

(Sixth Embodiment) Below, FIG.
With reference to (g) to (g), another method for forming the dielectric thin film element of the present invention will be described.

First, as shown in FIG. 11A, a Locos oxide film 516 having a film thickness of about 500 nm is formed on the surface of the silicon substrate 10 to form an element isolation region, and then a gate electrode 517 is formed. A select transistor including the source / drain regions 518 and the like is formed. After that, the first silicon oxide film 519 is formed as an interlayer insulating film by a CVD method to form 50
A film having a thickness of about 0 nm is formed, and then a contact hole having a diameter of 0.5 μm is formed. Next, after filling the contact hole with polysilicon by the CVD method, the surface is flattened by the CMP method to form a polysilicon plug 520.

Next, as shown in FIG. 11B, an amorphous tantalum silicon nitride film (about 100 nm in thickness) is formed as a diffusion barrier layer 22 on the polysilicon plug 520 by the DC magnetron reactive sputtering method. TaS
iN film) is formed. Heat treatment is performed in a nitrogen atmosphere to stabilize the tantalum silicon nitride film. This heat treatment may not be necessary depending on the film forming conditions.

The TaSiN film used in this embodiment was formed under the following conditions: an alloy target having an elemental molar ratio of Ta: Si = 10: 3, a substrate temperature of 500 ° C., a sputtering power of 2000 W, and a sputtering gas pressure. 0.7 Pa, Ar flow rate / N ₂ flow rate ratio is 3/2. The heat treatment conditions are as follows: a temperature rising rate of 5 ° C./min and a holding temperature of 6 in a pure nitrogen atmosphere
The temperature is 00 ° C. and the holding time is 1 hour. The tantalum silicon nitride film formed under the above conditions was confirmed to have an amorphous structure by X-ray diffraction, and further, the composition ratio was confirmed to be Ta _0.85 Si _0.15 N _0.41 by Auger spectroscopy. .

An iridium layer is formed as the lower electrode layer 24 on the diffusion barrier layer 22 by the DC magnetron sputtering method.
DC power 0.5 kW, substrate temperature 500 ° C., gas pressure 0.
The film thickness was 6 nm and the film thickness was 150 nm. Sputter gas is A
Only r gas is used. Next, as shown in FIG.
SrBi, which is a ferroelectric substance, is formed on the substrate as a dielectric film 625.
_{A 2} Ta ₂ O ₉ thin film (SBT thin film) is formed. A spin-on method is used as the forming method. First, a precursor solution in which constituent elements are dispersed in a solvent is prepared, the precursor solution is applied to a substrate using a spinner at a rotation speed of 3000 rpm, and dried in air at 150 ° C. for 10 minutes.
Then, after calcination is performed in the air at 400 ° C. for 30 minutes, crystallization is performed at 700 ° C. for 1 hour. These steps are repeated three times, and the SBT thin film is used as the dielectric film 625.
The thickness is about 0 nm.

Further, on the dielectric film 625, the interlayer insulation film 2 is formed.
7 is formed to a thickness of about 50 nm by the CVD method. The interlayer insulating film 27 is provided to prevent the SBT surface from being directly exposed to plasma when the mask is removed, resulting in damage and deterioration of characteristics. Note that this layer may be omitted when the characteristic recovery process is performed after etching. If the upper electrode layer is formed first, the dielectric film 625 may be formed, and then the upper electrode may be formed on the dielectric film 625 and then the inter-layer insulating film 27 may be formed.

Next, a TaSiN film is formed as an etching resistant film 40 serving as a mask on the interlayer insulating film 27 under the same conditions as the diffusion barrier layer 22. A resist mask 550 is formed by the same method as in the fifth embodiment, and is patterned into 0.8 to 2.5 μm square by photolithography. The etching resistant film 40 is etched using the formed resist pattern. At this time, the interlayer insulating film 2
7 is also etched into the same shape. For etching the interlayer insulating film 27, Cl ₂ gas and C ₂ F ₆ gas are used. Here, the etching rate of the inter-layer insulating film 27 is TaSiN layer 4
If it is faster than 0, the film becomes rough. As shown in FIG. 6, when the flow rate ratio of C ₂ F ₆ is about 50% or less with respect to the total flow rate, the etching rate of the TaSiN layer 40 becomes faster than that of the silicon oxide film (interlayer insulating film 27). However, since the flow rate ratio of C ₂ F ₆ exits are left in the case of less than 20%, C ₂
The flow rate ratio of F ₆ is preferably about 20% or more and 50% or less.

After patterning the etching resistant film 40 and the interlayer insulating film 27, the resist pattern 550 is removed (FIG. 11D).

Next, TaSiN film (etching resistant film) 4
Using the mask of 0, the SBT thin film 625 that is the dielectric layer 625 and the Ir film 24 that is the lower electrode layer 24 are etched.

As shown in FIG. 4, the etch rate of the SBT thin film 25 gradually decreases until the amount of oxygen added is about 50% of the total flow rate, and becomes sharply slower than that. For that reason,
When etching, the oxygen flow rate is 20% of the total flow rate.
% Or more and 50% or less is desirable. In this embodiment, both the SBT thin film 625 and the Ir thin film 24 are C
Etching is performed under the conditions of l ₂ / O ₂ = 61/16 SCCM and RF = 100 W to obtain the shape shown in FIG. In this etching process, the TaSiN film is oxidized by oxygen gas, and as a result, the etching resistance is improved. The TaSiN film (the etching resistant film 40 ′ and the diffusion barrier layer 22 ′) thus oxidized is protected by the thin Ta ₂ O ₅ film.
It is composed of a SiN layer.

Next, as shown in FIG. 11F, the etching resistant film 40 'and the underlying diffusion barrier layer 22' are simultaneously etched. The etching conditions at this time are the same as in the fifth embodiment, with a Cl ₂ flow rate of about 50 SCCM and RF.
Power is about 100W. The etching gas at this time is not limited to chlorine, but a fluorine-based halogen gas,
Alternatively, a mixed gas thereof may be used.

Next, as shown in FIG. 11G, after forming the second silicon oxide film 521, a contact hole is formed. After that, the upper electrode 28 is formed, and further the first aluminum lead electrode 522 is formed.

In this embodiment, Ir is used as the metal forming the electrode layer, but Pt, Rh, Os, Rc or Ru is used.
You may use metals, such as. All of these metals are
Used as a material for electrodes in high-dielectric and ferroelectric devices.

In the above description, chlorine gas of Cl ₂ and oxidizing gas of O ₂ are used as the gas for etching the lower electrode layer 24 and the dielectric layer 25, but the present invention is not limited to this. HCl as chlorine-based gas,
BCl ₃ , Cl ₂ , CCl ₄ , CH _x Cl _4-x , COCl ₂ ,
S ₂ Cl ₂ , PCl ₃ , CCl _x Br _4-x , NOCl, Si
Cl _4, etc., CF _4, C ₂ F ₄ , CH as halogenated gas
_{F 3, C 2 F 6,} C 3 F 8, C 4 F 10, SF 6, S 2 F 2, CHF
Cl ₂ , BrF ₃ , BrF ₅ , HBr, HF, BF ₃ , CO
F _2, NF ₃ , SiF ₄ , XeF ₂ , CF _x Cl _4-x , CHF
Cl ₂ , ClF ₃ , BBr ₃ , CBr ₄ , CF _x Br _4-x , C
Dry etching may be performed using HFBr ₂ , S ₂ Br ₂ or the like (where x is an integer of 4 or less), a gas such as O ₂ or O ₃ or N ₂ O, or a mixed gas thereof as the oxidizing gas. .

As the etching resistant film 40 and the diffusion barrier layer 22, in addition to TaSiN, HfSiN and Ti are used.
A film that easily oxidizes such as N or TiAlN may be used.
It is not necessary to limit the composition of these compounds in consideration of the effect of etching, and any composition can be etched by the etching method of the present invention. However, in consideration of the electrical characteristics or heat resistance, the diffusion barrier layer 22 is, for example, 0.7 in the case of a Ta _x Si _1-x N _y film.
More preferably, it is in the range of 5 <x <0.95 and 0.3 <y <0.5.

In addition, TaSiN, HfSiN, TiN or the like.
Or a mask formed of TiAlN (etching resistant film)
540) and etching the diffusion barrier layer 22
HCl, BCl₃, Cl₂, CCl_Four, CH_xCl
_4-x, COCl₂, S₂Cl₂, PCl₃, CCl_xB
r_4-x, NOCl, SiCl_Four, CF_Four, C₂F_Four, CH
F₃, C₂F₆, C₃F₈, C_FourF_Ten, SF_6,S₂F₂, CHF
Cl₂, BrF₃, BrF_Five, HBr, HF, BF₃, CO
F₂, NF₃, SiF_Four, XeF₂, CF_xCl_4-x, CHF
Cl₂, ClF₃, BBr₃, CBr_Four, CF_xBr_4-x, C
HFBr₂, And S₂Br ₂(However, x is an integer of 4 or less)
By using one or more gases selected from the group comprising
The etching can be completed. In addition, these
When using a oxidizable nitrogen compound as a mask
Is O₂And O₃And N₂Oxidizing gas such as O is halogen gas or
Is added to halogenated gas for etching,
About 20% or more of the total amount of oxygen may be added.

Further, between the silicon oxide film 519 and the diffusion barrier layer 22, a compound containing one or more elements selected from the group containing Ti, Ta, Co, Ni, Hf, Mo, and W was formed. A buffer layer (adhesion layer) may be formed.

By using the above forming method, the fifth
The same effect as that of the above embodiment can be obtained. Further, the number of steps can be significantly reduced by etching the dielectric and the electrodes at once. From these facts, the method of the present patent makes it possible to perform highly accurate etching for forming a fine capacitor and form a high-density dielectric element.

(Seventh Embodiment) Below, FIG.
With reference to (h) to (h), still another method for forming the dielectric thin film element of the present invention will be described.

First, as shown in FIG. 12A, a locos oxide film 516 having a film thickness of about 500 nm is formed on the surface of the silicon substrate 10 to form an element isolation region, and then a gate electrode 517 is formed. A select transistor including the source / drain regions 518 and the like is formed. After that, the first silicon oxide film 519 is formed as an interlayer insulating film by a CVD method to form 50
A film having a thickness of about 0 nm is formed, and then a contact hole having a diameter of 0.5 μm is formed. Next, after filling the contact hole with polysilicon by the CVD method, the surface is flattened by the CMP method to form a polysilicon plug 520.

Next, as shown in FIG. 12 (b), an amorphous tantalum silicon nitride film (about 100 nm thick) is formed as a diffusion barrier layer 22 on the polysilicon plug 520 by the DC magnetron reactive sputtering method. TaS
iN film) is formed. Heat treatment is performed in a nitrogen atmosphere to stabilize the tantalum silicon nitride film. This heat treatment may not be necessary depending on the film forming conditions.

The film forming conditions for the TaSiN film used in this embodiment are: an alloy target having an elemental molar ratio of Ta: Si = 10: 3, a substrate temperature of 500 ° C., a sputtering power of 2000 W, and a sputtering gas pressure of 0.7 Pa, Ar flow rate / N ₂ flow rate ratio is 3/2. The heat treatment conditions are as follows: a temperature rising rate of 5 ° C./min and a holding temperature of 6 in a pure nitrogen atmosphere
The temperature is 00 ° C. and the holding time is 1 hour. The tantalum silicon nitride film formed under the above conditions was confirmed to have an amorphous structure by X-ray diffraction, and further, the composition ratio was confirmed to be Ta _0.85 Si _0.15 N _0.41 by Auger spectroscopy. .

An iridium layer is formed as the lower electrode layer 24 on the diffusion barrier layer 22 by the DC magnetron sputtering method.
DC power 0.5 kW, substrate temperature 500 ° C., gas pressure 0.
The film thickness was 6 nm and the film thickness was 150 nm. Sputter gas is A
Only r gas is used. Next, as shown in FIG.
As a dielectric film 725 on the substrate, SrBi which is a ferroelectric substance is used.
_{A 2} Ta ₂ O ₉ thin film (SBT thin film) is formed. As a forming method, a spin-on method is used on the substrate.

After that, as described in the fifth embodiment,
A resist mask is formed on the dielectric layer 725 and is patterned into 0.8 to 2.5 μm square by photolithography. Using the formed resist pattern, the dielectric film 725 is dry-etched using, for example, a halogen-based gas to pattern the dielectric layer 725 (FIG. 12C). After that, the resist mask is peeled off. After that, RTA (Rapid Thermal an
A heat treatment of 700 ° C. × 30 sec is applied by using the annealing method to recover the damage caused by the SBT etching.

Thereafter, as shown in FIG. 12D, an interlayer insulating film 727 is formed, and the surface of the interlayer insulating film 727 is flattened by reflow or CMP. This flattening of the surface is for improving the processing accuracy of the TaSiN mask formed on the upper surface, and if sufficient processing accuracy can be obtained,
It is not necessary to perform the flattening process.

Next, a TaSiN layer 40 serving as a mask is formed on the interlayer insulating film 727 under the same conditions as the diffusion barrier layer 22. Next, a resist mask 50 is formed, and TaSiN is used.
And the interlayer insulating film was etched (FIG. 12).
(E)). For etching the TaSiN layer and the interlayer insulating film, a gas system of C1 ₂ / C ₂ F ₆ = 40 / 40SCCM, R
FPpower = 100W. By setting the chlorine-based gas and the fluorine-based gas in the same amount, the etching rates of TaSiN and the interlayer insulating film become almost the same. After etching each film under the conditions, the resist mask 50 is removed.

Next, as shown in FIG. 12F, using the TaSiN mask 40 formed as described above, the Ir layer as the electrode layer 24 is etched in the same manner as in the fifth and sixth embodiments.

Next, as shown in FIG. 12G, the mask 40 and the underlying diffusion barrier layer 22 of TaSiN are simultaneously etched as in the fifth and sixth embodiments.

Next, as shown in FIG. 12H, after forming the second silicon oxide film 521, a contact hole is formed. After that, the upper electrode 28 is formed, and further the first aluminum lead electrode 522 is formed.

In this embodiment, Ir is used as the metal constituting the electrode layer, but Pt, Rh, Os, Rc or Ru is used.
You may use metals, such as. All of these metals are
Used as a material for electrodes in high-dielectric and ferroelectric devices.

In the above description, chlorine gas of Cl ₂ and oxidizing gas of O ₂ are used as the gas for etching the lower electrode layer 24 and the dielectric layer 25, but the present invention is not limited to this. HCl as chlorine-based gas,
BCl ₃ , Cl ₂ , CCl ₄ , CH _x Cl _4-x , COCl ₂ ,
S ₂ Cl ₂ , PCl ₃ , CCl _x Br _4-x , NOCl, Si
Cl _4, etc., CF _4, C ₂ F ₄ , CH as halogenated gas
_{F 3, C 2 F 6,} C 3 F 8, C 4 F 10, SF 6, S 2 F 2, CHF
Cl ₂ , BrF ₃ , BrF ₅ , HBr, HF, BF ₃ , CO
F _2, NF ₃ , SiF ₄ , XeF ₂ , CF _x Cl _4-x , CHF
Cl ₂ , ClF ₃ , BBr ₃ , CBr ₄ , CF _x Br _4-x , C
Dry etching may be performed using HFBr ₂ , S ₂ Br ₂ or the like (where x is an integer of 4 or less), a gas such as O ₂ or O ₃ or N ₂ O, or a mixed gas thereof as the oxidizing gas. .

As the etching resistant film 40 and the diffusion barrier layer 22, in addition to TaSiN, HfSiN and Ti are used.
A film that easily oxidizes such as N or TiAlN may be used.
It is not necessary to limit the composition of these compounds in consideration of the effect of etching, and any composition can be etched by the etching method of the present invention. However, in consideration of the electrical characteristics or heat resistance, the diffusion barrier layer 22 is, for example, 0.7 in the case of a Ta _x Si _1-x N _y film.
More preferably, it is in the range of 5 <x <0.95 and 0.3 <y <0.5.

Further, when removing the mask (etching resistant film 40) formed of TaSiN, HfSiN, TiN or TiAlN and etching the diffusion barrier layer 22, HCl, BCl ₃ , Cl ₂ , CCl ₄ , CH _x. C
l _4-x , COCl ₂ , S ₂ Cl ₂ , PCl ₃ , CCl _x Br
_4-x , NOCl, SiCl ₄ , CF ₄ , C ₂ F ₄ , CHF ₃ ,
C ₂ F ₆ , C ₃ F ₈ , C ₄ F ₁₀ , SF _6, S ₂ F ₂ , CHFC
l ₂ , BrF ₃ , BrF ₅ , HBr, HF, BF ₃ , COF
₂ , NF ₃ , SiF ₄ , XeF ₂ , CF _x Cl _4-x , CHFC
l ₂ , ClF ₃ , BBr ₃ , CBr ₄ , CF _x Br _4-x , CH
Etching can be completed by using one or more gases selected from the group including FBr ₂ and S ₂ Br ₂ (where x is an integer of 4 or less). Further, when using these oxidizable nitrogen compounds as a mask, an oxidizing gas such as O ₂ , O ₃ or N ₂ O is added to a halogen gas or a halogenated gas for etching, and for example, the total amount of oxygen is About 20% or more.

Further, between the silicon oxide film 519 and the diffusion barrier layer 22, a compound containing one or more elements selected from the group containing Ti, Ta, Co, Ni, Hf, Mo and W was formed. A buffer layer (adhesion layer) may be formed.

According to the method of this embodiment, the same effect as that of the previous embodiment can be obtained. Thus, by processing the SBT layer, which is a dielectric layer, in advance and recovering the plasma damage, and then covering with the interlayer insulating film, it is possible to reduce the plasma damage from the sidewall to the ferroelectric in the subsequent process. From these facts, the method of the present invention makes it possible to form a highly accurately processed element included in a fine capacitor.

(Eighth Embodiment) FIG. 13A is shown below.
A method of forming the upper electrode layer 28 in the above embodiment will be described with reference to (d).

The structure of FIG. 11F is manufactured by the method of the sixth embodiment. Then, as shown in FIG.
A second silicon oxide film 521 is formed by the CVD method to have a thickness of about 700 nm. A contact hole is formed in the second silicon oxide film 521 so as to reach the dielectric layer 625.

Next, as shown in FIG. 13B, the upper electrode layer 28 is formed. Ir is used for the upper electrode layer 28 in the present embodiment. Next, on the upper electrode layer 28, a TaSiN mask (thickness 20 to 50) which is an etching resistant film 840 is formed.
0 nm) in the same manner as in the previous embodiment,
It is used as a mask for processing the upper electrode layer 28.

Next, as shown in FIG. 13C, the upper electrode layer 28 is formed with Cl ₂ / O ₂ = about 64/16 SCCM and RF =
Etching is performed at about 100W. As can be seen from the results of the graphs of FIGS. 4 and 9 under this condition, the upper electrode layer 28 (Ir film) and the interlayer insulating film 521 (silicon oxide film)
The etching selection ratio with respect to is about 1.5, and the upper electrode layer 2
8 and the etching resistant film 840 (TaSiN film) have a selection ratio of about 6 or more. By using the above etching conditions, the upper electrode layer 28 can be processed with good uniformity, and the amount of overetching of the interlayer insulating film 521 can be minimized. Next, the etching resistant film 84
Remove 0. Finally, as shown in FIG. 13D, the first aluminum electrode 522 is formed.

In this embodiment, since the mask 840 is very thin, there is no residue left on the side wall, and the microloading is greatly reduced. Further, as described in the previous embodiment, the patterning accuracy depends on the accuracy of the TaSiN film (etching resistant film 840), and
The accuracy of the film depends on the accuracy of the resist pattern for forming it. The resist pattern is for forming only the TaSiN film, and the film thickness of the resist pattern itself can be reduced. Therefore, in order to improve the depth of focus and the resolution, miniaturization can be easily performed as compared with the case of using a conventional thick resist. According to this embodiment, it is possible to perform highly accurate etching for forming a fine capacitor.

(Ninth Embodiment) A method of forming a ferroelectric memory cell according to the present invention will be described below with reference to FIG. The present embodiment is different from the fifth to eighth embodiments in the configuration of the upper electrode layer. As shown in FIG. 14, the upper electrode layer 928 is formed on the dielectric layer 25,
Through the contact hole in the silicon oxide film 521,
It is connected to the extraction electrode 922 on the silicon oxide film 521.

The method of forming each layer of the ferroelectric memory cell of this embodiment is basically the same as the method of the fifth to eighth embodiments. Below, the formation method is roughly demonstrated. First, a locos oxide film 516 having a thickness of about 500 nm is formed on the surface of the silicon substrate 10 to form an element isolation region. Next, the gate electrode 517 and the source / drain region 51
A select transistor including 8 etc. is formed. Then, a first silicon oxide film 519 is formed as an interlayer insulating film by a CVD method.
To a thickness of about 500 nm, and then a contact hole with a diameter of 0.5 μm is formed. Next, after filling the contact hole with polysilicon by the CVD method, the surface is flattened by the CMP method to form a polysilicon plug 520.

Next, on the polysilicon plug 520, D
The diffusion barrier layer 22 is formed by the C magnetron reactive sputtering method.
As an amorphous tantalum silicon nitride film (TaSiN film) with a film thickness of about 100 nm is formed. Heat treatment is performed in a nitrogen atmosphere to stabilize the tantalum silicon nitride film. This heat treatment may not be necessary depending on the film forming conditions. The TaSiN film is formed under the following conditions: an alloy target having an elemental molar ratio of Ta: Si = 10: 3.
Substrate temperature is 500 ° C., sputter power is 2000 W, sputter gas pressure is 0.7 Pa, Ar flow rate / N ₂ flow rate ratio is 3
/ 2. The heat treatment conditions are a temperature rising rate of 5 ° C./min, a holding temperature of 600 ° C., and a holding time of 1 hour in a pure nitrogen atmosphere.

An iridium layer is formed as the lower electrode layer 24 on the diffusion barrier layer 22 by the DC magnetron sputtering method.
DC power 0.5 kW, substrate temperature 500 ° C., gas pressure 0.
The film thickness was 6 nm and the film thickness was 150 nm. Sputter gas is A
Only r gas is used. Next, a SrBi ₂ Ta ₂ O ₉ thin film (SBT thin film), which is a ferroelectric substance, is formed as a dielectric film 25 on the substrate.
To form.

Then, by the DC magnetron sputtering method,
After forming the upper electrode 928 with a film thickness of about 50 nm, etching is performed by the electrode processing method according to the present invention. After the ferroelectric film 25 is etched, the lower electrode layer 24 and the diffusion barrier layer 22 are further etched by the method described above.

After that, a second silicon oxide film 521 is formed as an interlayer insulation film by the CVD method, a contact hole is formed, and an upper electrode 928 of the ferroelectric capacitor is formed.
An aluminum extraction electrode 922 connected to the above is formed by a DC magnetron sputtering method.

In the above embodiment, the MOD (Metal Organ) method is used as the dielectric film forming method in addition to the spin-on method.
Ic Deposition) method, vacuum deposition method, reactive magnetron sputtering method, MOCVD (organic metal CVD) method, or the like may be used. Although SBT is used as the dielectric thin film, SrBi ₂ Nb ₂ O is used as another ferroelectric thin film.
₉ , Bi ₄ Ti ₃ O ₁₂ , BaBi ₂ Nb ₂ O _9, BaBi ₂ Ta
₂ O _9, PbBi ₂ Nb ₂ O _9, PbBi ₂ Ta ₂ O _9, SrBi ₄
Ti ₃ O ₁₅ , PbBi ₄ Ta ₄ O ₁₅ , Na _0.5 Bi _4.5 Ti ₄
O ₁₅ , K _0.5 Bi _4.5 Ti ₄ O ₁₅ , Sr ₂ Bi ₄ Ti ₅ O ₁₈ ,
Ba ₂ Bi ₄ Ti ₅ O _18, Pb ₂ Bi ₄ Ti ₅ O _18, etc.,
As the high dielectric thin film, (Ba _x, Sr _1-x ) TiO ₃ or the like can be used. In addition to polysilicon, tungsten or the like may be used as the contact plug material.

By the etching method of the electrode layer etc. of the present invention,
High-precision processing is possible. According to the present invention, it is possible to manufacture a high density ferroelectric memory cell.

[0168]

EFFECTS OF THE INVENTION By using an etching resistant film which is easily oxidized as a mask for selectively etching an electrode layer or the like, the mask at the time of etching can be made as thin as 1/20 as compared with the conventional method. It will be possible. Therefore, the generation of residue on the side wall of the mask and the influence of microloading are eliminated. As a result, the in-plane uniformity of processing accuracy is dramatically improved.

Further, since the mask can be easily formed, miniaturization can be easily performed. By using such a method for forming a dielectric element, it becomes possible to perform high-precision processing, and it is possible to realize a high-density ferroelectric memory.

[Brief description of drawings]

FIG. 1 is a sectional view of an essential part of a basic structure of a dielectric thin film element according to the present invention.

2A to 2E are cross-sectional views showing a manufacturing process of a dielectric thin film element according to the present invention.

FIG. 3 is a schematic view of an ECR etching apparatus used in the present invention.

FIG. 4 shows the oxygen flow rate ratio of the present invention, SBT thin film, and TaSi.
6 is a graph showing the relationship with the etch rates of the N film and the Ir film.

5A to 5D are cross-sectional views showing another manufacturing process of the dielectric thin film element according to the present invention.

FIG. 6 is a flow rate ratio of C ₂ F ₆ / C1 ₂ and Ta in the present invention.
6 is a graph showing the relationship between SiN and the etch rate of an interlayer insulating film.

7 (a) to 7 (d) are cross-sectional views showing still another manufacturing process of the dielectric thin film element according to the present invention.

8A to 8E are cross-sectional views showing still another manufacturing process of the dielectric thin film element according to the present invention.

FIG. 9 is a graph showing the relationship between the oxygen flow rate ratio and the etch rate of a silicon oxide film in the present invention.

10A to 10H are cross-sectional views showing still another manufacturing process of the dielectric thin film element according to the present invention.

11A to 11G are cross-sectional views showing still another manufacturing process of the dielectric thin film element according to the present invention.

12 (a) to 12 (h) are cross-sectional views showing still another manufacturing process of the dielectric thin film element according to the present invention.

13 (a) to 13 (d) are cross-sectional views showing still another manufacturing process of the dielectric thin film element according to the present invention.

FIG. 14 is a diagram showing a cross section of a ferroelectric memory cell formed according to the present invention.

[Explanation of symbols]

10 substrate 11 silicon oxide film 20 multilayer thin film 22 diffusion barrier layer 24 lower electrode layers 25, 325, 625, 725 dielectric layers 27, 327, 727 interlayer insulation film 28, 928 upper electrode layers 40, 440, 540, 840 resistance Etching film (Ta
SiN film) 50,550 Resist pattern 80 Solenoid coil 81 Wafer 82 Electrode 83 O ₂ gas inlet 84 Halogen gas inlet 88 2.45 GHz microwave 89 13.56 MHz high frequency 516 Locos oxide layer 517 gate electrode 518 source / drain region 519 First silicon oxide film 520 Polysilicon plug 521 Second silicon oxide film 522 First aluminum extraction electrode

─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-11-158663 (JP, A) JP-A-9-266200 (JP, A) JP-A-6-318573 (JP, A) TABARA S. , WSi2 / Polysilicon Gate Etching Hinging TiN Hard Mask in Connection with Photolithist, Jpn. J. Appl. Phy s. , Japan, April 1997, Vol. 36, pp. 2508-2513 (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 21/3065 H01G 4/33 H01L 21/31

Claims (14)

(57) [Claims] 1. A step of forming a multilayer thin film including a lower electrode layer on a substrate, and a pattern of a first nitride layer containing a metal element having an oxidizable property is formed on the multilayer thin film. And a step of patterning the lower electrode layer into a desired shape by selectively etching the multilayer thin film with a mixed gas containing an oxidizing gas using the pattern of the first nitride layer as a mask. And a step of removing the pattern of the first nitride layer.
And the multilayer thin film is a dielectric layer formed on the lower electrode layer.
And a diffusion burr formed between the substrate and the lower electrode layer.
And a diffusion barrier layer.
Mutual diffusion of elements between the substrate and the dielectric layer is prevented.
And removing the pattern of the first nitride layer comprises:
By selectively removing the barrier layer, the desired shape is obtained.
A method of manufacturing a dielectric thin film element , which comprises the step of patterning in a pattern . 2. The multilayer thin film includes an interlayer insulating film formed between the dielectric layer and the first nitride layer, and forming a pattern of the first nitride layer. Is
The method for manufacturing a dielectric thin film element according to claim 1 , comprising patterning the interlayer insulating film. 3. A step of forming a diffusion barrier layer on a substrate, a step of forming a multilayer thin film including a lower electrode layer and a dielectric layer on the diffusion barrier layer, and a step of forming a multilayer thin film on the multilayer thin film. Forming a pattern of an oxidizable first nitride layer containing at least one of the elements constituting the diffusion barrier layer; and oxidizing the pattern of the first nitride layer as a mask. A step of patterning the lower electrode layer into a desired shape by selectively etching the multilayer thin film using a mixed gas containing a gas; and a step of removing the pattern of the first nitride layer, A method of manufacturing a dielectric thin film element including the following. Wherein the step of removing the pattern of the first nitride layer, the diffusion barrier layer, comprising the step of patterning the desired shape by selectively removing, according to claim 3 Manufacturing method of dielectric thin film element. Wherein said first nitride layer has the diffusion barrier same composition as the layer, the production method of the dielectric thin film element according to any one of claims 1 to 4. 6. The diffusion barrier layer is made of TaSiN, Hf.
The method for manufacturing a dielectric thin film element according to claim 5 , wherein the dielectric thin film element is formed of SiN, TiN or TiAlN. Wherein said first nitride layer, having a diffusion barrier layer thickness greater than, the production method of the dielectric thin film element according to any one of claims 1 to 6. 8. A step of forming an upper electrode layer on the dielectric layer, and a pattern of a second nitride layer containing a metal element, which is oxidizable, on the upper electrode layer. And a step of patterning the upper electrode into a desired shape by selectively etching the upper electrode with a mixed gas containing an oxidizing gas using the pattern of the second nitride layer as a mask. It encompasses method for producing a dielectric thin film element according to any one of claims 1 to 7. Wherein said first nitride layer, as its composition, Ta, contains an element selected from the group consisting of Hf and Si, a dielectric body according to any one of claims 1 to 8 Method for manufacturing thin film element. 10. The thickness of the first nitride layer is from 20 to 20.
In the range of 500 nm, the production method of the dielectric thin film element according to any one of claims 1 to 9. 11. The step of forming the pattern of the first nitride layer comprises a first gas containing a halogen group element, a second gas containing a halogen group element, or the first gas and the second gas. A mixed gas with the above gas is used as an etching gas, and the first gas is HCl, BCl ₃ , Cl ₂ , CCl ₄ ,
CH _x Cl _4-X , COCl ₂ , S ₂ Cl ₂ , PCl ₃ , CCl
_x Br _4-x, is selected from the group consisting of NOCl and SiCl _4, the gas said _{second, CF 4, C 2 F 4} , CHF 3, C 2 F 6, C
₃ F ₈ , C ₄ F ₁₀ , SF ₆ , S ₂ F ₂ , CHFCl ₂ , Br
F ₃ , BrF 5, HBr, HF, BF ₃ , COF ₂ , NF ₃ ,
SiF ₄ , XeF ₂ , CF _x Cl _4-x , CHFCl ₂ , Cl
Selected from the group consisting of F ₃ , BBr ₃ , CBr ₄ , CF _x Br _4-x , CHFBr ₂ and S ₂ Br ₂ (where x is an integer of 4 or less), and the second gas in the mixed gas is The ratio is 20 % or more and 50
% Or less, The manufacturing method of the dielectric thin film element according to any one of claims 1 to 10 . 12. The oxidizing gas, N ₂ O gas, O ₃ is selected from the group consisting of gas and O ₂ gas includes at least one gas, to any one of claims 1 to 11 A method of manufacturing the dielectric thin film element according to claim 1. Ratio of 13. The oxidizing gas in the mixed gas is 70% or less 2 0% or more, of claims 1 to 12
A method for manufacturing a dielectric thin film element according to any one of 1. 14. The method of claim 13, wherein the gas mixture further comprises a compound gas containing a halogen gas or a halogen group element, method for producing a dielectric thin film element according to any one of claims 1 to 13.