JP2005115762A - Expansion unit of information processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a system that can be quickly and surely restored from failure by initializing only an expansion unit with failure, in spite of a plurality of expansion units being addable. <P>SOLUTION: When expansion units are mounted to the body 2 of a programmable display 1 in the order of expansion units 3 to 4, the control part 21 of the body 2 can access the control parts 31, 41 of the expansion units 3, 4 through a bus 11. Under this condition, if the expansion unit 3 fails, the initialization processing part 24 of the body 2 sends an abort signal and a signal for specifying the expansion unit 3 to the bus 11. The initializing process part 35 of the expansion unit 3 determines whether the specifying signal indicates its own device; if the signal indicates its own device, the initialization processing part 35 initializes the control part 31, and after the initialization is finished, sends an enable signal indicating the end of the initialization to the bus 11. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an expansion unit for adding a function to an information processing apparatus that requires quick and reliable return from an abnormal state.

  Conventionally, for example, as shown in Patent Document 1 described later, an additional function is provided instead of providing a circuit for realizing all the assumed additional functions in preparation for the case where different additional functions are required depending on applications. A programmable display provided with a connector for adding an extension unit to be realized is used.

  In the programmable display, when an additional function is required in a certain application, an extension unit for realizing the additional function according to the application is attached to the connector of the programmable display, and the programmable display is connected to the connector. The function of the expansion unit is used.

Thereby, the function can be efficiently extended to the programmable display at a lower cost than the configuration in which a circuit for realizing all the assumed additional functions is provided in the programmable display.
JP 2001-117507 A (publication date: April 27, 2001)

  However, the above conventional configuration is basically intended to mount one extension unit, and a plurality of extension units cannot be provided. In this case, if each expansion unit can be initialized only by a system reset signal even though a plurality of expansion units can be added by the bus, when an abnormality occurs in a certain expansion unit, The expansion unit must also be initialized. Also, in this case, the system cannot start normal operation until the time determined to finish initialization of all the expansion units has elapsed, so it takes time to recover from the abnormal state.

  The present invention has been made in view of the above-mentioned problems, and its purpose is to initialize only the expansion unit in which an abnormality has occurred even though a plurality of expansion units can be added, so that the abnormality can be detected early and reliably. The object is to realize a system capable of returning from a state.

  In order to solve the above-described problem, the expansion unit of the information processing apparatus according to the present invention connects the two connectors and the two connectors, and connects the information processing apparatus connected to one of the two connectors or the other expansion. While the initialization instruction signal is transmitted to one of the bus, the bus for connecting the unit, the other extension unit connected to the other unit, and the own device to the bus, and the signal line of the bus, the bus Determine whether the signal for specifying the expansion unit transmitted to other signal lines indicates the own device. If it indicates the own device, initialize the own device. In addition, it is characterized by comprising initialization processing means for outputting a response signal indicating completion of initialization to one of the signal lines of the bus when the initialization processing is completed.

  Further, in addition to the above configuration, the bus includes a common signal line, and the extension unit can access an address to be accessed by a signal group transmitted through the common signal line in a plurality of times. The initialization processing means transmits and receives a command indicating processing contents to be accessed and data related to the processing, and the initialization processing means automatically transmits the command based on the specific signal transmitted through the common signal line. The necessity of device initialization may be determined.

  In addition to the above configuration, the two connectors are cascade-connected to the information processing apparatus or other extension unit connected to one of the two connectors, the own device, and another extension unit connected to the other. And determining the position of the address area of its own device in the address space of the information processing device based on the address information notified from the information processing device or other expansion unit in the previous stage. The address information may be changed according to a predetermined size of the address area occupied by the own device, and may be provided with an address area determining means for sending to the other extension unit at the next stage. Good.

  As described above, the expansion unit of the information processing apparatus according to the present invention includes the two connectors, the bus, and the initialization processing unit, and the information processing apparatus connected to one of the two connectors by the bus. Alternatively, another extension unit, the own device, and another extension unit connected to the other are connected by bus. Therefore, if necessary, an expansion unit can be attached to the information processing apparatus, and a necessary number of expansion units can be attached to the information processing apparatus by repeating the operation of attaching another expansion unit to the expansion unit. The information processing apparatus can use the function of each expansion unit by accessing each expansion unit connected to the bus by itself.

  Further, in the above configuration, since the initialization processing means determines whether or not it is an initialization instruction to the own device based on a signal for specifying the extension unit transmitted together with the initialization instruction signal. Although a plurality of expansion units can be connected by bus, only a specific expansion unit can be initialized without initializing other expansion units.

  In the above configuration, since the initialization processing means outputs the response signal to the bus, the member instructing the initialization can detect that the initialization is completed by the response signal. Therefore, it is possible to grasp that the specific expansion unit becomes available again at an earlier point in time, and use of the specific expansion unit can be resumed.

  Further, in the configuration in which the shared signal line is provided in addition to the above configuration, the extension unit can determine the address to be accessed and the access target by the signal group transmitted through the shared signal line in a plurality of times. Since a command indicating processing contents and data related to processing are transmitted and received, a bus for address signal transmission, command transmission, and data transmission is provided separately, and these signals are transmitted simultaneously. The number of buses can be reduced compared to

  Here, even if the number of signal lines is reduced, if the data transmission speed is kept the same, the operating frequency of the signal lines increases, so the allowable range for timing deviation when transmitting and receiving signals Becomes narrower. In addition, even if signals are transmitted on the same signal line, the meaning of the signal changes depending on how many times the signal is transmitted. Therefore, the transmitting device (information processing apparatus or expansion unit) and the receiving device If the recognition of the number of signal transmissions with the (information processing apparatus or expansion unit), in other words, the recognition of the meaning of the currently transmitted signal is different from each other, the signal cannot be transmitted normally. . For example, if the transmitting device has already transmitted a certain signal and the receiving device enters a state of waiting for the signal, that is, the current signal line is waiting for the signal. If the signal is interpreted as being transmitted or not, data cannot be transmitted or received normally. As described above, when data or the like is transmitted by the signal group, the expansion unit enters the abnormal state, and thereafter, there is a possibility that the data or the like cannot be transmitted / received normally.

  However, in the above configuration, the initialization processing means initializes its own device based on the extension unit specifying signal transmitted together with the initialization instruction signal. Here, since the initialization instruction signal and the identification signal are transmitted simultaneously on the bus, unlike the transmission of the address and the like, there is no difference in state, and the expansion unit is reliably initialized. it can. In the above configuration, since the specific signal is transmitted by the common signal, the number of signal lines required for the bus can be further reduced.

  As a result, the number of signal lines can be greatly reduced, and the occupied area of the connector and the number of terminals of the connector can be reduced. Therefore, the manufacturing cost can be reduced and the design difficulty can be lowered. Moreover, since the volume of the connector can be reduced, the structure of a member (for example, an outer wall) that forms the expansion unit can be simplified. Furthermore, since the number of signal lines can be greatly reduced, noise radiated from the expansion unit can be suppressed, and the cost required for noise countermeasures can be reduced.

  In addition to the above configuration, in the configuration in which the address area determining means is provided, when the information processing apparatus gives address information to the first extension unit and indicates the position of the address area allocated to the extension unit, the extension unit The address area determining means changes the address information in accordance with the size of the address area occupied by the own device, and sends the address information to the other extension unit at the next stage. Further, the address area determining means of each expansion unit determines the position of the address area allocated to the own device based on the address information from the previous expansion unit and determines the size of the address area occupied by the own device. In response, the address information is changed and sent to the next expansion unit.

  Thereby, the address area of each expansion unit can be automatically determined regardless of the size of the address area occupied by each expansion unit. Therefore, it is possible to reduce the user's trouble when attaching the expansion unit to the information processing apparatus, that is, when adding a function to the information processing apparatus.

  An embodiment of the present invention will be described below with reference to FIGS. That is, the expansion unit according to the present embodiment is suitable for, for example, being mounted on a programmable display as an information processing apparatus that requires quick and reliable return from an abnormal state and extending the function of the programmable display. Is used. For example, the programmable display is suitably used as a graphic operation panel of a control system, for example, in the vicinity of a control target device such as a belt conveyor, and displays the status of the control target to notify the operator. A control instruction can be output to each control object according to the operation.

  Here, before explaining the operation when each expansion unit is individually restored from the abnormal state, the general operation of the entire programmable display will be described. As shown in FIG. 1, the programmable display 1 according to the present embodiment is shown. The main body (information processing device) 2 is provided with a connector C21 for mounting one of the expansion units 3, 4,... (For example, 3). Each expansion unit (which will be described by taking 3 as an example below) is provided with two connectors C31 and C32, one connector C31 being the main body 2 and the other being the other expansion unit (for example, 4). ). In the above description, the case of the extension unit 3 directly connected to the main body 2 has been described as an example. However, in the case of the extension unit (for example, 4) connected to the main body 2 via the extension unit, The connector C41 can be connected to the expansion unit (3 in the case of FIG. 1), and the other connector C42 can be connected to another expansion unit (not shown).

  Thereby, although a desired number of extension units can be mounted, the connector C21 provided in the main body 2 of the programmable display 1 is compared with a configuration in which a connector for connecting to each expansion unit is provided in the main body 2 separately. Can be reduced.

  Logically, the expansion units 3 and 4 that are directly connected (attached to the main body 2) or indirectly connected (connected through other expansion units) are described later. As shown in FIG. 1, among the address areas AA that can be assigned to the expansion units 3... In the address space that can be accessed from the main body 2, different address areas AA 0 and AA 1 and AA 2 are assigned. Yes.

  Further, in a state where the extension units 3 and 4 are connected to the main body 2, the extension units connected to each other via the wiring (a circuit if necessary) inside the main body 2 and the connectors C21, C31, C32, and C41. The bus 11 is configured by the internal wirings (circuits as necessary) of the 3.4, and the control unit 21 of the main body 2 and the control units 31 and 41 of the expansion units 3 and 4 are connected to the bus 11. It is connected to the.

  Further, when accessing the desired address in the address area assigned to the desired expansion unit, the control unit 21 of the main body 2 sends a signal indicating the address to the bus 11 and each expansion unit 3. The control units 31 and 41 of 4 determine whether or not the signal sent to the bus 11 indicates the address area allocated to itself, and if it is determined that the signal is within its own address area, Accept access to.

  As a result, the main body 2 accesses the resource allocated to the desired address of the desired extension unit 3 or 4 by accessing the desired address in the address area allocated to the desired extension unit 3 or 4. It is possible to use the function of the resource (for example, capture of a video signal, output of a video signal to an additional display device, etc.). As a result, the programmable display 1 having the function can be realized simply by attaching the expansion unit 3 or 4 having the necessary function to the main body 2, and the expansion unit 3 or 4 can be realized for each use of the programmable display 1. The number of models to be prepared in advance is different from the case of preparing a programmable display of different models that have built-in functions in advance or the case of preparing a programmable display that has all the functions that may be required in advance. In addition, it is possible to realize the programmable display 1 that does not have an extra function.

  The bus 11 according to the present embodiment includes a signal line LSD [15: 0] for transmitting a signal SD [15: 0] used for address and data transmission, and the main body 2 is one of the expansion units 3 and 4. The signal line LA for transmitting the abort signal ABORT_L for instructing initialization and the extension units 3 and 4 instructed for initialization transmit the enable signal CMDEN_L for notifying the main body 2 of the end of initialization. A signal line LE is provided. The bus 11 according to the present embodiment is a synchronous bus, and the bus 11 is provided with a signal line LCK for transmitting the clock signal SGCLK of the bus 11, and the main body 2 and the expansion unit 3. The circuits connected to the bus 11 (control units 21, 31, 41, and initialization processing units 24, 35, 45 and address recognition unit 23 described later) operate in synchronization with the clock signal SGCLK. In the present embodiment, the frequency of the clock signal SGCLK is set to 24.576 [MHz]. Further, the bus 11 according to the present embodiment has a signal line for transmitting a reset signal RESET_L for resetting the entire system, in addition to the signal lines LSD [15: 0], LA, LE and LCK, and A power supply line for supplying power from the main body 2 of the programmable display 1 to each of the expansion units 3 and 4 is also provided (none is shown). In this specification, [15: 0] indicates a bit range (upper limit value: lower limit value), and the above-described signal line LSD [15: 0] includes the 15th to 0th bits. It means that it is composed of 16 signal lines for transmission. For convenience of explanation, [] is omitted when not necessary.

  Further, each of the extension units (for example, 3) is provided with the signal lines LCK, LSD, LA, LE, and signal lines constituting a part of each of the signal lines LCK, LSD, LA, LE. Further, one end of these signal lines is connected to a terminal corresponding to each signal line in one connector C31, and the other end is connected to a terminal corresponding to each signal line in the other connector C32. Has been. Further, the connector C21 of the main body 2 is provided with terminals corresponding to the respective signal lines, and the terminals of the respective connectors C21 to C42 correspond to the respective signal lines when the respective connectors C21 to C42 are mounted. The terminals are arranged so that the terminals are connected to each other. Therefore, the bus 11 can be configured by connecting the expansion units 3 and 4 to the main body 2. As long as the bus 11 can transmit the above-described signals SD, ABORT_L, CMDEN_L, and SGCLK, each expansion unit 3 or 4 may include a buffer circuit disposed on the bus 11.

  In the present embodiment, the signal line LSD is not only shared for address transmission and data transmission by time division, but also in the transmission direction of the bus 11 (from the main body 2 to the expansion unit 4). The direction from the extension unit 4 to the main body 2) is also used for transmission of the change instruction and transmission of an acknowledge signal indicating that the change instruction has been completed.

  In other words, in the present embodiment, as shown in FIG. 3, a command indicating a process such as read / write or the like of a command by a plurality of signals SD transmitted through the signal line LSD for each clock cycle of the clock signal SGCLK. A target address, read / written data, an instruction to change the data transmission direction, and an acknowledge signal are transmitted.

  As a result, when address signals and data signals are transmitted in parallel, that is, signal lines for transmitting address signals and data signals are separately provided on the bus, and address signals and data signals are transmitted in one clock. Compared with the configuration, the bus width of the bus 11 can be narrowed, so that the occupied area and the number of terminals of the connectors C21 to C42, the number of wirings, and the radiated noise can be reduced.

  More specifically, when the control unit 21 of the main body 2 receives data from a resource at a certain address of a certain extension unit (when reading), the control unit 21 of the main unit 2 starts the period (read cycle) during which a signal related to the read is transmitted. The command and address indicating read are transmitted in two clocks, the transmission direction change instruction CHG is transmitted in the next clock, the transmission direction change completion report (acknowledge signal ACK), and the data transmitted subsequently That is, it waits for data read from the address. In addition, while the command is being transmitted (during the first clock), the control unit 21 sets the enable signal CMDEN_L to active (low level in the example in the figure) and is transmitting the command. Is notified to each expansion unit 3.

  In the present embodiment, as shown in FIG. 4, the signal CMD transmitted through the signal line LSD at the first clock of the read cycle is a command indicating the read (in the example shown, the ninth bit and the eighth bit of the signal CMD). As well as the high-order bits of the address (in the example shown, the 23rd to 16th bits of the address; the 7th to 0th bits of the signal CMD). The remaining bits (lower 15th to 0th bits) of the address are transmitted as the signal ADD transmitted to the 1st clock. FIG. 4 illustrates the case of accessing the extension unit 3, and the address indicates any address in the address area AA 0 allocated to the extension unit 3. Further, a part of the signal CMD (15th to 12th bits in the example of FIG. 4) is different from the value of the part of the same bit position of the acknowledge signal ACK so that it can be distinguished from the acknowledge signal ACK. (In the example of FIG. 4, all are set to “1”).

  Further, in the present embodiment, the bit width of the upper bits of the address is set so that it is possible to specify which of the expansion units 3... Specifically, in this embodiment, as shown in FIG. 2, the address area AA that can be assigned to each expansion unit 3... Is divided into eight address areas AA0 to AA7, and each address area AA0 to AA7. Among them, the continuous address areas corresponding to the number required for each expansion unit 3... Can be allocated to each expansion unit 3. Each address area has a size that can be expressed by 17 bits (128 Kbytes when addresses are assigned in units of bytes). Therefore, since each of the address areas AA0 to AA7 can be distinguished by the 19th to 17th bits of the address, the bit width of the upper bit includes the relevant bit (in this example, the 23rd to 16th bits). Up to 8 bits). For example, as shown in FIG. 2, in this embodiment, since the extension unit 3 is allocated to the address area AA0, in FIG. 4, the 19th to 17th bits of the address, that is, the CMD signal CMD. The 3rd to 1st bits are set to “000”.

  On the other hand, the control units 31 and 41 of the extension units 3 and 4 determine whether the signal is an acknowledge signal ACK or a command based on the signal CMD or ACK transmitted through the signal line LSD while the enable signal CMDEN_L is active. In the case of a command, the contents of the command and a part of the address are grasped, and it is determined whether or not the address is included in the address area assigned to itself.

  For example, in the first clock of the read cycle, the signal CMD indicates that the value of the bit position (15th to 12th bits) for identifying the acknowledge is not an acknowledge, and for the command The value at the bit position (9th and 8th bits) indicates a read. Further, in the signal CMD, the value of the bit position (the third bit to the first bit) for distinguishing the address areas AA0 to AA7 for each extension unit is “000” and is assigned to the extension unit 3. The address area AA0 is shown.

  Therefore, the control unit 31 of the expansion unit 3 determines that the reading is instructed to itself and communicates with the control unit 21 of the main body 2. Specifically, when the control unit 31 acquires the signal ADD transmitted to the second clock, the control unit 31 determines from the upper bits included in the signal CMD of the first clock and the lower bits included in the signal ADD. The control unit 21 recognizes the address to be accessed and reads data from the address. Further, the control unit 31 of the extension unit 3 is a clock after the command (change instruction CHG) for instructing the change of the transmission direction is output from the control unit 21 of the main body 2 to the signal line LSD, The clock after the clock that outputs the acknowledge signal ACK to the signal line LSD and transmits the acknowledge signal ACK at the clock that enables the read data to be output to the signal line LSD or the clock before it. At the next clock (in the example shown in the figure), the read data is output to the signal line LSD. Note that the control unit 31 sets the enable signal CMDEN_L to be active in the clock that transmits the acknowledge signal ACK.

  On the other hand, in the above example, since the upper bits of the address included in the signal CMD indicate access to the expansion unit 3, the control unit 41 of the expansion unit 4 determines that it is not access to itself, In the read cycle, output to the signal line LSD is stopped. In FIGS. 3 and 4, the access to the extension unit 3 has been described as an example. However, in the case of access to the extension unit 4, the control unit 31 of the extension unit 3 stops the output to the signal line LSD. The control unit 41 of the expansion unit 4 responds to the control unit 21 of the main body 2.

  Thereby, the control unit 21 of the main body 2 can read data from a desired address of the extension units 3 and 4 attached to the main body 2. In FIG. 3, CS *, RD *, READY *, and PDATA (16) are a chip select signal in the expansion unit 3, a signal for instructing reading, a signal indicating that reading is possible, and data, respectively. This indicates a signal, and an asterisk at the end of the signal indicates low active.

  On the other hand, when writing data to a resource at a certain address of a certain expansion unit, the control unit 21 of the main body 2 has the first two clocks in a period (write cycle) for transmitting a signal related to the writing as shown in FIG. Then, the command and address indicating the write are transmitted, the data WDT to be written at the next clock is transmitted, and the transmission direction change instruction CHG is transmitted at the next clock, and the acknowledge indicating that the writing is completed. Wait for transmission of signal ACK.

  Also in this case, as shown in FIG. 6, in the signal CMD transmitted at the first clock of the write cycle, bits (15th to 12th bits) for distinguishing from the acknowledge signal ACK are provided, as in the read cycle. ), Bits indicating the command (9th and 8th bits), and bits indicating the upper bits of the address (7th to 0th bits), and the control units of the expansion units 3 and 4 31 and 41 determine whether the signal is an acknowledge signal ACK or a command based on the signal CMD or ACK transmitted through the signal line LSD while the enable signal CMDEN_L is active. As well as part of the address and determine whether the address is included in the address area assigned to it. It is.

  Here, since FIG. 5 exemplifies writing to the extension unit 3, the bits (19th to 17th bits of the address) for identifying each of the above address areas among the upper bits are as follows: The value is “000” indicating the address area AA0 assigned to the expansion unit 3. Therefore, the control unit 31 of the expansion unit 3 specifies an address from the lower bit indicated by the signal ADD transmitted by the second clock and the upper bit of the address, and among the resources of itself, to the resource at the address. Write the data transmitted in the third clock. Further, when the control unit 31 of the extension unit 3 succeeds in the writing after the transmission direction change instruction CHG is transmitted, the control unit 31 outputs the acknowledge signal ACK to the signal line LSD and succeeds in the writing to the control unit 21 of the main body 2. To be notified.

  On the other hand, in the above example, since the upper bits of the address included in the signal CMD indicate access to the expansion unit 3, the control unit 41 of the expansion unit 4 determines that it is not access to itself, In the write cycle, output to the signal line LSD is stopped. 5 and 6, the access to the expansion unit 3 has been described as an example. However, in the case of access to the expansion unit 4, the control unit 31 of the expansion unit 3 stops the output to the signal line LSD. The control unit 41 of the expansion unit 4 responds to the control unit 21 of the main body 2.

  Thereby, the control unit 21 of the main body 2 can write data to a desired address of the extension units 3 and 4 attached to the main body 2. In FIG. 5, LCS_L, LWR_L, LREADY_L and LD (16) respectively indicate a chip select signal, a signal for instructing writing, a signal indicating that writing has been completed, and a data signal in the expansion unit 3. _L attached to the end of the signal indicates low active.

  Next, a configuration for automatically assigning any of the address areas AA0 to AA7 to each of the attached expansion units 3 and 4 and an operation at the time of assignment will be described. That is, as shown in FIG. 1, the programmable display 1 according to the present embodiment includes a transmission path that is cascade-connected to each other separately from the bus 11 by the main body 2 and the expansion units 3 and 4 attached thereto. 12 is configured.

  In the transmission line 12, the main body 2 that is the foremost stage is provided with an initial address instruction unit 22 that outputs an initial address. On the other hand, each expansion unit 3 (4) includes an occupied address storage unit 32 (42) for storing data indicating the size of the address area occupied by the expansion unit 3 (4), and a main body 2 (expansion unit 3) as a preceding device. The address information received via the connectors C21 and C31 (C32 and C41) is changed in accordance with the data and output to the next stage, and the change circuit 33 (43) before and after the change circuit 33 (43) An address recognition unit 34 (44) that determines an address area assigned to itself based on the subsequent address information and transmits the address region to the control unit 31 (41) is provided. The members 32 to 34 or the members 42 to 44 correspond to the address area determining means described in the claims.

  In this embodiment, as described above, the address areas AA that can be assigned to the expansion units 3... Are assigned to eight addresses AA0 to AA7. Therefore, the address information is transmitted through the three signal lines LAA [2: 0], and the terminals connected to these signal lines in the connectors C21, C32, and C42 on the next stage are the connectors C21. When the front-stage connectors C31, C41,... Are attached to C32, C42, they are arranged at positions where they are connected to the corresponding terminals of these connectors C31, C41,.

  In the present embodiment, the expansion unit closer to the main body 2 among the expansion units 3... Is assigned to a lower address area among the address areas AA0 to AA7. The initial address instruction unit 22 outputs a value (“000”) indicating the re-lower address area AA0 to the signal line LAA, for example, by grounding each signal line. Note that “close to the main body 2” indicates the closeness of the connection relationship between the expansion units 3..., And the expansion unit 3 directly connected to the main body 2 is closest to the main body 2 and is connected to the expansion unit. 4 comes next.

  On the other hand, in this embodiment, since the extension unit closer to the main body 2 is assigned to a lower address area, the change circuit 33 (43) of each extension unit 3 (4) is realized by an adder. The change circuit 33 (43) adds the size of the address area occupied by the extension unit 3 (4) stored in the occupied address storage unit 32 (42) to the address information received from the previous stage, and adds The result is output to the next stage. The occupied address storage unit 32 (42) stores the size of the address area in units of the size of the address areas AA0 to AA7.

  For example, as shown in FIG. 2, the expansion unit 3 according to the present embodiment occupies one address area as large as the address areas AA0 to AA7. "Is stored, and when the main body 2 and each of the expansion units 3 and 4 are connected as shown in FIG. 1, the change circuit 33 outputs a value (" 001 ") indicating the address area AA1 as address information. In this case, the address recognition unit 34 uses the address information “000” and “001” before and after the change circuit 33, and the address area assigned to the expansion unit 3 is from the address area AA0 corresponding to the previous value “000”. It is determined that the address area is the address area AA0 immediately before the address area AA1 corresponding to the subsequent value “001”, that is, the address area AA0. On the other hand, since the expansion unit 4 occupies two address areas, "010" is stored in the occupied address storage unit 42 of the expansion unit 4, and when connected as shown in FIG. As a result, a value (“011”) indicating the address area AA3 is output as address information. Therefore, the address recognition unit 34 determines that the address areas AA1 and AA2 are allocated to itself based on the address information before and after the change circuit 33.

  On the other hand, the main body 2 of the programmable display 1 is provided with an address recognition unit 23 connected to the bus 11, and the control unit 31 (41) of each expansion unit 3 (4) is assigned to itself. When a read command to a predetermined address is received on the basis of the start address of the address area, it is possible to respond with its own function and the size of the address area occupied by itself.

  Therefore, the address recognizing unit 23 issues the read command to the predetermined address in the first address area (AA0), thereby functioning the expansion unit (3 in the example of FIG. 1) that is mounted first, and The size of the occupied address area can be acquired. Further, the address recognizing unit 23 adds the both from the start address of a certain extension unit 3 and the size of each address area occupied by the extension unit 3 (each address unit), for example. The function of the expansion unit 4 mounted next is obtained by obtaining the start address of the address area assigned to the expansion unit 4 mounted on the unit 3 and issuing a read command to the predetermined address in the address region, and Get the size of the occupied address area. As a result, the address recognition unit 23 can grasp the respective functions and assigned address areas for all of the attached extension units 3 and 4, and can transmit them to the control unit 21.

  Moreover, in this embodiment, each control part 21,31,41 is comprised so that it can identify whether another expansion unit is mounted next to itself, and each expansion unit 3 (4) is comprised. The control unit 31 (41) is configured to report the identification result together with the response to the read command. Specifically, each of the control units 21, 31, and 41 is connected to a terminal pulled up to a high level via a resistor, for example, among the connectors C 21, C 32, and C 42 on the next stage side. On the other hand, among the terminals provided on the front-side connectors C31, C41,..., The terminal corresponding to the pulled-up terminal is grounded. Therefore, each control unit 21, 31 and 41 identifies whether or not the extension unit is installed next to itself by confirming whether or not the pulled-up terminal is at a high level, and displays the identification result. Can report. Thus, in this embodiment, since the address recognition unit 23 can also acquire the identification result, it is assumed that the expansion unit is next installed, and when the above read command is transmitted and cannot be read normally, Compared to the configuration in which it is determined that the next expansion unit is not installed, it is possible to grasp the respective functions and assigned address areas of all the installed expansion units 3 and 4 faster and more reliably. .

  In this example, the case where the address recognition unit 34 (44) determines the address area assigned to itself based on the address information before and after the change circuit 33 (34) has been described as an example. Since the size of the address area to be occupied is determined, by referring to this size, the allocated address area is determined based only on the previous or subsequent address information, and is transmitted to the control unit 31 (41). Can do.

  In this example, the case where the extension unit closer to the main body 2 is assigned to a lower address area has been described as an example. However, the extension unit closer to the main body 2 is assigned to a higher address area. May be. In this case, the initial address instruction unit 22 outputs a value indicating the highest address area (for example, AA7) as the initial address, and the change circuit 33 (43) of each expansion unit 3 (4) receives from the previous stage. The value from the occupied address storage unit 32 may be subtracted from the address information.

  By the way, it is only necessary that the expansion units 3 and 4 can continue to operate normally. However, the expansion units 3 and 4 may malfunction due to various factors. In particular, when the signal line LSD is driven in a time-sharing manner as in this embodiment, in order to ensure the same data transfer speed as when the bus width is expanded without the time-sharing driving, the driving frequency Therefore, an allowable transmission timing shift must be shortened, and there is a risk of malfunction due to, for example, the influence of noise. Furthermore, when the meaning of the signal transmitted through the signal line LSD changes depending on the clock number of the read or write cycle as in this embodiment, the main body 2 and the extension unit of the programmable display 1 If the recognition of the clock number with respect to 3 (4), in other words, the recognition of the meaning of the currently transmitted signal is different from each other, the signal cannot be transmitted normally.

  For example, when the main unit 2 has already transmitted the transmission direction change instruction CHG, for example, the expansion unit 3 (4) enters a state of waiting for the change instruction CHG, that is, If it is interpreted that the signal line LSD is transmitting the change instruction CHG or any other signal, data cannot be transmitted and received normally thereafter.

  In contrast, as shown in FIG. 1, the main body 2 of the programmable display device 1 according to the present embodiment is provided with an initialization processing unit 24 connected to the bus 11, and the initialization processing unit 24. When, for example, an instruction from the control unit 21 or monitoring of the bus 11 detects that a timeout has occurred while the control unit 21 of the main body 2 is accessing any of the resources of the expansion units 3 and 4, 7, the active abort signal ABORT_L is output to the signal line LSA of the bus 11, and the signal ID for specifying the expansion unit including the resource is transmitted to the signal line LSD of the bus 11. To instruct the expansion unit to initialize.

  For example, as shown in FIG. 8, the signal ID is an address area in which the value of a bit at a specific position (for example, the third bit to the first bit) includes the resource, as in FIG. As a result, the extension unit assigned to the address area can be specified. For example, the example of FIG. 8 shows a case where a timeout occurs in the resource of the extension unit 3 and the extension unit 3 is instructed to initialize, so that the value of the bit is the address area allocated to the extension unit 3 A value (“000”) indicating AA0 is set.

  On the other hand, each expansion unit 3 (4) is connected to the bus 11 as initialization processing means described in the claims, and an initialization processing unit 35 (45) that receives an initialization instruction from the initialization processing unit 24. ) Is provided. The initialization processing unit 35 (45) monitors the abort signal ABORT_L transmitted through the signal line LA. When the abort signal ABORT_L becomes active, the signal on the signal line LSD at that time (more precisely, the above-mentioned Based on the value of the bit at a specific position), it is determined whether or not the abort signal ABORT_L instructs the initialization of the own device, and if it is determined that the initialization of the own device is instructed, the control unit 31 Instruct the initialization to (41).

  For example, in the example of FIG. 8, the bit of the signal ID is set to a value indicating the address area AA0. In the extension unit 3, the address recognition unit 34 shown in FIG. The area is recognized as an address area AA0. Therefore, the initialization processing unit 35 of the extension unit 3 determines that the abort signal is based on the fact that the bit of the signal ID indicates an area recognized by the address recognition unit 34 as being allocated to the own device. It is determined that ABORT_L is instructing initialization of the own device, and the control unit 31 is instructed to initialize. On the other hand, in the case of this example, the initialization processing unit 45 of the extension unit 4 determines that the abort signal ABORT_L does not indicate initialization of the own device, so the control unit 41 of the extension unit 4 The normal processing is continued without performing.

  Thereby, in the programmable display 1 which concerns on this embodiment, even if it is a case where abnormality has generate | occur | produced in any (for example, 3) of the expansion units 3 * 4 with which the main body 2 was mounted | worn, another expansion unit (in this case) Can instruct initialization only to the expansion unit (3) in which an abnormality has occurred without initializing 4).

  Note that the initialization processing unit 35 (45) of each expansion unit 3 (4) only monitors the signal on the signal line LSD when the abort signal ABORT_L becomes active, and the control unit 31 (41). Unlike the above, the processing is not changed depending on the clock number of the cycle. Therefore, even when the control unit 31 (41) runs out of control, the initialization instruction to the own device can be received without any trouble, and the initialization can be instructed to the control unit 31 (41) of the own device.

  Furthermore, in each expansion unit 3 (4) according to the present embodiment, the initialization processing unit 35 (45), for example, by the notification from the control unit 31 (41) or the monitoring of a specific resource, When the completion of initialization 41) is detected, the enable signal CMDEN_L is made active as shown in FIG. 7, and the initialization processing unit 24 of the main body 2 is notified of the completion of initialization.

  On the other hand, in the main body 2 of the programmable display 1, the address recognition unit 23 monitors the enable signal CMDEN_L for a period after the abort signal ABORT_L is activated, and instructs initialization when the enable signal CMDEN_L becomes active The extension unit 3 (4) has determined that the initialization has been completed and, for example, the resource of the extension unit 3 (4) is re-accessed to a resource in which a timeout has occurred, and after the recovery from the abnormality A predetermined process is performed as the process.

  As a result, the initialization processing unit 24 of the main body 2 of the programmable display 1 according to the present embodiment is compared with the configuration in which the post-processing is performed after a predetermined time has elapsed as the maximum required time for initialization. At an earlier point in time, it is possible to grasp that the expansion unit in which an abnormality has occurred becomes usable again, and the use of the expansion unit can be resumed.

  By the way, in the above, by attaching each expansion unit 3 or 4 to the main body 2 of the programmable display 1, the transmission path 12 is configured, and the address information sent from the previous stage by each expansion unit 3 or 4 The address area to be assigned to each expansion unit 3 or 4 is determined by changing the size according to the size of the address area occupied by the transmission unit and transmitting it to the next stage. However, the present invention is not limited to this. For example, before the expansion units 3 and 4 are attached, the expansion units 3 and 4 receive the designation of the address area by the user, for example, by reading the setting of the dip switch, and are assigned to the own device based on the designation. An address area may be identified. However, if the address area is set as in the present embodiment, each expansion unit 3 or 4 is independent of the number of expansion units 3 or 4 to be mounted and the size of the address termination area occupied by each. Since it is possible to automatically recognize the address area assigned to the own device, it is possible to greatly reduce the user's labor when attaching the extension units 3.

  In the above description, the extension unit 3 (4) that has received the initialization instruction has been described to notify the end of initialization by the enable signal CMDEN_L. However, if the end of initialization can be notified, the end of the initialization is completed. The signal line for transmitting the signal is not limited to this.

  For example, instead of the enable signal CMDEN_L, a signal line for response (for notification of completion of initialization) is provided on the bus 11, and after transmitting the signal ID for specifying the expansion unit 3 (4), the abort signal If ABORT_L is set to inactive, the main body 2 of the programmable display device 1 can access another extension unit 3 (4) while a certain extension unit 3 (4) is performing the initialization process.

  Even in this configuration, while the abort signal ABORT_L is active, a signal indicating the expansion unit 3 (4) to be initialized can be transmitted by the signal line LSD. Can be used only for the signal line. In this case, since only the extension unit 3 (4) instructing initialization responds, if only one extension unit 3 (4) is instructed to initialize, the signal line provided on the bus 11 The increased number can be reduced to one. On the other hand, if a plurality of signal lines are provided for transmission of response signals, it is possible to instruct initialization to the plurality of extension units 3 (4) at the same time and wait for responses from the respective units simultaneously. Even in this case, the signal line LSD is occupied only during the period in which the abort signal ABORT_L is active. After the signal ID is transmitted, the extension of the signal line LSD is set by setting the abort signal ABORT_L to inactive. While initializing the units 3..., The main body 2 of the programmable display 1 can access other extension units using the signal line LSD.

  In the present embodiment, the members 21 to 24, 24, 31 to 35, and 41 to 45 provided in the main body 2 and the expansion units 3 and 4 of the programmable display 1 are, for example, ASIC (Application Specific Integrated). These components are realized by a circuit stored in a storage unit such as a ROM or RAM by an arithmetic unit such as a CPU, and an input device such as a touch panel or a liquid crystal display device. You may implement | achieve by controlling communication means, such as an output means or an interface circuit. In this case, these members can be realized by reading a recording medium (for example, a CD-ROM) on which the program is recorded and causing the calculation means to execute the program. Further, for example, if a program for downloading a program via a serial cable, a local area network, or another communication path is installed in the computer in advance, the program is transferred to the computer via the communication path. Can also be distributed. However, the initialization processing unit 35 (45) receives an initialization instruction when an abnormality occurs, for example, by interrupting the arithmetic means by the abort signal ABORT_L, and so on when the abnormality occurs. It is desirable that the configuration can be received, or only these members 35 (45) can be realized by a circuit different from the calculation means.

  Of the expansion units attached to the main unit, only the expansion unit in which an abnormality has occurred can be quickly and surely restored from the abnormal state.For example, the function of the programmable display can be expanded immediately from the abnormal state. The present invention can be suitably used for expanding the functions of an information processing apparatus that requires a reliable return.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 illustrates an embodiment of the present invention, and is a block diagram illustrating a configuration of a main part of a programmable display device and a main part of an extension unit attached thereto. It is drawing which shows the address area allocated to each said expansion unit. It is a timing chart which shows the signal transmitted through the signal line of a bus | bath, and the inside of an expansion unit, when the main body of the said programmable display reads data from an expansion unit. It is drawing which shows an example of the value of the signal which flows into each signal line of the said bus | bath. 6 is a timing chart showing signals transmitted through each signal line of the bus and the inside of the extension unit when the main body writes data to the extension unit. It is drawing which shows an example of the value of the signal which flows into each signal line of the said bus | bath. It is a timing chart which shows the signal transmitted to the said bus | bath when abnormality has generate | occur | produced. It is drawing which shows an example of the value of the signal which flows into each signal line of the said bus | bath.

Explanation of symbols

2 Body (Information processing device)
3.4 Expansion unit 11 Bus 32/42 Occupied address storage unit (address area determination means)
33.43 Change circuit (address area determination means)
34.44 Address recognition unit (address area determination means)
35.45 Initialization processing unit (initialization processing means)
C31 / C32 / C41 / C42 Connector LSD signal line (common signal line)

Claims (3)

Two connectors,
A bus for connecting the information processing apparatus or other expansion unit connected to one of the two connectors, another expansion unit connected to the other, and the own device via a bus while connecting the connectors ,
While the initialization instruction signal is transmitted to one of the signal lines of the bus, the identification signal for identifying the extension unit transmitted to the other signal line of the bus is If the self-device is indicated, the self-device is initialized, and when the initialization process is completed, a response indicating the completion of initialization is sent to one of the bus signal lines. An expansion unit for an information processing apparatus, comprising: initialization processing means for outputting a signal. The above bus includes a common signal line,
The extension unit transmits and receives an address to be accessed, a command indicating the processing contents of the access target, and data related to the processing by a signal group transmitted through the shared signal line in a plurality of times.
2. The information processing apparatus according to claim 1, wherein the initialization processing unit determines whether or not the own device needs to be initialized based on the specific signal transmitted through the shared signal line. Expansion unit. The both connectors are provided with terminals for cascading the information processing apparatus or other extension unit connected to one of the two connectors, the own device, and another extension unit connected to the other. And
Based on the address information notified from the information processing apparatus or other expansion unit in the previous stage, the position of the address area of the own apparatus in the address space of the information processing apparatus is determined, and the predetermined occupation of the own apparatus is determined. 3. An address area determining means for changing the address information according to the size of the address area to be transmitted and sending the address information to the other extension unit at the next stage. Expansion unit for information processing equipment.

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