JP2005110818A - Game machine - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To carry out the processing of starting a controller normally at the closing of a power source or in the return of the power source back. <P>SOLUTION: A game machine is provided with a CPU (central processing unit) and a memory for temporarily storing data. When electric power is supplied to the game machine from an external power source, the power is supplied to the CPU and a memory from a power source circuit. On the other hand, when the supply of the power to the game machine from the external power source is shut down, the power is supplied to the memory from a backup power source. At the closing of the power source or in the return of the power source to the normal condition, the CPU writes data into a prescribed address of the memory (S4) and the data is read out of the prescribed address of the memory (S6) to determine whether the data written at the step S4 coincides with the data read out at the step S6 (S8). The steps S4 and S6 are repeated until the coincidence of the data is determined at the step S8, and when the coincidence of the data is found at the step S8, a normal startup processing is started (after S10). <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a gaming machine having a backup power source that backs up data stored in a memory at the time of power interruption such as a power failure, and more specifically, control when power is turned on or power is restored regardless of the remaining capacity of the backup power source. The present invention relates to a technique for starting up a device correctly.

A gaming machine disclosed in Patent Document 1 is known as a gaming machine having a function of backing up data stored in a memory at the time of power interruption such as a power failure.
The gaming machine disclosed in Patent Document 1 includes a main control board (having a CPU, ROM, and RAM) that controls the progress of the game, and a payout control board (having a CPU, ROM, and RAM) that controls payout of prize balls. . The main control board and the payout control board are connected to a power supply circuit. The power supply circuit converts the power supplied from the external power supply into a predetermined voltage and supplies it to each control board.
A backup power supply constituted by a capacitor is connected to the RAM of the main control board and the RAM of the payout control board. The capacitor for the backup power supply stores power while power is supplied from the power supply circuit to each control board (that is, while power is supplied from the external power supply to the gaming machine), and from the external power supply to the gaming machine. When the power supply is cut off, the stored power is supplied to the RAM of the main control board and the RAM of the payout control board. As a result, the data stored in the RAM of each control board is retained even while the power supply to the gaming machine is shut off.

By the way, the data stored in the RAM of the main control board and the RAM of the payout control board includes data relating to award balls to be paid out to the player, and is closely related to the profit of the player. For this reason, in order to reliably protect the player's profit, it is necessary to reliably supply power to the RAM from the backup power source until the power source is restored after the power source is shut off.
On the other hand, the recovery period from when the power is shut off until the power is restored varies depending on the cause of the power failure. For this reason, when designing a backup power supply, it is necessary to assume a longer recovery period. Further, the capacitor constituting the backup power source has a large variation for each component, and further, since charging and discharging are repeated every day, the charging capacity gradually decreases due to deterioration.
For these reasons, a capacitor having a large capacity is used as a capacitor for a backup power supply (the gaming machine of Patent Document 1 uses a capacitor capable of storing and holding data for about three days from the time of power-off. .)

However, when the capacity of the capacitor for the backup power supply increases, the rising speed of the capacitor voltage (that is, the voltage applied to the RAM) when the power is turned on becomes slow. For this reason, if the game machine is not turned on for a long time and the power is turned on when the remaining capacity of the capacitor is reduced, the voltage applied to the RAM becomes the operable voltage of the RAM. It takes a long time.
Therefore, before the voltage applied to the RAM becomes the operable voltage of the RAM, the voltage of the control power supply supplied to the CPU of each control board may be higher than the operable voltage of the CPU. If the CPU starts processing before the voltage applied to the RAM becomes the operable voltage of the RAM, data cannot be stored in the RAM, and the CPU processing will not start normally.
Therefore, in the gaming machine of Patent Document 1, a monitoring circuit for monitoring the voltage of the backup power supply is provided, and the voltage of the backup power supply is monitored by the monitoring circuit when the power is turned on or when the power is restored. The CPU of each control board starts processing when the value exceeds.
Japanese Patent No. 3120754

In the gaming machine of Patent Document 1 described above, by providing a monitoring circuit that monitors the backup power supply, the CPU of each control board can start processing normally when the power is turned on or when the power is restored.
However, since the gaming machine is provided with a monitoring circuit for monitoring the backup power source, there is a problem that the cost increases accordingly. In particular, the rise time of the backup power supplied to the RAM is longer than the rise time of the control power supplied to the CPU when the gaming machine has not been turned on for a long time. Therefore, if the amusement store is open almost every day (that is, the power is turned off the night after the business is closed and the power is turned on before the next morning, the power supply is used for backup power) The remaining capacity of the capacitor is sufficient, and the above phenomenon hardly occurs. For this reason, it is unacceptable in terms of cost effectiveness to provide a monitoring circuit for a situation that can rarely occur and to increase the cost.

  The present invention has been made in view of the above-described circumstances, and an object of the present invention is to provide a control device at the time of power-on or power-up according to the remaining capacity of the backup power supply without providing a monitoring circuit for monitoring the backup power supply. It is an object of the present invention to provide a gaming machine that enables normal startup processing.

The gaming machine according to the present application created to solve the above problems is connected to a CPU, a memory accessible to the CPU, and temporarily connected to an external power source, and connected to the CPU and the memory. A power supply circuit to be supplied; and a backup power supply disposed between the power supply circuit and the memory. Data stored in the memory by supplying the power stored in the backup power supply while power is being supplied from the power supply circuit to the memory is supplied to the memory when the power supply from the power supply circuit to the memory is cut off. Is held only while the stored power is consumed.
In this gaming machine, when power is turned on or power is restored, the CPU (1) writes data to a predetermined address in the memory, (2) reads data from the predetermined address in the memory, (3 ) Determining whether or not the data written in (1) and the data read in (2) match, and until the data is determined to match in the step (3) The steps (1) and (2) are repeated, and when it is determined that the data match in the step (3), a normal start-up process is started (means 1).

(Operation and effect of gaming machine described in means 1) In this gaming machine, when power is turned on or power is restored, the CPU first writes data to a predetermined address in the RAM, and then reads and writes data from the address. It is determined whether the read data matches the read data. That is, instead of indirectly determining that the RAM can normally operate when the power supplied to the RAM becomes the operable voltage of the RAM, it is directly determined whether or not the RAM can normally perform the storage operation. Then, if the RAM is capable of normal storage operation, normal startup processing is started. Therefore, since normal startup processing is started after confirming that the RAM can normally perform the storage operation, the processing can be normally started without providing a monitoring circuit for monitoring the power supplied to the RAM. Can be raised.

  In the gaming machine according to means 1, the CPU performs the steps (1) to (3) for a plurality of addresses in the memory, and performs all the determinations of (3) performed for each address. It is preferably programmed to start a normal start-up process when it is determined that the data match (means 2).

(Operation and effect of the gaming machine described in the means 2) In this gaming machine, the steps (1) to (3) are performed on a plurality of addresses of the memory, so that the RAM can be normally stored. It can be confirmed more reliably.

  In the gaming machine according to the first aspect, the CPU starts normal startup processing when a result that the data matches is obtained a plurality of times in succession in the determination of the step (3). (Means 3).

(Operation and effect of the gaming machine described in the means 3) In this gaming machine, after the result of the determination of the step (3) that the RAM is normally capable of storing operation is obtained a plurality of times, Start normal startup processing. Therefore, the CPU processing can be started up more reliably.

  Hereinafter, an embodiment in which the present invention is applied to a control board (for example, a main control board, a payout control board) installed in a pachinko machine will be described with reference to the drawings. FIG. 1 is a diagram showing a one-chip microcomputer mounted on a control board and a power supply line to the one-chip microcomputer. As shown in FIG. 1, a one-chip microcomputer 10 (hereinafter simply referred to as a microcomputer 10) mounted on a control board is equipped with a CPU 20, a ROM (not shown), and a RAM 22. The CPU 20 is connected to the ROM and RAM 22 so as to be accessible. The CPU 20 performs various game processes according to the program stored in the ROM, and at that time, performs a data write operation and a data read operation on the RAM 22.

  Control power Vc (+5 V) is supplied from the power supply circuit (not shown) to the CPU 20 of the microcomputer 10 described above. The control power supply Vc is produced by a power supply circuit disposed on the back surface of the pachinko machine. That is, the power supply circuit is connected to an external AC power supply, and converts the AC power supplied from the external AC power supply to the pachinko machine into a + 5V DC power supply.

On the other hand, a capacitor 18 for backup power and a control power source Vc are connected to the RAM 22 of the microcomputer 10. Specifically, the control power supply Vc is connected to the ground via the resistor 12 (current limiting resistor to the Zener diode) and the Zener diode 14. The intermediate point between the resistor 12 and the Zener diode 14 is connected to the RAM 22 via the backflow preventing diode 16. One end of a capacitor 18 is connected to an intermediate point between the diode 16 and the RAM 22, and the other end of the capacitor 18 is connected to the ground.
Therefore, the control power supply Vc (+5 V) is stepped down to a predetermined voltage (+3.3 V) by the Zener diode 14. Capacitor 18 is charged by the stepped-down control power supply Vc, the voltage across the capacitor 18 (hereinafter, referred to as the capacitor voltage _{V B)} is applied to the RAM 22. While the control power supply Vc is normal, power is supplied from the control power supply Vc to the RAM 22 by the amount of power consumed by the RAM 22. On the other hand, when the power supply from the control power supply Vc is stopped due to a power failure or the like, the power stored in the capacitor 18 is supplied to the RAM 22. For this reason, even if the power is cut off due to a power failure or the like, the data in the RAM 22 is stored and held for the amount of power stored in the capacitor 18. In the present embodiment, the data stored in the capacitor 18 can be stored and held for about three days from the time of power-off by the power stored in the capacitor 18.

Here, a change with time of the control power supply Vc and a change with time of the capacitor voltage V _B (voltage applied to the RAM 22) when the power is turned on (or when the power is restored) will be described. Figure 2 is a time course of the control power supply Vc (lower graph), showing together the aging of the capacitor voltage V _B (upper graph).
As shown in FIG. 2, the control power supply Vc gradually rises from 0 V when the pachinko machine is turned on. On the other hand, the capacitor voltage V _B has a voltage corresponding to the remaining capacity of the capacitor 18 when the power is turned on, and gradually rises from that voltage. As is apparent from the above description, the capacitor voltage V _B increases as the charge amount of the capacitor 18 increases. Since the capacitor 18 has a large capacity and is charged via the resistor 12, the charging takes time. Therefore, the voltage variation rate of the capacitor voltage V _B (voltage rise rate per unit time) is small compared with the voltage change rate of the control power supply Vc (voltage rise rate per unit time). Therefore, when the power is on in a state where the remaining capacity of the capacitor 18 is relatively still, if it control power supply Vc rises from the rise of the capacitor voltage V _B of the (power-on in FIG. (1) ), the power-on in a state where the capacitor 18 is fully discharged is performed, when the control power supply Vc before rises capacitor voltage V _B rises (power-on in FIG. 2). For this reason, if the power-on reset of the CPU 20 is performed when the control power supply Vc rises, the RAM 22 may not be operable when the CPU 20 starts processing.

Therefore, when the power-on reset is performed, the CPU 20 of the present embodiment first confirms whether or not the RAM 22 is operable, and performs normal startup processing after the confirmation. FIG. 3 shows a flowchart of processing at the time of power-on reset of the CPU 20 (that is, when the power to the pachinko machine is turned on).
As shown in FIG. 3, when the power-on reset is performed, the CPU 20 first performs initialization processing such as access permission of the built-in RAM (S2). Next, data is written to a predetermined address provided for determination in the work area of the RAM 22 (S4), and then data is read from the written address (S6). Then, it is determined whether or not the data written in step S4 matches the data read in step S6 (S8).
If the data written in step S4 and the data read in step S6 do not match [NO in step S8], the RAM 22 is unstable (that is, the capacitor voltage V _B is less than the operable voltage of the RAM 22). Therefore, the process returns to step S4 and the processing from step S4 is performed.
Conversely, if the data written in step S4 matches the data read in step S6 (YES in step S8), the RAM 22 is in a stable state, so the determination area in the RAM 22 is cleared, and the step Proceed to S10. In step S10, it is determined whether or not the RAM clear switch is turned on (S10). A RAM clear switch provided for each gaming machine is a switch that is operated by a store clerk or the like at a game store when the power is turned on, and is turned on when data stored in the RAM 22 is cleared.

If the RAM clear switch is ON [YES in step S10], the RAM 22 is cleared (S14), and then the process proceeds to the main process (S16). Accordingly, when the RAM clear switch is operated, the RAM 22 is cleared, and the pachinko machine starts processing from the initial state. In addition, the main process of step S16 is a process periodically performed when a game is performed in a pachinko machine, and is the same process as a process performed in a conventionally known pachinko machine.
On the other hand, if the RAM clear switch is not turned on [NO in step S10], it is first confirmed by a checksum whether the work area of the RAM 22 is normal (S14). Next, if the RAM 22 is not normal [NO in step S12], the RAM 22 is cleared (S14), and the process proceeds to the main process in step S16. Conversely, if the RAM 22 is normal (YES in step S12), the process proceeds to the main process in step S16. Therefore, the processing is resumed using the data stored and held in the RAM 22 while the power is shut off.

As is apparent from the above description, in the present embodiment, the CPU 20 that has been power-on reset by turning on the power first checks whether or not the write operation and the read operation to the RAM 22 are possible, and the RAM 22 is operable. Only when the normal startup process (in FIG. 3, the processes other than steps S2 to S8 according to the present invention, for example, S10 to S14 and setting of a default value in a game control (not shown) to a predetermined address) , Setting of default state of electronic components such as CPU I / F and peripheral IC). Therefore, if the capacitor 18 is powered on is performed in the state of full discharge (i.e., when the rise of the capacitor voltage V _B is slower than the rise of the control power supply Vc) But a successful start-up process of the CPU20 be able to.
In the present embodiment, the CPU 20 directly checks whether or not the RAM 22 is operable. If the RAM 22 is operable, the CPU 20 quickly starts up. Therefore, the start-up process can be started at an optimal timing according to the remaining capacity of the capacitor 18 without being affected by hardware aging such as deterioration of the capacitor 18.
Further, CPU 20 in order to quickly start startup process when the RAM22 are operable, to complete even a short time start-up process over the prior art (technique for monitoring the value of the capacitor voltage V _B) Can do. That is, when the CPU 20 is power-on reset when the capacitor voltage V _B exceeds a predetermined threshold, the threshold of the capacitor voltage V _B (threshold for determining whether to power-on the CPU 20) is set in the RAM 22 for safety. It must be set higher than the operable voltage. For this reason, even if the RAM 22 becomes operable, the CPU 20 may not be immediately reset to power-on. However, in this embodiment, in order to determine whether or not the RAM 22 can be operated by directly accessing the RAM 22, the start-up process is started immediately after the RAM 22 becomes operable. For this reason, a pachinko machine can be quickly launched even compared with the conventional technology.
Further, in the present embodiment, it is not necessary to provide a monitoring circuit for monitoring the capacitor voltage V _B, to confirm whether the RAM22 by executing the diagnostic program by CPU20 has become operational. Therefore, the cost increase can be suppressed by the amount that the monitoring circuit is not provided. Further, since there is no need to provide a monitoring circuit, it is not necessary to allocate a special port or the like for receiving a signal from the monitoring circuit to the microcomputer 10.

  As mentioned above, although one Embodiment of this invention was described in detail, this is only an illustration and does not limit a claim. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.

(1) Although the above-described embodiment is an example in which the present invention is applied to one control board, the present invention can also be applied to each of a plurality of control boards equipped in a gaming machine. For example, the present invention can be applied to each of a main control board and a payout control board installed in a pachinko machine.
Here, in order for the payout control board to reliably receive a game command such as a payout command transmitted from the main control board, the main control board needs to pay out the payout command, etc. after the payout control board has completed the startup process. It is necessary to send a game command. On the other hand, when the power is turned on, the CPU of each control board repeatedly checks whether or not the operation of the RAM is possible, and the timing at which the CPU of each control board completes the startup process varies depending on the remaining capacity of the backup power supply.
Therefore, the main control board needs to determine whether or not the payout control board has completed the startup process. Further, when any of the control boards does not finish the RAM confirmation process, it is necessary to notify a store clerk or the like of the game store. In order to satisfy this requirement, the configuration shown in FIG. 4 can be employed.

FIG. 4 is a diagram for explaining processing between both control boards when the power is turned on when the present invention is applied to the main control board and the payout control board. As shown in FIG. 4, the main control board 22 transmits a check command to the payout base control board 24 when the operation check of the RAM at the time of power-on is completed and the startup process is completed. Next, the process waits until an acknowledgment signal (ACK signal) output from the payout control board 24 is received. If the ACK signal is not received even after a predetermined time has elapsed since the check command was transmitted, the main control board 22 outputs the check command toward the payout control board 24 again. Thereafter, the main control board 22 outputs a check command to the payout control board 24 every predetermined time until receiving the ACK signal. When an ACK signal is received from the payout control board 24, a game process for a pachinko game is started. Therefore, the game command transmitted from the main control board 22 is surely received by the payout control board 24.
On the other hand, a state display LED 26 for displaying the state of the pachinko machine is connected to the payout control board 24. The payout control board 24 waits when the operation check of the RAM at the time of power-on is completed and the start-up process is completed. When a check command is received from the main control board 22, the payout control board 24 turns on the status display LED 26 and outputs an ACK signal to the main control board 22.
As is clear from the above description, when the main control board 22 cannot complete the RAM operation check, the check command is not output from the main control board 22. For this reason, the status display LED 26 is not lit. On the other hand, when the payout control board 24 cannot complete the RAM operation check, the payout control board 24 cannot receive the check command from the main control board 22, and the status display LED 26 is not lit. Therefore, if both the control boards 22 and 24 do not rise normally, the status display LED 26 is not turned on. For this reason, the state of the pachinko machine can be determined based on whether or not the state display LED 26 is lit.

(2) In the above-described embodiment, whether the RAM is operable by writing data to one address of the RAM, then reading the data from the address, and confirming whether or not both data match. Judged whether or not. However, the RAM operation check may be performed for a plurality of addresses in the RAM. That is, the CPU writes data, reads data, and determines whether or not they match each other for a plurality of addresses in the RAM, and when all of the determinations made for each address match, Subsequent startup processing may be started.
For example, the CPU first writes data to the address A of the RAM, reads the data, and determines whether the two data match. Next, data writing to the RAM address B, data reading, and whether or not the two data match are determined. The same processing is performed for the address C in the RAM. Then, if the determination made for each of the RAM addresses A, B, and C is correct, the subsequent processing is started. With this configuration, it is possible to reliably determine whether or not the RAM is operable, so that the CPU processing can be started more reliably.
In each of the above-described configurations, a timer may be further waited for a predetermined time after it is determined that the RAM is operable, and then a normal startup process may be started. With this configuration, the CPU operation can be started more reliably.
Furthermore, the process of determining whether the written data and the read data match is repeated, and when the result that the written data matches the read data continues multiple times, normal startup processing is started. You may make it do. Even with such a configuration, normal startup of the CPU can be ensured.

(3) In the embodiment shown in FIG. 1, the present invention is applied to a case where the control voltage of the CPU and the control voltage of the RAM are different, but the control voltage of the CPU and the control of the RAM as shown in FIG. The present invention can also be applied to the case where the voltage is the same.
In the pachinko machine, in order to make it as difficult as possible to illegally rewrite the contents of the backed up RAM, a backup capacitor 18 may be provided on another substrate 30 as shown in FIG. Therefore, noise enters from the harness connecting the backup capacitor 18, which may affect the contents of the RAM 22. Therefore, in order to remove noise that may enter from the power supply terminal of the RAM 22, a filter including a resistor 23 and a capacitor 29 is provided as shown in FIG.
In such a case, when the characteristics of the resistor 23 and the capacitor 29 constituting the filter are changed depending on the magnitude of noise to be removed, etc., the relationship between rising edges of the power supplied to the CPU 20 and the RAM 22 becomes as shown in FIG. There is. Therefore, by applying the present invention, the CPU 20 directly confirms whether or not the RAM 22 is operable, and if the RAM 20 is operable, the CPU 20 and the RAM 22 are transferred to the next process only when the process proceeds to the next process. The characteristic values of the resistor 23 and the capacitor 29 can be determined without worrying about the rise relationship of the power supply to be supplied.

(4) In the embodiment shown in FIG. 1, as shown in FIG. 3, the CPU determines whether or not the RAM clear switch has been pressed when the power is turned on. It was the structure which clears the memory information. However, as a method of clearing information stored in the RAM, a switch is provided in parallel with the backup capacitor, and by turning on this switch, the charge of the backup capacitor is forcibly consumed and the information stored in the RAM is cleared. It can also be taken.
When such a method is employed, the relationship between the power supplied to the CPU and the power supplied to the RAM when the power is next turned on is as shown in FIG. However, even in such a case, by applying the present invention, since the CPU directly checks the operation of the RAM and then proceeds to the next process, the CPU can be started up normally.

(5) Each embodiment described above is an example in which the present invention is applied to a pachinko machine. However, the present invention can be applied to a gaming machine including a control device having a backup function, such as a slot machine. It can also be applied to other gaming machines.

  In addition, the technical elements described in the present specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings achieves a plurality of objects at the same time, and has technical utility by achieving one of the objects.

The figure which shows the one-chip microcomputer mounted in the control board of this embodiment, and the power supply line to this one-chip microcomputer. And aging of the control power supply Vc, shows together and aging of the capacitor voltage V _B. The flowchart which shows the process sequence at the time of the power-on reset of CPU. The figure for demonstrating the process of each control board at the time of power activation, when the technique of this application is applied to a main control board and a payout control board. The figure which shows the whole structure of the other form to which the technique of this application is applied.

Explanation of symbols

10. One-chip microcomputer 12. Resistance 14. Zener diode 16. Diode 18. Capacitor 20. CPU
22..RAM

Claims (1)

CPU,
A memory that is accessible to the CPU and temporarily stores data;
A power supply circuit connected to an external power supply and supplying power to the CPU and the memory;
A backup power supply arranged between the power supply circuit and the memory,
The power stored in the backup power supply while power is being supplied from the power supply circuit to the memory is supplied to the memory when the power supply from the power supply circuit to the memory is cut off, so that the data stored in the memory is predetermined. A gaming machine that only holds time,
When the power is turned on or restored, the CPU (1) writes data to a predetermined address in the memory, (2) reads data from the predetermined address in the memory, and (3) in (1) Determining whether or not the written data matches the data read in (2), and (1) and (2) until it is determined in the step (3) that the data match. The game machine is programmed to start normal startup processing when it is determined that the data match in the step (3).

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