JP2005109586A - Input processing circuit in ethernet switch - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize reduction in circuit scale of a shortest packet length monitor circuit for detecting and discarding an abnormality in the shortest packet length of a received packet, or the like, in an Ethernet switch. <P>SOLUTION: Registers in parallel arrangement provided in a shortest packet length monitor circuit and used for holding data during a waiting time for counting and recognizing abnormal packets having a packet length shorter than the shortest length are also used in FIFO for waiting reassembly of packet on the poststage. Packet discarding processing at the time of incomplete packet length is also used in a packet discarding circuit at the time of back pressure, parity detection in a coupling circuit for reassembling packets. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

The present invention is installed in an input processing unit of an Ethernet switch, and for an input Ethernet packet that is randomly input with a variable length size from a minimum of 64 bytes to a maximum of 1518 bytes, the packet length is equal to or greater than the minimum packet length defined by the Ethernet standard. This is related to a reduction in the size of the circuit configuration of the packet collection and monitoring circuit portion, which has a function of monitoring that and preventing the passage of ineligible packets of the shortest length or less.

  FIG. 8 is an overall configuration diagram of a conventional Ethernet switch.

In FIG. 8, reference numeral 100 denotes a switching processing unit, 200 denotes an interface card, and 300 denotes a physical port or other Ethernet switch.
In the Ethernet card 200, 210 is an input processing unit, 220 is an output processing unit, and 230 is an external interface unit that processes physical interface functions.

  FIG. 9 shows the internal configuration of the input processing unit 210.

  In FIG. 9, a packet having a length equal to or shorter than the shortest packet length is discarded without being regarded as an abnormal packet. In addition, when a waveform breakage occurs due to high-speed waveform transmission, the occurrence of an error in the entire packet occurs when the appearance interval of the head detection pulse i_SOP pulse of the packet used for packet length detection occurs at an interval less than the minimum packet length. It has a function that does not pass received packets.

In FIG. 9, 211 is a parallel / parallel conversion circuit that further converts a 32-bit parallel input packet frame into a 64-bit parallel output, 212 is a shortest packet length monitoring circuit related to the present invention, and 213 is a packet frame. A header / payload separation unit 214 for separating the header and the payload is a data FIFO for temporarily storing the payload, and has a 64-bit width and a maximum frame length packet holding function. 215 is a CAM (Content Addressable Memory) that stores the correspondence between the destination MAC address included in the received packet and the output port, and 216 accesses the CAM to determine the transmission port from the MAC address in the header, and for transmission The header processing unit 217 for generating a new header of the header 217 is a header FIFO for temporary storage of headers, and 218 is a coupling unit that combines the header and the payload again, generates a frame, and transmits the frame.
The combining unit 218 receives a back-pressure packet or a parity packet transmitted for suppressing traffic from the source Ethernet switch or the like when the destination Ethernet switch is congested, causing a buffer overflow or the like. And has a function of discarding the packet (blocking passage).

  FIG. 10 shows a conventional shortest packet length monitoring circuit 212 and a subsequent block. In FIG. 10, 11 is a FF for holding the start position detection pulse i_SOP of the received packet, 12 is a FF for holding the end position detection pulse i_EOP of the received packet, 13 is a FF for holding 64-bit parallel expanded data, 21 is a packet length measurement counter for received packets, 31 is a shift register for i_SOP delay, 32 is a shift register for i_EOP delay, 33 is a 64-bit parallel shift register for data delay, and 40 is a packet length measurement counter I_SOP and i_EOP are controlled according to the value of, and an error output is output when a packet shorter than the shortest packet length is detected from the output of the counter 21. The logic control circuit 51 is an error detection circuit 51. Error detection pulse hold FF, 52, re-hole i_SOP The hold FF 53 for outputting to the next stage as o-SOP is re-holding o_EOP, and the hold FF 54 for outputting to the next stage as o-EOP is a FF for holding data having a 64-bit width. , 60 is a subsequent block unit that performs block control so that data is not transmitted to the subsequent stage when the output of the hold FF 51 is an error detection output.

The post-stage block unit 60 includes all the post-stage circuits in the Ethernet input processing circuit, such as the separation unit 213, the data FIFO 214, and the coupling unit 218 in FIG.
In the normal state, the subsequent block unit outputs the packet start position detection pulse SOP, the end position detection pulse EOP, and parallel conversion data having a 64-bit width to the subsequent stage.
As is clear from FIG. 10, in the conventional shortest pulse length monitoring circuit, it is confirmed that the SOP and EOP pulses are normally detected during the period when the counter counts that the pulse length is equal to or shorter than the shortest pulse length. In the meantime, the received data must be held. For this reason, a parallel shift register 33 having a 64-bit width and a ten-stage configuration is required.
In this way, hold the Ethernet bucket for a minimum of 72 bytes (64 bits x 9), which is the sum of the 8-byte printable part and the 64-byte body part. Depending on the SOP and EOP detection results, packet rejection and post-transmission are performed. In order to decide, a delay register of 64 bits × (9 + 1) stages is required for the determination waiting time and the processing margin time.
In the conventional monitoring circuit for the shortest packet length, etc., the parallel shift register for waiting for the determination of the shortest packet length occupies nearly 80% of the total number of transistors, and no parallel register for waiting for determination is required. If possible, the circuit scale can be greatly reduced.

  The problem to be solved is a shortest packet length monitoring circuit for a received packet in an Ethernet switch, and a packet length monitoring circuit having a function equivalent to the conventional one even without a parallel shift register for reception data delay processing for waiting for the shortest packet length determination Is to provide.

  The present invention for solving the above-mentioned problems is as follows: “In the input processing circuit in the Ethernet switch, a counter that counts whether the received packet length is less than or equal to the shortest pulse length, a data FIFO that temporarily stores the data of the received packet, Combines the header and the data, and discards the data portion of the received packet read from the FIFO, the start instruction pulse of the received packet, and the end position pulse when the counter detects a received packet of the shortest length or less. An input processing circuit in an Ethernet switch characterized by having a circuit ”is provided.

According to the present invention, it is possible to eliminate the time-shifting shift register installed in the shortest pulse monitoring circuit of the conventional input processing circuit of the Ethernet switch, and the circuit scale of the entire input processing circuit can be reduced.

  An input processing circuit for an Ethernet switch according to the present invention is a multistage parallel register provided for the purpose of retaining data during a packet length check circuit in a monitoring circuit for packet length, etc. Can also be used as a queuing FIFO in the subsequent stage, thereby realizing a reduction in the circuit scale of the entire packet length monitoring circuit and input processing circuit.

A counter that counts whether the received packet length is less than or equal to the shortest pulse length, a data FIFO that temporarily holds the data of the received packet, and a header after rewrite processing are combined with the data. When detected, the data packet of the received packet read from the FIFO and a coupling circuit for discarding the start instruction pulse and end position pulse of the received packet are provided.

FIG. 1 shows a shortest packet length monitoring circuit and a subsequent block of the present invention.
In FIG. 1, 11 is a FF for holding the start position detection pulse i_SOP of the received packet, 12 is a FF for holding the end position detection pulse i_EOP of the received packet, and 13 and 34 are for holding 64-bit parallel expanded data. FF, 21 is a packet length measurement counter of the received packet, 31 is a shift register for i_SOP delay, 32 is a shift register for i_EOP delay, and 40 is less than the shortest packet length according to the value of the packet length measurement counter A logic control circuit 51 that outputs an Error signal at the same time and controls the passage of i_SOP and i_EOP, 51 is a logic control circuit 40, and holds error detection pulse FF 52 at the time of error detection, re-holds i_SOP, and -Hold FF 53 for output to the subsequent stage as SOP, re-hold i_EOP , Hold FF, 60 for outputting to the next stage as the O-EOP is subsequent block.

  In the normal state, the subsequent block unit outputs the packet start position detection pulse SOP, the end position detection pulse EOP, and parallel conversion data having a 64-bit width to the subsequent stage.

  As is apparent from FIG. 1, the shortest pulse detection circuit of the present invention omits the 10-stage 64-bit width shift register for counting the data length that the conventional shortest packet length detection circuit 212 of FIG. As a result, the circuit scale of the shortest packet length detection circuit is significantly reduced (about 1/5).

  FIG. 2 is a detailed view of the subsequent block of the present invention.

  In FIG. 2, 213 is a header / payload separator that separates a packet frame into a header and a payload, 214 is a data FIFO that temporarily stores SOP, EOP, and payload data. Has a holding function. 215 is a CAM (Content Addressable Memory) that stores the correspondence between the destination MAC address included in the received packet and the output port, and 216 accesses the CAM to determine the transmission port from the MAC address in the header, and for transmission The header processing unit 217 for generating a new header of the header 217 is a header FIFO for temporary storage of headers, and 218 is a coupling unit that combines the header and the payload again, generates a frame, and transmits the frame. Further, 218a in the sub-block configuration in the combining unit 218 performs read address designation from the data FIFO, header FIFO, etc., which are the buffer memory in the previous stage, reads out the data signals and header signals in a predetermined order, and sends them to the subsequent stage. A read selection circuit, 218b is a parity check circuit for simple error check in the packet data, 218c is a combination circuit that combines the data signal and header signal from the read selection circuit 218, and assembles and sends it to the original Ethernet packet, 218d An interrupt signal and Ethernet packet output selection processing circuit 219a by the user receives an instruction from the user, and a CPU processing unit 219b for sending various control signals such as an interrupt processing signal to the output selection processing circuit 218d, The latter stage Ethernet Receiving a backpressure signal from the output processing unit of the switch, back-pressure processing unit for performing the suppressing process in the output packet is.

  In FIG. 2, through the separation unit 213, a synchronization frame pulse FP_1 and an error signal ERR_1 signal at the time of detecting a packet shorter than the shortest length are applied to the coupling unit.

  The frame pulse FP_1 is a packet start confirmation pulse, and ERR_1 is applied with a delay of one clock.

  If no packet with the shortest length is detected, since the ERR_1 signal is not applied to the combination processing circuit 218c, the Ethernet packet read from the data FIFO 214 and the header FIFO and reassembled is sent to the output selection circuit 218. Then, it is output to the switch 100 as it is.

  When a packet shorter than the shortest length is detected, ERR_1 is applied to the combination processing circuit 218c, so that an Ethernet packet read from the data FIFO 214 and the header FIFO and reassembled is output at the prohibited gate. It is prohibited and is not output to the switch 100.

  As a result, in order to hold the received data while confirming that the SOP and EOP pulses have been detected normally, the parallel shift register 33 having a 64-bit width and a 10-stage configuration that the shortest pulse monitoring circuit has is not available. Necessary.

  Hereinafter, the operation of the shortest long pulse detection circuit 212 according to the present invention and the operation of the coupling processing circuit 218d in the coupling unit 218 will be described with reference to time charts showing basic operations.

  FIG. 3 is a time chart when a normal packet is received.

  In the figure, sr_sop, sr_ctr10, and sr_eop are output signals generated in the process in which the counter 21 and the logic control circuit 40 output the o_SOP, o_EOP, and Err signals as output signals upon receipt of the input signals i_SOP and i_EOP. Yes (the same applies to FIGS. 4 to 6).

  As shown in FIG. 3, since i_SOP and i_EOP detect the start position and end position of a packet at a time interval longer than the shortest packet, the logic control circuit 40 does not output an ERR signal.

  Therefore, the combination processing circuit 218 passes the Ethernet packet read from the data FIFO 214 and assembled together with the header portion as it is.

  FIG. 4 is a time chart when a packet is received that is shorter than the shortest packet length.

As shown in FIG. 4, when the counter detects that the interval between the start position i_EOP and the end position i_SOP is less than the shortest packet length, the logic circuit 40 outputs an ERR signal. In response to this ERR signal, the coupling processing unit circuit in the subsequent coupling unit 218 discards the error packet, the unnecessary synchronization instruction SOP, and EOP.

  This is realized by applying a prohibiting pulse for control to the prohibiting gate of the coupling processing circuit unit by an FP indicating a synchronization position with the packet and an Error signal applied with a delay of one clock.

  FIG. 5 is a time chart when the SOP abnormality occurs.

  Since the SOP cannot arrive at an interval equal to or shorter than the shortest pulse length, the logic circuit 40 also outputs an ERR signal in this case, and the combining processing unit 218c of the combining unit 218 passes the packet, SOP, and EOP. Is prohibited and disposed of.

  This SOP abnormality can be detected by being reset by the first SOP and resetting again before the value of the counter that has started counting reaches the count number of a predetermined minimum packet length.

  FIG. 6 is a time chart when EOP abnormality occurs.

  In the case of the example in FIG. 6, since EOP is received by mistake immediately after SOP and EOP are received at normal time intervals, there is no effect on the subsequent operation. Therefore, the EOP reception error in this example is ignored, the logic circuit 40 does not perform ERR output, and the reassembled received packet is sent to the switch 100.

If an error EOP occurs at a time position equal to or shorter than the shortest pulse length, the logic circuit 40 outputs an ERR signal, and the coupling processing unit 218c of the coupling unit 218 prohibits the passage of packets, SOP, and EOP. Dispose of it.
FIG. 7 is a flowchart for explaining the operation of the input processing unit of the present invention.

  In step S0, packet arrival (i_SOP detection) is continuously monitored. In step S1, when i_SOP is input, the counter 21 is once reset, takes a value of 0, and starts counting the pulse length. In step 2, upon receiving the count start in step S 1, the logic control circuit 40 starts monitoring the output of the counter 21. Case 1 is a normal case in which i_EOP arrives at a normal interval. In this case, no error pulse is generated, and the data pulse once written in the data FIFO 214 in step S3 in step S3. Is combined with the output of the header FIFO 217 and output from the output selection circuit 218d. Case 2 is a case where i_EOP arrives at an interval equal to or shorter than the shortest packet length. In this case, in step S4, the counter stops the counting operation, and in step S5, the logic control circuit 40 performs synchronization processing in the subsequent block. In addition to o_SOP and o_EOP, an error signal indicating that the input packet is an error packet having a length not more than the shortest length is output. In step S6, the combination processing circuit 218c to which the Error signal is applied prohibits the passage of the Ethernet packet combining the outputs of the data FIFO 214 and the header FIFO 217 by the prohibit gate, and discards the packet.

  Case 3 is a case where the i_SOP pulse arrives at an interval equal to or shorter than the shortest pulse length due to a waveform detection error or the like. In this case, the counter 21 is reset again before reaching the shortest packet length in step S6. Since this is not a normal operation, the logic control circuit 40 proceeds to step S5, outputs an error pulse, and in step S6, a packet discard process is performed by the connection processing circuit.

  Case 4 is a case where i_EOP occurs continuously at an interval equal to or shorter than the shortest pulse interval. In this case, since the previous i_EOP is normally received, it is ignored in step S8, and no error signal is output. Return to and continue monitoring.

  The circuit scale of the shortest pulse monitoring circuit unit in the input processing circuit of the Ethernet switch can be greatly reduced, and the apparatus can be reduced in size and power consumption.

3 is a shortest packet length monitoring circuit and a subsequent block of the present invention. It is detail drawing of the back | latter stage block of this invention. It is a time chart at the time of receiving a normal packet. It is a time chart at the time of packet reception shorter than the shortest packet length. It is a time chart at the time of SOP abnormality generation. It is a time chart at the time of EOP abnormality occurrence. It is operation | movement description flowchart of the input process part of this invention. It is a whole block diagram of the conventional Ethernet switch. This is an internal configuration of the input processing unit 210. This is a conventional shortest packet length monitoring circuit 212 and a subsequent block.

Explanation of symbols

11-14, 51-54 FF
21 counter 31 to 33 shift register 40 logical control circuit 100 switch 200 interface card 300 physical port or other Ethernet switch 210 input processing unit 220 output processing unit 230 external interface unit for processing physical interface function 212 shortest length packet monitoring circuit 60 subsequent stage Block 213 Separation unit 214 Data FIFO
215 CAM
216 Header processing unit 217 Header FIFO
218 coupling unit 218a read selection circuit 218b parity processing circuit 218c coupling processing circuit 218d output selection circuit

Claims (1)

In the input processing circuit in the Ethernet switch,
A counter that counts whether the received packet length is less than or equal to the shortest pulse length,
A data FIFO that temporarily holds the data of the received packet;
Header and data after rewrite processing,
And a combining circuit for discarding the data portion of the received packet read from the FIFO, the start instruction pulse of the received packet, and the end position pulse when a received packet having a length equal to or shorter than the shortest length is detected in the counter.
An input processing circuit in an Ethernet switch characterized by comprising:

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