JP2005109207A - Light emitting element and method of manufacturing the same - Google Patents

Light emitting element and method of manufacturing the same Download PDF

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JP2005109207A
JP2005109207A JP2003341760A JP2003341760A JP2005109207A JP 2005109207 A JP2005109207 A JP 2005109207A JP 2003341760 A JP2003341760 A JP 2003341760A JP 2003341760 A JP2003341760 A JP 2003341760A JP 2005109207 A JP2005109207 A JP 2005109207A
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Kazunori Hagimoto
和徳 萩本
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Shin Etsu Handotai Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing light emitting element by which a compound semiconductor layer containing a light emitting layer can be stuck surely to an element substrate through metallic layers, by suppressing the cracking of the compound semiconductor layer, particularly, the formation of cracks in the circumference of a junction alloy layer formed in the jointing interfaces of the compound semiconductor layer with the metallic layers, even when the compound semiconductor layer is thin and warped, or the like. <P>SOLUTION: The junction alloy layer 31 is formed on the second principal surface of the compound semiconductor layer 50 in a state where part of the layer 31 further cuts into the semiconductor layer 50 side than the second principal surface, and the remaining part of the layer 31 is protruded from the second principal surface. A laminate 130' is produced on the second principal surface of the semiconductor layer 50 having the alloyed jointing layer 31 by laminating the metallic layers 10a and 10b and element substrate 7 upon another, and the compound semiconductor layer 50 is stuck to the element substrate 7 through the metallic layers 10a and 10b by sticking the laminate 130' to the semiconductor layer 50 and heating the laminate 130' to a sticking temperature. The laminate 130' is pressed against the layer 50. Then the pressing for sticking is started at a temperature lower than the sticking temperature, and the temperature rise of the laminate 130' from the pressing starting temperature to the sticking temperature is started at timing delayed from the pressing timing. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

この発明は発光素子の製造方法に関する。   The present invention relates to a method for manufacturing a light emitting device.

特開2001−339100号公報JP 2001-339100 A

発光ダイオードや半導体レーザー等の発光素子において高輝度化を図ろうとした場合、素子からの光取出し効率が極めて重要となる。特許文献1をはじめとする種々の公報には、成長用のGaAs基板を除去する一方、補強用のSi基板(導電性を有するもの)を、反射用のAu層を介して除去面に貼り合わせる技術が開示されている。このAu層は反射率が高く、また、反射率の入射角依存性が小さいので、光取出し効率の向上を図る上で有利である。   When trying to increase the brightness of a light emitting element such as a light emitting diode or a semiconductor laser, the light extraction efficiency from the element is extremely important. In various publications including Patent Document 1, a growth GaAs substrate is removed, and a reinforcing Si substrate (having conductivity) is bonded to a removal surface through a reflective Au layer. Technology is disclosed. This Au layer has a high reflectivity, and since the dependency of the reflectivity on the incident angle is small, it is advantageous for improving the light extraction efficiency.

上記の方法においては、発光層部や電流拡散層を含む薄い化合物半導体層を、半導体や金属からなる素子基板に貼り合わせる工程が必須となる。一般に、発光素子に多用されるIII−V族化合物半導体は脆く欠けやすい特性を有しており、薄い化合物半導体層を素子基板に貼り合わせる際には、その貼り合わせの加圧力が不均一であると、該化合物半導体層に割れや欠けが極めて生じやすくなり、不良に直結する問題がある。こうした割れや欠けは、多数個の発光素子チップを一括形成する貼り合わせウェーハの状態で、目視確認できるようなマクロな割れ等ももちろん問題になるが、発光素子の性能という点では、次のようなミクロクラックの発生も影響が深刻である。   In the above method, a step of bonding a thin compound semiconductor layer including a light emitting layer portion and a current diffusion layer to an element substrate made of a semiconductor or metal is essential. In general, a group III-V compound semiconductor frequently used in a light-emitting element has a characteristic that it is brittle and easily chipped, and when a thin compound semiconductor layer is bonded to an element substrate, the pressure applied is not uniform. Then, there is a problem that the compound semiconductor layer is very easily cracked or chipped and directly connected to a defect. Such cracks and chips are of course also a problem of macro cracks that can be visually confirmed in the state of a bonded wafer in which a large number of light emitting element chips are collectively formed. The occurrence of micro cracks is also serious.

金属層と発光層部との間には、両者の接触抵抗を低減するために接合合金化層を配置する必要がある。この接合合金化層は、発光層部への金属層の貼り合わせ面に、AuGeNi合金等からなる接合金属層を分散形成し、次いで熱処理することにより発光層部をなす化合物半導体と合金化して接合合金化層とする。そして、この発光層部の主表面を接合合金化層とともに金属層で覆い、素子基板と重ね合わせて加圧及び加熱を行ない貼り合わせると、接合合金化層の周囲部分をなす発光層部領域にミクロクラックが多数発生することがある。このようなミクロクラックは、発光駆動時の導通路をなす接合合金化層を起点に形成されるため、接触抵抗の増大や電流リークにつながる可能性がある。また、通電時に電流が集中してクラック伝播が進みやすく、電流リークが次第に顕著になって、発光強度の経時的な劣化も引き起こしやすい。化合物半導体層には、成長用の基板との格子定数の不一致や線膨張係数の相違等により反りを生じることがあるが、上記のような不具合は、こうした反りにより一層発生しやすい傾向にある。また、貼り合わせ時において発光層部内の温度分布により熱応力を生じている場合にも、該不具合が助長されやすい傾向にある。   In order to reduce the contact resistance between the metal layer and the light emitting layer portion, it is necessary to dispose a bonding alloyed layer. This bonding alloyed layer is formed by dispersing a bonding metal layer made of an AuGeNi alloy or the like on the bonding surface of the metal layer to the light emitting layer portion, and then alloying with the compound semiconductor forming the light emitting layer portion by heat treatment. Alloyed layer. Then, the main surface of the light emitting layer part is covered with a metal layer together with the bonding alloying layer, and is bonded to the element substrate by applying pressure and heating to form a light emitting layer part region surrounding the bonding alloying layer. Many microcracks may occur. Such micro cracks are formed starting from a bonded alloying layer that forms a conduction path during light emission driving, and thus may increase contact resistance and current leakage. In addition, current is concentrated during energization and crack propagation is likely to proceed, current leakage gradually becomes more prominent, and light emission intensity is likely to deteriorate over time. The compound semiconductor layer may be warped due to a mismatch in lattice constant with the growth substrate, a difference in linear expansion coefficient, or the like, but the above-described defects tend to be more likely to occur due to such warpage. In addition, when the thermal stress is generated due to the temperature distribution in the light emitting layer at the time of bonding, the defect tends to be promoted.

本発明の課題は、発光層部を含む化合物半導体層が薄く、また反り等を生じている場合であっても、化合物半導体層の割れ、特に、金属層との接合界面に形成された接合合金化層周囲におけるクラック形成を抑制しつつ、素子基板と化合物半導体層との金属層を介した貼り合わせを確実に行なうことができる発光素子の製造方法と、該本発明の製造方法によってはじめて実現可能となる発光素子であって、金属層を介して素子基板と化合物半導体層とが貼り合わされた構造を有し、接合合金化層の周囲における化合物半導体層へのクラック形成を低減することにより、接触抵抗が低くしかも長期にわたって良好な発光強度を維持することができる発光素子とを提供することにある。   The problem of the present invention is that even when the compound semiconductor layer including the light emitting layer portion is thin and warps, the compound semiconductor layer is cracked, in particular, a bonded alloy formed at the bonding interface with the metal layer. A method for manufacturing a light-emitting element capable of surely bonding the element substrate and the compound semiconductor layer through the metal layer while suppressing the formation of cracks around the insulating layer, and can be realized only by the manufacturing method of the present invention A light emitting device having a structure in which an element substrate and a compound semiconductor layer are bonded via a metal layer, and reducing contact formation by reducing the formation of cracks in the compound semiconductor layer around the bonded alloyed layer. An object of the present invention is to provide a light emitting element having low resistance and capable of maintaining good light emission intensity over a long period of time.

課題を解決するための手段及び発明の効果Means for Solving the Problems and Effects of the Invention

本発明の発光素子の製造方法は、発光層部を有する化合物半導体層に金属層を介して素子基板が貼り合わされた発光素子を製造するためのものであり、
化合物半導体層の第二主表面に金属層と素子基板とを重ね合わせた積層体を作成し、該積層体を第一加圧部材と第二加圧部材との間にて貼り合わせ加圧しつつ貼り合わせ温度に加熱することにより、化合物半導体層と素子基板とを金属層を介して貼り合わせるとともに、
貼り合わせ温度よりも低温にて貼り合わせ加圧を開始する一方、該加圧開始時の温度から貼り合わせ温度に到達するまでの積層体の昇温を、当該加圧開始よりも遅れたタイミングにて開始することを特徴とする。
The method for producing a light emitting element of the present invention is for producing a light emitting element in which an element substrate is bonded to a compound semiconductor layer having a light emitting layer part via a metal layer,
A laminated body in which a metal layer and an element substrate are superimposed on the second main surface of the compound semiconductor layer is created, and the laminated body is bonded and pressed between the first pressure member and the second pressure member. By heating to the bonding temperature, the compound semiconductor layer and the element substrate are bonded via the metal layer,
While starting the laminating pressurization at a temperature lower than the laminating temperature, the temperature rise of the laminate from the temperature at the start of pressurization until reaching the laminating temperature is delayed at a timing later than the start of the pressurization. It is characterized by starting.

化合物半導体層を金属層を介して素子基板に貼り合わせる際に、その貼り合わせ温度への昇温時において温度分布が安定化しないうちに、貼り合わせの設定圧力に向けた昇圧を急速に行なうと、脆い化合物半導体層に割れやクラックが生じる場合がある。貼り合わせのために介在する金属層は、加熱状態で加圧されると塑性流動を起こす傾向にあるが、昇圧が過度に急速に行なわれると該塑性流動が圧力上昇に追従しきれず、加圧力の不均一を招きやすくなる。このような加圧力の不均一は化合物半導体層に反りが生じていると一層著しくなる。そして、貼り合わせ温度への昇温時に生ずる積層体の温度分布不均一の影響(例えば、熱的な応力分布の発生など)がこれに重なることで、化合物半導体層への割れが助長されるものと考えられる。   When a compound semiconductor layer is bonded to an element substrate via a metal layer, if the temperature distribution is not stabilized at the time of raising the temperature to the bonding temperature, the pressure is rapidly increased to the set pressure of the bonding. In some cases, the brittle compound semiconductor layer is cracked or cracked. The metal layer intervening for bonding tends to cause plastic flow when pressurized in a heated state, but if the pressure is increased excessively rapidly, the plastic flow cannot fully follow the pressure rise, and the applied pressure is increased. It becomes easy to invite non-uniformity. Such non-uniformity of the applied pressure becomes more significant when the compound semiconductor layer is warped. And the effect of non-uniform temperature distribution of the laminate (for example, generation of thermal stress distribution) that occurs when the temperature rises to the bonding temperature overlaps with this, which promotes cracks in the compound semiconductor layer it is conceivable that.

また、貼り合わせに先立って化合物半導体層側と素子基板側とに金属層を振り分けて配置し、化合物半導体層側の金属層と素子基板側の金属層とを貼り合わせる場合、貼り合わせ温度への加熱(特に大気中での加熱)に伴う種々の要因により、両金属層の貼り合わせ面が酸化や変質を受けることがある。しかし、上記の方法を採用すると、両金属層を重ねて加圧密着させた後、加圧開始時点の温度から最終的な貼り合わせ温度までの昇温を開始するようにしたから、各金属層の貼り合わせ面の酸化や変質の影響を軽減でき、強固な貼り合わせ状態を容易に得ることができる。   Further, prior to bonding, when the metal layers are distributed and arranged on the compound semiconductor layer side and the element substrate side, and the metal layer on the compound semiconductor layer side and the metal layer on the element substrate side are bonded together, Due to various factors accompanying heating (particularly heating in the atmosphere), the bonded surfaces of both metal layers may be oxidized or altered. However, when the above method is adopted, after the two metal layers are stacked and press-contacted, the temperature rise from the temperature at the start of pressurization to the final bonding temperature is started. The effect of the oxidation and alteration of the bonding surface can be reduced, and a strong bonding state can be easily obtained.

なお、加圧開始時の積層体の温度は室温(例えば20℃前後)であってもよいし、上記本発明の効果が損なわれない範囲で室温よりも高温に設定することもできる。   The temperature of the laminate at the start of pressurization may be room temperature (for example, around 20 ° C.), or may be set to a temperature higher than room temperature as long as the effects of the present invention are not impaired.

より具体的な方法の第一は、化合物半導体層の第二主表面に、該化合物半導体層との接触抵抗を低減する合金成分を含有した接合金属層を分散形成して合金化熱処理することにより、該接合金属層と化合物半導体層とが合金化した接合合金化層を、一部が第二主表面よりも化合物半導体層側に食い込み、残余の部分が第二主表面から突出した形態で形成し、
接合合金化層の形成された化合物半導体層の第二主表面に金属層と素子基板とを重ね合わせた積層体を作成し、該積層体に対する貼り合わせ加圧を一定の設定圧力にて行なうとともに、
設定圧力に向けた昇圧の途上で、設定圧力よりも低い中間圧力にて昇圧を中断することにより該中間圧力を保持した後、昇圧を再開することを要旨とする。
The first of the more concrete methods is to disperse and form a bonding metal layer containing an alloy component that reduces contact resistance with the compound semiconductor layer on the second main surface of the compound semiconductor layer, and then heat-treat with the alloy. The joining alloyed layer in which the joining metal layer and the compound semiconductor layer are alloyed is formed in such a manner that a part of the joining alloying layer bites into the compound semiconductor layer side of the second main surface and the remaining part protrudes from the second main surface. And
A laminated body in which a metal layer and an element substrate are superposed on the second main surface of the compound semiconductor layer on which the bonded alloying layer is formed is formed, and bonding pressure is applied to the laminated body at a constant set pressure. ,
The gist is to resume the pressure increase after maintaining the intermediate pressure by interrupting the pressure increase at an intermediate pressure lower than the set pressure during the pressure increase toward the set pressure.

本発明者が検討したところ、貼り合わせ温度への昇温時において温度分布が安定化しないうちに、貼り合わせの設定圧力に向けた昇圧を急速に行なうと、化合物半導体層の特に接合合金化層の周囲にミクロクラックが生じやすくなることがわかった。すなわち、昇圧が過度に急速となったときの金属層の塑性流動の遅れによる、加圧力の不均一(さらには化合物半導体層の反り)の影響が、積層体の温度分布不均一の影響と重なると、荷重集中しやすい接合合金化層の周囲では、脆い化合物半導体へのミクロクラック発生がより助長されやすくなると考えられる。   As a result of investigation by the present inventor, when the temperature distribution is not stabilized at the time of raising the temperature to the bonding temperature and the pressure is rapidly increased toward the set pressure of the bonding, the compound semiconductor layer, in particular, the bonded alloyed layer. It was found that microcracks are likely to occur around That is, the influence of non-uniform pressure (and warping of the compound semiconductor layer) due to the delay of plastic flow of the metal layer when the pressure is excessively rapid overlaps with the non-uniform temperature distribution of the laminate. It is considered that the generation of microcracks in the brittle compound semiconductor is more facilitated around the bonded alloyed layer where the load is likely to concentrate.

そこで、上記方法においては、昇圧開始後において、最終的な設定圧力よりも低い中間圧力に到達したら、そこで昇圧を一旦中断し、該中間圧力を所定の時間だけ保持するようにした。つまり、中間圧力への保持により設定圧力までの昇圧を作為的に遅らせることで、積層体の温度分布を安定化させるためのいわば時間稼ぎを行なうことができ、ひいては温度分布不均一による不都合な応力発生等を抑制することができる。その結果、目視確認できるようなマクロな割れはもちろん、接合合金化層の周囲における化合部半導体層へのミクロクラック発生も効果的に抑制することができるようになる。   Therefore, in the above method, when the intermediate pressure lower than the final set pressure is reached after the start of the pressure increase, the pressure increase is temporarily stopped there and the intermediate pressure is held for a predetermined time. In other words, it is possible to gain time by stabilizing the temperature distribution of the laminate by artificially delaying the pressure increase to the set pressure by maintaining the intermediate pressure. Generation | occurrence | production etc. can be suppressed. As a result, not only macro cracks that can be visually confirmed, but also microcrack generation in the compound semiconductor layer around the bonded alloyed layer can be effectively suppressed.

この場合、上記中間圧力への保持中において積層体の貼り合わせ温度に向けた昇温を継続するとさらによい。つまり、中間圧力への保持により設定圧力までの昇圧を作為的に遅らせ、その間に貼り合わせ温度への昇温を先行させることによって、温度分布不均一による不都合な応力発生等を抑制した状態で、最終的な設定圧力への加圧を継続できる。こっれにより、化合物半導体層への割れ発生を効果的に抑制しつつ、また、昇圧の能率も高めることができる。   In this case, it is further preferable that the temperature rise toward the bonding temperature of the laminate is continued while maintaining the intermediate pressure. In other words, by holding the intermediate pressure intentionally, the pressure increase to the set pressure is artificially delayed, and in the meantime, by raising the temperature to the bonding temperature in advance, in a state of suppressing the unfavorable stress generation due to the uneven temperature distribution, Pressurization to the final set pressure can be continued. As a result, it is possible to effectively suppress the generation of cracks in the compound semiconductor layer and to increase the efficiency of pressure increase.

具体的な方法の第二は、発光素子は、発光層部がAlGaInP又はInAlGaNからなり、金属層がAuを主成分とするAu系金属層を有するものであり、素子基板がSi基板であり、
化合物半導体層の第二主表面に、該化合物半導体層との接触抵抗を低減するコンタクト用合金成分を含有した接合金属層を分散形成して合金化熱処理することにより、該接合金属層と化合物半導体層とが合金化した接合合金化層を、一部が第二主表面よりも化合物半導体層側に食い込み、残余の部分が第二主表面から突出した形態で形成し、
接合合金化層の形成された化合物半導体層の第二主表面に金属層の一部となるべきAuを主成分とする第一Au系金属層を形成し、他方、Si基板の貼り合わせ面に金属層の一部となるべきAuを主成分とする第二Au系金属層を形成し、第一Au系金属層と第二Au系金属層とを重ね合わせて積層体を作成し、該積層体を第一加圧部材と第二加圧部材との間にて貼り合わせ加圧しつつ貼り合わせ温度に加熱することにより、第一Au系金属層と第二Au系金属層とを貼り合わせにより結合するとともに、
Si基板からのSi成分が第二Au系金属層へ拡散するのを防ぐSi拡散阻止層を、Si基板と第二Au系金属層との間に形成し、
貼り合わせ加圧の設定圧力を5kPa以上1000kPa以下、貼り合わせ温度を200℃以上280℃以下、設定圧力での保持時間を10分以上60分以下に設定して貼り合わせを行なうことを特徴とする。
The second specific method is that the light emitting element has a light emitting layer portion made of AlGaInP or InAlGaN, the metal layer has an Au-based metal layer mainly composed of Au, and the element substrate is a Si substrate.
A bonding metal layer containing a contact alloy component for reducing contact resistance with the compound semiconductor layer is dispersedly formed on the second main surface of the compound semiconductor layer, and alloying heat treatment is performed, whereby the bonding metal layer and the compound semiconductor are formed. A bonded alloyed layer formed by alloying with the layer, a part of which bites into the compound semiconductor layer side of the second main surface, and the remaining part protrudes from the second main surface;
A first Au-based metal layer mainly composed of Au to be a part of the metal layer is formed on the second main surface of the compound semiconductor layer on which the bonding alloying layer is formed. A second Au-based metal layer mainly composed of Au to be a part of the metal layer is formed, and a first Au-based metal layer and a second Au-based metal layer are overlapped to form a stacked body. By bonding and pressing the body between the first pressure member and the second pressure member to the bonding temperature, the first Au-based metal layer and the second Au-based metal layer are bonded together. And combine
Forming a Si diffusion prevention layer between the Si substrate and the second Au-based metal layer to prevent the Si component from the Si substrate from diffusing into the second Au-based metal layer;
Bonding is performed by setting the pressure for bonding pressure to 5 kPa to 1000 kPa, the bonding temperature to 200 ° C. to 280 ° C., and the holding time at the setting pressure to 10 minutes to 60 minutes. .

上記方法では、適用対象となる発光素子の素子基板としてSi基板を用いる。この場合、化合物半導体層の第二主表面に金属層の一部となるべき第一Au系金属層を形成し、他方、Si基板の貼り合わせ面に金属層の一部となるべき第二Au系金属層を形成し、第一Au系金属層と第二Au系金属層とを貼り合わせにより結合する方法を採用することが可能である。Si基板はドーピングにより発光素子として十分な導電性を容易に確保することができ、しかも安価である。また、第一Au系金属層と第二Au系金属層との貼り合わせは、Au系金属層同士の親和力が強いために、比較的低温でも十分な貼り合わせ強度を容易に得られる利点がある。また、AuとSiとは比較的低温で冶金的な反応(具体的には共晶反応:Au−Si二元系の共晶温度は363℃)を起こしやすいが、Au系金属層同士の貼り合わせ工程を採用すれば、こうした反応を生ずる温度よりも低温で貼り合わせが可能となるため、Si基板とAu系金属層との冶金的な反応により反射面の状態が損なわれる不具合を回避できる利点がある。なお、貼り合わせ温度のさらなる低温化を図るためには、第一Au系金属層と第二Au系金属層とを、いずれもAu含有率が95質量%以上とすることが望ましい。   In the above method, a Si substrate is used as an element substrate of a light emitting element to be applied. In this case, a first Au-based metal layer that should be a part of the metal layer is formed on the second main surface of the compound semiconductor layer, and a second Au that should be a part of the metal layer on the bonding surface of the Si substrate. It is possible to adopt a method in which a metal system layer is formed and the first Au system metal layer and the second Au system metal layer are bonded together by bonding. The Si substrate can easily ensure sufficient conductivity as a light emitting element by doping, and is inexpensive. Further, the bonding between the first Au-based metal layer and the second Au-based metal layer has an advantage that a sufficient bonding strength can be easily obtained even at a relatively low temperature because the affinity between the Au-based metal layers is strong. . In addition, Au and Si are likely to cause metallurgical reaction (specifically, eutectic reaction: eutectic temperature of Au—Si binary system is 363 ° C.) at a relatively low temperature. Adopting the bonding process enables bonding at a temperature lower than the temperature at which such a reaction occurs, so that the problem that the state of the reflecting surface is impaired by the metallurgical reaction between the Si substrate and the Au-based metal layer can be avoided. There is. In order to further reduce the bonding temperature, it is desirable that the Au content of both the first Au-based metal layer and the second Au-based metal layer is 95% by mass or more.

この場合、貼り合わせが完了する前の第二Au系金属層には、前述の加圧クッション層の軟化処理など、上記の共晶反応温度よりも低温であって室温よりは高温の熱履歴が加わることがある。この場合、Si基板と第二Au系金属層とが反応を起こさずとも、Au中のSi原子の拡散速度が比較的大きいため、第二Au系金属層の表面にSiが拡散により湧き上がることがある。この場合、貼り合せ処理を大気中で行うと、第二Au系金属層の表面に湧き上がったSiが酸化され、第一Au系金属層との貼り合わせ強度が大幅に低下することがある。そこで、Si基板からのSi成分が第二Au系金属層へ拡散するのを防ぐSi拡散阻止層を、Si基板と第二Au系金属層との間に形成しておくことが望ましい。このようなSi拡散阻止層を設けておくことで、第二Au系金属層にSiが拡散により湧き上がること、ひいては、第一Au系金属層との貼り合わせ強度低下を効果的に抑制することができる。このようなSi拡散阻止層としては、Ti、Ni及びCrのいずれかを主成分とする金属層、ないしSn、Pb、In及びGaの1種又は2種以上からなるSi拡散阻止成分を含有したAu又はAgを主成分とする金属層を好適に採用することができる。なお、貼り合わせ熱処理をアルゴンや窒素などSi酸化に対して不活性な雰囲気で実施することにより、第二Au系金属層の表面にSiが多少拡散しても第一Au系金属層との貼り合わせを問題なく行うことができる場合には、Si拡散阻止層を省略することも可能である。   In this case, the second Au-based metal layer before the bonding is completed has a thermal history that is lower than the eutectic reaction temperature and higher than room temperature, such as the softening treatment of the pressure cushion layer described above. May join. In this case, even if the Si substrate and the second Au-based metal layer do not react with each other, the diffusion rate of Si atoms in Au is relatively high, so that Si springs up on the surface of the second Au-based metal layer due to diffusion. There is. In this case, when the bonding process is performed in the atmosphere, Si that is springed up on the surface of the second Au-based metal layer is oxidized, and the bonding strength with the first Au-based metal layer may be significantly reduced. Therefore, it is desirable to form a Si diffusion prevention layer between the Si substrate and the second Au-based metal layer for preventing the Si component from the Si substrate from diffusing into the second Au-based metal layer. Providing such a Si diffusion blocking layer effectively suppresses Si from springing up due to diffusion in the second Au-based metal layer, and consequently, a reduction in bonding strength with the first Au-based metal layer. Can do. As such a Si diffusion blocking layer, it contained a metal layer mainly composed of any one of Ti, Ni and Cr, or a Si diffusion blocking component consisting of one or more of Sn, Pb, In and Ga. A metal layer mainly composed of Au or Ag can be preferably used. Note that the bonding heat treatment is performed in an atmosphere inert to Si oxidation such as argon or nitrogen, so that even if Si diffuses slightly on the surface of the second Au-based metal layer, the bonding with the first Au-based metal layer can be performed. If the alignment can be performed without any problem, the Si diffusion blocking layer can be omitted.

AlGaInP又はInAlGaNからなる薄い化合物半導体層の場合、成長用基板との格子定数の不一致や線膨張係数の相違等により反りを生じていることが極めて多い。このような化合物半導体層を、Au系金属層を介してSi基板と貼り合わせることを考慮した場合、貼り合わせを貼り合わせ加圧の設定圧力は5kPa以上1000kPa以下、貼り合わせ温度を200℃以上280℃以下、設定圧力での保持時間を10分以上60分以下に設定して貼り合わせを行なうことが望ましい。化合物半導体層側とSi基板側とにそれぞれ形成したAu系金属層同士の密着状態を高めるには、化合物半導体層に上記の割れやクラック(特に、接合合金化層周囲のミクロクラック)が生じない範囲で貼り合わせ圧力をなるべく高く設定し、柔らかいAu系金属層同士の塑性流動的な追従変形を促して、反りに抗してAu系金属層同士を均一に密着させつつ相互拡散を生じさせることが、均一で強固な貼り合わせ状態を得る上で重要である。   In the case of a thin compound semiconductor layer made of AlGaInP or InAlGaN, warping is very often caused by a mismatch in lattice constant with a growth substrate, a difference in linear expansion coefficient, or the like. In consideration of bonding such a compound semiconductor layer to an Si substrate through an Au-based metal layer, the setting pressure of the bonding pressure is 5 kPa or more and 1000 kPa or less, and the bonding temperature is 200 ° C. or more and 280. It is desirable to perform bonding by setting the holding time at 10 ° C. or lower and the set pressure at 10 to 60 minutes. In order to increase the adhesion between Au-based metal layers formed on the compound semiconductor layer side and the Si substrate side, the above-mentioned cracks and cracks (particularly, microcracks around the bonded alloyed layer) do not occur in the compound semiconductor layer. Set the bonding pressure as high as possible in the range, promote plastic fluid follow-up deformation between soft Au-based metal layers, and cause mutual diffusion while evenly adhering Au-based metal layers against warping However, it is important for obtaining a uniform and strong bonded state.

具体的には、設定圧力が上記の下限値未満となった場合、圧力不足のためAu系金属層同士の密着が十分に進まず、均一な貼り合わせ状態が得にくくなる。また、貼り合わせ温度が上記の下限値未満となった場合、貼り合わせ状態を形成するためのAu系金属層間の相互拡散速度が低下し、均一な貼り合わせ状態が得にくくなる。また、保持時間が10分未満では、貼り合わせ面内全域に渡ってAu系金属層間の相互拡散を均一に進行させることが困難となり、結果的に均一な貼り合わせ状態が得られなくなる。他方、設定圧力が上限値を超えた場合は薄い化合物半導体層に割れやクラック(特に前述のミクロクラック)が生じやすくなる。また、貼り合わせ温度が上限値を超えた場合は、Si基板からAu系金属層へのSi拡散が進みやすくなり、金属層が形成する反射面への沸き上がりにより反射率低下等の不具合を生じやすくなる。さらに、保持時間が60分を超えることは、貼り合わせ工程の能率を考慮すると望ましくないし、Si基板からのSi拡散により反射率が低下する懸念も増加する。   Specifically, when the set pressure is less than the above lower limit value, the adhesion between the Au-based metal layers does not sufficiently proceed due to insufficient pressure, making it difficult to obtain a uniform bonded state. Further, when the bonding temperature is less than the above lower limit value, the interdiffusion rate between the Au-based metal layers for forming the bonding state decreases, and it becomes difficult to obtain a uniform bonding state. In addition, if the holding time is less than 10 minutes, it becomes difficult to cause the interdiffusion between Au-based metal layers to progress uniformly over the entire bonding surface, and as a result, a uniform bonding state cannot be obtained. On the other hand, when the set pressure exceeds the upper limit, cracks and cracks (particularly, the aforementioned microcracks) are likely to occur in the thin compound semiconductor layer. In addition, when the bonding temperature exceeds the upper limit, Si diffusion from the Si substrate to the Au-based metal layer is likely to proceed, causing problems such as a decrease in reflectivity due to boiling to the reflecting surface formed by the metal layer. It becomes easy. Furthermore, it is undesirable for the holding time to exceed 60 minutes in view of the efficiency of the bonding process, and there is an increased concern that the reflectivity will decrease due to Si diffusion from the Si substrate.

加圧時におけるAu系金属層同士の塑性流動的な追従変形には時間を要するため、設定圧力への昇圧速度を過度に大きく設定しすぎると、反りに抗したAu系金属層の変形が昇圧に追従しきれなくなって、化合物半導体層に割れやクラック、特に、荷重集中しやすい接合合金化層周囲へのミクロクラックが発生しやすくなる。この場合、設定圧力へ昇圧を行なう際の昇圧速度を100kPa/分以下に抑制すると、上記の不具合を効果的に防止することができる。なお、過度に昇圧速度を小さくすることは貼り合わせ工程の能率低下にもつながるので、昇圧速度は、例えば1kPa/分以上に設定することが望ましい。   Since plastic fluid follow-up deformation between Au-based metal layers during pressurization takes time, if the pressure increase rate to the set pressure is set too large, the deformation of the Au-based metal layer against the warpage is increased. Thus, cracks and cracks in the compound semiconductor layer, in particular, microcracks around the bonded alloyed layer that tends to concentrate the load are likely to occur. In this case, if the pressure increase rate at the time of pressure increase to the set pressure is suppressed to 100 kPa / min or less, the above-described problem can be effectively prevented. In addition, since excessively reducing the pressure increase rate also leads to a reduction in the efficiency of the bonding process, it is desirable to set the pressure increase rate to, for example, 1 kPa / min or more.

上記具体的方法の第二は、前記具体的方法の第一と組み合わせること、すなわち、貼り合わせ温度よりも低温にて貼り合わせ加圧を開始する一方、該加圧開始時の温度から貼り合わせ温度に到達するまでの積層体の昇温を、当該加圧開始よりも遅れたタイミングにて開始する方法を結合することができ、化合物半導体層へのクラック発生防止に寄与する。   The second of the above specific methods is combined with the first of the above specific methods, that is, the bonding pressure is started at a temperature lower than the bonding temperature, while the bonding temperature is determined from the temperature at the start of the pressing. It is possible to combine a method of starting the temperature rise of the laminated body until reaching the point of time at a timing delayed from the start of pressurization, which contributes to prevention of cracks in the compound semiconductor layer.

そして、上記本発明の方法を採用することにより、以下の本発明の発光素子を実現することが可能となる。すなわり、本発明の発光素子は、AlGaInP又はInAlGaNからなる発光層部を有する化合物半導体層に、Auを主成分とするAu系金属層を有した金属層を介して素子基板が貼り合わされ、
金属層と化合物半導体層との接合界面に、該化合物半導体層との接触抵抗を低減する合金成分を含有した接合金属層を化合物半導体層と合金化させた接合合金化層が、該接合合金化層の一部が化合物半導体層側に食い込み、残余の部分が金属層に食い込むように接合界面に分散形成され、
かつ、分散形成された接合合金化層の総数をNとし、個々の接合合金化層のうち、その周囲において該接合合金化層と接触する化合物半導体層にクラックを生じているものの個数をN1としたとき、N1/Nが0.05以下であることを特徴とする。
By employing the method of the present invention, the following light emitting device of the present invention can be realized. That is, in the light emitting device of the present invention, the device substrate is bonded to the compound semiconductor layer having the light emitting layer portion made of AlGaInP or InAlGaN through the metal layer having the Au-based metal layer mainly composed of Au,
A bonded alloyed layer obtained by alloying a bonded metal layer containing an alloy component that reduces contact resistance with the compound semiconductor layer with the compound semiconductor layer at the bonded interface between the metal layer and the compound semiconductor layer is formed into the bonded alloy. A part of the layer bites into the compound semiconductor layer side, and the remaining part bites into the metal layer so as to be dispersed and formed at the bonding interface.
In addition, the total number of the bonded alloyed layers formed in a dispersed manner is N, and the number of the individual bonded alloyed layers that have cracks in the compound semiconductor layer in contact with the bonded alloyed layer is N1. N1 / N is 0.05 or less.

本発明の発光素子は、上記本発明の製造方法により製造可能であり、貼り合わせ時に荷重集中しやすい接合合金化層の周囲において、ミクロクラックの発生を効果的に防止できる結果、複数分散形成する接合合金化層のうち、クラックを生じているものの個数比率を0.05以下(つまり、5%以下)とすることができる。その結果、接合合金化層と化合物半導体層との接触抵抗の増大や電流リークが生じにくくなるほか、通電時の電流集中によるクラック伝播、ひいては発光強度の経時的な劣化が起こりにくく、長期にわたって高い発光性能を維持できる。   The light-emitting device of the present invention can be manufactured by the above-described manufacturing method of the present invention, and as a result of effectively preventing the occurrence of microcracks around the bonded alloyed layer that tends to concentrate the load at the time of bonding, a plurality of dispersions are formed. Of the bonded alloyed layers, the number ratio of those having cracks can be 0.05 or less (that is, 5% or less). As a result, contact resistance between the bonded alloying layer and the compound semiconductor layer is less likely to increase and current leakage occurs, and crack propagation due to current concentration during energization, and thus degradation over time in light emission intensity, is unlikely to occur and is high over a long period of time. Luminous performance can be maintained.

次に、本発明の発光素子の製造方法においては、化合物半導体層の第一主表面側に結合層を介して仮支持基板を貼り合わせ、さらに該化合物半導体層の第二主表面に金属層と素子基板とを重ね合わせた積層体を該仮支持基板とともに第一加圧部材と第二加圧部材との間で挟圧・加熱することができる。薄い化合物半導体層に仮支持基板が貼り合わされていることで、積層体を形成する際の化合物半導体層のハンドリングが極めて容易になる。その結果、ハンドリング失敗による化合物半導体層の破損確率が減じられ、ひいては発光素子の製造歩留まり向上に寄与する。仮支持貼り合わせ体に組み込む化合物半導体層の全厚が7μm以上30μm以下と薄い場合は、上記仮支持基板を用いる効果が特に顕著に発揮される。この場合、結合層を高分子材料結合層にて構成しておけば、化合物半導体層を素子基板に貼り合わせた後に、高分子材料結合層を加熱軟化又は有機溶剤に溶解することにより、仮支持基板を化合物半導体層から容易に分離することができる。   Next, in the method for producing a light-emitting element of the present invention, a temporary support substrate is bonded to the first main surface side of the compound semiconductor layer via a bonding layer, and a metal layer is further formed on the second main surface of the compound semiconductor layer. The laminated body on which the element substrate is overlaid can be sandwiched and heated between the first pressure member and the second pressure member together with the temporary support substrate. Since the temporary support substrate is bonded to the thin compound semiconductor layer, handling of the compound semiconductor layer when forming the stacked body becomes extremely easy. As a result, the damage probability of the compound semiconductor layer due to the handling failure is reduced, which contributes to the improvement of the manufacturing yield of the light emitting elements. When the total thickness of the compound semiconductor layer incorporated in the temporary support bonded body is as thin as 7 μm or more and 30 μm or less, the effect of using the temporary support substrate is particularly remarkable. In this case, if the bonding layer is composed of a polymer material bonding layer, after the compound semiconductor layer is bonded to the element substrate, the polymer material bonding layer is softened by heating or dissolved in an organic solvent to provide temporary support. The substrate can be easily separated from the compound semiconductor layer.

高分子材料結合層は、熱硬化性の高分子材料、特にエポキシ樹脂又はウレタン樹脂にて構成すると、貼り合わせ熱処理時に高分子材料結合層からのガス発生を効果的に抑制でき、ガス成分による化合物半導体層の汚染(特に炭素による汚染)や、急激なガス発生による化合物半導体層の割れなどをより効果的に防止することができる。   When the polymer material bonding layer is composed of a thermosetting polymer material, particularly an epoxy resin or a urethane resin, it is possible to effectively suppress gas generation from the polymer material bonding layer during the bonding heat treatment, and a compound due to a gas component. It is possible to more effectively prevent contamination of the semiconductor layer (particularly contamination by carbon) and cracking of the compound semiconductor layer due to rapid gas generation.

また、本発明の発光素子の製造方法においては、化合物半導体層と素子基板とを重ね合わせた積層体を作成し、各々金属本体を有する第一加圧部材と第二加圧部材との間にて、第一加圧部材の金属本体と積層体の第一主表面との間、及び第二加圧部材の金属本体と積層体の第二主表面との間の少なくともいずれかに熱可塑性高分子材料からなる加圧クッション層を介在させた状態で該積層体を配置し、加圧クッション層が軟化する貼り合わせ温度に積層体を加熱しつつ、第一加圧部材と第二加圧部材との間で該積層体を、軟化した加圧クッション層を介して加圧することにより、化合物半導体層と素子基板とを貼り合わせることができる。   Further, in the method for manufacturing a light-emitting element of the present invention, a laminate in which a compound semiconductor layer and an element substrate are overlapped is created, and a first pressurizing member and a second pressurizing member each having a metal main body are formed. And at least one between the metal main body of the first pressure member and the first main surface of the laminate and between the metal main body of the second pressure member and the second main surface of the laminate. The first pressurizing member and the second pressurizing member are disposed while the laminated body is disposed in a state where a pressure cushion layer made of a molecular material is interposed, and the laminate is heated to a bonding temperature at which the pressure cushion layer is softened. The compound semiconductor layer and the element substrate can be bonded together by pressing the laminated body through a softened pressure cushion layer.

既に説明した通り、化合物半導体層に割れや欠けが発生する要因は、この貼り合わせ圧力の面内分布が不均一になることに集約される。こうした貼り合わせ圧力の不均一化は、素子基板や化合物半導体層に生じている厚さ不均一や反りにより助長される。このうち、素子基板の厚さ不均一は、研削、研磨ないしエピタキシャル成長の不均一によって生ずることが多い。研削、研磨あるいはエピタキシャル成長が不均一になると、基板の主表面は互いに平行とならず、一方が他方に対して傾斜することになり、その傾斜の向きに対応して基板厚さの不均一が生じ、化合物半導体層を重ねて積層体とした後も、その積層体の厚さ不均一となって引き継がれる。また、反りの問題は、成長用基板上にヘテロエピタキシャル成長される化合物半導体層において、該成長用基板とエピタキシャル層との格子定数の不一致や線膨張係数の相違等により発生しやすい。いずれの場合も、積層体の肉厚部や反りによる突出部には、加圧部材の加圧面が偏って当たるため加重が集中しやすく、化合物半導体層の割れや欠けの直接的な要因となるのである。   As already explained, the factors that cause cracking and chipping in the compound semiconductor layer are summarized in that the in-plane distribution of the bonding pressure becomes non-uniform. Such non-uniform bonding pressure is promoted by non-uniform thickness and warpage generated in the element substrate and the compound semiconductor layer. Among these, the non-uniform thickness of the element substrate is often caused by non-uniform grinding, polishing or epitaxial growth. If grinding, polishing, or epitaxial growth becomes uneven, the main surfaces of the substrate will not be parallel to each other, and one will be inclined with respect to the other, resulting in uneven substrate thickness corresponding to the direction of the inclination. Even after the compound semiconductor layers are stacked to form a laminated body, the thickness of the laminated body becomes nonuniform and is inherited. Further, the problem of warpage is likely to occur in a compound semiconductor layer heteroepitaxially grown on a growth substrate due to a mismatch in lattice constant between the growth substrate and the epitaxial layer, a difference in linear expansion coefficient, or the like. In either case, the pressure surface of the pressure member is biased against the thick part of the laminated body or the protruding part due to warping, so that the load tends to concentrate, which is a direct factor of cracking or chipping of the compound semiconductor layer. It is.

そこで、少なくともどちらかの加圧部材の金属本体と積層体との間に熱可塑性高分子材料からなる加圧クッション層を介在させ、その熱可塑性高分子材料が軟化する貼り合わせ温度を設定し、貼り合わせ時に加圧クッション層を軟化させた状態とする。そして、その軟化した加圧クッション層を介して上記貼り合わせ温度にて、第一加圧部材と第二加圧部材との間で積層体を加圧することにより貼り合わせを行なう。軟化した加圧クッション層は流動性を示すので、積層体に厚さの不均一や反り等を生じていても、貼り合わせの加圧により積層体(もしくは該積層体と加圧部材との間に介在する別部材:例えば、化合物半導体層に結合される後述の仮支持基板)との接触面に倣うように変形し、結果として積層体に対し面内方向に均一に加圧力を付加することができる。従って、貼り合わせの対象となる化合物半導体層がごく薄い場合でも、上記のような厚さ不均一や反りの影響による割れ(前述のミクロクラック含む)や欠けの発生を極めて効果的に防止ないし抑制することができる。   Therefore, a pressure cushion layer made of a thermoplastic polymer material is interposed between the metal main body of at least one of the pressure members and the laminate, and a bonding temperature at which the thermoplastic polymer material is softened is set. The pressure cushion layer is softened at the time of bonding. Then, bonding is performed by pressing the laminate between the first pressure member and the second pressure member at the bonding temperature through the softened pressure cushion layer. Since the softened pressure cushion layer exhibits fluidity, the laminated body (or between the laminated body and the pressure member) can be pressed by bonding even if the laminated body has uneven thickness or warpage. Another member intervening: for example, deformed to follow a contact surface with a temporary support substrate (to be described later) bonded to the compound semiconductor layer, and as a result, a uniform pressure is applied to the laminate in the in-plane direction. Can do. Therefore, even when the compound semiconductor layer to be bonded is very thin, cracks (including the above-mentioned microcracks) and chipping due to the effects of uneven thickness and warping are extremely effectively prevented or suppressed. can do.

特に、積層体を形成する化合物半導体層に反りが生じている場合は、加圧クッション層を介した均一な圧力付加により、該反りを矯正しつつ素子基板への貼り合わせを行なうことができるようになる。具体的には、化合物半導体層に生じている反りが、化合物半導体層の主表面外径をd(mm)、化合物半導体層に生じている反りの厚さ方向の変位をu(μm)として、u/dの値にて7(μm/mm)以下の範囲に収まっている場合は、加圧クッション層を用いることにより、割れ欠けの発生を抑制した状態で、化合物半導体層を素子基板に対し反りを矯正しつつ貼り合わせることができる。   In particular, when the compound semiconductor layer forming the laminate is warped, it can be bonded to the element substrate while correcting the warp by applying a uniform pressure through the pressure cushion layer. become. Specifically, the warpage occurring in the compound semiconductor layer is defined as d (mm) as the main surface outer diameter of the compound semiconductor layer, and u (μm) as the displacement in the thickness direction of the warpage occurring in the compound semiconductor layer. When the u / d value falls within a range of 7 (μm / mm) or less, the use of the pressure cushion layer allows the compound semiconductor layer to be attached to the element substrate in a state in which generation of cracks is suppressed. Can be bonded while correcting the warp.

加圧クッション層は、(加圧部材の)金属本体の表面に形成された高分子材料コーティング層とすることができる。加圧クッション層を高分子材料コーティング層の形で加圧部材の加圧面に一体化することで、積層体を加圧部材間に配置する際に、加圧クッション層の準備に工数がかからなくなり、ひいては貼り合わせ工程の高能率化を図ることができる。一方、加圧クッション層は、金属本体と積層体との間に着脱可能に挿入される高分子材料シートとすることもできる。加熱状態で加圧を反復すれば、加圧クッション層は徐々に消耗し、また永久変形も蓄積されてゆくので、適当な回数で交換する必要がある。加圧クッション層を上記のような高分子材料シートにて形成しておけば、寿命が到来したときの交換が非常に容易である。他方、高分子材料コーティング層として形成する場合は、寿命到来した古いコーティング層を研磨等により除去して、新しいコーティング層を再形成する必要がある。   The pressure cushion layer can be a polymeric material coating layer formed on the surface of the metal body (of the pressure member). By integrating the pressure cushion layer with the pressure surface of the pressure member in the form of a polymer material coating layer, it takes time to prepare the pressure cushion layer when placing the laminate between the pressure members. As a result, it is possible to improve the efficiency of the bonding process. On the other hand, the pressure cushion layer may be a polymer material sheet that is detachably inserted between the metal body and the laminate. If pressurization is repeated in a heated state, the pressure cushion layer gradually wears out and permanent deformation accumulates, so it is necessary to replace it at an appropriate number of times. If the pressure cushion layer is formed of the polymer material sheet as described above, it is very easy to replace it when the end of its life is reached. On the other hand, when forming as a polymer material coating layer, it is necessary to remove the old coating layer which has reached the end of its life by polishing or the like and re-form a new coating layer.

上記の高分子材料コーティング層又は高分子材料シートはフッ素系樹脂にて構成することができる。フッ素系樹脂は耐熱性に優れ、大気中でも比較的高温まで安定性を保ち、金属等との反応も起こしにくい上、表面の摩擦係数も小さい。従って、積層体への樹脂の付着や、擦れ等により積層体を傷つけたりする不具合を生じにくく、また、加圧部材の金属本体との反応による変質等も起こしにくい。本発明に使用可能なフッ素系樹脂としては、例えばポリフッ化ビニリデン(PVDF)、ポリテトラフルオロエチレン(PTFE)、4‐フルオロエチレン‐6‐フルオロプロピレン共重合体(FEP)、4‐フルオロエチレン‐パーフルオロアルキルビニルエーテル共重合体(PFA)、4‐フルオロエチレン‐エチレン共重合体(ETFE)、ポリビニルフルオライド(PVF)、フルオロエチレン‐炭化水素系ビニルエーテル共重合体、ポリクロロトリフルオロエチレン(PCT)などを例示できる。   Said polymeric material coating layer or polymeric material sheet can be comprised with a fluorine resin. Fluororesin has excellent heat resistance, maintains stability to relatively high temperatures in the atmosphere, does not easily react with metals, and has a small surface friction coefficient. Accordingly, it is difficult to cause a problem that the laminated body is damaged due to adhesion or rubbing of the resin to the laminated body, and deterioration due to reaction of the pressure member with the metal main body is hardly caused. Examples of the fluororesin usable in the present invention include polyvinylidene fluoride (PVDF), polytetrafluoroethylene (PTFE), 4-fluoroethylene-6-fluoropropylene copolymer (FEP), 4-fluoroethylene-par Fluoroalkyl vinyl ether copolymer (PFA), 4-fluoroethylene-ethylene copolymer (ETFE), polyvinyl fluoride (PVF), fluoroethylene-hydrocarbon vinyl ether copolymer, polychlorotrifluoroethylene (PCT), etc. Can be illustrated.

他方、化合物半導体層の第一主表面側に、加圧クッション層をなす熱可塑性高分子材料からなる高分子材料結合層を介して仮支持基板を貼り合わせ、積層体を該仮支持基板とともに第一加圧部材と第二加圧部材との間で貼り合わせ加圧しつつ貼り合わせ温度に加熱することもできる。この方法によると、高分子材料結合層が加圧クッション層として機能することによる効果に加え、薄い化合物半導体層に仮支持基板が貼り合わされていることで、積層体を形成する際の化合物半導体層のハンドリングが極めて容易になる利点も生ずる。   On the other hand, a temporary support substrate is bonded to the first main surface side of the compound semiconductor layer via a polymer material bonding layer made of a thermoplastic polymer material forming a pressure cushion layer, and the laminate is bonded together with the temporary support substrate. It is also possible to heat to the bonding temperature while applying pressure between the one pressure member and the second pressure member. According to this method, in addition to the effect of the polymer material bonding layer functioning as a pressure cushion layer, the compound semiconductor layer when forming the laminate by bonding the temporary support substrate to the thin compound semiconductor layer There is also an advantage that handling is extremely easy.

発光素子は、化合物半導体層の光取出面となる第一主表面の一部を覆う形で光取出面側電極が形成される一方、該化合物半導体層の第二主表面に、発光層部からの光を光取出面側に反射させる反射面を有した金属層を介して素子基板が貼り合わされたものとすることができる。この場合、前記の積層体は、素子基板、金属層及び化合物半導体層がこの順序にて積層され、かつ、金属層と化合物半導体層との間に、該化合物半導体層と該金属層との接触抵抗を低減するための貼り合わせ側接合合金化層を配置したものとして形成することができる。反射率の高い金属層を介して貼り合わせを行なうことで、発光素子の光取出し効率を向上させることができる。この場合、化合物半導体層と金属層との接触抵抗を低減するために、両者の間には接合金属層を分散配置して熱処理により合金化する工程が必須である。これを考慮して本発明の発光素子の製造方法は、仮支持基板を用いて以下のように実施することができる。すなわち;
成長用基板の第一主表面上に化合物半導体層をエピタキシャル成長する化合物半導体層成長工程と、
化合物半導体層の第一主表面側に光取出面側電極を形成する光取出面側電極形成工程と、
化合物半導体層の第二主表面側に成長用基板が付随した状態で、光取出面側電極が形成された化合物半導体層の第一主表面に結合層を介して仮支持基板を貼り合わせ、その後、成長用基板を除去することにより、化合物半導体層と仮支持基板とが貼り合わされた仮支持貼り合わせ体を形成する仮支持貼り合わせ体形成工程と、
成長用基板の除去により露出した化合物半導体層の第二主表面に貼り合わせ側接合金属層を形成する貼り合わせ側接合金属層形成工程と、
貼り合わせ側接合金属層を化合物半導体層と合金化させて貼り合わせ側接合合金化層とする貼り合わせ側合金化熱処理を、仮支持貼り合わせ体の状態で行なう貼り合わせ側合金化熱処理工程と、
該貼り合わせ側合金化熱処理の終了後に、貼り合わせ温度を貼り合わせ側合金化熱処理工程よりも低温に設定して貼り合わせ処理を行なうことにより、該化合物半導体層の第二主表面に金属層を介して素子基板を貼り合せた素子基板貼り合わせ体を作成する素子基板貼り合わせ工程と、
素子基板貼り合わせ体から仮支持基板を分離する仮支持基板分離工程と、をこの順序にて実施する。
In the light emitting device, the light extraction surface side electrode is formed so as to cover a part of the first main surface which becomes the light extraction surface of the compound semiconductor layer, while the light emission layer portion is formed on the second main surface of the compound semiconductor layer. The element substrate may be bonded through a metal layer having a reflection surface that reflects the light of the light to the light extraction surface side. In this case, in the stacked body, the element substrate, the metal layer, and the compound semiconductor layer are stacked in this order, and the contact between the compound semiconductor layer and the metal layer is between the metal layer and the compound semiconductor layer. It can be formed as a laminated side bonded alloyed layer for reducing resistance. The light extraction efficiency of the light-emitting element can be improved by performing bonding through a metal layer having a high reflectance. In this case, in order to reduce the contact resistance between the compound semiconductor layer and the metal layer, it is essential to dispose the bonding metal layer between them and alloy them by heat treatment. Considering this, the method for manufacturing a light emitting device of the present invention can be carried out as follows using a temporary support substrate. Ie;
A compound semiconductor layer growth step of epitaxially growing the compound semiconductor layer on the first main surface of the growth substrate;
A light extraction surface side electrode forming step of forming a light extraction surface side electrode on the first main surface side of the compound semiconductor layer;
In the state where the growth substrate is attached to the second main surface side of the compound semiconductor layer, the temporary support substrate is bonded to the first main surface of the compound semiconductor layer on which the light extraction surface side electrode is formed via the bonding layer, and then A temporary support bonded body forming step of forming a temporary support bonded body in which the compound semiconductor layer and the temporary support substrate are bonded by removing the growth substrate;
A bonding side bonding metal layer forming step of forming a bonding side bonding metal layer on the second main surface of the compound semiconductor layer exposed by removing the growth substrate;
A bonding side alloying heat treatment step in which a bonding side alloying heat treatment is performed in the state of a temporary support bonded body by alloying the bonding side bonding metal layer with the compound semiconductor layer to form a bonding side bonding alloyed layer;
After completion of the bonding-side alloying heat treatment, a metal layer is formed on the second main surface of the compound semiconductor layer by performing a bonding treatment by setting the bonding temperature to be lower than the bonding-side alloying heat treatment step. An element substrate bonding step of creating an element substrate bonded body in which the element substrates are bonded together,
A temporary support substrate separation step of separating the temporary support substrate from the element substrate bonded body is performed in this order.

上記の方法によると、成長用基板の第一主表面上に化合物半導体層をエピタキシャル成長した後、さらにその第一主表面側に光取出面側電極を形成する。そして、該光取出面側電極が形成された化合物半導体層の第一主表面に、結合層を介して仮支持基板を貼り合わせ、さらに、成長用基板を化学エッチング等により除去する。仮支持基板が貼り合わされていることにより、成長用基板が除去されても化合物半導体層には仮支持基板が補強体として随伴しているので、エッチング中の泡アタック等により化合物半導体層が破損する不具合を効果的に防止できる。   According to the above method, after the compound semiconductor layer is epitaxially grown on the first main surface of the growth substrate, the light extraction surface side electrode is further formed on the first main surface side. Then, a temporary support substrate is bonded to the first main surface of the compound semiconductor layer on which the light extraction surface side electrode is formed via a bonding layer, and the growth substrate is removed by chemical etching or the like. Since the temporary support substrate is bonded to the compound semiconductor layer as a reinforcing body even if the growth substrate is removed, the compound semiconductor layer is damaged by a bubble attack or the like during etching. Defects can be effectively prevented.

III−V族化合物半導体からなる化合物半導体層の場合、接合金属層は、例えばAu、AgあるいはAlを主成分(50質量%以上)とし、コンタクト用合金成分として、Ge、Sb、Sn、Be及びZnの1種又は2種以上を含有したものを使用することができる。AuGe、AuGeNi、AuSn、AuSbはn型半導体層との接触抵抗低減効果に優れ、AuZn及びAuBeはp型半導体層との接触抵抗低減効果に優れる。このような接合金属層に対する合金化熱処理は、300℃以上450℃以下の温度で行うことが好ましい。合金化熱処理温度が300℃未満では化合物半導体層と接合金属層との合金化が十分に進まず、接触抵抗増大につながる。他方、450℃より高温では合金化の効果は飽和し、むしろ、発光層部への合金成分拡散や発光層部内のドーパント濃度プロファイルの拡散劣化などを防止する観点からは、温度を不必要に高く設定することは得策でないので、合金化熱処理の温度の上限は450℃に設定する。また、合金化熱処理温度は比較的高温であるため、化合物半導体層の酸化劣化等を防止するために、その処理はアルゴンや窒素などの不活性ガス雰囲気中で行なう。   In the case of a compound semiconductor layer made of a III-V group compound semiconductor, the bonding metal layer has, for example, Au, Ag or Al as a main component (50% by mass or more), and Ge, Sb, Sn, Be and What contains 1 type (s) or 2 or more types of Zn can be used. AuGe, AuGeNi, AuSn, and AuSb are excellent in the contact resistance reduction effect with the n-type semiconductor layer, and AuZn and AuBe are excellent in the contact resistance reduction effect with the p-type semiconductor layer. Such alloying heat treatment for the bonding metal layer is preferably performed at a temperature of 300 ° C. or higher and 450 ° C. or lower. If the alloying heat treatment temperature is less than 300 ° C., alloying between the compound semiconductor layer and the bonding metal layer does not proceed sufficiently, leading to an increase in contact resistance. On the other hand, the effect of alloying is saturated at a temperature higher than 450 ° C., but rather, the temperature is unnecessarily high from the viewpoint of preventing diffusion of alloy components into the light emitting layer and diffusion deterioration of the dopant concentration profile in the light emitting layer. Since it is not a good idea to set, the upper limit of the temperature of the alloying heat treatment is set to 450 ° C. Also, since the alloying heat treatment temperature is relatively high, the treatment is performed in an inert gas atmosphere such as argon or nitrogen in order to prevent oxidative degradation of the compound semiconductor layer.

上記の方法によれば、成長用基板が除去された化合物半導体層の第二主表面に貼り合わせ側接合金属層を形成した後、合金化熱処理をまず行ない、その後、該化合物半導体層の第二主表面に金属層を介して素子基板を貼り合せる。これにより、貼り合わせ側接合金属層と接した状態で貼り合わせ用の金属層に合金化熱処理の熱履歴が加わることがなくなり、貼り合わせ側接合金属層の成分(特に、コンタクト用合金成分)が金属層面内に拡散して反射率を落とす不具合を効果的に防止できる。   According to the above method, after forming the bonded-side bonding metal layer on the second main surface of the compound semiconductor layer from which the growth substrate has been removed, the alloying heat treatment is first performed, and then the second of the compound semiconductor layer is performed. An element substrate is bonded to the main surface via a metal layer. As a result, the heat history of the alloying heat treatment is not added to the bonding metal layer in contact with the bonding side bonding metal layer, and the component of the bonding side bonding metal layer (particularly, the alloy component for contact) is reduced. The problem of diffusing in the metal layer surface and reducing the reflectivity can be effectively prevented.

また、光取出面側電極自身又は該光取出面側電極と化合物半導体層との間に配置された光取出面側接合金属層と、化合物半導体層とを合金化するための光取出側合金化熱処理を、上記素子基板貼り合わせ工程の前に実施する。その結果、光取出面側電極と化合物半導体層との接触抵抗を十分に低減できる。そして、光取出面側電極の合金化熱処理もまた素子基板の貼り合わせ前に行なわれるので、その熱履歴により貼り合わせ側接合金属層の成分が金属層面内に拡散して反射率を落とす不具合を防止できる。また、化合物半導体層の第二主表面側と、反射金属層の反射面側との合金化も抑制されるため、これも反射率向上に寄与する。   Also, the light extraction side alloying for alloying the light extraction surface side electrode itself or the light extraction surface side bonding metal layer disposed between the light extraction surface side electrode and the compound semiconductor layer and the compound semiconductor layer Heat treatment is performed before the element substrate bonding step. As a result, the contact resistance between the light extraction surface side electrode and the compound semiconductor layer can be sufficiently reduced. Since the alloying heat treatment of the light extraction surface side electrode is also performed before the bonding of the element substrates, the thermal history causes the problem that the components of the bonding side bonded metal layer diffuse into the metal layer surface and reduce the reflectance. Can be prevented. In addition, alloying between the second main surface side of the compound semiconductor layer and the reflective surface side of the reflective metal layer is also suppressed, and this also contributes to an improvement in reflectance.

光取出側合金化熱処理の実施のタイミングは、素子基板貼り合わせ工程の前であればよく、以下のような種々のパターンから選択できる:
(1)仮支持基板の貼り合わせ前に実施する;
(2)仮支持基板の貼り合わせ後、貼り合わせ側合金化熱処理工程前に別途実施する;
(3)貼り合わせ側合金化熱処理工程を光取出側合金化熱処理に兼用する。
このうち、(3)の工程が工数削減に最も寄与することは明らかである。
The timing of performing the light extraction side alloying heat treatment may be before the element substrate bonding step, and can be selected from the following various patterns:
(1) Perform before bonding the temporary support substrate;
(2) After the temporary support substrate is bonded, separately before the bonding-side alloying heat treatment step;
(3) The bonding side alloying heat treatment step is also used as the light extraction side alloying heat treatment.
Of these, it is clear that the process (3) contributes most to man-hour reduction.

特に、前述の本発明の製造方法の第二を採用する場合、貼り合わせ温度を、上記の合金化熱処理温度よりはるかに低温である200℃以上280℃以下で行なうので、均一に貼り合わせを行なうため、その設定圧力及び貼り合わせ温度での保持時間が10分以上と長いにもかかわらず、接合金属層の成分(特に、接触抵抗を低減するための合金成分)が金属層面内に拡散する不具合を効果的に抑制できる。   In particular, when the second manufacturing method of the present invention is adopted, the bonding temperature is 200 ° C. or higher and 280 ° C. or lower, which is much lower than the alloying heat treatment temperature. Therefore, although the holding time at the set pressure and the bonding temperature is as long as 10 minutes or more, the bonding metal layer component (particularly, the alloy component for reducing contact resistance) diffuses in the metal layer surface. Can be effectively suppressed.

次に、仮支持貼り合わせ体形成工程においては、高分子材料結合層を介して化合物半導体層に仮支持基板を貼り合わせることができる。この場合、仮支持基板分離工程において、高分子材料結合層を加熱して軟化させることにより、素子基板貼り合わせ体から仮支持基板を分離することができる。高分子材料結合層は熱可塑性高分子材料(ワックスを含む)にて構成されるので、化合物半導体層上への塗布も容易であり、また、仮支持基板が工程上不要となった場合は、高分子材料結合層を加熱軟化させることにより容易に化合物半導体層から分離することができる。   Next, in the temporary support bonded body forming step, the temporary support substrate can be bonded to the compound semiconductor layer via the polymer material bonding layer. In this case, in the temporary support substrate separation step, the temporary support substrate can be separated from the element substrate bonded body by heating and softening the polymer material bonding layer. Since the polymer material bonding layer is composed of a thermoplastic polymer material (including wax), it can be easily applied onto the compound semiconductor layer, and when the temporary support substrate is no longer necessary in the process, It can be easily separated from the compound semiconductor layer by heating and softening the polymer material bonding layer.

なお、加圧クッション層は、仮支持基板を積層体(の化合物半導体層)に結合するための高分子材料結合層とともに、加圧部材の金属本体と積層体(あるいは仮支持基板)との間に配置される、前述の高分子材料コーティング層ないし高分子材料シートとを併用することも可能である。これにより、貼り合わせ時に化合物半導体層に割れや欠け等が生ずることを、一層効果的に抑制することができる。   The pressure cushion layer is formed between the metal body of the pressure member and the laminate (or the temporary support substrate) together with the polymer material bonding layer for bonding the temporary support substrate to the laminate (the compound semiconductor layer). It is also possible to use in combination with the above-described polymer material coating layer or polymer material sheet disposed in the above. Thereby, it can suppress more effectively that a crack, a chip | tip, etc. arise in a compound semiconductor layer at the time of bonding.

次に、本発明の発光素子の製造方法においては、上記の高分子材料結合層を加熱して軟化させた後、積層体に対する貼り合わせ加圧の昇圧を開始することが望ましい。該方法によると、高分子材料結合層を予め軟化させ、流動性を高めておいてから貼り合わせ加圧の昇圧を開始することで、積層体に付加される加圧力の均一化効果をより高めることができ、ひいては積層体に含まれる化合物半導体層の割れ等を効果的に防止することができる。   Next, in the method for manufacturing a light-emitting element according to the present invention, it is desirable to start increasing the pressure of bonding to the laminate after heating and softening the polymer material bonding layer. According to this method, the polymer material bonding layer is softened in advance and the fluidity is increased, and then the pressure increase of the bonding pressure is started, thereby further enhancing the effect of equalizing the pressure applied to the laminate. As a result, cracking of the compound semiconductor layer contained in the laminate can be effectively prevented.

素子基板としてSi基板を用いる場合、化合物半導体層の第二主表面に金属層の一部となるべき第一Au系金属層を形成し、他方、Si基板の貼り合わせ面に金属層の一部となるべき第二Au系金属層を形成し、第一Au系金属層と第二Au系金属層とを貼り合わせにより結合することができる。貼り合わせ温度のさらなる低温化を図るためには、加圧クッション層として高分子材料コーティング層又は高分子材料シートのいずれかと高分子材料結合層とを併用し、かつ、高分子材料結合層として高分子材料コーティング層又は高分子材料シートを形成する熱可塑性高分子材料よりも軟化温度の低いものを採用することができる。そして、貼り合わせ温度以下であって高分子材料結合層が軟化する中間温度に積層体を加熱し、該中間温度への到達以降に積層体に対する貼り合わせ加圧の昇圧を開始し、該昇圧開始後に積層体を中間温度から貼り合わせ温度に向けて昇温する。中間温度への加熱により高分子材料結合層を十分に軟化させ、その状態で貼り合わせ加圧の最終的な設定圧力に向けた昇圧を開始することで、積層体の温度があまり上昇しない状態で2つのAu系金属層同士に均一に加圧力を付加できる。その結果、Si基板側からAu系金属層へのSi拡散を抑制しつつ、第一Au系金属層と第二Au系金属層との清浄な主表面同士を互いに密着しあった状態とすることができる。そして、該加圧の途上で積層体を中間温度から貼り合わせ温度に向けてさらに昇温することにより、清浄な状態で密着しあった第一Au系金属層と第二Au系金属層とを拡散接合することができ、比較的短時間で強固な貼り合わせ状態を得ることができる。該効果は、中間温度に積層体を保持した状態で、積層体に対する貼り合わせ加圧の昇圧を開始することで一層高められる。   When a Si substrate is used as the element substrate, a first Au-based metal layer to be a part of the metal layer is formed on the second main surface of the compound semiconductor layer, while a part of the metal layer is formed on the bonding surface of the Si substrate. A second Au-based metal layer to be formed can be formed, and the first Au-based metal layer and the second Au-based metal layer can be bonded together. In order to further reduce the bonding temperature, either a polymer material coating layer or a polymer material sheet and a polymer material binding layer are used in combination as a pressure cushion layer, and a high polymer material binding layer is used. A material having a softening temperature lower than that of the thermoplastic polymer material forming the molecular material coating layer or the polymer material sheet can be employed. Then, the laminated body is heated to an intermediate temperature that is equal to or lower than the bonding temperature and the polymeric material bonding layer is softened, and after the intermediate temperature is reached, pressure increase of the bonding pressure to the laminated body is started, and the pressure increase starts. Later, the laminate is heated from the intermediate temperature toward the bonding temperature. In the state where the temperature of the laminate does not rise so much by sufficiently softening the polymer material bonding layer by heating to the intermediate temperature and starting the pressure increase toward the final set pressure of the bonding pressure in that state The applied pressure can be applied uniformly between the two Au-based metal layers. As a result, clean main surfaces of the first Au metal layer and the second Au metal layer are kept in close contact with each other while suppressing Si diffusion from the Si substrate side to the Au metal layer. Can do. Then, by further raising the temperature of the laminate from the intermediate temperature to the bonding temperature in the course of the pressurization, the first Au-based metal layer and the second Au-based metal layer that are in close contact with each other in a clean state are obtained. Diffusion bonding can be performed, and a strong bonding state can be obtained in a relatively short time. The effect can be further enhanced by starting the pressure increase of the bonding pressure to the laminate while keeping the laminate at an intermediate temperature.

加圧クッション層を設ける場合も、貼り合わせ加圧の設定圧力は5kPa以上1000kPa以下、貼り合わせ温度を200℃以上280℃以下、設定圧力での保持時間を10分以上60分以下に設定して貼り合わせを行なうことが、やはり望ましい。設定圧力が上記の下限値未満となった場合、加圧クッション層がある程度軟化していても、圧力不足のため上記追従変形が十分に進行せず、均一な貼り合わせ状態が得にくくなる。また、貼り合わせ温度が上記の下限値未満となった場合、貼り合わせ状態を形成するためのAu系金属層間の相互拡散速度が低下するとともに、加圧クッション層の軟化も不足しがちとなり、均一な貼り合わせ状態が得にくくなる。また、保持時間が10分未満では、加圧クッション層の追従変形のための流動が不足しやすいこととも相俟って、貼り合わせ面内全域に渡ってAu系金属層間の相互拡散を均一に進行させることが困難となり、結果的に均一な貼り合わせ状態が得られなくなる。   Even when a pressure cushion layer is provided, the set pressure for bonding pressure is set to 5 kPa to 1000 kPa, the bonding temperature is set to 200 ° C. to 280 ° C., and the holding time at the set pressure is set to 10 minutes to 60 minutes. It is also desirable to perform bonding. When the set pressure is less than the lower limit, even if the pressure cushion layer is softened to some extent, the follow-up deformation does not proceed sufficiently due to insufficient pressure, making it difficult to obtain a uniform bonded state. In addition, when the bonding temperature is less than the above lower limit value, the interdiffusion rate between the Au-based metal layers for forming the bonding state is lowered, and the pressure cushion layer is apt to be insufficiently softened, and is uniform. It is difficult to obtain a proper bonding state. In addition, when the holding time is less than 10 minutes, the mutual diffusion between the Au-based metal layers is made uniform over the entire bonding surface in combination with the fact that the flow for the follow-up deformation of the pressure cushion layer tends to be insufficient. It becomes difficult to advance, and as a result, a uniform bonding state cannot be obtained.

他方、最終圧力が上限値を超えた場合は薄い化合物半導体層に割れやクラックが生じやすくなる。また、貼り合わせ温度が上限値を超えた場合は、Si基板からのSi拡散により反射率低下等の不具合を生じやすくなる。さらに、保持時間が60分を超えることは、貼り合わせ工程の能率を考慮すると望ましくないし、Si基板からのSi拡散により反射率が低下する懸念も増加する。   On the other hand, when the final pressure exceeds the upper limit, the thin compound semiconductor layer is likely to be cracked or cracked. Moreover, when the bonding temperature exceeds the upper limit value, defects such as a decrease in reflectance are likely to occur due to Si diffusion from the Si substrate. Furthermore, it is undesirable for the holding time to exceed 60 minutes in view of the efficiency of the bonding process, and there is an increased concern that the reflectivity will decrease due to Si diffusion from the Si substrate.

以下、本発明に係る発光素子の製造方法の実施形態を、図面を参照して説明する。図1は、本発明の適用対象となる発光素子の概念図である。該発光素子100は、素子基板としてのシリコン単結晶よりなるシリコン基板7(本実施形態ではn型であるがp型でもよい)の第一主表面上に、金属層としてのAu系金属層10を介して発光層部24が貼り合わされた構造を有してなる。本実施形態において各層及び基板の主表面は、図1のごとく、発光素子100の光取出面PFを上側にした状態を正置状態として、該正置状態における図面上側に表れる面を第一主表面、下側に表れる面を第二主表面として統一的に記載する。従って、工程説明の都合上、上記正置状態に対し上下を反転した転置状態にて図示を行なう場合は、該図示における第一主表面と第二主表面の上下関係も反転する。   Hereinafter, an embodiment of a method for manufacturing a light emitting device according to the present invention will be described with reference to the drawings. FIG. 1 is a conceptual diagram of a light emitting element to which the present invention is applied. The light-emitting element 100 includes an Au-based metal layer 10 as a metal layer on a first main surface of a silicon substrate 7 (in this embodiment, n-type but may be p-type) made of silicon single crystal as an element substrate. It has a structure in which the light-emitting layer portion 24 is bonded via. In the present embodiment, the main surfaces of the layers and the substrate, as shown in FIG. 1, are defined as a state where the light extraction surface PF of the light emitting element 100 is on the upper side, and a surface appearing on the upper side of the drawing in the normal state is a first main surface. The surface, the surface appearing on the lower side, is uniformly described as the second main surface. Therefore, for convenience of description of the process, when the drawing is performed in a transposed state that is upside down with respect to the normal state, the vertical relationship between the first main surface and the second main surface in the drawing is also reversed.

発光層部24は、ノンドープの(AlGa1−xIn1−yP(ただし、0≦x≦0.55、0.45≦y≦0.55)混晶からなる活性層5を、第一導電型クラッド層、本実施形態ではp型(AlGa1−zIn1−yP(ただしx<z≦1)からなるp型クラッド層6と、第一導電型クラッド層とは異なる第二導電型クラッド層、本実施形態ではn型(AlGa1−zIn1−yP(ただしx<z≦1)からなるp型クラッド層4とにより挟んだ構造を有し、活性層5の組成に応じて、発光波長を、緑色から赤色領域(発光波長(ピーク発光波長)が550nm以上670nm以下)にて調整できる。 The light emitting layer portion 24 is an active layer 5 made of a non-doped (Al x Ga 1-x ) y In 1-y P (where 0 ≦ x ≦ 0.55, 0.45 ≦ y ≦ 0.55) mixed crystal. a first-conductivity-type cladding layer, in this embodiment the p-type cladding layer 6 made of p-type (Al z Ga 1-z) y in 1-y P ( except x <z ≦ 1), the first conductivity type the second-conductivity-type cladding layer different from the clad layer, in this embodiment interposed by an n-type (Al z Ga 1-z) y in 1-y P ( except x <z ≦ 1) p-type clad layer 4 made of According to the composition of the active layer 5, the emission wavelength can be adjusted in the green to red region (the emission wavelength (peak emission wavelength) is 550 nm or more and 670 nm or less).

発光層部24の第一主表面上には、AlGaAs(AlInPでもよい)からなる電流拡散層20が形成され、発光層部24とともに化合物半導体層50を構成している。電流拡散層20の第一主表面の略中央には、発光層部24に発光駆動電圧を印加するための光取出面側電極9(例えばAu電極)が形成されている。該光取出面側電極9と電流拡散層20との間には、光取出側接合合金化層としてのAuBe接合合金化層9a(例えばBe:2質量%)が配置されている。そして、電流拡散層20の第一主表面における光取出面側電極9の周囲の領域が、発光層部24からの光取出領域PFを形成している。なお、光取出面側電極9の全体をAuBe合金にて構成し、接合合金化層9aを省略することも可能である。電流拡散層20の厚さが5μm未満では面内の電流拡散効果が低下して光取出し効率の低下を招く場合がある。他方、電流拡散層20の厚さが28μmを超えると、該電流拡散層20をエピタキシャル成長する際の熱履歴により発光層部24の活性層5へのドーパント拡散が進み、発光効率の低下につながる場合がある。なお、本実施形態では、p型クラッド層6が光取出面側に位置する積層形態としているが、n型クラッド層4が光取出面側に位置する積層形態としてもよい(この場合、電流拡散層20はn型にする必要があり、また、接合合金化層9aはAuGeNi等で構成する)。   A current diffusion layer 20 made of AlGaAs (AlInP may be used) is formed on the first main surface of the light emitting layer portion 24, and constitutes a compound semiconductor layer 50 together with the light emitting layer portion 24. A light extraction surface side electrode 9 (for example, an Au electrode) for applying a light emission driving voltage to the light emitting layer portion 24 is formed substantially at the center of the first main surface of the current diffusion layer 20. Between the light extraction surface side electrode 9 and the current diffusion layer 20, an AuBe bonding alloyed layer 9a (for example, Be: 2% by mass) as a light extraction side bonding alloyed layer is disposed. A region around the light extraction surface side electrode 9 on the first main surface of the current diffusion layer 20 forms a light extraction region PF from the light emitting layer portion 24. It is also possible to configure the entire light extraction surface side electrode 9 with an AuBe alloy and omit the bonding alloyed layer 9a. If the thickness of the current diffusion layer 20 is less than 5 μm, the in-plane current diffusion effect may be reduced and the light extraction efficiency may be reduced. On the other hand, when the thickness of the current diffusion layer 20 exceeds 28 μm, dopant diffusion into the active layer 5 of the light emitting layer portion 24 proceeds due to thermal history when the current diffusion layer 20 is epitaxially grown, leading to a decrease in light emission efficiency. There is. In the present embodiment, the p-type cladding layer 6 is a laminated form in which the light-extracting surface is located, but the n-type clad layer 4 may be in a laminated form in which it is located on the light-extracting side (in this case, current diffusion). The layer 20 must be n-type, and the bonded alloying layer 9a is made of AuGeNi or the like).

n型クラッド層4及びp型クラッド層6の厚さは、例えばそれぞれ0.8μm以上4μm以下(望ましくは0.8μm以上2μm以下)であり、活性層5の厚さは例えば0.4μm以上2μm以下(望ましくは0.4μm以上1μm以下)である。発光層部24全体の厚さは、例えば2μm以上10μm以下(望ましくは2μm以上5μm以下)である。さらに、電流拡散層20の厚さは、例えば5μm以上28μm以下(望ましくは8μm以上15μm以下)である。従って、化合物半導体層50の厚さは、例えば7μm以上38μm以下(望ましくは5μm以上15μm以下)である。   The thickness of the n-type cladding layer 4 and the p-type cladding layer 6 is, for example, 0.8 μm or more and 4 μm or less (preferably 0.8 μm or more and 2 μm or less), and the thickness of the active layer 5 is 0.4 μm or more and 2 μm, for example. Or less (desirably 0.4 μm or more and 1 μm or less). The total thickness of the light emitting layer portion 24 is, for example, 2 μm to 10 μm (desirably 2 μm to 5 μm). Furthermore, the thickness of the current spreading layer 20 is, for example, 5 μm or more and 28 μm or less (desirably 8 μm or more and 15 μm or less). Therefore, the thickness of the compound semiconductor layer 50 is, for example, 7 μm or more and 38 μm or less (desirably 5 μm or more and 15 μm or less).

他方、シリコン基板7の裏面には、その全体を覆うように裏面電極(例えばAu電極である)15が形成されている。該裏面電極15とシリコン基板7との間には基板側接合合金化層として、AuSb接合合金化層16が介挿されている。なお、AuSb接合合金化層16に代えてAuSn接合合金化層を基板側接合合金化層として用いてもよい。   On the other hand, a back surface electrode (for example, an Au electrode) 15 is formed on the back surface of the silicon substrate 7 so as to cover the whole. An AuSb bonding alloyed layer 16 is interposed between the back electrode 15 and the silicon substrate 7 as a substrate side bonding alloyed layer. Instead of the AuSb bonding alloyed layer 16, an AuSn bonding alloyed layer may be used as the substrate side bonding alloyed layer.

シリコン基板7は、Si単結晶インゴットをスライス・研磨して製造されたものであり、その厚みは例えば100μm以上500μm以下である。そして、発光層部24に対し、Au系金属層10を挟んで貼り合わされている。Au系金属層10は、化合物半導体層50側の第一Au系金属層10aと、シリコン基板7側の第二Au系金属層10bとが貼り合わせにより一体化したものであり、見かけ上は単一のAu系金属層である。これら第一Au系金属層10a及び第二Au系金属層10b(ひいてはAu系金属層10)は、純AuもしくはAu含有率が95質量%以上のAu合金よりなる。   The silicon substrate 7 is manufactured by slicing and polishing a Si single crystal ingot, and the thickness thereof is, for example, 100 μm or more and 500 μm or less. Then, it is bonded to the light emitting layer portion 24 with the Au-based metal layer 10 interposed therebetween. The Au-based metal layer 10 is formed by laminating the first Au-based metal layer 10a on the compound semiconductor layer 50 side and the second Au-based metal layer 10b on the silicon substrate 7 side. One Au-based metal layer. The first Au-based metal layer 10a and the second Au-based metal layer 10b (and thus the Au-based metal layer 10) are made of pure Au or an Au alloy having an Au content of 95% by mass or more.

発光層部24とAu系金属層10(第一Au系金属層10a)との間には、貼り合わせ側接合合金化層としてAuGeNi接合合金化層31(例えばGe:15質量%、Ni:10質量%)が形成されており、素子の直列抵抗低減に貢献している。AuGeNi接合合金化層31は、Au系金属層10の第一主表面上に分散形成されている。接合合金化層31は、Au系金属層10と化合物半導体層50との接合界面において、それぞれ、一部が化合物半導体層50側に食い込み、残余の部分がAu系金属層10に食い込んでいる。   Between the light emitting layer portion 24 and the Au-based metal layer 10 (first Au-based metal layer 10a), an AuGeNi bonding alloyed layer 31 (for example, Ge: 15% by mass, Ni: 10) as a bonding-side bonding alloyed layer. % By mass), which contributes to reducing the series resistance of the element. The AuGeNi bonding alloyed layer 31 is dispersedly formed on the first main surface of the Au-based metal layer 10. The bonding alloyed layer 31 partially bites into the compound semiconductor layer 50 side at the bonding interface between the Au-based metal layer 10 and the compound semiconductor layer 50, and the remaining portion bites into the Au-based metal layer 10.

また、従来の発光素子においては、図16に示すように、後述する貼り合わせ工程にて荷重集中しやすい接合合金化層31の周囲に、脆い化合部半導体層50へのミクロクラック(microcrack)MCが多数発生する傾向にあった。しかし、後述の本発明特有の製造工程を採用することにより、図15に示すように、上記のようなミクロクラックMCの形成が抑制される。具体的には、分散形成された接合合金化層31の総数をNとし、個々の接合合金化層31のうち、その周囲において該接合合金化層31と接触する化合物半導体層50にクラックを生じているものの個数をN1としたとき、N1/Nが0.05以下(つまり、5%以下、望ましくは1%以下)とされている。   Further, in the conventional light emitting device, as shown in FIG. 16, the microcrack MC to the brittle compound semiconductor layer 50 is formed around the bonding alloyed layer 31 where load is likely to concentrate in the bonding process described later. Tended to occur in large numbers. However, by employing the manufacturing process unique to the present invention described later, the formation of the microcracks MC as described above is suppressed as shown in FIG. Specifically, the total number of bonded alloyed layers 31 formed in a dispersed manner is N, and among the individual bonded alloyed layers 31, cracks are generated in the compound semiconductor layer 50 in contact with the bonded alloyed layer 31 in the periphery thereof. N1 / N is 0.05 or less (that is, 5% or less, preferably 1% or less), where N1 is the number of objects.

図1に戻り、シリコン基板7と第二Au系金属層10bとの間には、基板側接合合金化層としてAuSb接合合金化層32(例えばSb:2質量%)が介挿されている。なお、AuSb接合合金化層32に代えてAuSn接合合金化層を用いてもよい。また、本実施形態においては、該AuSb接合金属層32の全面が、後述の貼り合わせ熱処理時においてシリコン基板7からのSi成分がAu系金属層10へ拡散するのを防ぐ拡散阻止層(具体的にはTi層である)10cにより覆われている。拡散阻止層10cの厚さは1nm以上10μm以下(本実施形態では200nm)である。なお、拡散阻止層はTi層に代えてNi層又はCr層にて構成してもよい。また、Au系金属層10(第二Au系金属層10b)は、該拡散阻止層10cの全面を覆う形でこれと接するように配置されている。   Returning to FIG. 1, an AuSb bonding alloyed layer 32 (for example, Sb: 2% by mass) is interposed between the silicon substrate 7 and the second Au-based metal layer 10b as a substrate-side bonding alloyed layer. Instead of the AuSb bonding alloyed layer 32, an AuSn bonding alloyed layer may be used. Further, in the present embodiment, the entire surface of the AuSb bonding metal layer 32 is a diffusion blocking layer that prevents the Si component from the silicon substrate 7 from diffusing into the Au-based metal layer 10 during the bonding heat treatment described later (specifically, Is a Ti layer). The thickness of the diffusion blocking layer 10c is 1 nm or more and 10 μm or less (200 nm in this embodiment). The diffusion blocking layer may be composed of a Ni layer or a Cr layer instead of the Ti layer. Further, the Au-based metal layer 10 (second Au-based metal layer 10b) is disposed so as to be in contact with the entire surface of the diffusion blocking layer 10c.

金属層をなすAu系金属層10は、本実施形態では反射層も兼ねるものとなっている。発光層部24からの光は、光取出面側に直接放射される光に、Au系金属層10による反射光が重畳される形で取り出される。Au系金属層10の厚さは、反射効果を十分に確保するため、80nm以上とすることが望ましい。また、厚さの上限には制限は特にないが、反射効果が飽和するため、コストとの兼ね合いにより適当に定める(例えば1μm以下)。なお、反射層も兼ねる金属層としてはAg系層の使用も可能である。例えば、第一Au系金属層10a及び第二Au系金属層10bに代え、第一Ag系層及び第二Ag系層を形成して両者を貼り合せることができる。この場合、貼り合わせ側接合合金化層は、AgGeNiなどのAg系材料にて構成することもできる。   In this embodiment, the Au-based metal layer 10 that forms the metal layer also serves as a reflective layer. The light from the light emitting layer portion 24 is extracted in a form in which the light reflected directly from the Au-based metal layer 10 is superimposed on the light emitted directly to the light extraction surface side. The thickness of the Au-based metal layer 10 is desirably 80 nm or more in order to ensure a sufficient reflection effect. Moreover, although there is no restriction | limiting in particular in the upper limit of thickness, since a reflection effect is saturated, it determines suitably (for example, 1 micrometer or less) by balance with cost. Note that an Ag-based layer can be used as the metal layer that also serves as the reflective layer. For example, instead of the first Au-based metal layer 10a and the second Au-based metal layer 10b, a first Ag-based layer and a second Ag-based layer can be formed and bonded together. In this case, the bonded side bonded alloyed layer can also be composed of an Ag-based material such as AgGeNi.

以下、上記発光素子100の製造方法の具体例について説明する。
まず、図2の工程1に示すように、成長用基板をなすGaAs単結晶基板1の主表面に、n型GaAsバッファ層2を例えば0.5μm、AlAsからなる剥離層3を例えば0.5μm、この順序にてエピタキシャル成長させる。その後、発光層部24として、n型クラッド層4(厚さ:例えば1μm)、AlGaInP活性層(ノンドープ)5(厚さ:例えば0.6μm)、及びp型クラッド層6(厚さ:例えば1μm)を、この順序にエピタキシャル成長させる。発光層部24の全厚は2.6μmである。また、さらにp型AlGaAsよりなる電流拡散層20を例えば5μmエピタキシャル成長させる。これら各層のエピタキシャル成長は、公知のMOVPE法により行なうことができる。Al、Ga、In、P及びAsの各成分源となる原料ガスとしては以下のようなものを使用できる;
・Al源ガス;トリメチルアルミニウム(TMAl)、トリエチルアルミニウム(TEAl)など;
・Ga源ガス;トリメチルガリウム(TMGa)、トリエチルガリウム(TEGa)など;
・In源ガス;トリメチルインジウム(TMIn)、トリエチルインジウム(TEIn)など。
・P源ガス;ターシャルブチルホスフィン(TBP)、ホスフィン(PH)など。
・As源ガス;ターシャルブチルアルシン(TBA)、アルシン(AsH)など。
Hereinafter, a specific example of the method for manufacturing the light emitting device 100 will be described.
First, as shown in step 1 of FIG. 2, an n-type GaAs buffer layer 2 is 0.5 μm, for example, and a release layer 3 made of AlAs is 0.5 μm, for example, on the main surface of a GaAs single crystal substrate 1 that is a growth substrate. Then, epitaxial growth is performed in this order. Thereafter, as the light emitting layer portion 24, an n-type cladding layer 4 (thickness: for example 1 μm), an AlGaInP active layer (non-doped) 5 (thickness: for example 0.6 μm), and a p-type cladding layer 6 (thickness: for example 1 μm). ) In this order. The total thickness of the light emitting layer portion 24 is 2.6 μm. Further, a current diffusion layer 20 made of p-type AlGaAs is epitaxially grown by 5 μm, for example. Epitaxial growth of each of these layers can be performed by a known MOVPE method. The following can be used as a source gas that is a component source of Al, Ga, In, P, and As;
Al source gas; trimethylaluminum (TMAl), triethylaluminum (TEAl), etc .;
Ga source gas; trimethylgallium (TMGa), triethylgallium (TEGa), etc .;
In source gas; trimethylindium (TMIn), triethylindium (TEIn), etc.
P source gas; tertiary butyl phosphine (TBP), phosphine (PH 3 ), etc.
As source gas; tertiary butyl arsine (TBA), arsine (AsH 3 ), etc.

また、ドーパントガスとしては、以下のようなものを使用できる;
(p型ドーパント)
・Mg源:ビスシクロペンタジエニルマグネシウム(CpMg)など。
・Zn源:ジメチル亜鉛(DMZn)、ジエチル亜鉛(DEZn)など。
(n型ドーパント)
・Si源:モノシランなどのシリコン水素化物など。
Moreover, as a dopant gas, the following can be used;
(P-type dopant)
Mg source: biscyclopentadienyl magnesium (Cp 2 Mg), etc.
Zn source: dimethyl zinc (DMZn), diethyl zinc (DEZn), etc.
(N-type dopant)
Si source: silicon hydride such as monosilane.

これによって、GaAs単結晶基板1上に発光層部24及び電流拡散層20からなる化合物半導体層50が形成される。該化合物半導体層50の厚さは7.6μmであり、GaAs単結晶基板1を除去した場合、これを単独で無傷にハンドリングすることは事実上不可能である。なお、化合物半導体層50の第一主表面には、この段階でAuBe接合金属層9a’(光取出面側接合合金化層)とこれを覆う光取出面側電極9をパターニング形成する。このあと、引き続き光取出側合金化熱処理を行ってAuBe接合金属層9a’を接合合金化層9aとしてもよいが、本実施形態では該光取出側合金化熱処理を、後述のAu系金属層10a側のAuGeNi接合合金化層31を形成する際の合金化熱処理に兼用させている。   As a result, the compound semiconductor layer 50 including the light emitting layer portion 24 and the current diffusion layer 20 is formed on the GaAs single crystal substrate 1. The thickness of the compound semiconductor layer 50 is 7.6 μm. When the GaAs single crystal substrate 1 is removed, it is practically impossible to handle it alone without being damaged. At this stage, the AuBe bonding metal layer 9a '(light extraction surface side bonding alloyed layer) and the light extraction surface side electrode 9 covering the same are patterned on the first main surface of the compound semiconductor layer 50. Thereafter, the light extraction side alloying heat treatment may be subsequently performed to change the AuBe bonding metal layer 9a ′ into the bonding alloying layer 9a. However, in this embodiment, the light extraction side alloying heat treatment is performed using an Au-based metal layer 10a described later. This is also used for the alloying heat treatment when forming the AuGeNi bonding alloyed layer 31 on the side.

次に、工程2に示すように、化合物半導体層50の第一主表面に高分子材料結合層111(後に加圧クッション層としても機能する)を、光取出面側電極9を覆う形態で塗付形成する。そして、工程3に示すように、高分子材料結合層111を加熱軟化させた状態で、別途用意した仮支持基板110を重ね合わせて密着させ、その後冷却して該高分子材料結合層111を硬化させることにより、化合物半導体層50と仮支持基板110とを高分子材料結合層111を介して貼り合わせた仮支持貼り合わせ体120を作成する(工程3)。なお、高分子材料結合層111を仮支持基板110に塗布形成し、これに化合物半導体層50を貼り合わせて仮支持貼り合わせ体120を形成してもよい。この時点では、化合物半導体層50の第二主表面側には、成長用基板であるGaAs単結晶基板1が付随した状態となっている。   Next, as shown in Step 2, a polymer material bonding layer 111 (which also functions as a pressure cushion layer later) is applied to the first main surface of the compound semiconductor layer 50 so as to cover the light extraction surface side electrode 9. Attached. Then, as shown in step 3, with the polymer material bonding layer 111 heated and softened, a separately prepared temporary support substrate 110 is stacked and adhered, and then cooled to cure the polymer material bonding layer 111. By doing so, the temporary support bonded body 120 in which the compound semiconductor layer 50 and the temporary support substrate 110 are bonded to each other via the polymer material bonding layer 111 is formed (step 3). Alternatively, the temporary support bonded body 120 may be formed by applying the polymer material bonding layer 111 to the temporary support substrate 110 and bonding the compound semiconductor layer 50 thereto. At this time, the GaAs single crystal substrate 1 as a growth substrate is attached to the second main surface side of the compound semiconductor layer 50.

仮支持基板110の材質は、後述の合金化熱処理時においても剛性を保ち、かつ、ガス発生等が少ない材料で構成する。具体的には、シリコン基板やセラミック板(例えばアルミナ板)、あるいは金属板等で構成することができる。その厚さは、例えば100μm以上500μm以下であるが、もっと厚くてもよい。他方、高分子材料結合層111としては、ホットメルト型接着剤やワックス類を用いることができ、具体的には、不活性ガス雰囲気中にて300℃以上450℃以下の温度範囲で後述の合金化熱処理を行なう際に、高分子材料結合層111の気化による化合物半導体層50の損傷等を避けるため、該300℃以上450℃以下の温度域での蒸気圧(定容積条件で測定した平衡蒸気圧とする)が10torr以下のものを使用する。このような高分子材料結合層111の形成に適したワックスの市販品としては、アピエゾン・ワックスW(M&I Materials Ltd.社製)、スペースリキッド(日化精工社製)あるいはプロテクトワックス等を例示することができる。   The material of the temporary support substrate 110 is made of a material that maintains rigidity even during an alloying heat treatment described later and that generates less gas. Specifically, a silicon substrate, a ceramic plate (for example, an alumina plate), or a metal plate can be used. The thickness is, for example, 100 μm or more and 500 μm or less, but may be thicker. On the other hand, hot-melt adhesives and waxes can be used as the polymer material bonding layer 111. Specifically, an alloy described later in a temperature range of 300 ° C. to 450 ° C. in an inert gas atmosphere. In order to avoid damage to the compound semiconductor layer 50 due to vaporization of the polymer material bonding layer 111 during the heat treatment, vapor pressure in the temperature range of 300 ° C. to 450 ° C. (equilibrium vapor measured under constant volume conditions) Pressure) is 10 torr or less. Examples of commercially available waxes suitable for the formation of the polymer material binding layer 111 include Apiezon Wax W (manufactured by M & I Materials Ltd.), Space Liquid (manufactured by Nikka Seiko Co., Ltd.), and protect wax. be able to.

次に、図3の工程4に示すように、仮支持貼り合わせ体120に付随している成長用基板としてのGaAs単結晶基板1を除去する。該除去は、例えば仮支持貼り合わせ体120(工程3参照)をGaAs単結晶基板1とともにエッチング液(例えば10%フッ酸水溶液)に浸漬し、バッファ層2と発光層部24との間に形成したAlAs剥離層3を選択エッチングすることにより、該GaAs単結晶基板1を仮支持貼り合わせ体120から剥離する形で実施することができる。なお、AlAs剥離層3に代えてAlInPよりなるエッチストップ層を形成しておき、GaAsに対して選択エッチング性を有する第一エッチング液(例えばアンモニア/過酸化水素混合液)を用いてGaAs単結晶基板1をGaAsバッファ層2とともにエッチング除去し、次いでAlInPに対して選択エッチング性を有する第二エッチング液(例えば塩酸:Al酸化層除去用にフッ酸を添加してもよい)を用いてエッチストップ層をエッチング除去する工程を採用することもできる。   Next, as shown in step 4 of FIG. 3, the GaAs single crystal substrate 1 as a growth substrate attached to the temporary support bonded body 120 is removed. For this removal, for example, the temporary support bonded body 120 (see step 3) is immersed in an etching solution (for example, a 10% aqueous hydrofluoric acid solution) together with the GaAs single crystal substrate 1 and formed between the buffer layer 2 and the light emitting layer portion 24. The GaAs single crystal substrate 1 can be peeled from the temporary support bonded body 120 by selectively etching the AlAs release layer 3 thus formed. It should be noted that an etch stop layer made of AlInP is formed in place of the AlAs release layer 3, and a GaAs single crystal is used by using a first etching solution (for example, ammonia / hydrogen peroxide mixed solution) having selective etching properties with respect to GaAs. Etch and remove the substrate 1 together with the GaAs buffer layer 2 and then etch stop using a second etchant that has selective etching properties with respect to AlInP (for example, hydrochloric acid: hydrofluoric acid may be added to remove the Al oxide layer) A step of etching away the layer can also be employed.

このようにして、GaAs単結晶基板1が除去された化合物半導体層50は、加圧クッション層としても機能する高分子材料結合層111を介して仮支持基板110と貼り合わされ、仮支持貼り合わせ体120を形成している。従って、化合物半導体層50がごく薄いにもかかわらず、GaAs単結晶基板1のエッチング除去時に泡等の衝撃で破壊される不具合を生じにくく、かつ、GaAs単結晶基板1の除去後も仮支持貼り合わせ体120の形で補強されているために、以降の工程に供する際のハンドリングを容易に行なうことが可能となる。   In this way, the compound semiconductor layer 50 from which the GaAs single crystal substrate 1 has been removed is bonded to the temporary support substrate 110 via the polymer material bonding layer 111 that also functions as a pressure cushion layer, and the temporary support bonded body. 120 is formed. Therefore, even though the compound semiconductor layer 50 is very thin, it is difficult to cause a problem of being destroyed by an impact such as bubbles when the GaAs single crystal substrate 1 is removed by etching, and temporary support sticking is performed even after the GaAs single crystal substrate 1 is removed. Since it is reinforced in the form of the mating body 120, it is possible to easily handle when it is used in the subsequent steps.

また、図10に示すように、仮支持基板110を貼り合わせない状態で成長用基板1を除去した場合、該成長用基板1上にエピタキシャル成長された化合物半導体層50には、成長用基板1との格子定数不一致や線膨張係数の相違等に起因した残留応力により強い反りを生ずる(なお、反り変位uは、層ないし基板を水平面上においたときの見かけの高さHから、層ないし基板の実厚さt0を減じた値として定義する)。しかし、図11に示すように、反りの小さい仮支持基板110を、高分子材料結合層111を介して化合物半導体層50に貼り合わせ、その状態で成長用基板1を除去すれば、化合物半導体層50が仮支持基板110に面内に引張られる形で矯正され、反り変位uを小さくすることができる。なお、成長用基板1を除去したあとの仮支持貼り合わせ体120(ひいては該仮支持貼り合わせ体120内の化合物半導体層50)の反り変位u(μm)は、化合物半導体層50の主表面外径をd(mm)として、u/dの値にて7(μm/mm)以下の範囲以下に収まるよう、エピタキシャル成長の条件や、発光層部24ないし電流拡散層20の組成及び厚さを調整しておくことが望ましい。発光層部24を構成するAlGaInP化合物は、結晶欠陥等をできるだけ少なくして内部量子効率を向上させるために、GaAs単結晶からなる成長用基板1との格子不整合率が可及的に縮小される組成が選択される。   As shown in FIG. 10, when the growth substrate 1 is removed without attaching the temporary support substrate 110, the compound semiconductor layer 50 epitaxially grown on the growth substrate 1 includes the growth substrate 1 and the growth substrate 1. Cause a strong warp due to residual stress caused by a mismatch in lattice constants, a difference in linear expansion coefficient, etc. (Note that the warp displacement u is determined from the apparent height H when the layer or substrate is placed on a horizontal plane. It is defined as a value obtained by subtracting the actual thickness t0). However, as shown in FIG. 11, if the temporary support substrate 110 with a small warp is bonded to the compound semiconductor layer 50 via the polymer material bonding layer 111 and the growth substrate 1 is removed in this state, the compound semiconductor layer 50 is corrected by being pulled by the temporary support substrate 110 in the plane, and the warp displacement u can be reduced. The warp displacement u (μm) of the temporary support bonded body 120 (and consequently the compound semiconductor layer 50 in the temporary support bonded body 120) after the growth substrate 1 is removed is outside the main surface of the compound semiconductor layer 50. Adjusting the epitaxial growth conditions and the composition and thickness of the light emitting layer portion 24 or the current diffusion layer 20 so that the diameter is d (mm) and the u / d value falls within the range of 7 (μm / mm) or less. It is desirable to keep it. In the AlGaInP compound constituting the light emitting layer portion 24, the lattice mismatch rate with the growth substrate 1 made of GaAs single crystal is reduced as much as possible in order to improve the internal quantum efficiency by minimizing crystal defects and the like. The composition is selected.

次に、工程5に示すように、上記仮支持貼り合わせ体120の状態で、GaAs単結晶基板1の除去により露出した化合物半導体層50の第二主表面にAuGeNi接合金属層31’を分散形成し、さらに該AuGeNi接合金属層31’をAuGeNi接合合金化層31とするための貼り合わせ側合金化熱処理を行なう。このとき、光取出面側電極9に対するAuBe接合金属層9a’の合金化も同時に行なうことができる(つまり、光取出側合金化熱処理にも兼用されている)。なお、化合物半導体層50の第二主表面の全面積に対するAuGeNi接合金属層の形成面積率は1%以上25%以下とする。   Next, as shown in step 5, in the state of the temporary support bonded body 120, an AuGeNi bonded metal layer 31 ′ is formed on the second main surface of the compound semiconductor layer 50 exposed by removing the GaAs single crystal substrate 1 in a dispersed manner. Further, a bonding-side alloying heat treatment is performed so that the AuGeNi bonded metal layer 31 ′ becomes the AuGeNi bonded alloyed layer 31. At this time, the AuBe bonding metal layer 9a 'can be alloyed with the light extraction surface side electrode 9 at the same time (that is, also used for light extraction side alloying heat treatment). The formation area ratio of the AuGeNi bonding metal layer with respect to the entire area of the second main surface of the compound semiconductor layer 50 is 1% or more and 25% or less.

AuGeNi接合金属層31’の成膜は、真空雰囲気にてスパッタリングあるいは真空蒸着等により行なわれる。具体的には該成膜を、温度60℃以上150℃以下、真空度(圧力)1×10−6torr以上1×10−4torr以下の条件下で行なう(必要であれば、仮支持貼り合わせ体120を図示しないヒータにより加熱することができる)。高分子材料結合層111として、上記温度範囲での蒸気圧が1×10−6torr以下のものを採用することで(前述の市販品はこの条件も満たす)、成膜される接合金属層31’の品質が、高分子材料結合層111からのガスにより低下する不具合を効果的に防止できる。 The AuGeNi bonding metal layer 31 ′ is formed by sputtering or vacuum deposition in a vacuum atmosphere. Specifically, the film formation is performed under the conditions of a temperature of 60 ° C. or more and 150 ° C. or less and a degree of vacuum (pressure) of 1 × 10 −6 torr or more and 1 × 10 −4 torr or less (if necessary, temporary support bonding is performed) The laminated body 120 can be heated by a heater (not shown)). By adopting a polymer material bonding layer 111 having a vapor pressure of 1 × 10 −6 torr or less in the above temperature range (the above-mentioned commercial product also satisfies this condition), the bonding metal layer 31 to be formed is formed. It is possible to effectively prevent a problem that the quality of 'deteriorates due to the gas from the polymer material bonding layer 111.

合金化熱処理は、300℃以上450℃以下の温度の不活性ガス雰囲気下で実施され、具体的には、大気圧と同程度のN等の不活性ガス雰囲気下で行なうことができる。使用する高分子材料結合層111は、上記温度範囲での蒸気圧が10torr以下であるので、高分子材料結合層111の急激な気化により化合物半導体層50が破損する不具合を効果的に防止できる。 The alloying heat treatment is performed in an inert gas atmosphere at a temperature of 300 ° C. or higher and 450 ° C. or lower. Specifically, the alloying heat treatment can be performed in an inert gas atmosphere such as N 2 at the same level as atmospheric pressure. Since the polymer material bonding layer 111 to be used has a vapor pressure of 10 torr or less in the above temperature range, the compound semiconductor layer 50 can be effectively prevented from being damaged due to rapid vaporization of the polymer material bonding layer 111.

また、シリコン基板7を別途用意し、その両主表面にAuSb接合金属層を形成して、さらに250℃以上360℃以下の温度域で合金化熱処理を行なうことにより、それぞれAuSb接合合金化層32,16とする。このうち、AuSb接合合金化層32上には、続く素子基板貼り合わせ工程においてシリコン基板7の成分が第二Au系金属層10bへ拡散するのを阻止する拡散阻止層10cを形成しておく。AuSb接合合金化層32の合金化熱処理は、Si拡散阻止層10cを形成後に行なう。他方、AuSb接合合金化層16上には裏面電極15を形成する。   Further, by separately preparing the silicon substrate 7, forming AuSb bonding metal layers on both main surfaces, and further performing alloying heat treatment in a temperature range of 250 ° C. or higher and 360 ° C. or lower, respectively, the AuSb bonding alloyed layer 32 is obtained. , 16. Among these, on the AuSb bonding alloying layer 32, a diffusion blocking layer 10c is formed that prevents the components of the silicon substrate 7 from diffusing into the second Au-based metal layer 10b in the subsequent element substrate bonding step. The alloying heat treatment of the AuSb bonding alloying layer 32 is performed after the Si diffusion blocking layer 10c is formed. On the other hand, the back electrode 15 is formed on the AuSb bonding alloying layer 16.

次に、素子基板貼り合わせ工程を行なう。具体的には、図3の工程6に示すように、仮支持貼り合わせ体120の状態で、化合物半導体層50の第二主表面に第一Au系金属層10aを形成し、他方、シリコン基板7の第一主表面側に第二Au系金属層10bを形成する。なお、各Au系金属層の形成は、真空雰囲気(スパッタリングあるいは真空蒸着等により)にて行なうことができる。具体的には、温度60℃以上150℃以下、真空度(圧力)1×10−6torr以上1×10−4torr以下の条件にて成膜を行なう。仮支持貼り合わせ体120側の第一Au系金属層10aを形成する場合は、高分子材料結合層111として、上記温度域での蒸気圧が1×10−6torr以下のものを採用することにより、高分子材料結合層111からのガスで、成膜されるAu系金属層の品質が低下する不具合を効果的に防止できる。 Next, an element substrate bonding step is performed. Specifically, as shown in Step 6 of FIG. 3, the first Au-based metal layer 10a is formed on the second main surface of the compound semiconductor layer 50 in the state of the temporary support bonded body 120, while the silicon substrate A second Au-based metal layer 10 b is formed on the first main surface side of 7. Each Au-based metal layer can be formed in a vacuum atmosphere (by sputtering or vacuum vapor deposition). Specifically, film formation is performed under conditions of a temperature of 60 ° C. or more and 150 ° C. or less and a degree of vacuum (pressure) of 1 × 10 −6 torr or more and 1 × 10 −4 torr or less. When the first Au-based metal layer 10a on the temporary support bonded body 120 side is formed, a polymer material bonding layer 111 having a vapor pressure of 1 × 10 −6 torr or less in the above temperature range is adopted. Accordingly, it is possible to effectively prevent a problem that the quality of the Au-based metal layer formed by the gas from the polymer material bonding layer 111 is deteriorated.

そして、仮支持貼り合わせ体120の第一Au系金属層10aとシリコン基板7の第二Au系金属層10bとを重ね合わせる。化合物半導体層50は、素子基板であるシリコン基板7と重ね合わされて積層体130を形成する。なお、化合物半導体層50の第一主表面には仮支持基板110が高分子材料結合層111を介して貼り合わされているので、該仮支持基板110付の積層体130を仮支持積層体130’と称することにする。そして、該仮支持積層体130’を、抵抗発熱ヒータ49が内蔵された第一加圧部材51と第二加圧部材52との間に配置し、抵抗発熱ヒータ49によって加熱しつつ両加圧部材51,52間で加圧して、第一Au系金属層10aと第二Au系金属層10bとを貼り合わせる(図5)。抵抗発熱ヒータ49は各加圧部材51,52の金属本体51a,52aに埋設され、金属本体51a,52aの加圧面には、熱可塑性のフッ素系樹脂(本実施形態ではポリテトラフルオロエチレン(商標名:テフロン))からなる、加圧クッション層としての高分子材料コーティング層150が、例えば50μm以上300μm以下の厚さにて形成されている。前述の高分子材料結合層111は、フッ素系樹脂からなる高分子材料コーティング層150よりも軟化温度が低いものが選定されている(例えば、ガラス転移温度が80℃以上90℃以下のものである)。   Then, the first Au-based metal layer 10a of the temporary support bonded body 120 and the second Au-based metal layer 10b of the silicon substrate 7 are overlapped. The compound semiconductor layer 50 is overlapped with the silicon substrate 7 that is an element substrate to form a stacked body 130. Since the temporary support substrate 110 is bonded to the first main surface of the compound semiconductor layer 50 via the polymer material bonding layer 111, the stack 130 with the temporary support substrate 110 is attached to the temporary support stack 130 ′. I will call it. Then, the temporary support laminate 130 ′ is disposed between the first pressure member 51 and the second pressure member 52 in which the resistance heating heater 49 is built, and both pressures are applied while being heated by the resistance heating heater 49. The first Au-based metal layer 10a and the second Au-based metal layer 10b are bonded together by applying pressure between the members 51 and 52 (FIG. 5). The resistance heater 49 is embedded in the metal bodies 51a and 52a of the pressurizing members 51 and 52, and a thermoplastic fluororesin (in this embodiment, polytetrafluoroethylene (trademark) is provided on the pressurizing surfaces of the metal bodies 51a and 52a. A polymer material coating layer 150 as a pressure cushion layer made of a name: Teflon)) is formed with a thickness of, for example, 50 μm to 300 μm. The polymer material bonding layer 111 is selected to have a softening temperature lower than that of the polymer material coating layer 150 made of a fluororesin (for example, a glass transition temperature of 80 ° C. or higher and 90 ° C. or lower). ).

貼り合わせ工程の詳細を図6に、また、貼り合わせ工程中の圧力と温度との制御パターンを図7にそれぞれ例示している。図6の工程1に示すように、抵抗発熱ヒータ49を発熱させ、最終的な貼り合わせ温度θ2よりも低い中間温度θ1まで加熱する。中間温度θ1は、例えば80℃以上150℃以下の範囲で、仮支持基板110を貼り合せている高分子材料結合層111(加圧クッション層)が軟化するように設定される。この状態で、仮支持積層体130’を両加圧部材51,52間に配置し、該仮支持積層体130’(ひいては高分子材料結合層111)の温度が上記中間温度θ1に安定するまで若干待機する。   FIG. 6 illustrates details of the bonding process, and FIG. 7 illustrates a control pattern of pressure and temperature during the bonding process. As shown in step 1 of FIG. 6, the resistance heater 49 is heated and heated to an intermediate temperature θ1 lower than the final bonding temperature θ2. The intermediate temperature θ1 is set, for example, in the range of 80 ° C. or more and 150 ° C. or less so that the polymer material bonding layer 111 (pressure cushion layer) to which the temporary support substrate 110 is bonded is softened. In this state, the temporary support laminate 130 ′ is disposed between the pressure members 51 and 52 until the temperature of the temporary support laminate 130 ′ (and thus the polymer material bonding layer 111) is stabilized at the intermediate temperature θ1. Wait a little.

仮支持積層体130’の温度が上記中間温度θ1に到達すれば、工程2に示すように、該中間温度θ1に保持した状態で、仮支持積層体130’への貼り合わせ加圧を開始する。この加圧は、両加圧部材51,52を駆動機構により相対的に接近させることにより行なう。高分子材料結合層111が予め十分に軟化していることで、該高分子材料結合層111は、反りや厚さ不均一を生じた化合物半導体層50の形状に追従して変形する。これにより、仮支持基板110側からの加圧力を面内に均一に伝達する圧力伝達媒体として機能し、化合物半導体層50の割れや、図16に示すようなミクロクラックMCの発生防止に効果を発揮する。特に、化合物半導体層50に反り変形が生じている場合、高分子材料結合層111の流動性を高めておくことで、化合物半導体層50の変形に対する拘束も弱まるので、割れやミクロクラックの防止効果は一層顕著となる。なお、中間温度θ1付近での昇温速度を小さくすれば、中間温度θ1での等温保持を必ずしも行なわなくてよい場合がある。   When the temperature of the temporary support laminated body 130 ′ reaches the intermediate temperature θ1, as shown in step 2, the pressure bonding to the temporary support laminated body 130 ′ is started in the state where the intermediate temperature θ1 is maintained. . This pressurization is performed by relatively bringing the pressure members 51 and 52 closer to each other by the drive mechanism. Since the polymer material bonding layer 111 is sufficiently softened in advance, the polymer material bonding layer 111 is deformed following the shape of the compound semiconductor layer 50 that is warped or has a non-uniform thickness. This functions as a pressure transmission medium that uniformly transmits the applied pressure from the temporary support substrate 110 side in the surface, and is effective in preventing cracks in the compound semiconductor layer 50 and microcracks MC as shown in FIG. Demonstrate. In particular, when the compound semiconductor layer 50 is warped and deformed, the restraint against deformation of the compound semiconductor layer 50 is weakened by increasing the fluidity of the polymer material bonding layer 111, so that the effect of preventing cracks and microcracks can be prevented. Becomes even more prominent. Note that if the rate of temperature increase near the intermediate temperature θ1 is reduced, isothermal holding at the intermediate temperature θ1 may not necessarily be performed.

なお、化合物半導体層50やSi基板7あるいは仮支持基板110の厚さ不均一や、高分子材料結合層111の塗付厚さの不均一等により、仮支持積層体130’の両主表面が傾斜している場合は、加圧部材51,52の加圧面同士が互いに平行となるように軸合わせされた油圧式や機械式の一軸駆動機構を用いると、加圧部材51,52の加圧面が仮支持積層体130’の主表面に偏って当たり、加圧力の不均一化が著しくなる。そこで、図9に示すように、第二加圧部材52の加圧面法線方向Oを可変に構成し、仮支持積層体130’の2つの主表面が互いに傾斜している場合は、第二加圧部材の加圧面法線O方向が仮支持積層体130’の第二主表面の法線方向Oと一致するように、該第二加圧部材52の仮支持積層体130’に対する加圧姿勢を矯正しつつ加圧駆動する加圧駆動機構53を設けておくとよい。第一加圧部材51の加圧面法線方向Oを固定にしておけば、第一加圧部材51の加圧面法線O方向も仮支持積層体130’の第一主表面の法線Oと一致した状態となる。例えば、加圧駆動機構53は、第二加圧部材52を、仮支持積層体130’に面しているのと反対側から流体圧を介して加圧駆動する流体加圧機構として構成することができる。該加圧駆動機構53の要部は、充填空間形成体55と可撓性密閉部材56とを有する。充填空間形成体55は、第二加圧部材52に対し、仮支持積層体130’に面しているのと反対側に加圧流体Fの充填空間54を形成し、該第二加圧部材52とともに充填空間54の区画壁の一部をなす。また、可撓性密閉部材56は、充填空間形成体55と第二加圧部材52とを充填空間54を密閉する形で連結するとともに、充填空間54内に加圧流体Fが圧入されたときの、第二加圧部材52の仮支持積層体130’に対する加圧姿勢の変化を吸収する働きをなす。加圧流体Fとしては空気等の気体のほか、油や水などの液体を用いてもよい。充填空間54への加圧流体Fの圧入力により、加圧力を所期の値に調整できる。 It should be noted that both main surfaces of the temporary support laminate 130 ′ are caused by non-uniform thickness of the compound semiconductor layer 50, Si substrate 7 or temporary support substrate 110, non-uniform coating thickness of the polymer material bonding layer 111, etc. When the pressure members 51 and 52 are inclined, the pressure surfaces of the pressure members 51 and 52 can be obtained by using a hydraulic or mechanical uniaxial drive mechanism in which the pressure surfaces of the pressure members 51 and 52 are aligned with each other. Is biased to the main surface of the temporary support laminate 130 ′, and the non-uniformity of the applied pressure becomes significant. Therefore, as shown in FIG. 9, when the pressure surface normal line direction O2 of the second pressure member 52 is configured to be variable and the two main surfaces of the temporary support laminate 130 ′ are inclined with respect to each other, The temporary support laminate 130 ′ of the second pressurizing member 52 so that the pressurizing surface normal O 2 direction of the two pressurizing members coincides with the normal direction O 4 of the second main surface of the temporary support laminate 130 ′. It is preferable to provide a pressurization drive mechanism 53 that performs pressurization while correcting the pressurization posture with respect to. If the pressing surface normal direction O 1 of the first pressing member 51 is fixed, the pressing surface normal O 1 direction of the first pressing member 51 is also normal to the first main surface of the temporary support laminate 130 ′. It becomes a state consistent with O 3 . For example, the pressurization drive mechanism 53 is configured as a fluid pressurization mechanism that pressurizes the second pressurization member 52 from the opposite side facing the temporary support laminate 130 ′ via fluid pressure. Can do. The main part of the pressure drive mechanism 53 includes a filling space forming body 55 and a flexible sealing member 56. The filling space forming body 55 forms a filling space 54 of the pressurized fluid F on the opposite side of the second pressurizing member 52 facing the temporary support laminate 130 ′, and the second pressurizing member 52 forms a part of the partition wall of the filling space 54. The flexible sealing member 56 connects the filling space forming body 55 and the second pressurizing member 52 so as to seal the filling space 54, and when the pressurized fluid F is pressed into the filling space 54. The second pressure member 52 serves to absorb the change in the pressure posture of the temporary support laminate 130 ′. As the pressurized fluid F, a liquid such as oil or water may be used in addition to a gas such as air. By applying pressure of the pressurized fluid F to the filling space 54, the applied pressure can be adjusted to a desired value.

化合物半導体層50側とSi基板7側とにそれぞれ形成したAu系金属層10a,10b同士の密着状態を高めるには、昇温下での加圧により柔らかいAu系金属層10a,10b同士の塑性流動的な追従変形を促して、反りに抗してAu系金属層10a,10b同士を均一に密着させつつ相互拡散を生じさせることが、均一で強固な貼り合わせ状態を得る上で重要である。加圧時の塑性流動的なAu系金属層10a,10b同士の追従変形には時間を要するため、設定圧力への昇圧速度を過度に大きく設定しすぎると、反りに抗したAu系金属層10a,10bの変形が昇圧に追従しきれなくなって、化合物半導体層50に割れやクラック、特に、図16のように、荷重集中しやすい接合合金化層31周囲へのミクロクラックが発生しやすくなる。また、加圧時の高分子材料結合層111の流動には一定の遅れが伴なうので、加圧に際しての昇圧速度を過度に大きく設定しすぎると、化合物半導体層50の形状に合わせた高分子材料結合層111の変形が昇圧に追従しきれなくなり、化合物半導体層50への割れやミクロクラックの発生が却って助長されることになる。従って、該昇圧速度は、このような不具合が生じないよう、例えば100kPa/分以下、望ましくは50kPa/分以下に設定するのがよい。ただし、過度に昇圧速度を小さくすることは貼り合わせ工程の能率低下にもつながるので、昇圧速度は1kPa/分以上に設定することが望ましい。   In order to increase the adhesion between the Au-based metal layers 10a and 10b formed on the compound semiconductor layer 50 side and the Si substrate 7 side, respectively, the plasticity between the soft Au-based metal layers 10a and 10b is increased by pressurization at a high temperature. In order to obtain a uniform and strong bonding state, it is important to promote fluid follow-up deformation and to cause mutual diffusion while evenly adhering the Au-based metal layers 10a and 10b against warping. . Since it takes time to follow and deform between the plastic fluid Au-based metal layers 10a and 10b during pressurization, if the pressure increase rate to the set pressure is set too large, the Au-based metal layer 10a resists warping. , 10b can no longer follow the pressure increase, and cracks and cracks in the compound semiconductor layer 50, in particular, microcracks around the bonded alloyed layer 31 where the load tends to concentrate as shown in FIG. In addition, since the flow of the polymer material bonding layer 111 during pressurization is accompanied by a certain delay, if the pressurization speed during pressurization is set excessively large, a high height that matches the shape of the compound semiconductor layer 50 is obtained. The deformation of the molecular material bonding layer 111 cannot follow the pressure increase, and the generation of cracks and microcracks in the compound semiconductor layer 50 is promoted. Accordingly, the boosting speed is set to, for example, 100 kPa / min or less, preferably 50 kPa / min or less so that such a problem does not occur. However, since excessively reducing the pressure increase rate also leads to a reduction in efficiency of the bonding process, it is desirable to set the pressure increase rate to 1 kPa / min or more.

仮支持積層体130’(積層体130)は上記中間温度θ1から最終的な貼り合わせ温度θ2までさらに昇温する。貼り合わせ温度θ2は200℃以上280℃以下であり、2つのAu系金属層10a,10b同士の拡散が十分に進行し、他方、Si基板7から第二Au系金属層10bへのSi拡散はそれほど急速に進行せず(Si拡散素子層10cによりSi基板7からのSi拡散が抑制されていることの効果も大きい)、かつ、加圧クッション層をなす高分子材料コーティング層150が軟化するように設定されている。図8に示すように、高分子材料コーティング層150が軟化した状態で貼り合わせ加圧を行なうと、反りを生じた仮支持積層体130’の主表面側表層部が軟化した高分子材料コーティング層150に食い込み、仮支持積層体130’の主表面形状に追従して高分子材料コーティング層150が変形する。これにより、貼り合わせの加圧力をAu系金属層10a,10bの貼り合わせ界面に対し、より均一に付与することができ、割れやミクロクラック防止に有効となる。   Temporary support laminated body 130 '(laminated body 130) is further heated from the intermediate temperature θ1 to the final bonding temperature θ2. The bonding temperature θ2 is 200 ° C. or more and 280 ° C. or less, and the diffusion between the two Au-based metal layers 10a and 10b proceeds sufficiently. On the other hand, the Si diffusion from the Si substrate 7 to the second Au-based metal layer 10b is It does not proceed so rapidly (the effect of suppressing Si diffusion from the Si substrate 7 by the Si diffusion element layer 10c is great) and the polymer material coating layer 150 forming the pressure cushion layer is softened. Is set to As shown in FIG. 8, the polymer material coating layer in which the main surface side surface layer portion of the temporary support laminate 130 ′ that has warped is softened when bonding and pressurization is performed in a state where the polymer material coating layer 150 is softened. The polymer material coating layer 150 is deformed following the main surface shape of the temporary support laminate 130 ′. Thereby, the applied pressure of bonding can be more uniformly applied to the bonding interface of the Au-based metal layers 10a and 10b, which is effective in preventing cracks and microcracks.

また、本実施形態では、貼り合わせ温度θ2よりも低い中間温度θ1での保持中に、貼り合わせの加圧を開始し、その加圧に一定時間(図7においてはt1)遅れる形で、中間温度θ1から貼り合わせ温度θ2への昇温を開始するようにしている。中間温度θ1が十分に低く、しかも本実施形態では拡散阻止層10cを設けているので、Si基板7から第二Au系金属層10bへのSi拡散はそれほど進まず、第一Au系金属層10aとの貼り合わせ面(第一主表面)も清浄な状態に保たれている。その状態で、貼り合わせの加圧を開始することで、Au系金属層10a,10b同士をSi拡散により汚染されない状態で均一に密着させることができる。   Further, in the present embodiment, during the holding at the intermediate temperature θ1 lower than the bonding temperature θ2, the pressing of the bonding is started, and the intermediate pressure is delayed by a certain time (t1 in FIG. 7). The temperature rise from the temperature θ1 to the bonding temperature θ2 is started. Since the intermediate temperature θ1 is sufficiently low and the diffusion blocking layer 10c is provided in the present embodiment, Si diffusion from the Si substrate 7 to the second Au-based metal layer 10b does not proceed so much, and the first Au-based metal layer 10a. The bonding surface (first main surface) is also kept clean. In this state, by starting the pressing of the bonding, the Au-based metal layers 10a and 10b can be uniformly adhered without being contaminated by the Si diffusion.

なお、貼り合わせ温度θ2への昇温時において、仮支持積層体130’(積層体120)の温度分布が十分安定化しないうちに、最終的な設定圧力P3(5kPa以上1000kPa以下)までの昇圧を急速に行なうと、化合物半導体層50に割れを生じやすくなる。本実施形態では、図7に示すように、昇圧開始後において、最終的な設定圧力P3よりも低い中間圧力P2に到達したら、そこで昇圧を一旦中断し、該中間圧力P2を保ちつつ所定の時間t2だけ保持する(図6:工程3)。そして、この中間圧力P2での保持中に、中間温度θ1から貼り合わせ温度θ2への昇温を開始し、その昇温開始にt2だけ遅れる形で、設定圧力P3への昇圧を再開するようにしている(設定圧力P3まで時間t3にて到達している)。つまり、中間圧力P2での保持により設定圧力P3までの昇圧を作為的に遅らせ、その間に貼り合わせ温度θ2への昇温を先行させることによって、仮支持積層体130’の温度分布を安定化させるためのいわば時間稼ぎを行なうことができ、温度分布不均一による不都合な応力発生等を抑制した状態で、最終的な設定圧力P3への加圧を継続できるので、化合物半導体層50での割れ発生を効果的に抑制することができる。また、中間圧力P2で保持することで、Au系金属層10a,10b同士の密着状態をより均一化することができる。その結果、目視確認できるようなマクロな割れはもちろん、接合合金化層31の周囲における化合部半導体層50へのミクロクラック発生も、より効果的に抑制することができるようになる。   At the time of raising the temperature to the bonding temperature θ2, the temperature is increased to the final set pressure P3 (5 kPa or more and 1000 kPa or less) before the temperature distribution of the temporary support laminate 130 ′ (laminate 120) is not sufficiently stabilized. If the step is rapidly performed, the compound semiconductor layer 50 is likely to be cracked. In the present embodiment, as shown in FIG. 7, after reaching the intermediate pressure P2 lower than the final set pressure P3 after the start of pressure increase, the pressure increase is temporarily interrupted there, and the intermediate pressure P2 is maintained for a predetermined time. Only t2 is held (FIG. 6: step 3). During the holding at the intermediate pressure P2, the temperature increase from the intermediate temperature θ1 to the bonding temperature θ2 is started, and the pressure increase to the set pressure P3 is resumed in a form delayed by t2 from the start of the temperature increase. (It reaches the set pressure P3 at time t3). In other words, the temperature distribution of the temporary support laminate 130 ′ is stabilized by delaying the pressure increase to the set pressure P3 by holding at the intermediate pressure P2 and, in advance, increasing the temperature to the bonding temperature θ2 in the meantime. In other words, the compound semiconductor layer 50 can be cracked because the final pressurization to the preset pressure P3 can be continued in a state in which time can be saved and inconvenient stress generation due to uneven temperature distribution is suppressed. Can be effectively suppressed. Further, by maintaining at the intermediate pressure P2, the adhesion state of the Au-based metal layers 10a and 10b can be made more uniform. As a result, the occurrence of microcracks in the compound semiconductor layer 50 around the bonded alloyed layer 31 as well as macro cracks that can be visually confirmed can be more effectively suppressed.

本実施形態では、中間圧力P2を最終設定圧力P3の50%以上70%以下に設定している。P2がP3の50%未満になると、Au系金属層10a,10b同士の密着状態の改善効果が不十分となる。他方、P2がP3の70%を超えると、化合物半導体層50での割れが生じやすくなる。また、中間圧力P2に至るまで、及び該中間圧力P2から最終設定圧力P3に至るまでの昇圧速度は、前述のごとくそれぞれ1kPa/分以上100kPa/分以下とすることで、化合物半導体層50への割れやミロクラックの発生を効果的に防止できる。ただし、図7に一点鎖線で示すように、中間圧力保持を省略し、該中間圧力保持期間をいわば吸収する形で、前後の期間の昇圧速度を減少させ、100kPa/分以下の一定の速度で設定圧力P3まで連続的に昇圧させることも可能である。   In the present embodiment, the intermediate pressure P2 is set to 50% or more and 70% or less of the final set pressure P3. When P2 is less than 50% of P3, the effect of improving the adhesion between the Au-based metal layers 10a and 10b becomes insufficient. On the other hand, when P2 exceeds 70% of P3, the compound semiconductor layer 50 is likely to be cracked. Further, the pressure increase rate from the intermediate pressure P2 to the final set pressure P3 is set to 1 kPa / min or more and 100 kPa / min or less as described above to reach the compound semiconductor layer 50. Generation of cracks and mirocracks can be effectively prevented. However, as shown by the one-dot chain line in FIG. 7, the intermediate pressure holding is omitted, and the intermediate pressure holding period is absorbed, so that the pressure increase rate in the preceding and following periods is reduced, and at a constant speed of 100 kPa / min or less. It is also possible to continuously increase the pressure to the set pressure P3.

温度が貼り合わせ温度θ2に到達し、加圧力が設定圧力P3に到達したら、その状態で10分以上60分以下の範囲で保持する。これにより、第一Au系金属層10a及び第二Au系金属層10bとの間に、化合物半導体層50に多少の反りが生じていても割れやミクロクラック等を生ずることなく、全面に渡って極めて均一な貼り合わせ状態を形成することができる。   When the temperature reaches the bonding temperature θ2 and the applied pressure reaches the set pressure P3, the temperature is maintained in the range of 10 minutes to 60 minutes. Thereby, even if some warp is generated in the compound semiconductor layer 50 between the first Au-based metal layer 10a and the second Au-based metal layer 10b, the entire surface without causing cracks or microcracks. An extremely uniform bonded state can be formed.

以上の一連の工程の作用・効果は以下のようにまとめることができる。すなわち、80℃以上150℃以下の中間温度θ1にて、1kPa/分以上100kPa/分以下に制御された条件で徐々に昇圧を行なうこと、さらには、設定圧力P3(5kPa以上1000kPa以下)の50%以上70%以下に調整された中間圧力P2にて保持を行なうことにより、軟化した高分子材料結合層111を介して第一Au系金属層10a及び第二Au系金属層10bとを均一に密着させることができ、両者の貼り合わせ界面にSi拡散の影響が及ぶことを効果的に防止できる。また、Si拡散素子層10cにより、Si基板7から第二Au系金属層10bへのSi拡散自体が抑制されていることの効果も大きい。そして、その中間温度θ1での保持中に加圧開始した後、貼り合わせ温度θ2に向けた昇温を再開することで、化合物半導体層50への割れやミクロクラック発生を効果的に抑制しつつ、仮支持積層体130’を貼り合わせ温度θ2及び設定圧力P3に到達させることができる。そして、その状態で10分以上60分以下の範囲で保持することにより、清浄な状態で密着した第一Au系金属層10a及び第二Au系金属層10b同士の拡散を、貼り合わせ面の全面に渡って均一に進行させることができ、極めて強固な貼り合わせ状態を得ることができる。また、貼り合わせ温度θ2が200℃以上280℃以下に設定されていることで、保持時間が60分以下に留まる限り、Si基板7からのSi拡散の影響も反射面(第一Au系金属層10aが形成する)に及びにくく、良好な反射率を達成できる。   The actions and effects of the above series of steps can be summarized as follows. That is, the pressure is gradually increased at an intermediate temperature θ1 of 80 ° C. or more and 150 ° C. or less under a condition controlled to 1 kPa / min or more and 100 kPa / min or less, and further, 50 of the set pressure P3 (5 kPa or more and 1000 kPa or less). By holding at an intermediate pressure P2 adjusted to not less than 70% and not more than 70%, the first Au-based metal layer 10a and the second Au-based metal layer 10b are uniformly distributed through the softened polymer material bonding layer 111. It can be made to adhere and can effectively prevent the influence of Si diffusion on the bonding interface between the two. In addition, the Si diffusion element layer 10c has a great effect that the Si diffusion itself from the Si substrate 7 to the second Au-based metal layer 10b is suppressed. Then, after pressurization is started during the holding at the intermediate temperature θ1, the temperature rise toward the bonding temperature θ2 is resumed, thereby effectively suppressing the occurrence of cracks and microcracks in the compound semiconductor layer 50. The temporary support laminate 130 ′ can be made to reach the bonding temperature θ2 and the set pressure P3. Then, by holding in that state for 10 minutes or more and 60 minutes or less, the diffusion of the first Au-based metal layer 10a and the second Au-based metal layer 10b that are in close contact with each other can be diffused over the entire bonding surface. Over a wide range, and a very strong bonding state can be obtained. In addition, since the bonding temperature θ2 is set to 200 ° C. or higher and 280 ° C. or lower, the influence of Si diffusion from the Si substrate 7 is also reflected on the reflecting surface (first Au-based metal layer) as long as the holding time remains 60 minutes or shorter. 10a is formed), and good reflectance can be achieved.

なお、第一Au系金属層10a及び第二Au系金属層10bとは、いずれも酸化しにくいAuを主体に構成されているので、上記貼り合わせ熱処理は、例えば大気中でも問題なく行なうことができる。また、本実施形態の工程では、この段階で既に光取出側及び貼り合わせ側の各合金化熱処理が既に終わっており、貼り合わせ熱処理がそれよりも低温で実施されることにより、接合合金化層からの合金成分がAu系金属層10からなる反射面の面内に拡散することが効果的に抑制され、前述のコンタクト用合金成分拡散率を30%以下に留めることができ、ひいてはより反射率の高い反射面を得ることができる。   Since the first Au-based metal layer 10a and the second Au-based metal layer 10b are mainly composed of Au that is difficult to oxidize, the bonding heat treatment can be performed without any problem even in the atmosphere, for example. . Further, in the process of this embodiment, the alloying heat treatment on the light extraction side and the bonding side has already been completed at this stage, and the bonding heat treatment is performed at a lower temperature than that, so that the bonding alloyed layer is formed. Is effectively suppressed from diffusing into the surface of the reflecting surface made of the Au-based metal layer 10, and the above-described alloy component diffusivity for the contact can be kept below 30%. Highly reflective surface can be obtained.

貼り合わせ熱処理が完了したら仮支持基板分離工程を行なう。仮支持基板分離工程は、図4の工程8に示すように、高分子材料結合層111を加熱・軟化させ、仮支持基板110を分離・除去する。なお、この分離は、工程7の貼り合わせ熱処理の際に同時に行なうことも可能である。その後、工程9に示すように、化合物半導体層50の第一主表面上に残存している高分子材料結合層111を、トルエンやケトン系溶剤(例えばメチルエチルケトン(MEK))等の有機溶剤を用いて溶解・除去する。   When the bonding heat treatment is completed, a temporary support substrate separation step is performed. In the temporary support substrate separation step, as shown in Step 8 of FIG. 4, the polymer material bonding layer 111 is heated and softened, and the temporary support substrate 110 is separated and removed. Note that this separation can be performed simultaneously with the bonding heat treatment in step 7. Thereafter, as shown in Step 9, the polymer material bonding layer 111 remaining on the first main surface of the compound semiconductor layer 50 is made of an organic solvent such as toluene or a ketone solvent (for example, methyl ethyl ketone (MEK)). Dissolve and remove.

なお、化合物半導体層50に接着された状態のまま仮支持基板110を有機溶剤中に浸漬して高分子材料結合層111を溶解し、仮支持基板110の分離を行なうようにしてもよい。また、高分子材料結合層111は、熱可塑性樹脂に代えてエポキシ樹脂やウレタン樹脂を採用することもできる。これにより、貼り合わせ加熱中における高分子材料結合層111からのガス発生をより効果的に抑制することができる。なお、エポキシ樹脂を使用する場合はアミン硬化型のもの、及びポリアミド硬化型のもの、のいずれを採用してもよい。高分子材料結合層111を熱硬化性樹脂にて構成する場合は、貼り合わせ加熱時に軟化させることができないので、該高分子材料結合層111自体を加圧クッション層として利用することはできない。この場合、前述の熱可塑性樹脂からなる高分子材料コーティング層150、あるいは熱可塑性樹脂からなる高分子材料シートを加圧クッション層として利用することが有効である。   Alternatively, the temporary support substrate 110 may be separated by immersing the temporary support substrate 110 in an organic solvent while being bonded to the compound semiconductor layer 50 to dissolve the polymer material bonding layer 111. Further, the polymer material bonding layer 111 may employ an epoxy resin or a urethane resin instead of the thermoplastic resin. Thereby, gas generation from the polymer material bonding layer 111 during the bonding heating can be more effectively suppressed. In addition, when using an epoxy resin, you may employ | adopt either an amine curable type and a polyamide curable type. In the case where the polymer material bonding layer 111 is composed of a thermosetting resin, the polymer material bonding layer 111 itself cannot be used as a pressure cushion layer because it cannot be softened at the time of bonding and heating. In this case, it is effective to use the polymer material coating layer 150 made of the aforementioned thermoplastic resin or the polymer material sheet made of the thermoplastic resin as the pressure cushion layer.

以上においては、理解を容易にする便宜上、貼り合わせ結合体130を作る工程を素子単体の積層形態にて図示しつつ説明していたが、実際は、複数の素子チップがマトリックス状に配列した形で一括形成された貼り合わせウェーハが作成される。そして、この貼り合わせウェーハを通常の方法によりダイシングして素子チップとし、これを支持体に固着してリード線のワイヤボンディング等を行った後、樹脂封止をすることにより最終的な発光素子が得られる。   In the above, for the purpose of facilitating understanding, the process of forming the bonded assembly 130 has been described in the form of a single element stack, but in practice, a plurality of element chips are arranged in a matrix. A bonded wafer formed in a lump is created. Then, the bonded wafer is diced by an ordinary method to form an element chip, which is fixed to a support and subjected to wire bonding of a lead wire, etc., and then sealed with a resin to obtain a final light emitting element. can get.

以上の実施形態では、図5に示すごとく、加圧部材51,52の金属本体部51a,52aの加圧面に高分子材料コーティング層150,150を加圧クッション層として形成していたが、図12に示すように、仮支持積層体130’と加圧部材51,52との間に、加圧クッション層をなす高分子材料シート151,151を着脱可能に配置するようにしてもよい。また、積仮支持層体130’の反りが小さい場合は、図13に示すように、高分子材料コーティング層ないし高分子材料シートの一方又は双方を省略することも可能である。図13は、高分子材料コーティング層ないし高分子材料シートの双方を省略し、仮支持基板110を貼り合わせるための高分子材料結合層111のみを加圧クッション層として設けた例である。   In the above embodiment, as shown in FIG. 5, the polymer material coating layers 150 and 150 are formed as the pressure cushion layers on the pressure surfaces of the metal main body portions 51a and 52a of the pressure members 51 and 52. 12, the polymer material sheets 151 and 151 forming the pressure cushion layer may be detachably disposed between the temporary support laminate 130 ′ and the pressure members 51 and 52. Further, when the warp of the provisional support layer 130 'is small, as shown in FIG. 13, one or both of the polymer material coating layer and the polymer material sheet can be omitted. FIG. 13 is an example in which both the polymer material coating layer and the polymer material sheet are omitted, and only the polymer material bonding layer 111 for bonding the temporary support substrate 110 is provided as a pressure cushion layer.

また、製造対象となる発光素子100は、図14に示すように、Au系金属層10(第一Au系金属層10a+第二Au系金属層10b)を専ら貼り合わせに用い、Au系金属層10とは別の反射用金属層10rを、Au系金属層10と化合物半導体層50との間に設けることもできる。このような反射用金属層10rとしては、Agを主成分とするAg系反射層や、Alを主成分とするAl系反射層を用いることができる。この場合、貼り合わせ側接合合金化層は、Ag系反射層の場合はAgGeNiなどのAg系材料にて、また、Al系反射層の場合はAlGeNiなどのAl系材料にて構成することもできる。製造工程は略同じであるが、コンタクト金属部32を反射用金属層10rで覆った後、さらに第一Au系金属層10aで覆う点が相違する。   In addition, as shown in FIG. 14, the light emitting device 100 to be manufactured uses an Au-based metal layer 10 (first Au-based metal layer 10a + second Au-based metal layer 10b) exclusively for bonding, and an Au-based metal layer. A reflective metal layer 10 r different from 10 may be provided between the Au-based metal layer 10 and the compound semiconductor layer 50. As such a reflective metal layer 10r, an Ag-based reflective layer mainly composed of Ag or an Al-based reflective layer mainly composed of Al can be used. In this case, the bonding-side bonded alloyed layer can be composed of an Ag-based material such as AgGeNi in the case of an Ag-based reflective layer, or an Al-based material such as AlGeNi in the case of an Al-based reflective layer. . The manufacturing process is substantially the same except that the contact metal portion 32 is covered with the reflective metal layer 10r and then covered with the first Au-based metal layer 10a.

さらに、Si基板7に代えて、GaP等からなる透明導電性基板を化合物半導体層に直接又はITO(Indium Tin Oxide)などの導電性酸化物層を介して貼り合わせた発光素子構造にも本発明を適用できる。   Further, the present invention is also applied to a light emitting element structure in which a transparent conductive substrate made of GaP or the like is bonded to a compound semiconductor layer directly or via a conductive oxide layer such as ITO (Indium Tin Oxide) instead of the Si substrate 7. Can be applied.

また、発光層部24は、活性層及びクラッド層が、InAlGaNあるいはMgZnOにて構成されたダブルへテロ構造を有するものとして構成することもできる。   Moreover, the light emitting layer part 24 can also be comprised as an active layer and a clad layer having a double hetero structure comprised of InAlGaN or MgZnO.

本発明の適用対象となる発光素子の一例を示す模式図。The schematic diagram which shows an example of the light emitting element used as the application object of this invention. 本発明の発光素子の製造方法の一例を示す工程説明図。Process explanatory drawing which shows an example of the manufacturing method of the light emitting element of this invention. 図2に続く工程説明図。Process explanatory drawing following FIG. 図3に続く工程説明図。Process explanatory drawing following FIG. 貼り合わせ装置の要部を説明する模式図。The schematic diagram explaining the principal part of a bonding apparatus. 貼り合わせ工程の一例を、より詳細に説明する図。The figure explaining an example of a bonding process in detail. 貼り合わせ工程における加熱及び加圧の制御パターンの一例を模式的に説明する図。The figure which illustrates typically an example of the control pattern of the heating and pressurization in a bonding process. 貼り合わせ工程における加圧クッション層の作用を模式的に示す説明図。Explanatory drawing which shows typically the effect | action of the pressurization cushion layer in a bonding process. より望ましい貼り合わせ装置の要部を説明する模式図。The schematic diagram explaining the principal part of a more preferable bonding apparatus. 化合物半導体層に反りが生ずる様子を説明する模式図。The schematic diagram explaining a mode that curvature generate | occur | produces in a compound semiconductor layer. 仮支持基板の貼り合わせにより化合物半導体層の反りが軽減される様子を説明する模式図。The schematic diagram explaining a mode that the curvature of a compound semiconductor layer was reduced by bonding of a temporary support substrate. 加圧クッション層の変形例を、貼り合わせ装置の要部とともに説明する模式図。The schematic diagram explaining the modification of a pressurization cushion layer with the principal part of a bonding apparatus. 加圧部材側の加圧クッション層を省略した例を示す模式図。The schematic diagram which shows the example which abbreviate | omitted the pressurization cushion layer by the side of a pressurization member. 本発明の適用対象となる発光素子の別例を示す模式図。The schematic diagram which shows another example of the light emitting element used as the application object of this invention. 貼り合わせ側接合合金化層の分散形成形態の一例を模式的に示す平面図。The top view which shows typically an example of the dispersion | distribution formation form of the bonding side joining alloying layer. 貼り合わせ側接合合金化層の周囲にて化合物半導体層にミクロクラックが形成される様子を示す平面図。The top view which shows a mode that a microcrack is formed in a compound semiconductor layer around the bonding side joining alloying layer.

符号の説明Explanation of symbols

1 GaAs単結晶基板(成長用基板)
7 シリコン基板(素子基板)
9 光取出側電極
9a’ AuBe接合金属層(光取出側接合金属層)
9a AuBe接合合金化層(光取出側接合合金化層)
10 Au系金属層(金属層)
10a 第一Au系金属層
10b 第二Au系金属層
20 電流拡散層
24 発光層部
31 AuGeNi接合合金化層(貼り合わせ側接合合金化層)
31d 拡散領域
50 化合物半導体層
51 第一加圧部材
51a 金属本体部
52 第二加圧部材
52a 金属本体部
100 発光素子
110 仮支持基板
111 高分子材料結合層(加圧クッション層)
120 仮支持貼り合わせ体
130 積層体
130’ 仮支持積層体
150 高分子材料コーティング層(加圧クッション層)
151 高分子材料シート(加圧クッション層)
MC ミクロクラック
1 GaAs single crystal substrate (growth substrate)
7 Silicon substrate (element substrate)
9 Light extraction side electrode 9a 'AuBe bonding metal layer (light extraction side bonding metal layer)
9a AuBe bonding alloying layer (light extraction side bonding alloying layer)
10 Au-based metal layer (metal layer)
DESCRIPTION OF SYMBOLS 10a 1st Au type metal layer 10b 2nd Au type metal layer 20 Current spreading layer 24 Light emitting layer part 31 AuGeNi joining alloying layer (bonding side joining alloying layer)
31d Diffusion region 50 Compound semiconductor layer 51 First pressure member 51a Metal main body 52 Second pressure member 52a Metal main body 100 Light emitting element 110 Temporary support substrate 111 Polymer material bonding layer (pressure cushion layer)
120 Temporary Support Laminated Body 130 Laminated Body 130 ′ Temporary Support Laminated Body 150 Polymer Material Coating Layer (Pressure Cushion Layer)
151 Polymer material sheet (pressure cushion layer)
MC micro crack

Claims (17)

発光層部を有する化合物半導体層に金属層を介して素子基板が貼り合わされた発光素子の製造方法であって、
前記化合物半導体層の第二主表面に前記金属層と前記素子基板とを重ね合わせた積層体を作成し、該積層体を第一加圧部材と第二加圧部材との間にて貼り合わせ加圧しつつ貼り合わせ温度に加熱することにより、前記化合物半導体層と前記素子基板とを前記金属層を介して貼り合わせるとともに、
前記貼り合わせ温度よりも低温にて前記貼り合わせ加圧を開始する一方、該加圧開始時の温度から前記貼り合わせ温度に到達するまでの前記積層体の昇温を、当該加圧開始よりも遅れたタイミングにて開始することを特徴とする発光素子の製造方法。
A method for manufacturing a light emitting device in which an element substrate is bonded to a compound semiconductor layer having a light emitting layer portion via a metal layer,
A laminated body in which the metal layer and the element substrate are overlaid on the second main surface of the compound semiconductor layer is created, and the laminated body is bonded between the first pressure member and the second pressure member. Bonding the compound semiconductor layer and the element substrate through the metal layer by heating to the bonding temperature while applying pressure,
While the laminating pressure is started at a temperature lower than the laminating temperature, the temperature rise of the laminate from the temperature at the start of pressurization until the laminating temperature is reached, A method for manufacturing a light emitting element, characterized by starting at a delayed timing.
前記化合物半導体層の第二主表面に、該化合物半導体層との接触抵抗を低減する合金成分を含有した接合金属層を分散形成して合金化熱処理することにより、該接合金属層と前記化合物半導体層とが合金化した接合合金化層を、一部が前記第二主表面よりも前記化合物半導体層側に食い込み、残余の部分が前記第二主表面から突出した形態で形成し、
前記接合合金化層の形成された前記化合物半導体層の第二主表面に前記金属層と前記素子基板とを重ね合わせた積層体を作成し、該積層体に対する前記貼り合わせ加圧を一定の設定圧力にて行なうとともに、
前記設定圧力に向けた昇圧の途上で、前記設定圧力よりも低い中間圧力にて昇圧を中断することにより該中間圧力を保持した後、前記昇圧を再開することを特徴とする請求項1記載の発光素子の製造方法。
A bonding metal layer containing an alloy component that reduces contact resistance with the compound semiconductor layer is dispersedly formed on the second main surface of the compound semiconductor layer and subjected to an alloying heat treatment to thereby form the bonding metal layer and the compound semiconductor. A bonded alloyed layer formed by alloying with the layer is formed in a form in which a part bites into the compound semiconductor layer side with respect to the second main surface and a remaining part protrudes from the second main surface;
A laminated body in which the metal layer and the element substrate are superimposed on the second main surface of the compound semiconductor layer on which the bonding alloyed layer is formed is formed, and the bonding pressure applied to the laminated body is set to a constant value. With pressure,
2. The pressure increase is resumed after maintaining the intermediate pressure by interrupting the pressure increase at an intermediate pressure lower than the set pressure in the course of the pressure increase toward the set pressure. Manufacturing method of light emitting element.
前記中間圧力への保持中において前記積層体の前記貼り合わせ温度に向けた昇温を継続することを特徴とする請求項2に記載の発光素子の製造方法。   The method for manufacturing a light-emitting element according to claim 2, wherein the temperature rise toward the bonding temperature of the laminated body is continued during the holding at the intermediate pressure. 前記発光素子は、前記発光層部がAlGaInP又はInAlGaNからなり、前記金属層がAuを主成分とするAu系金属層を有するものであり、前記素子基板がSi基板であり、
前記化合物半導体層の第二主表面に、該化合物半導体層との接触抵抗を低減する合金成分を含有した接合金属層を分散形成して合金化熱処理することにより、該接合金属層と前記化合物半導体層とが合金化した接合合金化層を、一部が前記第二主表面よりも前記化合物半導体層側に食い込み、残余の部分が前記第二主表面から突出した形態で形成し、
前記接合合金化層の形成された前記化合物半導体層の前記第二主表面に前記金属層の一部となるべきAuを主成分とする第一Au系金属層を形成し、他方、前記Si基板の貼り合わせ面に前記金属層の一部となるべきAuを主成分とする第二Au系金属層を形成し、前記第一Au系金属層と前記第二Au系金属層とを重ね合わせて積層体を作成し、該積層体を第一加圧部材と第二加圧部材との間にて貼り合わせ加圧しつつ貼り合わせ温度に加熱することにより、前記第一Au系金属層と前記第二Au系金属層とを貼り合わせにより結合するとともに、
前記Si基板からのSi成分が前記第二Au系金属層へ拡散するのを防ぐSi拡散阻止層を、前記Si基板と前記第二Au系金属層との間に形成し、
前記貼り合わせ加圧の設定圧力を5kPa以上1000kPa以下、前記貼り合わせ温度を200℃以上280℃以下、前記設定圧力での保持時間を10分以上60分以下に設定して前記貼り合わせを行なうことを特徴とする請求項1ないし請求項3のいずれか1項に記載の発光素子の製造方法。
In the light emitting element, the light emitting layer portion is made of AlGaInP or InAlGaN, the metal layer has an Au-based metal layer mainly composed of Au, and the element substrate is a Si substrate.
A bonding metal layer containing an alloy component that reduces contact resistance with the compound semiconductor layer is dispersedly formed on the second main surface of the compound semiconductor layer and subjected to an alloying heat treatment to thereby form the bonding metal layer and the compound semiconductor. A bonded alloyed layer formed by alloying with the layer is formed in a form in which a part bites into the compound semiconductor layer side with respect to the second main surface and a remaining part protrudes from the second main surface;
A first Au-based metal layer mainly composed of Au to be a part of the metal layer is formed on the second main surface of the compound semiconductor layer on which the bonding alloying layer is formed, while the Si substrate Forming a second Au-based metal layer mainly composed of Au to be a part of the metal layer on the bonding surface, and superimposing the first Au-based metal layer and the second Au-based metal layer. A laminated body is prepared, and the laminated body is heated between the first pressure member and the second pressure member while being bonded and pressurized to a bonding temperature. Bonding and bonding two Au-based metal layers,
Forming a Si diffusion preventing layer between the Si substrate and the second Au-based metal layer to prevent Si components from the Si substrate from diffusing into the second Au-based metal layer;
The bonding is performed by setting the pressure for bonding pressure to 5 kPa to 1000 kPa, the bonding temperature to 200 ° C. to 280 ° C., and the holding time at the set pressure to 10 minutes to 60 minutes. The method for manufacturing a light-emitting element according to claim 1, wherein:
前記化合物半導体層の第一主表面側に結合層を介して仮支持基板を貼り合わせ、さらに該化合物半導体層の第二主表面に前記金属層と前記素子基板とを重ね合わせた積層体を該仮支持基板とともに前記第一加圧部材と前記第二加圧部材との間で挟圧・加熱することを特徴とする請求項1ないし請求項4のいずれか1項に記載の発光素子の製造方法。   A laminated body in which a temporary support substrate is bonded to the first main surface side of the compound semiconductor layer via a bonding layer, and the metal layer and the element substrate are superimposed on the second main surface of the compound semiconductor layer, 5. The light-emitting element according to claim 1, wherein the first pressure member and the second pressure member are sandwiched and heated together with the temporary support substrate. Method. 前記結合層が高分子材料結合層からなり、前記化合物半導体層を前記素子基板に貼り合わせた後に、前記高分子材料結合層を加熱軟化又は有機溶剤に溶解することにより、前記仮支持基板を前記化合物半導体層から分離することを特徴とする請求項5記載の発光素子の製造方法。   The bonding layer is composed of a polymer material bonding layer, and after the compound semiconductor layer is bonded to the element substrate, the polymer material bonding layer is heated and softened or dissolved in an organic solvent, whereby the temporary support substrate is 6. The method for manufacturing a light-emitting element according to claim 5, wherein the light-emitting element is separated from the compound semiconductor layer. 前記高分子材料結合層がエポキシ樹脂又はウレタン樹脂からなることを特徴とする請求項6記載の発光素子の製造方法。   The method for manufacturing a light-emitting element according to claim 6, wherein the polymer material bonding layer is made of an epoxy resin or a urethane resin. 第一加圧部材の金属本体と前記積層体の第一主表面との間、及び第二加圧部材の金属本体と前記積層体の第二主表面との間の少なくともいずれかに熱可塑性高分子材料からなる加圧クッション層を介在させた状態で該積層体を配置し、前記加圧クッション層が軟化する貼り合わせ温度に前記積層体を加熱しつつ、前記第一加圧部材と前記第二加圧部材との間で該積層体を、軟化した前記加圧クッション層を介して加圧することにより、前記化合物半導体層と前記素子基板とを前記金属層を介して貼り合わせることを特徴とする請求項1ないし請求項7のいずれか1項に記載の発光素子の製造方法。   High thermoplasticity between at least one of the metal body of the first pressure member and the first main surface of the laminate and between the metal body of the second pressure member and the second main surface of the laminate. The laminated body is disposed with a pressure cushion layer made of a molecular material interposed, and the laminated body is heated to a bonding temperature at which the pressure cushion layer softens, while the first pressure member and the first pressure member are heated. The laminate is pressed between the two pressure members through the softened pressure cushion layer, and the compound semiconductor layer and the element substrate are bonded to each other through the metal layer. The manufacturing method of the light emitting element of any one of Claim 1 thru | or 7. 前記加圧クッション層は、前記金属本体の表面に形成された高分子材料コーティング層であることを特徴とする請求項8記載の発光素子の製造方法。   9. The method of manufacturing a light emitting device according to claim 8, wherein the pressure cushion layer is a polymer material coating layer formed on a surface of the metal body. 前記加圧クッション層は、前記金属本体と前記積層体との間に着脱可能に挿入される高分子材料シートであることを特徴とする請求項8記載の発光素子の製造方法。   9. The method of manufacturing a light emitting element according to claim 8, wherein the pressure cushion layer is a polymer material sheet that is detachably inserted between the metal body and the laminate. 前記高分子材料コーティング層又は前記高分子材料シートがフッ素系樹脂からなることを特徴とする請求項9又は請求項10に記載の発光素子の製造方法。   The method for manufacturing a light-emitting element according to claim 9, wherein the polymer material coating layer or the polymer material sheet is made of a fluororesin. 前記化合物半導体層の第一主表面側に、前記加圧クッション層をなす前記熱可塑性高分子材料からなる高分子材料結合層を介して仮支持基板を貼り合わせ、前記積層体を該仮支持基板とともに前記第一加圧部材と前記第二加圧部材との間で前記貼り合わせ加圧しつつ前記貼り合わせ温度に加熱することを特徴とする請求項8ないし請求項11のいずれか1項に記載の発光素子の製造方法。   A temporary support substrate is bonded to the first main surface side of the compound semiconductor layer via a polymer material bonding layer made of the thermoplastic polymer material forming the pressure cushion layer, and the laminate is attached to the temporary support substrate. The heating is performed to the bonding temperature while the bonding pressure is applied between the first pressure member and the second pressure member. Of manufacturing the light-emitting device. 前記発光素子は、前記化合物半導体層の光取出面となる第一主表面の一部を覆う形で光取出面側電極が形成される一方、該化合物半導体層の第二主表面に、前記発光層部からの光を前記光取出面側に反射させる反射面を有した金属層を介して前記素子基板が貼り合わされたものであり、前記積層体を、前記素子基板、前記金属層及び前記化合物半導体層がこの順序にて積層され、かつ、前記金属層と前記化合物半導体層との間に、該化合物半導体層と該金属層との接触抵抗を低減するための貼り合わせ側接合合金化層を配置したものとして形成し、
成長用基板の第一主表面上に前記化合物半導体層をエピタキシャル成長する化合物半導体層成長工程と、
前記化合物半導体層の第一主表面側に前記光取出面側電極を形成する光取出面側電極形成工程と、
前記化合物半導体層の第二主表面側に前記成長用基板が付随した状態で、前記光取出面側電極が形成された前記化合物半導体層の前記第一主表面に前記結合層を介して前記仮支持基板を貼り合わせ、その後、前記成長用基板を除去することにより、前記化合物半導体層と前記仮支持基板とが貼り合わされた仮支持貼り合わせ体を形成する仮支持貼り合わせ体形成工程と、
前記成長用基板の除去により露出した前記化合物半導体層の第二主表面に貼り合わせ側接合金属層を形成する貼り合わせ側接合金属層形成工程と、
前記貼り合わせ側接合金属層を前記化合物半導体層と合金化させて前記貼り合わせ側接合合金化層とする貼り合わせ側合金化熱処理を、前記仮支持貼り合わせ体の状態で行なう貼り合わせ側合金化熱処理工程と、
該貼り合わせ側合金化熱処理の終了後に、前記貼り合わせ温度を前記貼り合わせ側合金化熱処理工程よりも低温に設定して貼り合わせ処理を行なうことにより、該化合物半導体層の第二主表面に金属層を介して素子基板を貼り合せた素子基板貼り合わせ体を作成する素子基板貼り合わせ工程と、
前記素子基板貼り合わせ体から前記仮支持基板を分離する仮支持基板分離工程と、をこの順序にて実施することを特徴とする請求項5、請求項6、請求項7及び請求項12のいずれか1項に記載の発光素子の製造方法。
In the light emitting element, the light extraction surface side electrode is formed so as to cover a part of the first main surface which becomes the light extraction surface of the compound semiconductor layer, while the light emission element is formed on the second main surface of the compound semiconductor layer. The element substrate is bonded through a metal layer having a reflection surface that reflects light from the layer portion to the light extraction surface side, and the stacked body includes the element substrate, the metal layer, and the compound. A semiconductor layer is laminated in this order, and a bonded-side bonded alloyed layer for reducing contact resistance between the compound semiconductor layer and the metal layer is provided between the metal layer and the compound semiconductor layer. Formed as an arrangement,
A compound semiconductor layer growth step of epitaxially growing the compound semiconductor layer on the first main surface of the growth substrate;
A light extraction surface side electrode forming step of forming the light extraction surface side electrode on the first main surface side of the compound semiconductor layer;
With the growth substrate attached to the second main surface side of the compound semiconductor layer, the temporary main surface of the compound semiconductor layer on which the light extraction surface side electrode is formed is interposed via the bonding layer. A temporary support bonded body forming step of forming a temporary support bonded body in which the compound semiconductor layer and the temporary support substrate are bonded by bonding the support substrate and then removing the growth substrate;
A bonding side bonding metal layer forming step of forming a bonding side bonding metal layer on the second main surface of the compound semiconductor layer exposed by removing the growth substrate;
Bonding side alloying in which the bonding side alloying heat treatment is performed in the state of the temporary support bonded body by alloying the bonding side bonding metal layer with the compound semiconductor layer to form the bonding side bonding alloyed layer. A heat treatment step;
After the bonding-side alloying heat treatment is completed, the bonding temperature is set lower than the bonding-side alloying heat-treating step, and the bonding process is performed, so that a metal is formed on the second main surface of the compound semiconductor layer. An element substrate bonding step of creating an element substrate bonded body in which the element substrates are bonded through the layers;
The temporary support substrate separation step of separating the temporary support substrate from the element substrate bonded body is performed in this order, wherein any one of claims 5, 6, 7, and 12 is performed. A method for producing a light-emitting element according to claim 1.
前記光取出面側電極と前記化合物半導体層との接触抵抗を低減するために、前記光取出面側電極自身又は該光取出面側電極と前記化合物半導体層との間に配置された光取出面側接合金属層と前記化合物半導体層とを合金化する光取出側合金化熱処理を、前記素子基板貼り合わせ工程の前に実施することを特徴とする請求項13記載の発光素子の製造方法。   In order to reduce the contact resistance between the light extraction surface side electrode and the compound semiconductor layer, the light extraction surface side electrode itself or a light extraction surface disposed between the light extraction surface side electrode and the compound semiconductor layer 14. The method for manufacturing a light emitting element according to claim 13, wherein light extraction side alloying heat treatment for alloying a side bonding metal layer and the compound semiconductor layer is performed before the element substrate bonding step. 前記高分子材料結合層を加熱して軟化させた後、前記積層体に対する貼り合わせ加圧の昇圧を開始することを特徴とする請求項12ないし請求項14のいずれか1項に記載の発光素子の製造方法。   The light emitting device according to claim 12, wherein after the polymer material bonding layer is heated and softened, the pressure increase of the bonding pressure to the stacked body is started. Manufacturing method. 前記素子基板としてSi基板を用い、前記化合物半導体層の前記第二主表面に前記金属層の一部となるべき第一Au系金属層を形成し、他方、前記Si基板の貼り合わせ面に前記金属層の一部となるべき第二Au系金属層を形成し、前記第一Au系金属層と前記第二Au系金属層とを貼り合わせにより結合するとともに、
前記加圧クッション層として前記高分子材料コーティング層又は前記高分子材料シートのいずれかと前記高分子材料結合層とを併用し、かつ、前記高分子材料結合層として前記高分子材料コーティング層又は前記高分子材料シートを形成する熱可塑性高分子材料よりも軟化温度の低いものを採用し、
前記貼り合わせ温度以下であって前記高分子材料結合層が軟化する中間温度に前記積層体を加熱し、該中間温度への到達以降に前記積層体に対する貼り合わせ加圧の昇圧を開始し、該昇圧開始後に前記積層体を前記中間温度から前記貼り合わせ温度に向けて昇温する特徴とする請求項15記載の発光素子の製造方法。
A Si substrate is used as the element substrate, and a first Au-based metal layer to be a part of the metal layer is formed on the second main surface of the compound semiconductor layer, and on the other hand, the Si substrate is bonded to the bonding surface. Forming a second Au-based metal layer to be a part of the metal layer, bonding the first Au-based metal layer and the second Au-based metal layer by bonding,
Either the polymer material coating layer or the polymer material sheet and the polymer material binding layer are used in combination as the pressure cushion layer, and the polymer material coating layer or the high material layer is used as the polymer material binding layer. Adopting a softening temperature lower than the thermoplastic polymer material that forms the molecular material sheet,
The laminated body is heated to an intermediate temperature that is equal to or lower than the bonding temperature and the polymer material bonding layer is softened, and after the intermediate temperature is reached, pressure increase of the bonding pressure to the laminated body is started, The method for manufacturing a light-emitting element according to claim 15, wherein the temperature of the laminated body is increased from the intermediate temperature toward the bonding temperature after the start of pressure increase.
AlGaInP又はInAlGaNからなる発光層部を有する化合物半導体層に、Auを主成分とするAu系金属層を有した金属層を介して素子基板が貼り合わされ、
前記金属層と前記化合物半導体層との接合界面に、該化合物半導体層との接触抵抗を低減する合金成分を含有した接合金属層を前記化合物半導体層と合金化させた接合合金化層が、該接合合金化層の一部が前記化合物半導体層側に食い込み、残余の部分が前記金属層に食い込むように前記接合界面に分散形成され、
かつ、分散形成された接合合金化層の総数をNとし、個々の接合合金化層のうち、その周囲において該接合合金化層と接触する前記化合物半導体層にクラックを生じているものの個数をN1としたとき、N1/Nが0.05以下であることを特徴とする発光素子。
An element substrate is bonded to a compound semiconductor layer having a light emitting layer portion made of AlGaInP or InAlGaN via a metal layer having an Au-based metal layer mainly composed of Au,
A bonded alloyed layer obtained by alloying a bonded metal layer containing an alloy component that reduces contact resistance with the compound semiconductor layer at the bonded interface between the metal layer and the compound semiconductor layer with the compound semiconductor layer, A part of the bonding alloying layer bites into the compound semiconductor layer side, and the remaining part is dispersedly formed at the bonding interface so as to bite into the metal layer,
In addition, the total number of the bonded alloyed layers formed in a dispersed manner is N, and among the individual bonded alloyed layers, the number of the compound semiconductor layers that are in contact with the bonded alloyed layer in the periphery thereof is N1 And N1 / N is 0.05 or less.
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