JP2005107771A - High-throughput data transfer system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the following problem of a data transfer system that data transfer throughput at a slave side is reduced when requests of a plurality of masters compete with one another to the same slave, and data transfer throughput at a master side is reduced when the same master frequently changes a target slave of a data transfer request. <P>SOLUTION: In this data transfer system, even in a state that the request from the master is absent, acknowledgement is returned to all the masters, and competition and permission are performed in the same cycle as the request of the master. The data transfer system is provided with a buffer for storing the request not capable of being outputted to the target slave, and performs an output of the request not capable of being outputted though permitting the output, to the target slave. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a device that outputs a data transfer request from a master device to a slave device (hereinafter referred to as a “slave module”), and in particular, transfers between memories directly to a slave module having a small buffer size such as an arithmetic unit ( The present invention relates to a data transfer apparatus that frequently performs data transfer by “DMA”).

In data transfer inside an electronic device such as a computer or a mobile phone, a device for adjusting data transfer contention may be used. This device is generally called an arbiter (in particular, a device that adjusts data transfer contention between devices connected to the bus is a bus arbiter).
Here, a device that transmits a data transfer request to the arbiter, for example, an arithmetic device is called a master, and a device that is a target of data transfer by the master is called a slave.

  In general, exchange of commands and data between a master and an arbiter and between an arbiter and a slave is performed in synchronization with a timer (generally “clock”) used between these devices. For example, one cycle of the clock (hereinafter referred to as “one cycle”) is required for the master to output a request for requesting the use of the slave to the arbiter. On the other hand, the contention determination in the arbiter, that is, whether or not the master can use the slave is performed within the same cycle as the reception of the request from the master. Then, in the next cycle of the contention determination, the arbiter gives a determination result to the master (specifically, a signal indicating permission or non-permission of access. Hereinafter, a signal indicating permission is referred to as “acknowledge” or “ac”). Send. That is, at least two cycles are required for the master to use the slave.

  Prior art relating to an arbiter is disclosed in Patent Document 1. In Patent Document 1, by providing a buffer memory in the arbiter, a decrease in throughput of data transfer from the master to the slave when requests from a plurality of masters to the same slave compete with each other is suppressed. Specifically, the arbiter disclosed in Patent Document 1 returns an acknowledgment to one master among the plurality of masters regardless of whether or not data transfer is possible in response to a data transfer request from a plurality of masters. On the other hand, the arbiter stores a data transfer request from the master that has not returned an ACK in the buffer. Then, during the data transfer based on the data transfer request of one master, the data transfer of the master performing the data transfer is completed by the arbiter performing a conflict determination between the requests stored in the buffer. It becomes possible to immediately output the data transfer request stored in the buffer to the slave.

JP-A-6-96012

  The conventional arbiter is not limited to Patent Document 1 described above, and it takes two cycles until the master can actually use the slave via the arbiter. Therefore, when data transfer requests of a plurality of masters compete for the same slave, it takes two cycles each time the master that obtains permission for data transfer is switched, and the data transfer throughput to the slave is reduced.

  In addition, when the same master frequently switches the slave that is the target of the data transfer request, it takes two cycles each time the target slave is switched, so the same problem as described above occurs. In particular, in both cases, when the data transfer amount in one request from the master is small or the data transfer amount is limited (for example, the storage capacity of the data storage buffer of the arithmetic unit included in the master or slave is small) Etc.) has a problem that the data transfer throughput of the master is reduced.

  According to the present invention, in a data transfer system (arbiter) for executing arbitration, an acknowledge is transmitted in advance to a master connected to the system. Specifically, the data transfer system returns an acknowledgment to all masters even when there is no request from the master. When a request requesting the use of a slave such as data transfer is output from the master, the data transfer system performs contention determination according to a predetermined priority order or a predetermined priority algorithm, and data transfer is possible in the next cycle. The master request to the slave.

  On the other hand, since the ACK is returned regardless of the request from the master, even if the request to the same slave competes, the master determines that the request is permitted and terminates the request. A buffer is provided in the data transfer system, and requests that cannot be output to the slave are stored in the buffer. The request stored in the buffer is determined as a determination target similar to a request output from another master, and when it is determined that the request can be output, the request is immediately output to the target slave.

  According to the present invention, the data transfer throughput does not decrease in the arbiter. In particular, high data transfer throughput can be ensured even in data transfer to a slave having a small buffer capacity.

  Further, according to the present invention, even if requests from a plurality of masters compete, the data transfer throughput in the target slave does not decrease.

  Hereinafter, although embodiment of this invention is described, it cannot be overemphasized that this invention is not limited to embodiment of this specification. First, before describing the details of the present embodiment, an outline of the apparatus according to the present embodiment will be briefly described.

  FIG. 1 is a diagram showing a configuration example of one embodiment of an arithmetic processing system to which the present invention is applied. The arithmetic processing system includes a CPU 1, an SDRAM 2, an accelerator 8, and a bus 3 for connecting them. This arithmetic processing system is employed as a device for processing data in a personal computer, a mobile phone, a server, a mobile terminal, or the like.

  The accelerator 8 is a circuit that specially processes, in place of the CPU 1, cryptographic processing among the arithmetic processing performed by the CPU 1. In this way, the processing performance of the arithmetic processing system is improved by distributing the processing between the CPU 1 and the accelerator 8.

  The accelerator 8 is a data transfer system 100 serving as an arbiter, a bus interface 4 that connects the data transfer system 100 and the bus 3 and converts a data transfer protocol between the bus 3 and the data transfer system 100, It has an SRAM 6 that is a data storage buffer, a cryptographic operation unit 7, and a DMAC 5 that controls data transfer between the SRAM 6 and the cryptographic operation unit 7.

The bus interface 4, SRAM 6, cryptographic operation unit 7, and DMAC 5 are connected to each other via the data transfer system 100.
In the configuration of FIG. 1, the arithmetic processing system performs cryptographic operations on data stored in the SDRAM 2 as follows. The arithmetic processing system transfers data from the SDRAM 2 to the SRAM 6 via the bus 3, the bus interface 4, and the data transfer system 100, and transfers data between the SRAM 6 and the cryptographic operation unit 7 based on the control of the DMAC 5. Do.

  Here, a configuration in which the SRAM 6 is omitted and a storage area is secured as a buffer in the cryptographic calculator 7 is also conceivable. However, if an attempt is made to secure a buffer in the cryptographic operation unit 7, the circuit scale increases. On the other hand, the SRAM 6 has a simple circuit layout configuration, and the circuit scale of the entire apparatus is smaller when the SRAM 6 is used than when the encryption calculator 7 is configured with a buffer having the same capacity. Therefore, in this embodiment, the buffer capacity of the cryptographic operation unit 7 is limited to a capacity that allows the cryptographic operation unit 7 to always execute the cryptographic operation, and the buffer capacity of the SRAM 6 is increased.

  For this reason, the DMAC 5 needs to frequently switch the data transfer destination between the SRAM 6 and the cryptographic calculator 7. On the other hand, since data transfer from the SDRAM 2 to the SRAM 6 is also performed, data transfer contention occurs in the SRAM 6. In general, it is known that when data transfer destination switching and data transfer conflict, the data transfer throughput decreases. In the present invention, the data transfer system 100 capable of suppressing this decrease is used.

In order to explain a data transfer method in the data transfer system 100, the system is simplified by dividing the data transfer request side and the data transfer side into a master and a slave, respectively.
FIG. 2 is a diagram illustrating a configuration in which two masters and two slaves are connected to the data transfer system 100. Here, the data transfer system 100 returns an acknowledgment to all connected masters even when there is no data transfer request from the master. Then, when a data transfer request for the slave is output from the master to the data transfer system 100, the data transfer system 100 performs a conflict determination according to a predetermined priority order or a predetermined priority algorithm, and the data transfer request is transmitted. In the next cycle, a master data transfer request capable of data transfer is output to the target slave.

  As a result, since the data transfer system can transmit an ACK to the master in the same cycle as the master data transfer request, the number of cycles required for the master to use the slave is 1. Therefore, the data transfer throughput does not decrease even if the data transfer request is switched and issued to slaves with different masters.

  However, since the data transfer system returns an ACK regardless of the master data transfer request, the master determines that the data transfer request is permitted and terminates the data transfer request even if requests to the same slave compete. However, the data transfer system 100 cannot output this request to the target slave. In order to solve this, the data transfer system of this embodiment has a buffer for storing a data transfer request from each master.

  When a data transfer request to the same slave competes, the data transfer system sends a request that cannot be output to the target slave (hereinafter also referred to as “target slave”), in other words, a master data transfer request with a low priority. Store in the buffer corresponding to the master. The data transfer request stored in the buffer is subject to contention determination in the same way as requests output from other masters when the target slave is ready for data transfer. On the other hand, it is output immediately. Thereby, even if data transfer requests of a plurality of masters compete, the data transfer throughput in the target slave does not decrease.

  Also, when the master data transfer request is stored in the buffer, the data transfer system interrupts the transfer of the ACK to the master that output the data transfer request (specifically, the ACK signal level is lowered) and stores it in the buffer. ACK is transmitted again when the received data transfer request is output to the target slave (by raising the ACK signal level), it is possible to prevent a plurality of data transfer requests from being sent to the data transfer system from one master. Therefore, a buffer having a size for one request may be provided for each master.

Details of this embodiment will be described below.
FIG. 2 is a diagram showing a device configuration example of the present embodiment, and shows a configuration in which two masters 101 a and 101 b and two slaves 121 a are connected to the data transfer system 100. However, the number of masters 101 and slaves 121 is not limited. The master 101 transmits a write or read data transfer request to the slave 121.

  In the following description, the master 101a is referred to as M1, the master 101b as M2, the slave 121a as S1, and the slave 121b as S2. Examples of the master include the bus interface 4 and the DMAC 5, and examples of the slave include the memory (SDRAM 2 and SRAM 6) and the cryptographic calculator 7.

  In a situation where a write request and a read request are made from the master 101 to the slave 121, a certain address area is allocated to each storage area of the slave 121, and the master 101 transfers data to the slave 121. In this case, the master 101 outputs a data transfer request including address information indicating an address indicating the storage area of the slave 121 to the data transfer system 100.

FIG. 3 is a diagram illustrating an internal configuration example of the data transfer system 100.
The data transfer system 100 includes an M1 buffer 105 connected to M1, an M2 buffer 115 connected to M2, an M1 request selector 201 connected to the M1 buffer 105 and M1, and an M2 request selector connected to the M2 buffer 115 and M2. 211, an M1 request selector 201, an S1 arbiter 205 connected to the M2 request selector 211 and S1, and an S2 arbiter 215 connected to the M1 request selector 201 and the M2 request selector 211 and S2.

  The M1 buffer 105 (M2 buffer 115) stores request and data information transmitted from the M1 (M2). The M1 request selector 201 (M2 request selector 211) controls transfer of data transfer requests transmitted from the M1 (M2) and the M1 buffer 105 (M2 buffer 115) to the slave. The S1 arbiter 205 (S2 arbiter 215) controls the transfer of requests and data between S1 (S2) and the M1 request selector 201 and M2 request selector 211.

  Each device is mutually connected by one or a plurality of signal lines. In the following description, it is assumed that the devices are connected to each other with different signal lines for each type of signal. However, a configuration in which the plurality of signal lines are grouped is also conceivable.

  Reference numeral 102 denotes a signal line for transmitting an ACK output from the M1 request selector 201 to M1. Reference numeral 103 denotes a signal line through which a data transfer request output from the M1 to the M1 request selector 201 and the M1 buffer 105 flows. The data transfer request transmitted through the signal line 103 includes write and read commands and address information specifying a predetermined storage area of the slave. A signal line 104 transfers data input / output between the M1, the M1 request selector, and the M1 buffer 105.

  A signal line 106 is used when a control signal for rewriting the M1 buffer 105 is transmitted from the M1 request selector 201. Reference numeral 107 denotes a signal line used when outputting the M1 data transfer request stored in the M1 buffer 105 to the M1 request selector 201. A signal line 108 is used when data is transferred from the M1 buffer 105 to the M1 request selector 201.

  The M1 request selector 201 selects a valid data transfer request from the M1 data transfer request received via the signal line 103 and the M1 data transfer request received from the M1 buffer 105 via the signal line 107. The selected data transfer request is output as a data transfer request to the S1 arbiter 205 or S2 arbiter 215 via the signal line 203.

  In the state where the data transfer request from M1 is being output to the S1 arbiter 205 or S2 arbiter 215, an ack returned from the arbiter (S1 arbiter 205 or S2 arbiter 215) connected to the slave that is the target of the data transfer request. Thus, the M1 request selector 201 determines whether or not the next data transfer request can be transmitted to the target slave, and transmits an ACK to the M1 and a control signal to the M1 buffer 105. Specifically, if the next data transfer request can be transmitted, that is, if the ACK is returned from the S1 or S2 arbiter while outputting the data transfer request to the S1 or S2 arbiter, the M1 request selector 201 , Keep the ACK effective for M1. On the other hand, if transmission is impossible, ACK to M1 is invalidated, and a control signal is transmitted to the M1 buffer 105 in order to store a data transfer request that cannot be transmitted in the M1 buffer 105. Further, the M1 request selector 201 transmits / receives data to / from M1 via the signal line 104 during data transfer, and transmits / receives data to / from the slave 121 via the signal line 204.

  A signal line 203 is used to transfer a data transfer request output from the M1 request selector 201 to the S1 arbiter 205 or the S2 arbiter 215. Reference numeral 204 denotes a signal line used for data transmission / reception among the M1 request selector 201, the S1 arbiter 205, and the S2 arbiter 215.

  S1 transfers the corresponding data to the S1 arbiter 205 via the signal line 123 according to the data transfer request information input from the S1 arbiter 205 via the signal line 122. The signal line 202 is a signal line for transferring an ACK output from the S1 arbiter 205 to the M1 request selector 201 and the M2 request selector 211. The S1 arbiter 205 performs a conflict determination on the data transfer requests from the M1 request selector 201 and the M2 request selector 211, and outputs an ack to the M1 request selector 201 or the M2 request selector 211. The S1 arbiter 205 controls data transfer between the S1, the M1 request selector 201, and the M2 request selector 215 via the signal lines 204 and 214 during data transfer.

  M2, M2 request selector 211, M2 buffer 215, S1 arbiter 205, S2 arbiter 215, S1 and S2 send / receive requests, ACKs and data by transferring data etc. in M1 and M1 request selectors, etc. It is done in the same way. However, signal lines 112, 113, and 114 are used to transmit and receive ACKs, requests, and data between the M2 and M2 request selectors. Signal lines 116, 117, and 118 are used for exchanging data and the like between the M2 request selector 211 and the M2 buffer. Further, signal lines 212, 213, and 214 are used for exchanging data and the like between the M2 request selector 211 and the S1 arbiter 205 and S2 arbiter 215. Signal lines 132 and 133 are used for exchanging data and the like between S2 and S2 arbiter 215.

Hereinafter, a case where M1 issues requests to S1 and S2 alternately and a case where M1 and M2 issue requests to S1 in parallel will be described. First, the former case will be described.
First, the M1 request selector 201 outputs an ACK to the M1 via the signal line 102, and the M2 request selector 211 outputs an ACK to the M2 via the signal line 112. In this state, when M1 requests data transfer or the like to S1, M1 outputs to M1 request selector 201 a data transfer request including address information designating an address allocated to the storage area of S1 and a write or read command. To do.

  The M1 request selector 201 outputs a data transfer request for S1 to the S1 arbiter 205 in accordance with the address information included in the data transfer request in the same cycle as the cycle in which the received data transfer request is output from M1. The S1 arbiter 205 that has received the data transfer request from the M1 request selector performs a conflict determination.

  At this time, since there is no data transfer request from another master 101, the S1 arbiter 205 outputs an ACK for the request to the M1 request selector 201 via the signal line 202. As described above, the data transfer request is output from M1 to the M1 request selector 201, the S1 arbiter 205 completes the contention determination, and the S1 arbiter 205 returns an ack to the M1 request selector 201 in one cycle.

  In the next cycle, the S1 arbiter 205 transmits the data transfer request received from the M1 request selector 201 to the S1 via the signal line 122. On the other hand, in M1, the data transfer request that has already been transferred to S1 is permitted to the data transfer system 100, and an ACK is transmitted from the M1 request selector 201 to M1 via the signal line 102. Therefore, M1 transfers data to S2. A request can be output. In this case, the data transfer system 100 that has received the data transfer request for S2 performs the same procedure as when the data transfer request for S1 is received.

Through the above processing, M1 can output a data transfer request in a continuous cycle even when it requests data transfer alternately to S1 and S2. In other words, even if the target slave that frequently makes data transfer requests is changed, the data transfer throughput in the master does not decrease. When the data transfer request is a write, the data accompanying the data transfer request is transmitted from the master 101 to the slave 121 via the signal line 104 or the like in the same cycle as the data transfer request. On the other hand, when the data transfer request is read, data corresponding to the data transfer request is output to the master 101 via the signal line 123 or the like from the slave 121 that has received the data transfer request.
Note that these data inputs / outputs only need to match the characteristics of the slave data input / output, and an original protocol may be used.

  FIG. 4 is a timing chart of signal input / output when data transfer requests are issued alternately from M1 to S1 and S2. From the first cycle (or earlier), an ACK is input to M1 via the signal line 102. In the second cycle, M1 outputs a data transfer request for S1 to the data transfer system 100. Here, for the sake of simplicity, it is assumed that the content of the data transfer request is written, and the data is output to the signal line 104 simultaneously with the data transfer request.

  The data transfer request and data are output to S1 in the third cycle, and transmission of the data transfer request from M1 to S1 in the second cycle is completed. On the other hand, since the data transfer request in the second cycle is permitted, M1 outputs a data transfer request for S2 in the third cycle. This request is output to S2 in the fourth cycle. With the above operation, M1 can alternately execute requests to S1 and S2 in successive cycles.

Next, a case where data transfer requests from M1 and M2 to S1 conflict will be described.
First, the M1 request selector 201 outputs an ACK to M1 via the signal line 102, and the M2 request selector 211 outputs an ACK to M2 via the signal line 112. In this state, M1 and M2 output the data transfer request including the address information indicating the storage area of S1 and the write or read command to the M1 request selector 201 and the M2 request selector 211, respectively.

  In the same cycle in which the data transfer request is output from M1, the M1 request selector 201 sends a data transfer request for S1 to the S1 arbiter 205 through the signal line 203 in accordance with the address information included in the data transfer request received from M1. Output via. On the other hand, the M2 request selector 211 outputs a data transfer request for S1 to the S1 arbiter 205 via the signal line 213 in accordance with the address information included in the data transfer request received from M2.

  The S1 arbiter 205 that has received the data transfer request from the M1 and the data transfer request from the M2 via the signal line 203 and the signal line 213 performs a conflict determination between the received data transfer requests. Here, description will be made assuming that M1 has a high priority. Since the priority order of M1 is high, the S1 arbiter 205 selects the data transfer request received from M1, and outputs an ACK to the M1 request selector 201 via the signal line 202.

  Note that the data transfer system holds information on the priority order in a buffer or the like. The priority order may be set or changed based on information from another device, or a fixed value may be set in advance. Furthermore, the priority order is not fixed, and a known method, for example, a configuration in which priority order is given cyclically or a processing order is randomly set is also conceivable.

  On the other hand, the M2 request selector 211 determines that the data transfer request is not permitted because the ACK is not returned although the data transfer request is output to S1, and signals a signal for controlling the M2 buffer. The data is output to the M2 buffer 115 via the line 116. This control signal is a signal for allowing the M2 request selector 211 to control the processing for storing the data transfer request received from the M2 in the temporary M2 buffer 115, specifically, permitting the storage of data in the M2 buffer 115. . At this time, the fact that the M2 request selector 211 outputs a control signal to the M2 buffer 115 in order to use the data transfer request stored in the M2 buffer 115 from the next cycle to determine the contention of the data transfer request, that is, the M2 buffer Information indicating that the data transfer request is stored in 115 is held.

  In the next cycle, the S1 arbiter 205 outputs the data transfer request received from M1 to S1. Thereby, transmission of the data transfer request from M1 to S1 is completed. On the other hand, since the data transfer request for S1 of M2 has not been transmitted to S1, the M2 request selector 211 lowers the acknowledgment for M2. Here, the M2 data transfer request that has not been transmitted is held in the M2 buffer 115 that has received the control signal from the M2 request selector 211 as a pair of the data transfer request and the data accompanying the data transfer request.

  Thereafter, the M2 buffer 115 continues to output the data transfer request stored therein and the accompanying data to the M2 request selector 211 via the signal lines 117 and 118.

  After the processing of the data transfer request from M1 is executed, the S1 arbiter 205 determines the contention for the data transfer request that is continuously transmitted from the M2 request selector 211. In this case, since the M2 request selector 211 holds the information for outputting the control signal to the M2 buffer in the previous process, the M2 request selector 211 determines that the data transfer request received from the M2 buffer 115 is the M2 data transfer request, The received data transfer request is output to the S1 arbiter 205 via the signal line 213. In this case, since it is assumed that there is no data transfer request from M1, the S1 arbiter 205 permits processing of the received data transfer request and returns an ack to the M2 request selector 211.

  The M2 request selector 211 that receives the ACK from the S1 arbiter 205 returns the ACK to the M2 again via the signal line 112. The M2 request selector 211 indicates that a control signal was output to the M2 buffer 115 held by the M2 request selector 211 in order to stop (invalidate) use of the data transfer request stored in the M2 buffer 115. Information, that is, information indicating that the data transfer request is stored in the M2 buffer 115 is deleted.

  When there is a data transfer request from M1, as described above, the S1 arbiter 205 determines again the conflict between the data transfer requests transmitted from M1 and M2. Here, since the priority of M1 is high, the processing of the data transfer request stored in the M2 buffer 115 is postponed, and the data transfer request stored in the M2 buffer 115 is held as it is.

  In the next cycle, the S1 arbiter 205 outputs the data transfer request received from the M2 request selector 211 to S1. Thereby, transmission of the data transfer request from M2 to S1 is completed. On the other hand, since the data in the M2 buffer 115 has been invalidated in the previous cycle, the M2 request selector 211 receives the data transfer request from the M2 received from the signal line 113 instead of the data transfer request received from the signal line 117 again. The data is transferred to the S1 arbiter 205 or the S2 arbiter 215.

  As described above, even when requests from a plurality of masters 101 conflict with S1, it is possible to process data transfer requests to S1 in a continuous cycle. Data input / output is the same as when data transfer requests are alternately transmitted from M1 to S1 and S2.

  FIG. 5 is a diagram illustrating an example of a signal input / output timing chart when the data transfer requests of M1 and M2 compete in S1. In the first cycle, an ack is input from M1 request selector 201 to M1, and an ack is input from M2 request selector 211 to M2. In the second cycle, M1 outputs a data transfer request for S1, and M2 outputs a data transfer request for S1. As described above, the contents of the data transfer request are written here, the data transfer request is accompanied by a data transfer request from M1, and the data transfer request is accompanied by a data transfer request from M2 via the signal lines 104 and 114, respectively. It is transmitted to the selector 201 and the M2 request selector 211.

  Since a data transfer request contention for S1 occurs in the second cycle, the contention determination is performed in the data transfer system 100, specifically, in the S1 arbiter 205. As a result, in this example, a data transfer request of M1 is output to S1 in the third cycle. On the other hand, since the transmission of the data transfer request is not permitted in M2, the ACK to M2 is lowered, and the data transfer request output from M2 in the second cycle is stored in the M2 buffer 115.

  In the subsequent cycle, the next data transfer request is input from M1, and the next data transfer request is also input from M2. However, the data transfer system 100 does not accept the M2 data transfer request, and makes a conflict determination between the data transfer request transferred before that and stored in the M2 buffer 115 and the newly received M1 data transfer request.

  As a result of the contention determination, the M1 data transfer request is output to S1 in the fourth cycle. Since the data transfer request of M2 in the third cycle has not yet been output to S1, the acknowledgment from the data transfer system 100 to M2 is still lowered. Therefore, M2 continues to output the data transfer request to the data transfer system 100. In the example of this figure, M2 continues to transfer the data transfer request until the seventh cycle after the processing of the data transfer request of M1 is completed.

  When processing of the data transfer request from M1 ends in the sixth cycle, the data transfer system 100 determines that the data transfer request stored in the M2 buffer 115 can be transmitted to S1, and in the seventh cycle, the data A transfer request is output to S1. As a result, the data transfer system 100 returns the acknowledgment to M2. M2 having received the ACK determines that the data transfer request transmitted to the data transfer system 100 from the third cycle is permitted, and further outputs the next data transfer request in the eighth cycle. Based on the data transfer request permitted in the seventh cycle, the data transfer request is transmitted to S1 in the eighth cycle. The data transfer request transmitted in the eighth cycle is output to S1 in the ninth cycle. The same applies to the request from M2 in the ninth cycle and the output to S1 in the tenth cycle. From the above operation, even when the requests of M1 and M2 compete, it is possible to make a request to S1 in a continuous cycle.

  According to this embodiment, since the data transfer system 100 can return an ACK in the same cycle as the master request, the data transfer throughput does not decrease even if the master switches the request to a different slave.

  Further, according to the present embodiment, the data transfer throughput in the slave does not decrease even if requests from a plurality of masters compete. On the other hand, when the master request is stored in the buffer, the data transfer system 100 lowers the ACK of the master that output the request, and returns the ACK again when the request stored in the buffer is output to the target slave. In order to operate as a transfer system, a buffer having a size corresponding to one request may be provided for each master.

  The number of masters and slaves may be any number. In this case, the data transfer system 100 has an arbiter corresponding to the number of slaves, and a data transfer request conflict determination is performed for each arbiter.

It is a figure which shows the system configuration example of this embodiment. It is a figure which shows the structural example of a master and a slave, and a data transfer system. It is a figure which shows the internal structural example of a data transfer system. It is a figure which shows the example of the timing chart at the time of the alternating request from the single master in this embodiment to several slaves. It is a figure which shows the example of the timing chart at the time of the request contention from the some master to the single slave in embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 ... Data transfer system, 101 ... M1, 105 ... M1 buffer, 111 ... M2, 115 ... M2 buffer, 121 ... S1, 131 ... S2, 201 ... M1 request selector, 211 ... M2 request selector.

Claims (7)

A data transfer system that arbitrates requests,
Send an acknowledge in advance to the master connected to the data transfer system,
A data transfer system for transferring a request transmitted from the master to a slave connected to the data transfer system. A data transfer system that arbitrates requests,
An acknowledgment is transmitted in advance to each of a plurality of masters connected to the data transfer system,
A data transfer system that receives both requests sent from the plurality of masters to a slave, transfers one of the requests to the slave, and stores the other request in a buffer of the data transfer system. The data transfer system according to claim 2, wherein
A data transfer system, wherein transmission of the acknowledge to the master that has transmitted the request stored in the buffer is stopped. The data transfer system according to claim 3, wherein
Transfer the request stored in the buffer to the slave after completion of processing the request transferred to the slave,
A data transfer system which resumes transmission of the stopped acknowledge. The data transfer system according to claim 4, wherein
One of the plurality of masters is a CPU, and the slave is a memory. The data transfer system according to claim 4, wherein
One of the plurality of masters is a CPU, and the slave is a cryptographic operation device. A data transfer method in an information processing system,
The mediation device that the information processing system has is
Send an acknowledge to each master beforehand,
Determine the conflict of multiple requests for one slave received from each master,
Send the request selected in the judgment to the slave,
Temporarily save requests that were not selected in the decision,
A data transfer method comprising: transferring the temporarily stored request to the slave after the processing of the selected request is completed.

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