JP2000250850A - Bus control device, master device, slave device and bus control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the use efficiency of a common bus by sending again an access request at timing suitable for the various states of slaves corresponding to a retry request from the slave. SOLUTION: This bus control device is provided with slave devices D and E outputting a signal expressing the state of disabling the execution of processing for the slave device corresponding to the access request in such a state, a retry information sending circuit 41 for generating and sending retry information expressing time to the change into state capable of executing the processing corresponding to the access request for the slave device on the basis of the signal from the slave device and master devices A, B and C for sending the access request of retry to the said slave device after the lapse of time designated by the retry information from the retry information sending circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus control device, a master device and a slave device, and a bus control method applied to a system having a plurality of master devices and slave devices connected to a common bus. The present invention relates to a technology for improving use efficiency.

[0002]

2. Description of the Related Art Conventionally, as shown in FIG. 18, a plurality of master devices (hereinafter simply referred to as "master") and a plurality of slave devices (hereinafter simply referred to as "slaves") are connected to a common bus. Known processing systems are known.

FIG. 18 shows an example in which a master A, a master B, a master C, a slave D, a slave E, and a bus arbiter F are connected to a common bus 10. Each master A, B and C has a timer device 300. In this timer device 300, each master A, B or C
Alternatively, when the access request made to E is not accepted, the time until the access request can be issued to the slave D or E again is measured. Although not shown, slaves D and E are connected to external devices such as a memory device and a display device.

Now, in this processing system, the master A
Access the slave D. in this case,
The master A first sends a bus use request to the bus arbiter F. If the common bus 10 is in a usable state, the bus arbiter F returns a bus use permission. The master A that has obtained the bus use permission sends an access request to the slave D using the common bus 10. When receiving the access request, the slave D starts a process corresponding to the access request if the slave D is in a state capable of responding to the access request.

However, when receiving the access request, the slave D may not be able to immediately respond to the access request for some reason. This includes a case where the cause is caused by the slave D itself and a case where the cause is caused by an external device connected to the slave D.

For example, if the cause is in the slave D itself, (1) if the slave D is executing a process for an access request from another master B or C, (2)
If there is no data in the buffer memory inside the slave D when there is a read access request from the master A, (3) immediately after the write access request, that is, at the time when the write operation is not completed, May be requested.

[0007] Further, as a case where there is a cause in an external device connected to the slave D, (4) when the master A requests access to a memory as an external device connected to the slave D, the memory is During the refresh operation, (5) the memory may be out of order.

[0008] Upon receiving the access request, the slave D
If the access request cannot be immediately responded to for some reason, a retry request is returned to the master A. The master A that has received the retry request from the slave D starts the timer device 300. Then, the master A sends an access request to the slave D again after the timer device 300 measures that the predetermined time has elapsed. This predetermined time is called “retry time” and is a time unique to each master. Each master stores therein data defining a retry time.

A device in which the slave D can operate only at a low speed, for example, a device that requires a long time to prepare data when there is a read access request, and a retry time specified by the master A Is shorter, the slave D often returns a retry request in response to the access request of the master A. As a result, the time during which the master A occupies the common bus 10 is increased, and the use efficiency of the common bus 10 is reduced and the power consumption is increased.

As a technique for solving such a problem, for example, Japanese Patent Laid-Open Publication No. Hei 3-201054 discloses "a common bus control method and its control device, a master device and a computer system". According to this document, in response to a retransmission request from a slave, the master retransmits an access request at a predetermined time interval unique to itself, thereby avoiding collision of access requests of each master device and controlling priority. A technique for performing this is disclosed. Further, when a slave busy response to a master request continues for a certain period of time, the master forcibly occupies the common bus until the slave changes to a ready state, thereby ensuring data transfer to the slave. It has been disclosed.

[0011] Further, a busy signal line for indicating that the slave is busy is provided on the common bus, and the master for transferring data to the slave freezes a bus occupancy request signal output with arbitration for acquiring the common bus until the slave is busy off. To suppress access from another master,
There is disclosed a technique for avoiding access collision from different masters. Further, when there is access from the master to the slave, the time from the access to the response is counted when the slave responds, and when the master retransmits the request signal while the slave is busy, the counting time A technique has been disclosed in which retransmission is performed later to reduce collision on the bus.

Further, Japanese Patent Application Laid-Open No. Hei 4-163659 discloses a "bus arbitration system". According to this document, when a retry response is returned from a bus slave of a read request destination to a requesting bus master, bus arbitration is performed only for a bus use request from another bus master for a certain period of time. In this case, the certain period is generated by a counter that operates according to the information stored in the table corresponding to each bus slave. As a result, the requesting bus master does not frequently send the access request to the requesting bus slave, so that the bus occupation time can be reduced.

[0013]

SUMMARY OF THE INVENTION The above-mentioned Japanese Patent Laid-Open Publication No. Hei 3-201
By using the technique disclosed in Japanese Patent Application Publication No. 054, it is possible to avoid collision of access requests from a plurality of masters. However, since the master manages the retry time, the access request is retransmitted irrespective of the constantly changing state of the slave. As a result, the problem that the slave repeatedly returns a retry request in response to a reaccess request from the master has not been solved, and the time for occupying the common bus cannot be reduced.

According to the technique disclosed in Japanese Patent Application Laid-Open No. 4-163659, information indicating a retry time until a master receiving a retry request from a slave can send an access request to the slave again. Is stored in a table for each slave, and a retry request is transmitted again after a lapse of time according to the contents of the table. However, the retry time allocated to each slave is fixed in consideration of the function of the slave. Therefore, when the state of the slave changes over time, the access request cannot be retransmitted at a timing suitable for the slave. As a result, the number of retries increases as described above, and the time for occupying the common bus cannot be reduced.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem. In response to a retry request from a slave, an access request is resent at a timing suitable for various states of the slave, thereby enabling a common bus to be retransmitted. It is an object of the present invention to provide a bus control device, a master device, a slave device, and a bus control method that can increase the use efficiency of a device.

[0016]

According to a first aspect of the present invention, there is provided a bus control apparatus which is capable of executing a process for an access request when the bus control device cannot execute a process for an access request.
A slave device that outputs a signal indicating the state, a retry information sending circuit that sends retry information based on a signal from the slave device, and after a time specified by retry information from the retry information sending circuit has elapsed. A master device for sending a retry access request to the slave device.

In this bus control device, the slave device that has received the access request transmits a signal indicating the status of the slave device at that time, for example, an idle state,
A signal indicating a state such as writing or refreshing is supplied to a retry information sending circuit. The retry information sending circuit creates retry information based on a signal from the slave device, in other words, retry information reflecting the state of the slave device, and sends it to the master device. The master device issues a retry access request after a lapse of a specified time from the slave device. Therefore, the slave device can receive a re-access request from the master device at a timing convenient for itself.

The first embodiment of the bus control device according to the first aspect
In the embodiment, the retry information sending circuit includes a table for storing retry information indicating a time required for the slave device to change from a state in which the slave device cannot execute a process for an access request to a state in which the slave device can execute the process, and a signal from the slave device. And a transmission circuit for selecting retry information corresponding to the signal from the table and transmitting the selected retry information to the master device.

In this case, the retry information sending circuit is
It may be formed in the slave device, or may be formed separately and independently from the master device and the slave device. Further, a bus arbiter for arbitrating the right to use a common bus for connecting the master device and the slave device may be further provided, and the retry information sending circuit may be formed in the bus arbiter.

Further, only the transmission circuit included in the retry information transmission circuit may be formed in the slave device, and the table may be formed independently of the master device and the slave device. Further, the apparatus further comprises a bus arbiter for arbitrating a right to use a common bus for connecting the master device and the slave device, wherein only a transmission circuit included in the retry information transmission circuit is formed in the slave device, and the table includes: , Can be formed in the bus arbiter.

According to this bus control device, if the master device sends a retry access request to the slave device after the time specified by the retry information received from the slave device, the access request is always accepted. . Therefore, since the access processing is completed by one retry, the occupation time of the common bus connecting the master device and the slave device can always be minimized. As a result, the bus utilization efficiency is improved, and in the case of read access,
The time from issuing an access request to obtaining data is minimized.

In a second embodiment of the bus control device according to the first aspect, the retry information sending circuit includes:
A first table storing first retry information indicating a time required for processing for a specific type of access request, a second table storing second retry information indicating a time required for processing for all types of access requests, Receiving a signal from the slave device, a first selection circuit for selecting first retry information corresponding to the signal from the first table, and a state from the slave device. A second selection circuit for selecting second retry information corresponding to the signal from the second table; a first retry information selected by the first selection circuit; and a second selection circuit selected by the second selection circuit. And an adder for adding the retry information to the master device and adding the result of the addition to the master device as retry information.

In the above-mentioned specific type of access request, even if an access request is issued to a slave device in an idle state, such as a read-type access request, data cannot be immediately prepared. Includes the type of access request that is returned.

In this bus control device, when a slave device receives an access request of a specific type in an idle state, it returns first retry information as retry information to the master device. As soon as an access request other than a specific type is received, processing for the access request is started. On the other hand, a state where the slave device cannot execute the process for the access request,
That is, when a specific type of access request is received while a process for another access request is already being executed, the result of adding the first retry information and the second retry information as retry information is returned to the master device. Upon receiving an access request other than a specific type, the master device returns second retry information corresponding to the currently processed access request to the master as retry information.

According to this bus control device, the first
The following effects are obtained in addition to the effects similar to those of the bus control device according to the embodiment. That is, in the case of the bus control device according to the first embodiment, the number of retry information prepared in the table is “the number of first retry information × the number of second retry information”. According to the bus control device of the embodiment, the number of retry information prepared in the table may be only “the number of first retry information + the number of second retry information”. Therefore, the capacity of the table can be reduced. Further, in the case of the bus control device according to the first embodiment, a result obtained by adding the first retry information and the second retry information as necessary is stored in the table as retry information.
According to the bus control device of the second embodiment, the first
Since the retry information or the second retry information is stored in the table as it is, the creation of the retry information is simplified.

Further, in the third embodiment of the bus control device according to the first aspect, further, a first table for storing first retry information indicating a predetermined time, and a second table indicating a time shorter than the predetermined time are further provided. A second table storing 2 retry information, and a first table corresponding to the first signal when the first signal is received from the slave device.
A first transmitting circuit for selecting retry information from the first table and transmitting the retry information to the slave device as retry information; and a second transmitting circuit for receiving a second signal from the slave device. And a second transmission circuit for selecting 2 retry information from the second table and transmitting the retry information to the slave device as retry information.

As the predetermined time, an arbitrary time can be used. For example, a time about the time required for the above-mentioned specific type of access request can be used. In addition, as a time shorter than the predetermined time, a time that is about a fraction of the predetermined time can be used.

In this bus control device, even if the master device sends a retry access request to the slave device after a lapse of time specified by the first retry information received from the slave device, the master device always receives the access request. Not always. If not accepted, the master device sends a retry access request to the slave device after a lapse of time specified by the second retry information received from the slave device. Hereinafter, the same operation is repeated until the access request is accepted.

According to this bus control device, the access processing may not be completed in one retry, so that the occupation time of the common bus connecting the master device and the slave device cannot always be minimized. Since it is sufficient to prepare several pieces of information and the second retry information, it is possible to reduce the capacity of the table and to simplify the creation of the retry information.

A slave device according to a second aspect of the present invention has a receiving circuit for receiving an access request for the same purpose as described above, and a slave circuit which cannot execute processing for the access request received by the receiving circuit. A retry information transmitting circuit for generating and transmitting retry information based on the state.

In the slave device according to the second aspect,
The retry information sending circuit includes: a table for storing retry information indicating a time period from a state in which processing for the access request cannot be executed to a state in which the processing can be executed; and a step for receiving the access request when the receiving circuit receives the access request. And a transmission circuit for selecting and transmitting retry information corresponding to the request from the table when the request cannot be executed.

Further, the retry information sending circuit stores a first table storing first retry information indicating a time required for processing a specific type of access request, and a time required for processing all types of access requests. A second table for storing second retry information to be displayed, and when the receiving circuit receives an access request of a specific type, first retry information corresponding to the type of the access request is selected from the first table. When the first selection circuit and the receiving circuit receive an access request, if processing for another access request is being executed, the second retry information corresponding to the type of the access request being executed is stored in the second selection circuit. A second selection circuit selected from a table; first retry information selected by the first selection circuit; and a second retry information selected by the second selection circuit. Sending circuit for sending the addition result by the adder and said adder for adding the distribution as retry information,
And can be configured.

Further, the retry information sending circuit includes a first table for storing first retry information indicating a predetermined time, a second table for storing second retry information indicating a time shorter than the predetermined time, and the receiving table. When the circuit receives the first access request and is in a state where processing for the access request cannot be executed, the first retry information corresponding to the state is selected from the first table and transmitted. When the sending circuit and the receiving circuit receive a second or subsequent access request, if the processing for the access request cannot be executed, second retry information corresponding to the state is stored in the second table. A second transmission circuit for selecting and transmitting.

The master device according to the third aspect of the present invention comprises:
For the same purpose as described above, a receiving circuit for receiving a retry request sent with retry information from a slave device, and a time specified by the retry information has elapsed in response to the retry request received by the receiving circuit. A control circuit for sending a retry access request to the slave device later.

Further, a bus control method according to a fourth aspect of the present invention is a bus control method for controlling a bus connecting a master device and a slave device for the same purpose as described above,
A first step of transmitting an access request from the master device to the slave device, and when the slave device is in a state where it cannot execute processing for the access request,
A second step of generating retry information based on the state and transmitting the retry information to the master device; and retrying from the master device to the slave device after a time specified by the retry information generated in the second step has elapsed. And a third step of transmitting the access request.

[0036]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to FIGS.
An example in which the present invention is applied to a processing system in which two masters and two slaves are connected to a common bus will be described. In the following, in order to simplify the description, illustration and description other than those necessary for understanding the present invention are omitted.

Embodiment 1 (1) Outline of Processing System FIG. 1 is a block diagram showing a configuration of a processing system to which a bus control device according to Embodiment 1 of the present invention is applied.
This processing system includes master A, master B, master C,
It comprises a slave D, a slave E, a common bus 10, a retry information bus 20, and a bus arbiter 50. The master A, master B, master C, slave D, and slave E are interconnected by a common bus 10 and a retry information bus 20.

As the masters A, B and C (hereinafter collectively referred to simply as "master" unless otherwise required), a CPU, a DMA device or the like is used. As the slaves D and E (hereinafter, simply referred to as "slaves" unless otherwise required), a memory control device, a disk control device, a display control device, and the like are used. Although not shown, external devices such as a memory device (DRAM, page ROM, etc.), a disk device, and a serial I / O device are connected to each slave.

The common bus 10 includes a command bus 11, an address bus 12, a data bus 13, and a control bus 1.
4 (see FIGS. 2 and 3). The command bus 11 is used by the master to send command data to the slave. This command data is a command that defines the operation of the slave, represented by a code of a plurality of bits. The type and number of commands are defined for each slave.

The address bus 12 is used by a master to send address data to a slave. The address data is used to specify a data storage location in the slave. The data bus 13 is a bidirectional bus, and is used for transmitting and receiving data between a master and a slave.

The control bus 14 is used for transmitting and receiving control signals between a master and a slave. The control signal includes a retry request signal R
TY, a bus use signal, a response signal, and a ready signal.

Each master sends a bus use request signal REQ for requesting use of the common bus 10 to the bus arbiter 5.
It has the function of sending to 0. Further, the master has a function of sending an access request to the slave in response to a bus use permission signal ACK sent from the bus arbiter 50 for permitting use of the common bus 10. Each master has a retry control circuit 31. When the master receives a retry request from the slave, the retry control circuit 31 determines the timing for resending the access request to the slave (details will be described later). The detailed configuration and operation of the master will be described later.

Each of the slaves performs various processes in response to an access request from the master. Each slave is provided with a retry information sending circuit 41 for generating and sending retry information. Here, "retry information"
This data represents the time from when the slave that has received the access request from the master returns the retry request to when it can accept the next access request from the master.
The retry information generated by the retry information sending circuit 41 is supplied to the master retry control circuit 31 via the retry information bus 20. The detailed configuration and operation of this slave will also be described later.

The bus arbiter 50 arbitrates the right to use the common bus 10. That is, when receiving the bus use request signal REQ from each master, the bus arbiter 50 determines one master having the highest priority and sends the bus use permission signal ACK to the master. Bus use permission signal ACK
Only the master that has received the data can transmit / receive data to / from the slave using the common bus 10.

The general operation of the processing system configured as described above will be described. When accessing the slave, the master first sends a bus use request signal REQ to the bus arbiter 50. Then, when a bus use permission signal ACK is sent from the bus arbiter 50, an access request is sent to the slave.

When the slave receiving this access request is in a state where it cannot immediately respond to the access request,
Returns a retry request to the master. At this time, the slave generates retry information in the retry information sending circuit 41 and sends it to the master retry control circuit 31 via the retry information bus 20. The master that has received the retry request from the slave sends the access request again to the slave after the time specified by the retry information has elapsed. At this point,
Since the slave is ready to respond to the access request, the slave processes the access request. In this manner, data is transmitted and received between the master and the slave.

(2) Detailed Description of Master Next, the detailed configuration and operation of the master and the slave will be described. Hereinafter, a case will be described in which a CPU is used as an example of a master and a memory control device is used as an example of a slave. It is assumed that a memory device composed of a DRAM is connected to the slave.

First, the detailed configuration of the master will be described with reference to the block diagram shown in FIG. This master
Retry control circuit 31, processor 32, command register 33, address register 34, data register 3
5, a controller 36 and a buffer circuit 37.

The processor 32 executes processing for realizing various functions as a master. The processor 32 includes a command register 33, an address register 3
4. The data register 35 and the controller 36 are connected. Further, a bus use permission signal ACK is input from the bus arbiter 50 to the processor 32.

The command register 33 is provided in the processor 32
, And sends the stored command data to the command bus 11. Command data includes single read access and burst read access (hereinafter sometimes collectively referred to as “read access”), and single write access and burst write access (hereinafter sometimes collectively referred to as “write access”). It consists of a code representing the type of access.

The address register 34 is provided in the processor 32
, And sends the stored access data to the address bus 12. The address data stored in the address register 34 includes a write address when the master writes data to the slave, a read address when reading data from the slave, and the like.

The data register 35 is composed of a bidirectional register and has two sets of input / output terminals. And
One input / output terminal is connected to the processor 32, and the other input / output terminal is connected to the buffer circuit 37. The data register 35 stores data from the processor 32 and stores the stored data in a buffer circuit 37.
To send to. The data register 35 stores the data from the buffer circuit 37 and sends the stored data to the processor 32. The data stored in the data register 35 includes write data when the master writes data to the slave, read data when reading data from the slave, and the like.

The controller 36 sends a bus use request signal R
A signal RQ for generating EQ is generated. This signal R
Q is supplied to a NAND gate 312 included in the retry control circuit 31. Further, when a command accompanied by data transfer is specified by the command data, the controller 36 generates a gate control signal GC for controlling the transfer direction of the data. This gate control signal GC is supplied to the buffer circuit 37.

The buffer circuit 37 is constituted by a bidirectional tristate buffer circuit having two sets of input / output terminals. One input / output terminal is connected to the data register 35, and the other input / output terminal is connected to the data bus 13. This buffer circuit 37 has a gate control signal G
When C is at a high level (hereinafter, referred to as “H level”), the data register 35 transfers to the data bus 13, and when C is at a low level (hereinafter, referred to as “L level”), to the data register 35 Transfer data.

The retry control circuit 31 includes a retry information register 310, a counter 311 and a NAND gate 31.
2 is comprised. Retry information register 310
Captures the retry information sent from the slave via the retry information bus 20 in synchronization with the retry request signal RTY also sent from the slave. The retry information taken into the retry information register 310 is supplied to the counter 311.

The counter 311 is used to count the retry time. The counter 311 starts counting down when the content of the retry information register 310 is set. Further, the counter 311 generates a count end signal indicating whether or not the currently held data is zero. This count end signal goes to L level if the contents of the counter 311 are not zero, and goes to H level if it is zero. The count end signal generated by the counter 311 is supplied to the NAND gate 312.

As the counter 311, a counter which is cleared when retry information is taken into the retry information register 310 and which counts up thereafter can be used. In this case, the counter 311 generates a count end signal indicating whether the currently held data matches the content of the retry information register 310.
The count end signal goes to the L level if the contents of the counter 311 do not match the contents of the retry information register 310, and goes to the H level if they match.

The NAND gate 312 has a counter 311
The logical AND of the count end signal from the controller 36 and the signal RQ from the controller 36 is further inverted and output. This NA
The output signal from the ND gate 312 is supplied to the bus arbiter 50 as a bus use request signal REQ (see FIG. 1).

In the retry control circuit 31, the counter 311 keeps the count end signal at the L level while the retry time specified by the retry information from the slave has not elapsed. Therefore, even if the controller 36 activates the signal RQ (H level) in this state, the bus use request signal REQ is not activated (L level). On the other hand, when the retry time elapses, the counter 3
Numeral 11 changes the count end signal to H level. Thus, the controller 36 can activate the bus use request signal REQ by setting the signal RQ to the H level. Thus, whether the master can send the bus use request signal REQ to the bus arbiter 50 is determined according to the retry information from the slave.

The bus use signal included in the control bus 14 is generated by a transfer control circuit (not shown) and is used to notify the slave that the common bus 10 is being used. The response signal is a signal input from the slave to the transfer control circuit, and is used by the slave to notify the master that the access request has been received. The ready signal is a signal input from the slave to the transfer control circuit, and is used by the slave to notify the master that data is ready.

(3) Detailed Description of Slave Next, the detailed configuration of the slave will be described with reference to the block diagram shown in FIG. The slave includes a retry information sending circuit 41, a command register 42, an address register 43, a data register 44, a controller 45,
Counter 46, memory interface (memory I / F)
47 and a buffer circuit 48. The memory interface 47 includes a buffer memory 470. The memory interface 47 is connected to a memory device 60 as an external device.

The command register 42 stores the command bus 1
1 and the stored command data is supplied to the controller 45. The address register 43 stores the address data from the address bus 12 and supplies the stored address data to the retry information sending circuit 41, the controller 45, and the memory interface 47.

The data register 44 is composed of a bidirectional register and has two sets of input / output terminals. And
One input / output terminal is connected to the data bus 13, and the other input / output terminal is connected to the retry information sending circuit 41 and the buffer memory 470. This data register 44
Stores the data from the data bus 13 and supplies the stored data to the retry information sending circuit 41 and the buffer memory 470. The data register 44 stores the data from the buffer memory 470 and sends out the stored data to the data bus 13.

The controller 45 has a command register 4
1 indicating the type of access based on the command data from the address register 2 and the address data from the address register 43.
An access signal AC1 and a second access signal AC2 are generated and supplied to the memory interface 47 and the retry information sending circuit 41, respectively. Specifically, the controller 45 operates as follows.

That is, in the case of a read access, the controller 45 first checks whether it is the first access request or the second access request. This is performed by comparing the content of a buffer memory (not shown) stored with the address data from the address register 43 while sequentially updating the received address data.

When it is determined that this is the first access request, since the data to be transferred to the master is not yet prepared in the buffer memory 470, the first access signal AC1 is generated and the memory interface 47 is generated.
To supply. Thereby, the memory interface 47
Starts reading data from the memory device 60. At the same time, the controller 45 sends the second access signal A
C2 is generated and supplied to the retry information sending circuit 41.
As a result, the retry information sending circuit 41 starts generating retry information. The second access signal AC2 includes an idle state signal END indicating that the access operation has been completed.

On the other hand, when the controller 45 determines that the request is the second access request, the data to be transferred is already prepared in the buffer memory 470, and the data in the buffer memory 470 is stored in the data register 44. And generates a first access signal AC1 for transfer to the memory interface 47. In this case, since there is no need to generate retry information, the second access signal AC2 is not generated. In the case of a write access, the controller 45 always outputs the first access signal AC1.
And the second access signal AC2, and supplies them to the memory interface 47 and the retry information sending circuit 41, respectively.

When the command data from the command register 42 indicates a burst read access or a burst write access, the controller 45 generates a signal indicating the transfer data length and supplies it to the counter 46. When the controller 45 cannot immediately respond to the access request from the master (for example, when there is a first read access request), the controller 45 outputs a retry request signal RT.
Generate Y. The retry request signal RTY is transmitted to the master retry control circuit 31 via the control bus 14.
Is supplied to the retry information register 310 included in the retry.

Further, when the command data from the command register 42 indicates a write access and the address data from the address register 43 indicates a predetermined specific address, the controller 45 outputs the write signal WR (details). (To be described later), and supplies it to the retry information sending circuit 41.

The counter 46 holds the remaining data length when the burst read access and the burst write access are performed. In this counter 46, the data length to be transferred from the controller 45 is set as an initial value.
Thereafter, it is decremented each time 1-byte data is transferred. The initial value of the counter 46 is the transfer data length DL
Is supplied to the memory interface 47. Also,
The contents of the counter 46 are supplied to the retry information sending circuit 41 as the remaining data length RL.

The memory interface 47 controls writing and reading of data to and from the memory device 60 and refresh of the memory device 60. The buffer memory 470 included in the memory interface 47 temporarily stores write data and read data. And
First access signal AC1 from controller 45, data length DL from counter 46, and address register 43
Memory 470 according to the address data from
Is written to the memory device 60,
Further, the data read from the memory device 60 is written into the buffer memory 470. The memory interface 47 supplies the retry information sending circuit 41 with a refresh signal REF indicating that the memory device 60 is performing a refresh process.

The details of the retry information sending circuit 41 will be described later.
One retry information is selected based on the second access signal AC2, the remaining data length DL, and the refresh signal REF, and is supplied to the buffer circuit. The retry information stored in the retry information sending circuit 41 is rewritable. Rewriting is performed in accordance with the write signal WR from the controller 45, the address data from the address register 43, and the data from the data register 44.

The buffer circuit 48 is constituted by a tri-state buffer circuit. The buffer circuit 48 sends the retry information from the retry information sending circuit 41 to the retry information bus 20 in synchronization with the retry request signal RTY from the controller.

The bus use signal included in the control bus 14 is a signal input from the master to a transfer control circuit (not shown), and is used to notify the slave that the common bus 10 is being used. . The response signal is generated by the transfer control circuit, and is used to notify the master that the access request has been received. The ready signal is generated by the transfer control circuit and is used to notify the master that data is ready.

Next, details of the retry information sending circuit 41 will be described with reference to the block diagram shown in FIG.
The retry information sending circuit 41 includes a state control circuit 410
And a time table 420. The state control circuit 410 includes a time table 4 in the sending circuit of the present invention.
Reference numerals 20 respectively correspond to the tables of the present invention.

The state control circuit 410 includes the controller 45
, The status signals ST1, ST2, ST3, ST4,... Indicating the current status of the slave based on the second access signal AC2 from the counter 46, the remaining data length RL from the counter 46, and the refresh signal REF from the memory interface 47.
Is generated and supplied to the time table 420.

Time table 420 is composed of a plurality of registers for storing retry information. Each register has an input terminal IN, an output terminal OUT, an output enable terminal OE, and a write enable terminal WE. State signals ST1, ST2, ST from state control circuit 410
, ST4,... Are supplied to the output enable terminal OE of each register. Then, the state signals ST1, ST
When any one of 2, ST3, ST4,... Is activated, the contents (retry information) of the register to which the activated state signal is supplied are output from the output terminal OUT.

The state control circuit 410 rewrites the contents of the time table 420 based on the address data from the address register 43 and the write enable signal WE1 based on the write signal WR from the controller 45.
WE2, WE3, WE4,... Are generated and supplied to the write enable terminal WE of each register.

Rewriting of the contents of the time table 420 is performed as follows. That is, the command data instructing the single write access from the master, the specific address and the retry information are stored in the command register 4 respectively.
2. When set in the address register 43 and the data register 44, the controller 45 generates a write signal WR and supplies it to the state control circuit 410. State control circuit 41
0 is a write enable signal WE1 based on the address data from the address register 43 and the write signal WR.
Activate any one of WE2, WE3, WE4,... As a result, data (retry information) from the data register is written from the input terminal IN to the register to which the activated write enable signal is supplied.

As described above, the contents of the time table 420 can be rewritten.
0 is changed to a memory element having another access speed, the time table 4
20 can be changed to retry information suitable for a memory element having another access speed.

In the above description, the time table 420 is constituted by a register.
M may be used. In addition, when the retry information is predetermined and does not need to be changed, the time table 420 can be configured by a ROM.

Next, a more detailed configuration of the state control circuit 410 will be described with reference to the block diagram shown in FIG. For the sake of simplicity, assume that this slave does not perform burst read / write access. Accordingly, the state control circuit 410 is supplied with the single read signal (e), the single write signal (f) and the idle state signal (h) as the second access signal AC2 from the controller 45, and the refresh signal from the memory interface 47. REF (g) is supplied, and the remaining data length DL from the counter 46 is not supplied. In FIG. 5, a configuration for writing data to the time table 420 is omitted.

The state control circuit 410 includes a current state register 411, a logic circuit 412, and a decoder 413. The logic circuit 412 can be composed of, for example, a decoder, random logic, associative memory, or ROM.

The current status register 411 stores bits A,
It consists of four bits, B, C and D, each bit storing the current state of the slave. Specifically, bit A stores whether an idle state is set, bit B stores a read process, bit C stores a write process, and bit D stores a refresh process. .

The logic circuit 412 changes each bit of the current state register 411 based on the single read signal (e), the single write signal (f), the idle state signal END (h), and the refresh signal REF (g). To generate a signal for In addition, the logic circuit 412
Signals O, P, Q and O for selecting one register in the time table 420 based on the signals (e), (f), (g) and (h) and the signal from the current state register 411. R is generated and supplied to the decoder 413. The decoder 413 outputs these signals O, P, Q and R
To decode the state signals ST1, ST2, ST3, ST
, Are generated, and the time table 4 is generated as described above.
20.

Next, the retry information stored in the time table 420 will be described. This retry information
Determined by slave specifications.

FIG. 6 shows an example of retry information stored in the time table 420 in the slave according to the first specification.
Shown in When the slave according to the first specification receives a read access request during execution of any of the read, write, and refresh processes, the slave saves the command data and address data at that time in a buffer memory (not shown). Then, when the processing being executed is completed, the reading of data from the memory device 60 is automatically started according to the saved command data and address data. Also, the slave sends retry information relating to a retry time (retry timing) to the master so that the master can make a read access request for retry when the data is prepared in the buffer memory 470.

When the slave receives a write access request during any of read, write and refresh processing, the slave saves the command data, address data and write data at that time in a buffer memory (not shown). Then, when the processing being executed is completed, data writing to the memory device 60 is automatically started in accordance with the saved command data, address data, and write data. The end of this write processing is not reported to the master. Therefore, a retry request does not occur when a write access request is received. Further, the refresh processing is performed only in the idle state, regardless of the operation of the master.

Now, the time from when the memory interface 47 instructs the memory device 60 to read data to the time when data is obtained in the buffer memory 470 is tr, the time required for read processing is trd, and the time required for write processing is trd. Is twr, and the time required for the refresh processing is trf, the retry time in each state of the slave is as follows. In the following, the retry information indicating the time tr is Tr, the retry information indicating the time trd is Trd, and the time t is
Retry information representing wr is represented by Twr, and retry information representing time trf is represented by Trf. Received read access in idle state (state 1): tr Received read access during read processing (state 2): trd + tr Received read access during write processing (state 3): twr + tr Received read access during refresh processing (state 3) State 4): trf + tr

Next, FIG. 7 shows an example of retry information stored in the time table 420 in the slave according to the second specification. The slave according to the second specification does not save the command data, the address data, and the write data at the time of receiving a write access during execution of any of the read, write, and refresh processes. Then, when the processing being executed is completed, retry information is transmitted to the master so that a retry write access request can be accepted from the master. Others are the same as the slave according to the first use described above.

In this case, the retry time in each state of the slave is as follows. Received read access in idle state (state 1): tr Received read access during read processing (state 2): trd + tr Received write access during read processing (state 5): trd Received read access during write processing (state 5) State 3): twr + tr Write access received during write processing (state 6): twr Read access received during refresh processing (state 4): trf + tr Write access received during refresh processing (state 7): trf

The above description is an example of a slave that does not perform burst read / write access.
Is supplied to the logic circuit 412 of the state control circuit 410. Also, the current status register 411
A bit indicating whether a burst read process is being performed and a bit indicating whether a burst write process is being performed are added. Further, the logic circuit 412 sends the decoder 41
The number of signals supplied to 3 is added according to the number of states to be generated. Then, the time required for the burst read processing is determined according to the remaining data length DL from the counter 46. Therefore, the time table 420 stores retry information corresponding to each of the remaining data lengths DL.

(4) Detailed Description of Operation of Processing System Next, an example of the operation of the processing system to which the bus control device of the first embodiment is applied in the above configuration will be described with reference to FIG.
This will be described with reference to the timing chart shown in FIG.
This timing chart shows an operation when a single memory access is performed in an idle state. It is assumed that the slave of this processing system is manufactured based on the first specification described above.

First, the processor 32 of the master starts the section P
While set in the command register 33 the command data specifying a single read access is _1, 8
As shown in (D), the address data A1 designating the read position in the memory device 60 is stored in the address register 3.
Set to 4. Then, at the end of the section P _1, Figure 8
As shown in (A), the bus use request signal REQ is activated (L level).

[0095] The bus arbiter 50 receiving this bus request signal REQ, if any to the common bus 10 is ready for use, as shown in FIG. 8 (B), activate the bus grant signal ACK at the beginning of the section P ₂ (H level).

[0096] Processor 32 that has received the bus grant signal ACK, as shown in FIG. 8 (C), the interval P ₂
At the beginning of the bus, activate the bus use signal (H level),
Single read command data is transferred to the command bus 11
The address data A1 is sent to the address bus 12 respectively. At this time, the buffer circuit 37 is controlled by the gate control signal GC from the controller 36 so that the data is transferred from the data bus 13 to the data register 35. Therefore, as shown in FIG. The bus 13 is in an undefined state. Thus, the read access request from the master to the slave is completed.

In the slave, the command data from the command bus 11 is set in the command register 42 in the section P ₂ , and the address data A 1 from the address bus 12 is stored in the address register 43 as shown in FIG. Is set to Here, if the command data indicates a read access, the controller 45 checks the address data from the address register 43 to determine whether the read access request is the first access request or the second access request. Find out.

As a result, since it is determined that the request is the first access request, the controller 45
_{At 3} , the first access signal AC1 is generated based on the command data from the command register 42 and supplied to the memory interface 47. Memory interface 47
Is currently in an idle state (not during a read process, a write process, or a refresh process), so that data is read from the memory device 60 in accordance with the first access signal AC1 and the address data A1 from the address register 43. To start.

[0099] Furthermore, controller 45 first when it is determined that the access request is a section P _3, the retry information transmission circuit generates the second access signal AC2 based on the command data and address data 41
To supply. Accordingly, the state control circuit 410 of the retry information sending circuit 41 recognizes that the single read access request has been made in the idle state, and activates the state signal ST1 representing "state 1" as shown in FIG. I do. As a result, the retry information Tr is read from the time table 420.

[0100] Then, the slave is a period P _4, as a response to the access request from the master, as shown in FIG. 8 (G), and returns a response signal generated by the transfer control circuit (not shown) to the master. At the same time, the slave
8, the retry request signal RTY generated by the controller 45 is returned to the master, and the retry information Tr read from the time table 420 is sent to the retry information bus 20 as shown in FIG. .

The master transmits the retry information Tr sent via the retry information bus 20 to the retry request signal RT.
It is set in the retry information register 30 in synchronization with Y.
The contents of the retry information register 310 are immediately set in the counter 311. Thereafter, the counter 311 starts counting down. Also, the master is shown in FIG.
As shown in, the bus signal is inactive (L level) at the end of period P _5, it releases the common bus 10. This allows other masters to use the common bus 10.

[0102] The above operation, the retry of the access request is suppressed in the 12 interval from the interval P ₄ by the retry information Tr until interval P _15. When the count completion signal from the counter 311 in the interval P ₁₆ is becomes H level, as shown in FIG. 8 (A), a bus use request signal REQ is activated again at the end of the section P _16. At this point, the data read from the memory device 60 is already stored in the buffer memory 47 in the slave.
It is aligned to 0.

[0103] The bus arbiter 50 receiving this bus request signal REQ, if any to the common bus 10 is ready for use, as shown in FIG. 8 (B), activate the bus grant signal ACK at the beginning of the section P ₁₇ To The processor 32 that has received the bus use permission signal ACK transmits the signal shown in FIG.
(C), the activate the bus signal at the beginning of the interval P _17, the command bus 11 command data of a single lead, and sends each address data A1 on the address bus 12. As described above, the retry access request to the master slave is completed.

[0104] In the slave, the interval P _17, along with the command data from the command bus 11 is set in the command register 42, as shown in FIG. 8 (F), the address data A1 from the address bus 12 the address register 43 Is set to If the command data indicates a read access, the controller 45 checks whether the read access request is a first access request or a second access request. Is determined. As a result, controller 45, in the interval P _18, the second access signal AC
Do not generate 2. Accordingly, as shown in FIG. 8 (F), Sarezu retry request signal RTY in the section P ₁₉ is activated, as shown in FIG. 8 (H), also never retry information to retry information bus 20 is sent .

[0105] In addition, in the section P _18, controller 45
Generates a first access signal AC1 for instructing data transfer from the buffer memory 470 to the data register 44, and supplies it to the memory interface 47. As a result, the data D stored in the buffer memory 470 is
1 is set in the data register 44.

[0106] Then, the slave is the interval P _19, as a response to the re-access request from the master, FIG 8 (G)
And a ready signal generated by a transfer control circuit (not shown) indicating that data transfer preparation is completed is returned to the master. Then, the data D1 stored in the data register 44 in the section P ₂₂ is sent to the data bus 13. On the other hand, in the master, the data D1 from the data bus 13 is set in the data register 35 via the buffer circuit 37 in the section ₂₃ . Processor 32
Captures the data set in the data register 35. Thus, a series of single read access operations is completed.

The above is the operation when the single memory read is performed in the idle state. If a single read access is made during the read, write or refresh processing, the retry information Trd + Trd is replaced in section ₄ instead of the retry information Tr. , Twr + Tr or Trf + Tr are sent to the master. As a result, the sections P _{4 to} P in FIG.
₁₅ extend by sections corresponding to Trd, Twr or Trf, respectively. Other operations are as described above.

According to the first embodiment, retry information corresponding to all states of the slave is stored in the time table 42.
Since it is set to 0, the master can obtain data in one retry and in the shortest time. As a result, the common bus 10 can be used with high efficiency.

[Second Embodiment] Next, a processing system to which a bus control device according to a second embodiment of the present invention is applied will be described. This processing system apparatus is the same as the first embodiment except for the configuration and operation of the retry information sending circuit.
Therefore, the retry information sending circuit will be mainly described below.

FIG. 9 is a block diagram showing a detailed configuration of the retry information sending circuit 51 used in the second embodiment. The retry information sending circuit 51 includes a state control circuit 510, a time table 520, and an adder 523. Note that the configuration for rewriting the contents of the time table 520 is the same as that of the first embodiment, and is not shown.

The time table 520 includes a basic time table 521 and an optional time table 522. The basic time table 521 and the option time table 522 are each composed of a plurality of registers.
Is the same as

The basic time table 521 stores basic retry information. This basic retry information corresponds to the first retry information of the present invention. Here, the “basic retry information” means that when the slave is in the idle state, the slave that has received the access request from the master returns the retry request and then can accept the access request from the master next This is data representing the time until. As the basic retry information, for example, the retry information Tr in the first embodiment is used.

The option time table 522
Stores option retry information. This option retry information corresponds to the second retry information of the present invention. Here, “option retry information” is data representing the time required for each access process. As the option retry information, for example, the retry information Trd, Twr, and Trf in the first embodiment is used.

The state control circuit 510 includes the controller 45
, Which indicates the current state of the slave, based on the second access signal AC2 from the controller, the remaining data length RL from the counter 46, and the refresh signal REF from the memory interface 47, and generates a basic time table 521. Output enable terminal OE of each register
To supply. Further, in parallel with the generation of the state signals ST10,..., The state signals ST20, ST21, ST23,
Are generated and supplied to the output enable terminal OE of each register of the option time table 522.

When one of the status signals ST10,... Is activated, the contents (basic retry information) of the register to which the activated status signal is supplied are output from the output terminal OUT. Is done. For example, when there is a first single read access, the state signal ST10 is activated, and the retry information Tr
Is output. The output basic retry information is supplied to one input terminal of the adder 523.

Further, the state signals ST20, ST21, ST
When one of 23,... Is activated, the contents (option retry information) of the register to which the activated state signal is supplied are output from the output terminal OUT. For example, when the slave receives the access request, the status signal ST20 is being read during the read processing, and the status signal ST21 is being written during the write processing.
If the state signal ST22 is being refreshed,
Each is activated, and retry information Trd, Twr or Trf is output from the option time table 522. The output option retry information is
The signal is supplied to the other input terminal of the adder 523.

The adder 523 is provided for the basic time table 52.
1 and the option retry information from the option time table 522, and outputs the result as retry information. The output signal from the adder 523 is supplied to the buffer circuit 48.

If none of the status signals ST10,... Is activated, the basic time table 5
21 outputs zero. Similarly, the state signals ST20, S20
If none of T21, ST23,... Is activated, the option time table 522 outputs zero. Therefore, for example, when there is a single read access request in the idle state, the adder 523 outputs the basic retry information from the basic time table 521 as retry information.

By the way, in the second embodiment,
The configuration of the state control circuit 510 according to the first embodiment described above.
Can be simplified as compared with the state control circuit 410 of FIG. That is, the state control circuit 510 can be configured to output the single read signal (e) included in the second access signal AC2 as the state signal ST10. Also, the bit B of the current status register 411 is used as the status signal ST20.
And bit C as the state signal ST21, and the state signal ST21.
The bit D can be directly output as 22. Therefore, the logic circuit 412 and the decoder 413
Is simpler than that of the first embodiment.

Next, an example of the operation of the processing system to which the bus control device of the second embodiment is applied in the above configuration will be described with reference to the timing chart shown in FIG. Here, the basic time table 521 stores retry information Tr, and the optional time table 522 stores retry information Trd, Twr.
And Trf are stored.

The timing chart shown in FIG. 10 shows an operation when a single read access is performed during a single write access. That is, if the slave is in the idle state, the data to be read should be ready at the time tr specified by the retry information Tr. However, the time twr required for the write processing is further required due to the influence of the single write access performed immediately before. Is shown. It is assumed that the slave of this processing system is manufactured based on the first specification described in the first embodiment.

The operation in which the master sends an access request to the slave is the same as in the first embodiment. The slave having received the access request, in the section P _2, together with the command data from the command bus 11 is set in the command register 42, as shown in FIG. 10 (F), address the address data A1 from the address bus 12 It is set in the register 43. Here, the controller 45
If the command data indicates a single read access, the address data from the address register 43 is checked to determine whether the access request is the first access request or the second access request.

As a result, it is determined that this is the first access request.
_{At 3} , the first access signal AC1 is generated based on the command data from the command register 42 and supplied to the memory interface 47. Memory interface 47
Is currently under write processing, so the first access signal A
C1 (command data) and address data are saved in a buffer memory (not shown). The memory interface 47 automatically reads the first access signal AC1 and the address data A1 saved in the buffer memory when the write processing is completed, and starts reading data from the memory device 60 according to these.

[0124] Furthermore, controller 45 first when it is determined that the access request is a section P _3, the retry information transmission circuit 41 generates the second access signal AC2 based on the command data and address data To supply. Accordingly, the state control circuit 410 of the retry information sending circuit 41 recognizes that a single read access request has been made during the write processing, and activates the state signals ST10 and ST20. As a result, the retry information Tr is read from the basic time table 521 and supplied to one input terminal of the adder 523. The retry information Twr is read from the option time table 522 and supplied to the other input terminal of the adder 523. Thus, the retry information Tr +
Twr is output.

[0125] Then, the slave is a period P _4, as a response to the access request from the master, Fig 10 (G)
, A response signal generated by a transfer control circuit (not shown) is returned to the master. At the same time, the slave
As shown in (H), the retry request signal RTY generated by the controller 45 is returned to the master, and
As shown in (K), the retry information Tr + Twr from the adder 523 is sent to the retry information bus 20.

At the master, the retry information Tr + Twr sent from the retry information bus 20 is set in the retry information register 30 in synchronization with the retry request signal RTY. The contents of the retry information register 310 are immediately set in the counter 311. Then, counter 3
11 starts a countdown. Further, the master, as shown in FIG. 10 (C), and the bus signal inactive at the end of period P _5, releases the common bus 10.
This allows other masters to use the common bus 10.

With the above operation, the retry information Tr + T
so that the retry of the access request is prevented in 18 sections from section P ₄ to interval P ₂₁ by wr. When the count completion signal from the counter 311 in the interval P ₂₂ is becomes H level, as shown in FIG. 10 (A), a bus use request signal REQ is activated again at the end of the section P _22. At this point, in the slave,
The data read from the memory device 60 is already in the buffer memory 470.

[0128] The bus arbiter 50 receiving this bus request signal REQ, if any to the common bus 10 is ready for use, as shown in FIG. 10 (B), activate the bus grant signal ACK at the beginning of the section P ₂₃ To The processor 32 that has received the bus use permission signal ACK transmits
0 (C), the activate the bus signal at the beginning of the interval P _23, the command bus 11 command data of a single lead, and sends each address data A1 on the address bus 12. As described above, the retry access request to the master slave is completed. Subsequent operations are the same as in the first embodiment.

The above is the operation when a single memory read is performed during the write processing. If there is a single read access during the idle state, the read processing or the refresh processing, instead of the retry information Twr + Tr in section ₄ , , Retry information Tr, Trd + Tr or Trf
+ Tr is sent to the master. As a result, the interval P ₄ to P ₂₁ in FIG. 10, respectively Trd, Twr or Tr
It only changes according to f, and the other operations are as described above.

In the first embodiment, retry information corresponding to all states of the slave is stored in the time table 420.
Therefore, the amount of retry information becomes enormous. On the other hand, according to the second embodiment, since the basic time table 521 and the optional time table 522 are separately provided, the capacity of the time table 520 can be reduced, and the amount of retry information to be created can be reduced. Can be. Further, since the retry information before the operation is stored in each register of the time table 520, it is possible to reduce errors in creating the retry information. For example, in the case of the second specification described in the first embodiment, seven types of retry information, state 1 to state 7, are required. On the other hand, according to the second embodiment, the retry information is Tr,
Four types of Trd, Twr, and Trf may be used. That is, since it is sufficient to create a timetable only for a specific state, the creation of the timetable is facilitated, and errors are greatly reduced. Further, as described above, the configuration of state control circuit 510 can be simplified as compared with the first embodiment. Further, as in the first embodiment, the master can obtain data in the first retry and in the shortest time, so that the common bus 10 can be used with high efficiency.

[Third Embodiment] Next, a processing system to which a bus control device according to a third embodiment of the present invention is applied will be described. This processing system differs from the processing systems according to the first and second embodiments described above in the following points. That is, in the processing systems according to the first and second embodiments, the access processing is always completed by one retry, whereas in the processing system according to the third embodiment, the access processing is not completed by one retry. There are cases.

That is, in this processing system, the first retry information having a predetermined value and the second retry information having a value smaller than the predetermined value are used as the retry information. Then, when the retry request is returned in response to the access request, the master issues the first retry access request after the time specified by the first retry information has elapsed. If a retry request is returned in response to the first retry access request, a second retry access request is issued after the time specified by the second retry information has elapsed. Thereafter, the second access request is repeated until the access processing is completed. Therefore, in the processing system according to the third embodiment, the access processing is not always completed by one retry.

For example, a memory module is connected to the slave so that a user can freely add or change the memory module, and a memory having a different response speed may be connected. In such a case, if some first retry information corresponding to a typical response speed is prepared, and second retry information is prepared accordingly, the user changes the memory module. It is not necessary to rewrite the time table every time, and the versatility is improved. Note that the method of selecting the retry information corresponding to the memory module may be such that a circuit that switches according to the response speed is mounted on the state control circuit.

The processing system to which the bus control device according to the third embodiment is applied is the same as the first and second embodiments except for the configuration and operation of the retry information sending circuit. Therefore, the retry information sending circuit will be mainly described below. Here, when the switch receives a read access request from the master, it does not matter whether the switch is in an idle state, during a read process, during a write process, or during a refresh process.
An example in which the retry information Tr corresponding to the read access is always returned to the master will be described.

FIG. 11 is a block diagram showing a configuration of a retry information sending circuit 61 used in the third embodiment.
The retry information sending circuit 61 includes a state control circuit 610
And a time table 620. The configuration for rewriting the contents of the time table 620 is the same as that of the first embodiment, and is not shown.

The time table 620 is composed of a first time table 621 and a second time table 622. The first time table 621 and the second time table 622 each include three registers, and the configuration of each register is the same as in the first embodiment. Note that the number of registers included in each of the first time table 621 and the second time table 622 is not limited to three, and can be arbitrarily determined.

The first time table 621 includes a first retry
B) Store the information. Optional as the first retry information
Can be used, for example, in the embodiment
2 stored in the basic time table 521
It is preferable to use the same data as the retry information.
In the following, the retry time is used as the first retry information.
t ₁, T_TwoAnd t_ThreeThree lits to generate each
Rye information T₁, T_TwoAnd T_ThreeShall be used.

The second time table 622 stores the second retry information. As this second retry information, it is preferable to use data having a value smaller than the first retry information. Hereinafter, a second retry information, it is assumed that three retries information for generating retry time t _4, t ₅ and t _6, respectively T _4, T ₅ and T ₆ are used.

In the case of the first access request, the state control circuit 610 outputs the second access signal AC2 from the controller 45, the remaining data length RL from the counter 46, and the refresh signal REF from the memory interface 47.
, The first state signals ST30, ST31, ST3
Generate 2. Generated first state signals ST30, ST
31 and ST32 are the first time table 621, respectively.
Is supplied to the output enable terminal OE of each register.
Further, in the case of the second or subsequent access request, the state control circuit 610 uses the second state signal ST4 based on each of the above signals.
0, ST41 and ST42 are generated. The generated second state signals ST40, ST41, ST42 are supplied to the output enable terminals OE of the respective registers of the second time table 622.

Then, the first state signals ST30, ST3
1. When any one of ST1 and ST32 is activated, the contents (first retry information) of the register to which the activated first state signal is supplied are output from the output terminal OUT. Supplied.
Similarly, when any one of the second state signals ST40, ST41, and ST42 is activated, the contents (second retry information) of the register to which the activated second state signal is supplied are output to the output terminal. The signal is output from OUT and supplied to the buffer circuit 48.

The first state signals ST30 to ST32 and the second
As the status signals ST40 to ST42, for example, a signal obtained by decoding a signal indicating the type of access can be used. Therefore, the state control circuit 410 has a configuration corresponding to the logic circuit 412 and the decoder 413 in the first embodiment.
It is easier than

Next, an example of the operation of the processing system to which the bus control device of the third embodiment is applied in the above configuration will be described with reference to a timing chart shown in FIG. This timing chart shows an operation when a single read access is performed during a single write access. That is, if the slave is in the idle state, the data to be read should be ready at time t ₂ , but the time t ₂ is further increased due to the influence of the immediately preceding write access.
Indicates a situation that requires _four . It is assumed that the slave of this processing system is manufactured based on the first specification described in the first embodiment.

The operation in which the master sends an access request to the slave is the same as in the first embodiment. The slave having received the access request, in the section P _2, together with the command data from the command bus 11 is set in the command register 42, as shown in FIG. 12 (F), address the address data A1 from the address bus 12 It is set in the register 43. Here, the controller 45
If the command data indicates a single read access, the address data from the address register 43 is checked to determine whether the access request is the first access request or the second access request.

As a result, it is determined that this is the first access request.
_{At 3} , the first access signal AC1 is generated based on the command data from the command register 42 and supplied to the memory interface 47. Memory interface 47
Is currently under write processing, so the first access signal A
C1 (command data) and address data are saved in a buffer memory (not shown). The memory interface 47 automatically reads the first access signal AC1 and the address data A1 saved in the buffer memory when the write processing is completed, and starts reading data from the memory device 60 according to these.

[0145] Furthermore, controller 45, since it is first access request, in the section P _3, the second access signal based on the command data and address data AC2
Is generated and supplied to the retry information sending circuit 41. Thereby, the state control circuit 41 of the retry information sending circuit 41
0 recognizes that the first single read access request has been made during the write processing, and activates the first state signal ST31. As a result, the first time table 62
1 retry information T ₂ is read from.

[0146] Then, the slave is a period P _4, as a response to the access request from the master, Fig 12 (G)
, A response signal generated by a transfer control circuit (not shown) is returned to the master. At the same time, the slave
As shown in FIG. 12H, the retry request signal RTY generated by the controller 45 is returned to the master and
As shown in (K), and sends a retry information T ₂ of the from the first time table 621 to retry information bus 20.

At the master, the retry information T ₂ sent from the retry information bus 20 is used as the retry request signal RTY.
Is set in the retry information register 30 in synchronism with.
The contents of the retry information register 310 are immediately set in the counter 311. Thereafter, the counter 311 starts counting down. Also, the master is shown in FIG.
As shown in (C), and the bus signal inactive at the end of period P _5, releases the common bus 10. This allows other masters to use the common bus 10.

[0148] The above operation, the retry of the access request is suppressed in the 12 interval from the interval P ₄ by the retry information T ₂ to interval P _15. When the count completion signal from the counter 311 in the interval P ₁₆ becomes the H level, as shown in FIG. 12 (A), the interval P ₁₆
END, the bus use request signal REQ is activated again. At this time, in the slave, the data read from the memory device 60 is still in the buffer memory 4.
Not in 70.

[0149] The bus arbiter 50 receiving this bus request signal REQ, if any to the common bus 10 is ready for use, as shown in FIG. 12 (B), activate the bus grant signal ACK at the beginning of the section P ₁₇ To The processor 32 that has received the bus use permission signal ACK transmits
As shown in 2 (C), to activate the bus signal at the beginning of the interval P _17, the command bus 11 command data of a single lead, and sends each address data A1 on the address bus 12.

[0150] In the slave, the interval P _17, along with the command data from the command bus 11 is set in the command register 42, as shown in FIG. 12 (F), the address data A1 from the address bus 12 the address register 43 Is set to Here, the controller 45
If the command data indicates a read access, the address data from the address register 43 is checked to determine whether the read access request is the first access request or the second access request.

As a result, it is determined that this is the second access request, but at this point, the data has not yet been stored in the buffer memory 470. Accordingly, the controller 45, the interval P _18, and supplies to the memory interface 47 and generates a first access signal AC1 based on the command data. If the write process is ongoing, the memory interface 47 saves the first access signal AC1 (command data) and address data in a buffer memory (not shown). The memory interface 47 outputs the first access signal AC saved in the buffer memory.
1 and the address data A1 are automatically read when the write processing is completed, and data reading from the memory device 60 is started in accordance with these.

[0152] Also, the controller 45 are the second access request (first retry of access request), the interval P _18, and generates the second access signal AC2 based on the command data and address data It is supplied to the retry information sending circuit 41. Thereby, the state control circuit 410 of the retry information sending circuit 41 recognizes that the first retry access request has been made during the write processing, and activates the second state signal ST40. As a result, from the second time table 622, the retry information T ₄
Is read.

[0153] Then, the slave is the interval P _19, as a response to the access request from the master, Fig 12 (G)
, A response signal generated by a transfer control circuit (not shown) is returned to the master. At the same time, the slave
As shown in FIG. 12H, the retry request signal RTY generated by the controller 45 is returned to the master and
As shown in (K), the retry information T ₄ output from the second time table 622 is sent to the retry information bus 20.

In the master, the retry information T ₄ sent from the retry information bus 20 is used as the retry request signal RTY.
Is set in the retry information register 30 in synchronism with.
The content of the retry information register 310 is
Set to 1 and the counter 311 starts counting down. In addition, as shown in FIG.
The bus use signal inactive at the end of the interval P _21, to release a common bus 10.

[0155] The above operation, the retry of the access request is prevented in three sections from section P ₁₉ by the retry information T ₄ to interval P _21. And section P
_When the count end signal from the counter 311 becomes H level at ₂₂ , the bus use request signal REQ is activated again at the end of the section P22 as shown in FIG. At this point, the data read from the memory device 60 is already stored in the buffer memory 47 in the slave.
It is aligned to 0.

[0156] The bus arbiter 50 receiving this bus request signal REQ, if any to the common bus 10 is ready for use, as shown in FIG. 12 (B), activate the bus grant signal ACK at the beginning of the section P ₂₃ To The processor 32 that has received the bus use permission signal ACK transmits
As shown in 2 (C), to activate the bus signal at the beginning of the interval P _23, the command bus 11 command data of a single lead, and sends each address data A1 on the address bus 12. As described above, the second retry access request to the master slave is completed. Subsequent operations are the same as in the first embodiment.

The above is an example in which the access process is completed by performing the retry process twice. However, when the retry process is performed three or more times, the processes in the sections P _{16 to} P ₂₂ are additionally executed. Further, the above-described example is an operation in the case where a single read access is performed during a write process.
Only the retry information selected from 0 is different, and substantially the same operation as described above is performed.

According to the third embodiment, since it is not always necessary to create data corresponding to all states of the external device and the slave as retry information, errors at the time of data creation can be reduced and the creation can be reduced. The amount of retry information to be performed can be reduced. As a result, the capacity of the time table can be reduced. Further, as described above, the configuration of state control circuit 510 can be simplified as compared with the first embodiment.

Next, a DRAM as an external device, a page R
A description will be given of a retry occurrence state when the OM and the hard disk device are adopted, and a processing system (first to third embodiments) suitable for each external device.

FIG. 13 is a histogram showing a retry situation when the external device connected to the slave is a DRAM. In this case, when a read access request is issued in the idle state, data can be obtained after a predetermined time. However, if some write access processing is performed when this read access request is issued, the read access processing cannot be started until all of the processing is completed. Therefore, the time from issuing a read access request to obtaining data is t ₁ , t ₁ ′, t ₁ ″,.
(T ₁ <t ₁ ′ <t ₁ ″ <...) Where t ₁ is a read access request in the idle state and t ₁ ′ is before the start of the read access. If one piece of data in the buffer memory 470 has to be written to the memory device 60, t ₁ ″ is equal to 2 in the buffer memory 470 before the read access starts.
In this case, a case in which pieces of data have to be written to the memory device 60 is shown.

When performing read access, for example,
When fresh, the refresh operation
Unable to start read access until finished. That
Data can be obtained after issuing a read access request
Time to t_Two, T_Two’, T _Two", ... (t_Two<
t_Two’<T_Two"<...)).
And t_TwoIs read access at the beginning of the refresh operation
If a request is made, t_Two’In the middle of the refresh operation
When a read access is issued, t_Two"Refresh
Each time a read access request is issued at the end of operation
Is represented.

Further, if, for example, a write access is performed when a read access request is issued and a fresh request having a higher priority than the read access is pending, the data is issued after the read access request is issued. The time required to obtain is longer.

As described above, the time from when a read access request is issued to when data is obtained varies depending on the state of the slave at the time when the read access request is issued, so that in the processing system according to the first embodiment, Is stored in the time table. In the processing system according to the second embodiment, t ₁ and t ₂ are stored in the basic time table,
_{(T 1 '-t 1),} (t 2 "-t 2), (t 2' -t 2),
(T ₂ ″ −t ₂ ) is stored in the option time table, and in the processing system according to the third embodiment, t ₁
And t ₂ are stored in the first time table, and Δt ₁ , Δt
₂ is stored in the second timetable. Here, it is preferable to select (t ₁ ′ −t ₁ ) as Δt ₁ . Δt
The ₂ preferable to choose a (t ₂ '-t _2).

FIG. 14 is a histogram showing a retry situation when the external device connected to the slave is a page ROM. The contents of the page corresponding to the accessed address are simultaneously read from the page ROM. Therefore, if the address of the read access request and the address of the previous access specifying the same page, the data is obtained from issues a read access request at time t _1. However, unless you specify the same page,
Time t ₂ (t ₁ <t ₂ ) is required until data is obtained.

In the processing system according to the first embodiment, t
₁ and t ₂ are stored in the time table as retry information. In the processing system according to the second embodiment, t ₁
Is stored in the basic time table, and (t ₂ −t ₁ ) is stored in the option time table. Further, in the processing system according to the third embodiment, t ₁ can be stored in the first time table, and (t ₂ −t ₁ ) can be stored in the second time table.

FIG. 15 is a histogram showing a retry situation when the external device connected to the slave is a hard disk device. The access time of the hard disk device is represented by the sum of the positioning time, the rotation waiting time, and the data transfer time. Since the positioning time and the rotation waiting time are determined by the current head position and the target position on the disk, and vary greatly, an average value can be used for each. The data transfer time is constant.

Therefore, the histogram has a variation as shown in FIG. 15 around the sum of the average positioning time t ₁ and the average rotation waiting time t ₂ . Therefore, on the slave,
Since the response time cannot be fully grasped, it is preferable to use the processing system according to the third embodiment.

[Embodiment 4] In the bus control devices according to Embodiments 1 to 3 described above, the retry information sending circuit is provided in each slave. In the fourth embodiment, the slave includes only the state control circuit in the retry information sending circuit, and the time table is provided in the bus arbiter.

FIG. 16 shows the configuration of a processing system to which the bus control device according to the fourth embodiment is applied. In this processing system, each slave includes a state control circuit 710 instead of the retry information sending circuit 41 in FIG. State control circuit 710 is the same as any of state control circuits 410, 510 and 610 in the first to third embodiments.

In this processing system, a bus arbiter device 500 is provided instead of the bus arbiter 50 in the first to third embodiments. This bus arbiter device 5
Reference numeral 00 denotes the same bus arbiter 50 as used in the first to third embodiments, a time table 501 and a buffer circuit 502.

The time table 501 is the same as in the first embodiment.
3 has the same configuration as any of the time tables 420, 520, and 620, and stores retry information required by all slaves. This timetable 501
Is supplied with a state signal from the state control circuit 710 of each slave. Further, the buffer circuit 502 is the same as the buffer circuit 48 used in the first to third embodiments. A retry request signal RTY included in the control bus 14 is supplied to an enable terminal of the buffer circuit 502.

In the above configuration, when issuing a retry request, the state control circuit 710 of each slave supplies a state signal to the time table 501 and supplies a retry request signal RTY to the enable terminal of the buffer circuit 502. As a result, the retry information is read from the time table 501 and sent to the retry information bus 20 in synchronization with the retry request signal RTY. Other operations are the same as those of the above-described first to third embodiments.

According to the fourth embodiment, since it is not necessary to provide a time table in the slave, the configuration of the slave is simplified. Also, since retry information of all slaves can be centrally managed, it is convenient for handling.

In the fourth embodiment, of the retry information sending circuit, the state control circuit is provided in the slave and the time table is provided in the bus arbiter. However, the entire retry information sending circuit may be provided in the bus arbiter. . According to this configuration, the configuration of the slave included in the processing system is simplified as compared with a case where the slave includes a retry information transmission circuit. For example, a slave can be designed by slightly changing an existing macro.

[Embodiment 5] In this embodiment 5,
The slave has only the state control circuit of the retry information sending circuit, and the time table is independently provided.

FIG. 17 shows the configuration of a processing system to which the bus control device according to the fifth embodiment is applied. In this processing system, each slave includes a state control circuit 710 instead of the retry information sending circuit 41 in FIG. Each state control circuit 710 is the same as any of the state control circuits 410, 510, and 610 in the first to third embodiments.

In this processing system, the time table 42 included in the slave in the first to third embodiments is included.
0, 520 or 620 is configured as an independent time table 70. A buffer circuit 71 is provided at an output terminal of the time table 70.

The time table 70 corresponds to the first to third embodiments.
Has the same configuration as any of the time tables 420, 520, and 620, and stores retry information required by all slaves. The time signal is supplied to the time table 70 from the state control circuit 710 of each slave. Further, the buffer circuit 71 is different from the first to third embodiments.
3 is the same as the buffer circuit 48 used in FIG. A retry request signal RTY included in the control bus 14 is supplied to an enable terminal of the buffer circuit 502.

In the above configuration, when issuing a retry request, the state control circuit 710 of each slave supplies a state signal to the time table 70 and supplies a retry request signal RTY to the enable terminal of the buffer circuit 71. As a result, the retry information is read from the time table 501 and sent to the retry information bus 20 in synchronization with the retry request signal RTY. Other operations are the same as those of the above-described first to third embodiments.

According to the fifth embodiment, since it is not necessary to provide a time table in the slave, the configuration of the slave is simplified. Also, since retry information of all slaves can be centrally managed, it is convenient for handling. Further, since a conventional bus arbiter can be used, there is no need for new development.

In the fifth embodiment, of the retry information sending circuit, the state control circuit is provided as the slave and the time table is provided independently. However, the entire retry information sending circuit is provided independently. Is also good. According to this configuration, as in the case of the fourth embodiment, the configuration of the slave included in the processing system is simpler than when the slave is provided with a retry information transmission circuit.

In the embodiments described above, the retry information bus 2 is used as a bus for transferring retry information to the master.
Although the dedicated bus such as 0 is used, the retry information can be transferred to the master using the data bus 13 included in the common bus 10. In this case, the processor 32 included in the master transmits the retry request signal RTY
In this case, the retry information may be fetched in synchronization with the retry information, and then set in the retry information register 310.

The processing system can be formed on one chip. In this case, a plurality of types of processing systems can be configured by changing the types of the master and the slave to be adopted according to needs. In this case, it is preferable to adopt a configuration in which the retry information transmission circuit is provided in the slave as described in the first to third embodiments. According to this configuration, when designing an integrated circuit, it is only necessary to design a plurality of slaves independently, determine a slave to be employed according to the type of processing system to be created, and arrange the slaves. The design of the integrated circuit is simplified.

In the above embodiments, the processing system having the bus arbiter has been described. However, the processing system having only one master or the processing system in which the priority of the bus use right is fixedly assigned to a plurality of masters is described. The system does not necessarily need to include a bus arbiter. Embodiments 1 to 3 and 5 can be applied to such a processing system.

[0185]

As described in detail above, according to the present invention,
A bus control device, a master device, a slave device, and a bus control method capable of improving the use efficiency of a common bus by retransmitting an access request at a timing suitable for various states of the slave in response to a retry request from the slave Can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a processing system to which a bus control device according to Embodiments 1 to 3 of the present invention is applied.

FIG. 2 is a block diagram showing a detailed configuration of a master used in a processing system to which the bus control devices according to the first to third embodiments of the present invention are applied.

FIG. 3 is a block diagram showing a detailed configuration of a slave used in a processing system to which the bus control devices according to the first to third embodiments of the present invention are applied.

FIG. 4 is a block diagram illustrating a detailed configuration of a retry information transmission circuit used in a processing system to which the bus control device according to the first embodiment of the present invention is applied;

FIG. 5 is a block diagram showing a detailed configuration of a state control circuit shown in FIG.

6 is a diagram showing an example of retry information stored in a time table shown in FIG.

FIG. 7 is a diagram illustrating another example of retry information stored in the time table illustrated in FIG. 4;

FIG. 8 is a timing chart showing an operation of the processing system to which the bus control device according to the first embodiment of the present invention is applied;

FIG. 9 is a block diagram illustrating a detailed configuration of a retry information transmission circuit used in a processing system to which the bus control device according to the second embodiment of the present invention is applied;

FIG. 10 is a timing chart illustrating an operation of a processing system to which the bus control device according to the second embodiment of the present invention is applied.

FIG. 11 is a block diagram showing a detailed configuration of a retry information sending circuit used in a processing system to which a bus control device according to a third embodiment of the present invention is applied.

FIG. 12 is a timing chart illustrating an operation of a processing system to which the bus control device according to the third embodiment of the present invention is applied;

FIG. 13 is a histogram showing a retry situation when an external device connected to a slave is a DRAM.

FIG. 14 shows that an external device connected to a slave is a page RO
13 is a histogram showing a retry situation when M is M;

FIG. 15 is a histogram showing a retry situation when an external device connected to a slave is a hard disk device.

FIG. 16 is a block diagram showing a configuration of a processing system to which a bus control device according to a fourth embodiment of the present invention is applied.

FIG. 17 is a block diagram showing a configuration of a processing system to which a bus control device according to a fifth embodiment of the present invention is applied.

FIG. 18 is a block diagram illustrating a configuration of a processing system to which a conventional buffer control device is applied.

[Explanation of symbols]

10 common bus 10 31 retry control circuit 41, 51, 61 retry information sending circuit 410, 510, 610, 710 state control circuit 70, 420, 501, 520, 620 time table 50 bus arbiter 500 bus arbiter device 521 basic time table 522 option time Table 523 Adder 621 First time table 622 Second time table A, B, C Master D, E Slave

Claims (20)

[Claims] 1. A slave device that outputs a signal indicating the status when processing for an access request cannot be executed, and retry information transmission that generates and transmits retry information based on a signal from the slave device. A bus control device comprising: a circuit; and a master device that sends a retry access request to the slave device after a time specified by retry information from the retry information sending circuit has elapsed. 2. A retry information transmitting circuit comprising: a table for storing retry information indicating a time required for the slave device to change from a state in which processing for an access request cannot be performed to a state in which the slave device can execute processing; and a signal from the slave device. 2. The bus control device according to claim 1, further comprising: a transmission circuit that selects, when receiving the signal, retry information corresponding to the signal from the table and transmits the retry information to the master device. 3. A retry information sending circuit comprising: a first table for storing first retry information representing a time required for processing a specific type of access request; and a time required for processing all types of access requests. A second table for storing second retry information to be represented, and a first selection for selecting, when receiving a signal from the slave device, first retry information corresponding to the signal from the first table. A second selection circuit that selects second retry information corresponding to the signal from the second table when receiving a state from the slave device; and a first retry selected by the first selection circuit. An adder that adds the information and the second retry information selected by the second selection circuit and sends the addition result as retry information to the master device. Bus control device according to claim 1, further comprising a transmitting circuit, city made. 4. The retry information sending circuit comprises: a first table for storing first retry information representing a predetermined time; and a second table for storing second retry information representing a time shorter than the predetermined time. A first retry information corresponding to the signal when the first signal is received from the slave device from the first table, and the first retry information is transmitted to the slave device as retry information. A transmitting circuit, when receiving a second signal from the slave device, selecting second retry information corresponding to the signal from the second table, and transmitting the second retry information to the slave device as retry information. 2. The slave device according to claim 1, further comprising: a transmission circuit comprising: two transmission circuits. 5. The bus control device according to claim 1, wherein the retry information sending circuit is formed in the slave device. 6. The bus control device according to claim 1, wherein said retry information sending circuit is formed independently of said master device and said slave device. 7. A bus arbiter for arbitrating a right to use a common bus for connecting the master device and the slave device, wherein the retry information transmitting circuit is formed in the bus arbiter. The bus control device according to claim 1. 8. The bus control device according to claim 1, wherein said master device, slave device and retry information sending circuit are formed on one chip. 9. A transmission circuit included in the retry information transmission circuit is formed in the slave device, and the table includes:
The bus control device according to any one of claims 1 to 4, wherein the bus control device is formed independently of the master device and the slave device. 10. A bus arbiter for arbitrating a right to use a common bus for connecting the master device and the slave device, wherein a transmission circuit included in the retry information transmission circuit is formed in the slave device. The bus control device according to claim 1, wherein the table is formed in the bus arbiter. 11. A receiving circuit for receiving an access request, and a retry information transmitting circuit for generating and transmitting retry information based on the state when processing for the access request received by the receiving circuit cannot be executed; And a slave device comprising: 12. A retry information sending circuit, comprising: a table for storing retry information indicating a time period from a state in which processing for the access request cannot be executed to a state in which the processing can be executed; and a receiving circuit receiving the access request. 12. The slave device according to claim 11, further comprising: a transmission circuit for selecting and transmitting, from the table, retry information corresponding to the access request when the process for the access request cannot be executed. 13. A retry information sending circuit, comprising: a first table for storing first retry information indicating a time required for processing for a specific type of access request; and a time required for processing for all types of access requests. A second table for storing second retry information to be displayed, and when the receiving circuit receives an access request of a specific type, first retry information corresponding to the type of the access request is selected from the first table. A first selection circuit, when receiving the access request by the receiving circuit, if processing for another access request is being executed, the second retry information corresponding to the type of the access request being executed is transmitted to the second selection circuit; A second selection circuit selected from a table; first retry information selected by the first selection circuit; and a second retry information selected by the second selection circuit. Sending circuit for sending the addition result by the adder and said adder for adding the distribution as retry information, the slave device of claim 11 having a city. 14. A retry information transmitting circuit, comprising: a first table for storing first retry information representing a predetermined time; a second table for storing second retry information representing a time shorter than the predetermined time; When the circuit receives the first access request and is in a state where processing for the access request cannot be executed, the first retry information corresponding to the state is stored in the first retry information.
A first sending circuit that selects and sends the selected access request from a table; and a second access request received by the receiving circuit when the access request cannot be processed. The slave device according to claim 11, further comprising: a second transmission circuit that selects and transmits 2 retry information from the second table. 15. The slave device according to claim 11, wherein said receiving circuit and said retry information sending circuit are formed on one chip. 16. A receiving circuit for receiving a retry request sent with retry information from a slave device, and retrying after a time specified by the retry information in response to the retry request received by the receiving circuit. A control circuit for sending an access request to the slave device.
And a master device comprising: 17. A bus control method for controlling a bus connecting a master device and a slave device, the first step of sending an access request from the master device to the slave device, wherein the slave device transmits the access request to the slave device. A step of generating retry information based on the state and sending the retry information to the master device in a state where the processing cannot be executed, and a time specified by the retry information generated in the second step has elapsed. A third step of sending a retry access request from the master device to the slave device after the
A bus control method comprising: 18. The second step includes: receiving an access request from the master device; and executing the access request from the state if the slave device cannot execute a process for the received access request. 18. The bus control method according to claim 17, further comprising the step of: generating retry information indicating a period until the state changes to a possible state and transmitting the retry information to the master device. 19. The method according to claim 19, wherein the second step is a step of receiving an access request from the master device, and if the received access request is a specific type of access request, a time required for processing the specific type of access request. Generating first retry information representing the time required to process the received access request; generating second retry information representing the time required for processing the received access request; and generating the second retry information and the second generated retry information.
18. The bus control method according to claim 17, further comprising: adding retry information to the master device, and transmitting the result of the addition to the master device as retry information. 20. The second step, comprising: receiving an access request from the master device; and, if the received access request is a first access request, a second time representing a predetermined time corresponding to the access request. 1
Generating retry information and sending it to the slave device as retry information; and if the received access request is a second access request, a second time representing a time shorter than the predetermined time corresponding to the access request. Generating the retry information and transmitting the retry information to the slave device as retry information.