JP2005107194A - Plane display device, display drive circuit and display drive method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent uneven pixel luminance caused by wire resistance. <P>SOLUTION: A plane display device is equipped with: a plurality of scanning lines Y; a plurality of signal lines X which intersect the plurality of the scanning lines Y; a plurality of display pixels PX each of which is driven corresponding to a voltage between a pair of the scanning line and the signal line which are arranged at each intersection position of the these scanning lines Y and the signal lines X; a Y driver 3 which successively drives the plurality of the scanning lines Y; and an X driver 2 which drives the plurality of the signal lines X while the plurality of the scanning lines Y are driven by the Y driver 3. The X driver 2 includes a plurality of driving signal outputting parts 22, 23 which outputs driving signals of pulse widths corresponding to the gradation level of a video signal to the plurality of signal lines X respectively and an output control line PL which supplies control voltages which shift the pulse voltage levels of these driving signals, and the output control line PL is wired so that the potential distribution of the output control line PL becomes a slope reverse to the potential distribution of a corresponding scanning line Y corresponding to the display pixels PX of each horizontal line. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a flat display device such as a field emission display (FED) in which a plurality of display pixels are configured by using, for example, surface conduction electron-emitting devices, and a display driving circuit and a display for the flat display device. The present invention relates to a driving method.

  The FED generally includes a display panel and a drive circuit that drives the display panel. The display panel includes a plurality of scanning lines extending in the horizontal (horizontal) direction, a plurality of signal lines extending in the vertical (vertical) direction intersecting with the scanning lines, and a plurality of positions arranged at intersections of the scanning lines and the signal lines. Display pixels (see, for example, Patent Document 1). In a display panel for color display, for example, three display pixels adjacent in the horizontal direction are used as color display pixels. Each display pixel includes a surface conduction electron-emitting device and a red (R), green (G), or blue (B) phosphor that emits light by an electron beam emitted from the electron-emitting device.

  The drive circuit includes a Y driver connected to one end of the plurality of scanning lines and an X driver connected to one end of the plurality of signal lines. The Y driver sequentially drives a plurality of scanning lines using the scanning signal, and the X driver drives the plurality of signal lines by a driving signal having a pulse width corresponding to the gradation level of the video signal while each scanning line is driven. To do. Each display pixel emits light with a luminance corresponding to the pixel voltage between the corresponding signal line and the corresponding scanning line.

By the way, each scanning line has a wiring resistance (that is, a distribution constant z), and generates a voltage drop that varies depending on the distance from the Y driver. For this reason, for example, even if the display pixels of one horizontal line are driven corresponding to video signals of the same gradation level, these display pixels cannot emit light with a uniform luminance distribution. The effective value of the pixel voltage is higher as the display pixel is closer to the Y driver and lower as the display pixel is farther from the Y driver. For this reason, luminance variations as shown in FIG. 10 occur.
JP 2002-221933 A

  In recent years, display panels having a horizontal aspect ratio of horizontal: vertical = 16: 9 are becoming mainstream. In the case of such a screen size, since a large number of display pixels are connected to each scanning line, the influence of the wiring resistance of this scanning line cannot be ignored. For example, when the number of color display pixels is horizontal: vertical = 1280: 720, 1280 × 3 (RGB) surface conduction electron-emitting devices are connected to a common scanning line. In this case, a potential difference of at least 2 to 3 V occurs between both ends of the scanning line due to a voltage drop at the wiring resistance. This enlarges the difference in pixel voltage that occurs between display pixels in one horizontal line, and makes the luminance distribution of these display pixels more non-uniform, thereby significantly reducing the display quality.

  By the way, it is general that the element characteristics of the display pixel, specifically the luminance characteristics, vary as shown in FIG. 10 depending on the element arrangement. In addition, there are similar variations in element characteristics of a plurality of output units that output drive signals to a plurality of signal lines in the driver IC, respectively. Such variation makes it difficult to obtain a uniform luminance distribution when these display pixels are driven based on video signals of the same gradation level, for example.

  In recent years, display panels having a horizontal aspect ratio of horizontal: vertical = 16: 9 are becoming mainstream. The number of color display pixels is, for example, horizontal: vertical = 1280: 720, and 1280 × 3 (RGB) surface conduction electron-emitting devices are arranged along the scanning line. Thus, the larger the screen, the more noticeable the luminance difference between the pixels when displaying a white image on the entire screen. This luminance difference is a factor that significantly lowers the display quality. It is conceivable to correct the video signal in consideration of variations in element characteristics, but as a result, the overall luminance is lowered.

  An object of the present invention is to provide a flat display device, a display drive circuit, and a display drive method that can prevent pixel luminance from becoming uneven due to wiring resistance.

  According to the present invention, a plurality of scanning lines, a plurality of signal lines intersecting with the plurality of scanning lines, a plurality of scanning lines and a plurality of signal lines are arranged at the intersecting positions, and between each pair of scanning lines and signal lines. A plurality of display pixels driven in accordance with the pixel voltage, a scanning line driver for sequentially driving the plurality of scanning lines, and a plurality of signal lines while each of the plurality of scanning lines is driven by the scanning line driver. A signal line driver for driving, and the signal line driver outputs a drive signal having a pulse width corresponding to the gradation level of the video signal to each of the plurality of signal lines, and the drive signal output unit. Including an output control line for supplying a control voltage for shifting the pulse voltage level of the output drive signal, and the output control line has the potential distribution of the output control line with respect to the plurality of drive signal output units. Flat panel display is wired is provided such that the slope of the potential distribution opposite the corresponding scanning line for display pixels in each horizontal line are connected via a plurality of signal lines.

  According to the present invention, a plurality of scanning lines, a plurality of signal lines intersecting with the plurality of scanning lines, a plurality of scanning lines and a plurality of signal lines are arranged at the intersecting positions, and between each pair of scanning lines and signal lines. A display driving circuit of a flat panel display device including a plurality of display pixels driven corresponding to a pixel voltage of a plurality of scanning lines, a scanning line driver that sequentially drives the plurality of scanning lines, and a plurality of scanning lines by the scanning line driver A signal line driver that drives a plurality of signal lines while each of the plurality of signal lines is driven, and each of the signal line drivers outputs a drive signal having a pulse width corresponding to the gradation level of the video signal to each of the plurality of signal lines. Drive signal output units, and output control lines for supplying a control voltage for shifting the pulse voltage level of the drive signals output from these drive signal output units. The output control lines are output to a plurality of drive signal output units. The display is wired so that the potential distribution of the control line has an inclination opposite to the potential distribution of the corresponding scanning line for the display pixels of each horizontal line connected to the plurality of drive signal output units via the plurality of signal lines. A drive circuit is provided.

  According to the present invention, a plurality of scanning lines, a plurality of signal lines intersecting with the plurality of scanning lines, a plurality of scanning lines and a plurality of signal lines are arranged at the intersecting positions, and between each pair of scanning lines and signal lines. A display driving method for a flat panel display device including a plurality of display pixels driven corresponding to a pixel voltage of the plurality of scanning lines, wherein the plurality of scanning lines are sequentially driven and each of the plurality of scanning lines is driven. A plurality of signal lines are driven, each of the plurality of signal lines is driven by a drive signal having a pulse width corresponding to the gradation level of the video signal, and the pulse voltage level of these drive signals is connected to each of the plurality of signal lines. Provided is a display driving method that is shifted by a control voltage from an output control line that is wired so as to have a potential distribution having a slope opposite to that of a corresponding scanning line with respect to a display pixel of a horizontal line.

  In these flat display devices, display drive circuits, and display drive methods, a plurality of signal lines are respectively driven by a drive signal having a pulse width corresponding to the gradation level of the video signal, and a plurality of pulse voltage levels of these drive signals are provided. Each of the horizontal lines connected to the signal line is shifted by a control voltage from an output control line wired so as to have a potential distribution having a slope opposite to that of the corresponding scanning line. Specifically, the pulse voltage level of the drive signal supplied to the display pixels of each horizontal line reflects the potential distribution of the output control line. In this case, even if the difference in pixel voltage occurs between display pixels on each horizontal line due to a voltage drop that depends on the wiring resistance of the scanning line, it is possible to eliminate the difference in pixel voltage by shifting the pulse voltage level. is there. Therefore, it is possible to prevent the pixel luminance from becoming non-uniform due to the wiring resistance.

  Hereinafter, a flat display device according to an embodiment of the present invention will be described with reference to the drawings. This flat display device is, for example, a field emission display (FED) device having a 720P high-vision XGA resolution in which the number of color display pixels is horizontal: vertical = 1280: 720.

  FIG. 1 schematically shows a circuit configuration of the flat display device. The flat display device includes a display panel 1, an X driver 2, a Y driver 3, an output voltage control circuit 4, and a video processing circuit 5. The display panel has m (= 720) scanning lines Y (Y1 to Ym) extending in the horizontal (horizontal) direction, and n (= 1280 × 3) extending in the vertical (vertical) direction intersecting these scanning lines Y1 to Ym. It includes m × n (= about 2.76 million) display pixels PX arranged at intersections of the signal lines X (X1 to Xn) and the scanning lines Y1 to Ym and the signal lines X1 to Xn. Each color display pixel is constituted by three display pixels PX adjacent in the horizontal direction. In this color display pixel, the three display pixels PX emit red light (R), green (G), and blue (B) emitted by the surface conduction electron-emitting devices 11 and the electron beams emitted from the electron-emitting devices 11, respectively. Of the phosphor 12. Each scanning line Y is used as a scanning electrode connected to the electron emitting element 11 of the display pixel PX on the corresponding horizontal line, and each signal line X is used as a signal electrode connected to the electron emitting element 11 of the display pixel PX on the corresponding column. Used.

  The X driver 2, the Y driver 3, the output voltage control circuit 4, and the video processing circuit 5 are arranged around the display panel 1 as a display driving circuit. The X driver 2 is a signal line driver connected to one end of the signal lines X1 to Xn, and the Y driver 3 is a scanning line driver connected to one end of the scanning lines Y1 to Ym. The video processing circuit 5 processes an RGB video signal supplied from an external signal source in a digital format. The Y driver 3 sequentially drives the scanning lines Y1 to Ym using the scanning signal, and the X driver 2 drives the signal lines X1 to Xn while each of the scanning lines Y1 to Ym is driven by the Y driver 3. The output voltage control circuit 4 controls the output voltage output from the X driver 2 as a processing result of the video processing circuit 5.

  The video processing circuit 5, for example, APL detection circuit (average detection circuit) 50 that detects the average level by summing up the levels of RGB video signals for one frame, and uniformly reduces the luminance of an image pattern having a large area of high luminance. Therefore, an ABL circuit (luminance limiting circuit) 51 that adjusts the RGB video signal based on the average level detected by the APL detection circuit 50, and a correction circuit 52 that corrects the gradation level of the RGB video signal output from the ABL circuit 51. including. The APL detection circuit 50 may be configured to detect at least one of the average gradation level of the RGB video signal for one or a plurality of frames and the average gradation level of the RGB video signal for one or a plurality of horizontal lines. . Further, the APL detection circuit 50 detects the average gradation level of the video signal for one or a plurality of frames or the video signal for one or a plurality of horizontal lines from the light emission current or the discharge current actually flowing through the plurality of display pixels PX. It may be configured.

  The X driver 2 samples and holds a video signal for one horizontal line supplied from the video processing circuit 5 in synchronization with the horizontal synchronization signal HD, and one horizontal line output from the line memory 20 in parallel. A drive signal generation unit 21 that generates n PWM drive signals respectively corresponding to video signals for lines is included. The drive signal generator 21 generates n pulse width modulation circuits 22 each generating a pulse signal having a pulse width proportional to the gradation level of the video signal of the corresponding pixel, and pulses of the pulse signal from each corresponding pulse width modulation circuit 22. It includes n output buffers 23 that output the reference voltage Vref from the drive reference voltage terminal to the signal lines X1 to Xn as PWM drive signals shown in FIG. 2 only for a period equal to the width. The pulse width modulation circuit 22 and the output buffer 23 constitute a drive signal output unit for one signal line X. The output voltage control circuit 53 is connected to the n pulse width modulation circuits 22 via the output control line PL, and changes the voltage level of the pulse signal generated from the pulse width modulation circuit 22 to change the voltage level of the PWM drive signal. A power supply voltage is supplied to the n pulse width modulation circuits 22 as a control voltage VC shifted from the reference voltage Vref by an increment ΔV.

  In FIG. 1, z is a wiring resistance distributed in each of the scanning lines Y1 to Yn, i11 to imn are light-emitting currents that flow when mxn surface conduction electron-emitting devices 11 are discharged, and Vy is Y The output terminal voltages of the driver 3, ΔV 1 to ΔVm are total values of voltage drops caused by the emission current flowing through the wiring resistances of the scanning lines Y 1 to Yn when the n surface conduction electron-emitting devices 11 are discharged. It is.

These ΔV1, ΔV2, ΔV3,... ΔVm have the following values.

ΔV1 = z × i11 + 2 × z × i12 + − − − − + n × z × i1n
ΔV2 = z × i21 + 2 × z × i22 + − − − − + n × z × i2n
ΔV3 = z × i31 + 2 × z × i32 + − − − − + n × z × i3n
ΔVm = z × im1 + 2 × z × im2 ++ − − − − + n × z × imn
When the display pixels PX of each horizontal line are driven via the signal lines X1 to Xn, light emission currents flow through the electron-emitting devices 11 of the display pixels PX except for those that display black among the display pixels PX, Further, all of these light emission currents flow to the Y driver 3 through one scanning line Y. Specifically, assuming that the maximum current of each display pixel PX is 500 μA at maximum, the current becomes 1.92 A in total.

  A display pixel PX farther from the Y driver 3 is affected by voltage drops ΔV1 to ΔVm depending on the wiring resistance and the light emission current. When the total wiring resistance of each scanning line Y is 4Ω and the voltage drop is simply obtained by current (1.92A) × wiring resistance (4Ω), this voltage drop is 7.68V. Actually, since the wiring resistance and current are dispersed, it becomes about 2V. If there is such a voltage drop, the pixel voltage applied to the surface conduction electron-emitting device 11 is lowered, and the original light emission ability cannot be exhibited.

  The output control line PL extends along the first to nth pulse width modulation circuits 22 respectively assigned to the signal line X1 to the signal line Xn in the X driver 2 to reduce the voltage drop generated in the scanning line Y as described above. Used to turn off. Specifically, the output control line PL shortens the electrical wiring length between the first to nth pulse width modulation circuit 22 and the output voltage control circuit 4 in the order of the first to nth pulse width modulation circuit 22. Wired to do so. Here, the output control line PL has a common wiring resistance z ′ between the two adjacent pulse width modulation circuits 22 and between the nth pulse width modulation circuit 22 and the output voltage control circuit 4. The wiring resistance z ′ of the output control line PL does not need to be the same as the wiring resistance z of each scanning line Y, but n display pixels in each scanning line Y in a state where the power supply voltage VC is output to the output control line PL. It must be a value commensurate with the voltage drop that occurs with respect to PX. In addition, since each signal line X has, for example, a wiring resistance z for the m display pixels PX similarly to the scanning line Y, the power supply voltage VC has a voltage drop ΔV1 to ΔVm in the first to mth scanning lines Y. Changes to match the difference.

  When the pulse width modulation circuit 22 sets a pulse width for 1024 gradations from the 0th gradation corresponding to the minimum level of the video signal to the 1023rd gradation corresponding to the maximum level of the video signal, FIG. As shown, the pulse width of the drive signal is set to 0 at the 0th gradation, set to T at the 1st gradation, and set to j times T at the jth gradation. Here, T is, for example, an effective video period in one horizontal scanning period so that the pulse width of the PWM drive signal does not exceed one horizontal scanning period even at the 1023th gray level when the gray level of the video signal is maximum. Is set in advance to a period equal to 1/1023.

  The Y driver 3 shifts the vertical synchronizing signal VD every one horizontal scanning period and outputs it from one of the m output terminals, and a pulse output as a scanning signal from these m output terminals, respectively. In response, m output buffers 32 are provided for outputting scanning signals to the scanning lines Y1 to Ym for each horizontal scanning period. This scanning signal is a negative voltage Vyon supplied from the scanning voltage terminal, and is output only for one horizontal scanning period as shown in FIG. In each electron-emitting device 11, discharge occurs when the sum of the voltage Vx (= Vref + ΔV) of the signal electrode and the voltage Vy of the scanning electrode exceeds the threshold, and the electron beam emitted thereby causes the phosphor 12 to be discharged. Excited.

  The correction circuit 52 shown in FIG. 1 includes, for example, a signal analysis circuit 55, a 1H delay circuit 56, and a correction value calculation unit 57 as shown in FIG.

  The signal analysis circuit 55 divides the video signal for one horizontal line supplied every horizontal scanning period into k blocks as shown in FIG. 4, for example, and analyzes the video signals of these blocks. If the number of display pixels in one horizontal line is n = 3840 and the number of display pixels in one block is set to 128 × 3, for example, the number of blocks is k = n / 128 × 3 = 10. The signal analyzing circuit 55 sums and averages the gradation levels of the video signals for one block different from each other, and k coefficients different from the average levels obtained from the video signal totaling section 55A. Are constituted by k number of arithmetic units 55B that respectively perform arithmetic processing of multiplying by. The 1H delay circuit 56 delays the RGB video signal by one horizontal scanning period and outputs it to the correction value calculation unit 57.

  The correction value calculation unit 57 determines a correction coefficient that changes in accordance with the calculation result obtained in block units from the calculation unit 55B with reference to the luminance of the darkest display pixel PX among the display pixels PX of one horizontal line. Then, a correction value corrected with this correction coefficient is calculated. In each block, assuming that the gradation level changes linearly, the correction coefficient is set to the value of the black circle located at the block boundary in FIG. In the correction circuit 52, the analysis of the video signal and the determination of the correction coefficient are performed while the video signal is delayed by the 1H delay circuit 56. Further, the correction coefficient can be further changed so as to have a desired correction degree by an external control signal supplied to a control terminal provided in an auxiliary manner in the correction value calculation unit 57 as shown in FIG. The output voltage control circuit 4 uniformly changes the power supply voltage VC as the horizontal line of the display pixel PX corresponding to the video signal corrected by the correction value calculation unit 57 is changed.

 Specifically, the output voltage control circuit 4 generates a plurality of PWM output power supply voltages set at different levels, and selects one of the PWM output power supply voltages selected for each horizontal line. A control voltage VC is supplied to the corresponding pulse width modulation circuit 22. In this case, each pulse width modulation circuit 22 generates a pulse signal at the voltage level of the corresponding control voltage VC, that is, the PWM output power supply voltage. Further, each output buffer 23 outputs an output voltage Vx (= Vref + ΔV) obtained by level-shifting the voltage Vref from the driving reference voltage terminal by an increment ΔV corresponding to the voltage level of the pulse signal from the corresponding pulse width modulation circuit 22. The output voltage Vx is output as a PWM drive signal shown in FIG. 2 to the signal lines X1 to Xn only for a period equal to the pulse width of the pulse signal.

  That is, the video signal processing circuit 5 analyzes the gradation level of the video signal for each horizontal line, and determines each of the differences due to the wiring resistance z of the scanning line Y and the wiring resistance z ′ of the output control line PL depending on the wiring pattern. It is used to change the gradation level of the video signal so as to alleviate the luminance gradient in the horizontal line. In the driver IC used as the X driver 2, when there are variations in the element characteristics of the output buffers 23 and the output units that output drive signals to the signal lines, the correction coefficient is set in consideration of the variations. Just decide.

  Here, the correction operation for the luminance gradient of one horizontal line will be further described. For example, the video signal has the maximum gradation level shown in FIG. 6 for all the display pixels PX of one horizontal line, and the control voltage VC is the uniform level VC0 shown in FIG. When supplied to the width modulation circuit 22, the output voltage of the X driver 2, that is, the pulse voltage level of the PWM drive signal is maintained at the constant reference voltage level Vref shown in FIG. 8 for all these display pixels PX. . In this case, the luminance of the display pixel PX on one horizontal line is inclined as indicated by a broken line in FIG. 9, for example.

  The output voltage control circuit 4 outputs, to the output control line PL, the control voltage VC that has been changed so as to be higher than the level VC0 by a certain level in order to eliminate such a luminance gradient. The potential distribution of the output control line PL for the first to nth pulse width modulation circuits 22 is opposite to the potential distribution of the scanning lines for the first to nth display pixels PX on one horizontal line depending on the wiring resistance z ′. Inclined. That is, as shown by the solid line in FIG. 7, the control voltage VC decreases as the distance from the Y driver decreases, more strictly, as the distance from the output voltage control circuit 4 increases. Supplied. As a result, the output voltage of the X driver, that is, the pulse voltage level of the drive signal output to the signal lines X1 to Xn is shifted from the reference voltage level Vref as shown by the solid line in FIG. The difference in pixel voltage caused by the wiring resistance z of the scanning line Y is eliminated, and the uniform maximum luminance level is maintained as shown in FIG. Here, as described above, the video processing circuit 5 has a variation in pixel luminance in one horizontal line caused by a difference between the wiring resistance z of the scanning line Y and the wiring resistance z ′ of the output control line PL depending on the wiring pattern as described above. In addition to correcting the video signal, the average value of the gradation level of the video signal is reflected in this correction. Specifically, the correction value calculation unit 57 changes the correction coefficient in accordance with the analysis result from the signal analysis circuit 55 to correct the gradation level of the video signal.

  In the flat display device of the above-described embodiment, n signal lines X are driven by drive signals having a pulse width corresponding to the gradation level of the video signal, and the pulse voltage levels of these drive signals are connected to these signal lines X. Each horizontal line is shifted by a control voltage from an output control line PL that is wired so as to have a potential distribution having a slope opposite to the potential distribution of the corresponding scanning line Y with respect to the display pixel PX of each horizontal line. Specifically, the pulse voltage level of the drive signal supplied to the display pixel PX on each horizontal line reflects the potential distribution of the output control line PL depending on the wiring resistance z ′. In this case, even if the difference in the pixel voltage VC occurs between the display pixels PX in each horizontal line due to a voltage drop depending on the wiring resistance z of the scanning line Y, the difference in the pixel voltage is eliminated by the shift of the pulse voltage level. It is possible. Therefore, it is possible to prevent the pixel luminance from becoming non-uniform due to the wiring resistance z of the scanning line Y.

  Further, since the pulse voltage level of the drive signal is shifted in order to eliminate the inclination of the pixel luminance due to the wiring resistance z, the darkest of the display pixels PX on one horizontal line without using this configuration. It is possible to avoid a decrease in luminance of the entire image that occurs when the gradation level of the video signal is corrected in alignment with the display pixel PX. This also reduces the degree of correction of the gradation level of the video signal, so that the reduction in dynamic range in gradation can be mitigated.

  Furthermore, since the correction coefficient of the video signal changes according to the average gradation level obtained by dividing the video signal for one horizontal line into a predetermined number of blocks, the brightness difference is a conspicuous bright image pattern. It is also possible to reflect the display status of whether or not there is in the correction coefficient.

  In the above-described embodiment, the three display pixels PX constituting the color pixel are arranged in a stripe in the horizontal direction. However, the present invention is also effective in a delta arrangement. The present invention can be applied not only to a method in which the Y driver 3 is arranged only on one side of the scanning lines Y1 to Ym, but also to a method in which two Y drivers are arranged on both sides of the scanning lines Y1 to Ym.

It is a figure which shows roughly the circuit structure of the flat display apparatus which concerns on one Embodiment of this invention. 2 is a time chart for explaining the operation of the flat display device shown in FIG. 1. It is a figure which shows the circuit structure of the video processing circuit shown in FIG. It is a figure which shows the block of the video signal divided in the signal analysis circuit shown in FIG. 5 is a graph showing correction coefficients set for the block of the video signal shown in FIG. 4. 2 is a graph showing a video signal for one horizontal line processed for each display pixel specified by a distance from a Y driver by the video processing circuit shown in FIG. 1. 2 is a graph showing a control voltage supplied to each display pixel specified by a distance from a Y driver to a drive signal output unit of the X driver shown in FIG. 1. 3 is a graph showing an output voltage output as a drive signal for each display pixel specified by the distance from the Y driver by the drive signal output unit of the X driver shown in FIG. 1. 3 is a graph showing pixel luminance obtained from a drive signal output for each display pixel specified by a distance from a Y driver by a drive signal output unit of the X driver shown in FIG. 1. 2 is a graph showing that a variation in luminance of the surface conduction electron-emitting device shown in FIG. 1 is caused by a difference in pixel voltage.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Display panel, 2 ... X driver, 3 ... Y driver, 4 ... Output voltage control circuit, 5 ... Image processing circuit, 11 ... Surface conduction electron-emitting device, 12 ... Phosphor, 50 ... APL detection circuit, 51 ... ABL circuit, 52... Correction circuit, 55... Signal analysis circuit, 56... 1H delay circuit, 57... Correction value calculation unit, X .. signal line, Y .. scanning line, PX.

Claims (21)

A plurality of scanning lines, a plurality of signal lines intersecting with the plurality of scanning lines, and pixel voltages between a pair of scanning lines and the signal lines respectively disposed at intersections of the plurality of scanning lines and the plurality of signal lines A plurality of display pixels driven corresponding to the plurality of scanning lines, a scanning line driver sequentially driving the plurality of scanning lines, and the plurality of signal lines while each of the plurality of scanning lines is driven by the scanning line driver. A plurality of drive signal output units for outputting a drive signal having a pulse width corresponding to the gradation level of the video signal to each of the plurality of signal lines, and the plurality of drives. An output control line for supplying a control voltage for shifting the pulse voltage level of the drive signal output from the signal output unit, wherein the output control line is a potential component of the output control line with respect to the plurality of drive signal output units. Is wired so as to have an inclination opposite to the potential distribution of the corresponding scanning line for the display pixels of each horizontal line connected to the plurality of drive signal output units via the plurality of signal lines. Display device. 2. The flat display device according to claim 1, further comprising a signal processing circuit that corrects the gradation level of the video signal based on the luminance of the darkest display pixel among the display pixels of at least one horizontal line. The signal processing circuit divides the video signal for one horizontal line into a predetermined number of blocks, obtains the average gradation level of the video signal in units of these blocks, and calculates the correction coefficient of the video signal for each display pixel in the corresponding block The flat display device according to claim 2, further comprising a correction circuit that changes in accordance with the gradation level. The flat display device according to claim 3, wherein the correction circuit is configured to change a correction coefficient of the video signal in response to an external control signal. The signal processing circuit further detects an average gradation level of one of the video signal for at least one frame and the video signal for at least one horizontal line, and the video signal based on a detection result of the average detection circuit. The flat display device according to claim 3, further comprising a luminance limiting circuit that is uniformly adjusted and supplied to the correction circuit. The flat display device according to claim 5, wherein the average detection circuit is configured to detect an average gradation level from a current that actually flows through the plurality of display pixels. The flat display device according to claim 1, wherein the display pixel includes a surface conduction electron-emitting device that emits an electron beam. A plurality of scanning lines, a plurality of signal lines intersecting with the plurality of scanning lines, and pixel voltages between a pair of scanning lines and the signal lines respectively disposed at intersections of the plurality of scanning lines and the plurality of signal lines A display driving circuit for a flat panel display device, the display line driving circuit corresponding to a scanning line driver for sequentially driving the plurality of scanning lines, and a plurality of scanning lines by the scanning line driver. A signal line driver that drives a plurality of signal lines while each is driven, and the signal line driver outputs a drive signal having a pulse width corresponding to the gradation level of the video signal to each of the plurality of signal lines. A plurality of drive signal output units; and an output control line that supplies a control voltage that shifts a pulse voltage level of the drive signal output from the plurality of drive signal output units. The potential distribution of the output control line with respect to the motion signal output unit has a slope opposite to the potential distribution of the corresponding scanning line with respect to the display pixels of each horizontal line connected to the plurality of drive signal output units via the plurality of signal lines. A display driving circuit, wherein the display driving circuit is wired as described above. 2. The display driving circuit according to claim 1, further comprising a signal processing circuit that corrects the gradation level of the video signal with reference to the luminance of the darkest display pixel among the display pixels of at least one horizontal line. . The signal processing circuit divides the video signal for one horizontal line into a predetermined number of blocks, obtains the average gradation level of the video signal in units of these blocks, and calculates the correction coefficient of the video signal for each display pixel in the corresponding block The display driving circuit according to claim 9, further comprising a correction circuit that changes in accordance with a gradation level. 11. The display driving circuit according to claim 10, wherein the correction circuit is configured to change a correction coefficient of the video signal in response to an external control signal. The signal processing circuit further detects an average gradation level of one of the video signal for at least one frame and the video signal for at least one horizontal line, and the video signal based on a detection result of the average detection circuit. The display driving circuit according to claim 10, further comprising a luminance limiting circuit that is uniformly adjusted and supplied to the correction circuit. 13. The display driving circuit according to claim 12, wherein the average detection circuit is configured to detect an average gradation level from a current that actually flows through the plurality of display pixels. 9. The display driving circuit according to claim 8, wherein the display pixel includes a surface conduction electron-emitting device that emits an electron beam. A plurality of scanning lines, a plurality of signal lines intersecting with the plurality of scanning lines, and pixel voltages between a pair of scanning lines and the signal lines respectively disposed at intersections of the plurality of scanning lines and the plurality of signal lines A display driving method for a flat panel display device including a plurality of display pixels driven corresponding to the plurality of display pixels, wherein the plurality of scanning lines are sequentially driven, and the plurality of scanning lines are driven while each of the plurality of scanning lines is driven. Each of the plurality of signal lines is driven by a drive signal having a pulse width corresponding to the gradation level of the video signal, and the pulse voltage levels of these drive signals are connected to the plurality of signal lines. A display driving method, characterized by being shifted by a control voltage from an output control line wired so as to have a potential distribution having a slope opposite to a potential distribution of a corresponding scanning line with respect to a display pixel of a horizontal line. 16. The display driving method according to claim 15, wherein the gradation level of the video signal is further corrected based on the luminance of the darkest display pixel among the display pixels of at least one horizontal line. The video signal for one horizontal line is divided into a predetermined number of blocks, the average gradation level of the video signal is obtained for each block, and the correction coefficient of the video signal for each display pixel corresponds to the average gradation level in the corresponding block. The display driving method according to claim 16, wherein the display driving method is changed. 18. The display driving method according to claim 17, wherein a correction coefficient of the video signal changes corresponding to an external control signal. The average gradation level of one of the video signal for at least one frame and the video signal for at least one horizontal line is detected, the video signal is uniformly adjusted based on the detection result, and the gradation of the video signal is adjusted after this adjustment. The display driving method according to claim 17, wherein level correction is performed. The display driving method according to claim 19, wherein an average gradation level is detected from a current that actually flows through the plurality of display pixels. The display driving method according to claim 15, wherein the display pixel includes a surface conduction electron-emitting device that emits an electron beam.

Images