JP2005101517A - Capacitive element and semiconductor memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a capacitive element having an lower electrode of a three-dimensional configuration and a capacitive insulating film of a ferroelectric material, and a semiconductor memory using the capacitive element, which can avoid an adverse influence on the data holding performance of the capacitive element by preventing a deterioration in the polarization characteristic of the ferroelectric material by a simple method. <P>SOLUTION: A capacitive element 22 has a lower electrode 19 of a three-dimensional configuration, an upper electrode 21 formed to be opposed to the lower electrode 19, and a capacitive insulating film 20 formed between the lower and upper electrodes 19 and 21 and made of a crystallized ferroelectric material. The capacitive insulating film 20 is set to have a thickness not smaller than 12.5 nm and not larger than 100 nm. When the ferroelectric material has a polycrystalline structure, the material are set to have crystalline grain diameters not smaller than 12.5 nm and not larger than 200 nm. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a capacitive element having a three-dimensional structure using a ferroelectric as a capacitive insulating film, and a semiconductor memory device using the capacitive element.

  In recent years, research and development have been actively conducted on ferroelectric films having spontaneous polarization characteristics with the aim of putting non-volatile RAM (Nonvolatile Random Access Memory) capable of writing and reading operations at a low voltage and high speed unprecedented. ing. In particular, a megabit-class semiconductor storage device mounted on a large-scale integrated circuit (LSI) composed of complementary metal-oxide semiconductors (CMOS) whose design rule is 0.18 μm or less. In order to realize the above, it is necessary to develop a capacitive element having a three-dimensional structure capable of realizing a large capacity even in a small area. In a capacitor element having this three-dimensional structure, it is usually necessary to form a ferroelectric film, which is a capacitor insulating film, on a lower electrode whose surface is uneven.

  In order to achieve further high integration, the capacitive element is three-dimensionalized to reduce the dimension in the lateral direction (direction parallel to the main surface of the substrate), while the ferroelectric film is used to secure the capacitance of the capacitive element. It is necessary to make the thickness as thin as possible. Therefore, good polarization characteristics must be realized for a ferroelectric film having a small thickness.

  Hereinafter, a capacitor according to a conventional example will be described with reference to FIGS. 6 and 7 (see, for example, Patent Document 1).

  FIG. 6 shows a cross-sectional structure of a main part of a conventional semiconductor memory device (DRAM) having a capacitive element having a three-dimensional structure. As shown in FIG. 6, a first silicon oxide film 102 is formed on a semiconductor substrate 101 on which semiconductor elements and wirings (not shown) are formed, and the first silicon oxide film 102 has an n-type. A plug 103 made of low-resistance polysilicon doped with impurities is formed. A silicon nitride film 104 and a second silicon oxide film 105 are sequentially deposited on the first silicon oxide film 102, and plugs 103 are provided on the silicon nitride film 104 and the second silicon oxide film 105. Deep holes 106 are respectively formed so as to expose the.

Each deep hole 106 has a diameter of about 0.3 μm and a depth of about 1.3 μm, and its aspect ratio is 4 or more. A lower electrode 107 made of polysilicon having a roughened surface is formed on the bottom and inner walls of each deep hole 106. A capacitor insulating film 108 made of a laminated body of a silicon nitride film and tantalum oxide (Ta ₂ O ₅ ) is deposited from below so as to cover the surface of the lower electrode 107, and a nitride film is deposited on the capacitor insulating film 108. An upper electrode 109 made of titanium (TiN) is deposited and formed. The lower electrode 107, the capacitor insulating film 108, and the upper electrode 109 constitute a capacitor element for information storage.

Here, the tantalum oxide (Ta ₂ O ₅ ) made of a high dielectric material used for the capacitor insulating film 108 has a film thickness that minimizes leakage current and tantalum oxide as shown in FIG. It is described that it is desirable to set the thickness in the range of 4 nm to 7 nm in order to satisfy the two constraints of minimizing the effective film thickness when converted to a silicon oxide film (SiO ₂ ).
JP 2001-53250 A (pages 5-9 [0036] to [0071], FIGS. 9 and 12)

  However, a configuration using a ferroelectric in the capacitor insulating film that constitutes the above-described conventional capacitive element cannot realize good characteristics, and therefore has a problem that a high-performance nonvolatile memory device cannot be realized. Yes.

  Hereinafter, this reason will be described in detail.

  When a high dielectric material such as tantalum oxide is used for the capacitor insulating film as in the conventional example, the leakage current through the capacitor insulating film is minimized and converted to a silicon oxide film when thinning the film. Only two points are important: minimizing the effective film thickness.

  On the other hand, when a ferroelectric material is used for the capacitor insulating film, data is stored using the spontaneous polarization characteristics of the ferroelectric material, so that excellent polarization characteristics can be realized when thinning the film. Is the most important issue. As a result of various studies on the subject, the present applicants have obtained the knowledge that when the thickness of the ferroelectric film falls below a certain thickness, the polarization characteristics deteriorate rapidly. It has also been found that the polarization characteristics deteriorate rapidly even when the crystal grain size of the ferroelectric film is below a certain size. Details are described below.

  Since the polarization of the ferroelectric film is expressed by the displacement of ions in the crystal, most regions of the ferroelectric film must be composed of crystals in order to achieve good polarization characteristics. However, the interface region between the ferroelectric film and the electrode is in an incomplete crystal or amorphous state. As a result, when the film thickness is reduced to such a thickness that the influence of the interface region becomes significant, it becomes impossible to realize good polarization characteristics. Also, when the crystal grain size of the ferroelectric is reduced, the amount of ion displacement in the crystal is reduced, and furthermore, the crystal region occupying the ferroelectric film is reduced, and conversely the grain boundary region is increased. Good polarization characteristics cannot be obtained.

  As described above, a conventional semiconductor memory device having a capacitor element has a problem that a high-performance nonvolatile memory device cannot be realized because good physical characteristics cannot be obtained when a ferroelectric is used for a capacitor insulating film. doing.

  The present invention solves the above-mentioned conventional problems, and in a capacitive element having a lower electrode having a three-dimensional shape and a capacitive insulating film made of a ferroelectric and a semiconductor memory device using the same, in a ferroelectric by a simple method It is an object to prevent the deterioration of polarization characteristics so as not to adversely affect the data retention characteristics of the capacitive element.

  In order to achieve the above object, a capacitive element according to the present invention includes a three-dimensional lower electrode, an upper electrode formed to face the lower electrode, a lower electrode and an upper electrode, A capacitor element having a capacitor insulating film made of a ferroelectric material is used, and the film thickness of the capacitor insulating film is set to 12.5 nm or more and 100 nm or less.

  According to the capacitive element of the present invention, as will be described later, since it is possible to prevent deterioration of the polarization characteristics of the ferroelectric material constituting the capacitive insulating film having a three-dimensional shape, a large-capacity nonvolatile semiconductor memory device having excellent data retention characteristics Can be realized with a small circuit area.

  In the capacitive element of the present invention, the ferroelectric has a polycrystalline structure, and the crystal grain size is preferably 12.5 nm or more and 200 nm or less.

  In this way, even when the ferroelectric is made of a polycrystalline material, it is possible to reliably prevent deterioration of the polarization characteristics of the ferroelectric.

In the capacitive element of the present invention, the voltage applied to the capacitive insulating film is preferably 0.3 V or more and 2.5 V or less. The electric field applied to the capacitor insulating film is preferably 250 kV / cm ² or more.

  In this case, since the ratio of the charge amount for determining the data “1” and the data “0” held in the capacitor element can be set to a sufficiently large value, a good data holding characteristic can be realized.

In the capacitive element of the present invention, the capacitor insulating _{film, SrBi 2 (Ta x Nb 1} -x) 2 O 9, Pb (Zr x Ti 1-x) O 3 and _{(Bi x La 1-x)} 4 Ti 3 O ₁₂ (x is preferably 0 ≦ x ≦ 1) and is preferably composed of one material. In this way, a ferroelectric film having excellent polarization characteristics can be realized.

  In the capacitive element of the present invention, the lower electrode preferably has a convex cross-sectional shape, and the ratio of the height and width (height / width) of the lower electrode is preferably 1 or more.

  In this case, the width of the lower electrode is preferably 0.2 μm or more and 1.0 μm or less.

  In this case, the surface area of the capacitor insulating film can be increased, so that a sufficient amount of charge can be accumulated to hold data and good polarization characteristics can be realized.

  In the capacitive element of the present invention, the lower electrode is formed along the bottom surface and the side surface of the hole formed in the first interlayer insulating film, and the ratio of the hole depth to the diameter (depth / width). The value of is preferably 1 or more.

  In this case, the hole diameter is preferably 0.2 μm or more and 0.8 μm or less.

  In this case, the surface area of the capacitor insulating film can be increased, so that a sufficient amount of charge can be accumulated to hold data and good polarization characteristics can be realized.

  A semiconductor memory device according to the present invention includes a capacitor element according to the present invention, a transistor having a source region and a drain region formed on a semiconductor substrate, and a second interlayer insulation formed on the semiconductor substrate so as to cover the transistor. And a plug contact formed on the second interlayer insulating film so as to be electrically connected to the source region or drain region of the transistor, and the lower electrode of the capacitor element is formed so as to be connected to the plug contact. It is characterized by.

  According to the semiconductor memory device of the present invention, since the capacitor element of the present invention is provided, a semiconductor having excellent data retention characteristics that can be formed on an LSI constituted by a CMOS transistor having a design rule of 0.18 μm or less. A storage device can be realized.

  According to the capacitive element and the semiconductor memory device using the same according to the present invention, the thickness of the capacitive insulating film made of a ferroelectric material and having a three-dimensional shape is set to 12.5 nm or more and 100 nm or less. In the case of a polycrystal, by setting the grain size to 12.5 nm or more and 200 nm or less, it is possible to prevent the polarization characteristics of the ferroelectric material from being deteriorated, and thus it is possible to realize good data retention characteristics. That is, since a capacitor and a semiconductor memory device having excellent operating characteristics can be realized by an extremely easy method, the capacitor can be miniaturized, and as a result, high integration can be realized.

(First embodiment)
A first embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 shows a cross-sectional configuration of a main part of a capacitive element having a three-dimensional structure according to the first embodiment of the present invention.

  As shown in FIG. 1, for example, the main surface of a semiconductor substrate 11 made of silicon (Si) is partitioned by an element isolation film 12 made of shallow trench isolation (STI) to form a plurality of element active regions. A gate insulating film 13 and a gate electrode 14 are selectively formed on each element active region, and a source / drain region 15 is provided on both sides of the gate electrode 14 in each element active region. Are formed, and the gate insulating film 13, the gate electrode 14, and the source / drain regions 15 constitute a memory cell transistor 16.

On the main surface of the semiconductor substrate 11, an interlayer insulating film 17 made of silicon oxide (SiO ₂ ) or silicon nitride (SiN) is formed so as to cover each memory cell transistor 16. A plurality of plugs 18 made of low resistance polysilicon doped with tungsten (W) or n-type impurities are electrically connected to one of the source / drain regions 15 of each memory cell transistor 16 in the interlayer insulating film 17. It is formed to be.

A plurality of lower electrodes 19 are formed on the interlayer insulating film 17 so as to be electrically connected to the plugs 18. Although the lower electrode 19 is not shown, the lower layer is formed of iridium (Ir), iridium oxide (IrO ₂ ), ruthenium (Ru), ruthenium oxide (RuO ₂ ), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN). ) And titanium nitride silicide (TiSiN), an oxygen barrier made of a single layer film or a laminated film, and an upper layer of platinum (Pt), iridium (Ir), iridium oxide (IrO ₂ ), ruthenium (Ru). ), Ruthenium oxide (RuO ₂ ), strontium ruthenium oxide (SrRuO ₃ ), or the like. Here, the lower electrode 19 has a substantially circular planar shape, and its width dimension (diameter) is 0.2 μm or more and 1.0 μm or less. The height of the lower electrode 19 is set to 0.2 μm or more and 1.0 μm in a range where the ratio of the height and width of the lower electrode 19 (height / width), that is, the aspect ratio is 1 or more. Yes.

The upper and side surfaces of each lower electrode 19 are ferroelectric strontium bismuth tantalum niobate (SrBi ₂ (Ta _x Nb _{1 -x} ) ₂ O ₉ ) (where x is 0 ≦ x ≦ 1, hereinafter. The same shall apply.). The capacitor insulating film 20 can be formed by, for example, a metal organic chemical vapor deposition (MOCVD) method, an atomic layer deposition method, a sputtering method, or the like that has excellent step coverage.

  As a feature of the first embodiment, the thickness of the capacitive insulating film 20 is set to 12.5 nm or more and 100 nm or less by adjusting the deposition time during film formation. At this time, the crystal grain size of the ferroelectric is such that, after the capacitor insulating film 20 is formed, a heat treatment is performed to determine the crystal nucleus density in the range of 500 ° C. to 700 ° C., for example, and then the crystal is grown at 800 ° C., for example. Thus, it is set in the range of 12.5 nm to 200 nm. Here, the crystal grain size means the longest diameter (major axis) in an arbitrary cross section of the capacitive insulating film 20 unless otherwise specified.

  The size of the crystal grain size is determined by the crystal nucleus density. By performing the heat treatment at 500 ° C. to 700 ° C., which is the temperature range of the heat treatment for determining the crystal nucleus density described above, in the cross section of an arbitrary portion of the capacitive insulating film 20. It can be set in the range of 12.5 nm to 200 nm. The reason for this will be described in detail below. Although there may be a particle size smaller than 12.5 nm, there is no problem as long as it does not affect the physical characteristics (polarization characteristics) of the ferroelectric.

An upper electrode made of platinum (Pt), iridium (Ir), iridium oxide (IrO ₂ ), ruthenium (Ru), ruthenium oxide (RuO ₂ ), strontium ruthenium oxide (SrRuO ₃ ), etc. 21, and the lower electrode 19, the capacitive insulating film 20, and the upper electrode 21 constitute a capacitive element 22 for storing information.

  As described above, according to the first embodiment, the film thickness of the capacitive insulating film 20 made of the ferroelectric material constituting the capacitive element 22 having a three-dimensional structure is set to 12.5 nm or more and 100 nm or less, and the capacitance Since the crystal grain size of the insulating film 20 is set to 12.5 nm or more and 200 nm or less, it is possible to prevent deterioration of the polarization characteristics of the capacitive insulating film 20 made of a ferroelectric.

  Hereinafter, the reason why the film thickness of the capacitive insulating film 20 made of a ferroelectric is set in the above range will be described with reference to FIGS.

FIG. 2 shows the minimum voltage assumed when the capacitive element 22 according to the first embodiment is used, that is, the remanent polarization (2Pr) measured at 1.0 V, and SrBi ₂ (Ta _x Nb) as a ferroelectric substance. _1-x ) represents the result of evaluation by changing the film thickness of the capacitive insulating film made of ₂ O ₉ . The capacitive element used for the measurement is formed on a flat base layer, and platinum (Pt) is used for the upper electrode and the lower electrode, respectively. The average grain size of each crystal grain size in the ferroelectric is 100 nm.

As shown in FIG. 2, in the region where the film thickness of the ferroelectric SrBi ₂ (Ta _x Nb _1-x ) ₂ O ₉ is 50 nm or more (A in the figure), the film thickness is obtained when the applied voltage is constant. Since the applied electric field becomes larger as the thickness is thinner, the remanent polarization increases. On the other hand, in the region where the film thickness of the ferroelectric SrBi ₂ (Ta _x Nb _1-x ) ₂ O ₉ is 50 nm or less (B in the figure), as described above, it is close to an incomplete crystal or amorphous. The inventors of the present application have found that the polarization characteristics of the ferroelectric substance are reduced because the influence of the interface region between the ferroelectric substance and the electrode is increased. That is, as the thickness of the ferroelectric film is reduced, the residual polarization decreases, and the semiconductor memory device does not operate normally below a certain thickness. Therefore, the film thickness becomes the lower limit value. In addition, the broken line part of the graph in FIG. 2 represents having extrapolated data.

FIG. 3 shows the result of evaluating the remanent polarization (2Pr) of the ferroelectric SrBi ₂ (Ta _x Nb _1-x ) ₂ O ₉ this time by changing the crystal grain size. As in the case of FIG. 2, the remanent polarization (2Pr) is measured at 1.0 V, the capacitive element used for the measurement is formed on a flat base layer, and platinum (Pt) is formed on the upper and lower electrodes. Used. The film thickness of the ferroelectric film is 50 nm. In addition, the broken line part of the graph in FIG. 3 represents having extrapolated data.

As shown in FIG. 3, in the region (C in the figure) where the average crystal grain size of each of the plurality of crystal grains of the ferroelectric SrBi ₂ (Ta _x Nb _1-x ) ₂ O ₉ is 50 nm or more. Since the crystal grain size in the film thickness direction is regulated by the film thickness and becomes a constant value of 50 nm, the residual polarization hardly changes. On the other hand, in the region where the crystal grain size of the ferroelectric SrBi ₂ (Ta _x Nb _1-x ) ₂ O ₉ is 50 nm or less (D in the figure), a plurality of crystal grains are included in the film thickness direction. The inventors have found that the influence of the crystal grain boundary region in the applied electric field direction of the capacitive element appears and the polarization characteristics are reduced. Further, when the crystal grain size of the ferroelectric is reduced, the amount of displacement of ions in the crystal is reduced and the residual polarization is reduced, and the semiconductor memory device does not operate normally below a certain crystal grain size. Therefore, the crystal grain size becomes the lower limit.

According to the knowledge of the inventors of the present application, it is known that the semiconductor memory device malfunctions when the remanent polarization in the ferroelectric film is 10 μC / cm ² or less.

  From the results shown in FIG. 2, the lower limit of the film thickness in the ferroelectric film is 12.5 nm, and the upper limit of the film thickness is 100 nm. Furthermore, from the results shown in FIG. 3, the lower limit of the crystal grain size in the ferroelectric film is 12.5 nm, and the upper limit of the crystal grain size is determined by the heat treatment conditions for the ferroelectric film that becomes the capacitive insulating film of this embodiment. The value is 200 nm.

  When the film thickness of the capacitor insulating film made of a ferroelectric is set in the above range, the voltage applied to the capacitor insulating film is preferably in the range of 0.3V to 2.5V. The electric field applied to the capacitor insulating film is preferably 250 kV / cm or more. The reason for this will be described with reference to FIG.

FIG. 4 shows the polarization-electric field characteristics (hysteresis loop) of a capacitive element using a ferroelectric SrBi ₂ (Ta _x Nb _1-x ) ₂ O ₉ as a capacitive insulating film. In the case of a capacitive element using a ferroelectric as a capacitive insulating film, it is possible to increase the difference between the amount of charge corresponding to retained data “1” and the amount of charge corresponding to data “0” as much as possible. This is equivalent to widening the operation margin. This is to increase the remanent polarization when the electric field (E) shown in FIG. 4 is 0, that is, to increase the difference between + Pr and −Pr in the figure. For this purpose, it is necessary to increase the electric field applied to the capacitive element as much as possible. The inventors of the present application have found through various experiments that the lower limit of the applied electric field is at least twice the electric field at which the polarization becomes 0, that is, the coercive field. Specifically, as shown in FIG. 4, since the value of the coercive electric field is 125 kV / cm, the lower limit value of the applied electric field is 250 kV / cm. When this electric field value corresponds to the film thickness of the capacitive insulating film, the applied voltage is as follows.

  That is, when the thickness of the capacitive insulating film is 12.5 nm, 250 kV / cm × 12.5 nm = 0.31 V, and when the thickness of the capacitive insulating film is 100 nm, 250 kV / cm × 100 nm = 2.5 V. It becomes. Therefore, if the applied voltage is set in the range of 0.3 V to 2.5 V, good data storage characteristics can be realized within the range of the film thickness of the capacitive insulating film.

It should be noted that the ferroelectric material constituting the capacitive insulating film 20 includes lead zirconium titanate ((Pb (Zr _x Ti _1-x ) O ₃ ) instead of SrBi ₂ (Ta _x Nb _1-x ) ₂ O _9. or bismuth lanthanum titanate _{((Bi x La 1-x} ) 4 Ti 3 O 12) ( here, x is 0 ≦ x ≦ 1.) can be used.

(Second Embodiment)
Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.

  FIG. 5 shows a cross-sectional configuration of a main part of a capacitive element having a three-dimensional structure according to the second embodiment of the present invention. In FIG. 5, the same components as those shown in FIG.

As shown in FIG. 5, the capacitor 22 according to the second embodiment includes a second interlayer made of silicon oxide (SiO ₂ ) or silicon nitride (SiN) formed on the first interlayer insulating film 17. The insulating film 27 is formed in a concave shape in cross section. Specifically, the second interlayer insulating film 27 is formed along the bottom and side surfaces of a plurality of openings (holes) 27 a formed so as to expose the plugs 18. As a result, the film-like lower electrode 19 is electrically connected to each plug 18.

  Here, the ratio between the depth and diameter of the hole 27a, that is, the value of depth / diameter (aspect ratio) is set to 1 or more. This is because the surface area of the lower electrode 19 described below is made as large as possible to increase the amount of charge that can be accumulated. In the range where the aspect ratio is 1 or more, the diameter of the hole 27a is 0.2 μm or more and 0.8 μm or less, and the depth of the hole 27a is 0.2 μm or more and 1.5 μm.

Although the lower electrode 19 is not shown, the lower layer is formed of iridium (Ir), iridium oxide (IrO ₂ ), ruthenium (Ru), ruthenium oxide (RuO ₂ ), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN). ) And titanium nitride silicide (TiSiN), an oxygen barrier made of a single layer film or a laminated film, and an upper layer of platinum (Pt), iridium (Ir), iridium oxide (IrO ₂ ), ruthenium (Ru). ), Ruthenium oxide (RuO ₂ ), strontium ruthenium oxide (SrRuO ₃ ), or the like. Here, the film thickness of the lower electrode 19 is 50 nm to 200 nm.

On the second interlayer insulating film 27, a capacitive insulating film 20 made of SrBi ₂ (Ta _x Nb _1-x ) ₂ O ₉ which is a ferroelectric is formed so as to cover the lower electrode 19 in the hole 27a. Has been. The capacitive insulating film 20 can be formed by a metal organic chemical vapor deposition method, an atomic layer deposition method, a sputtering method, or the like that has excellent step coverage. Here, the film thickness of the capacitive insulating film 20 is set to 12.5 nm or more and 100 nm or less. Further, the crystal grain size of the capacitive insulating film 20 at this time is set to 12.5 nm or more and 200 nm or less. The reason for this is as described in the first embodiment.

Platinum (Pt), iridium (Ir), iridium oxide (IrO ₂ ), ruthenium (Ru), ruthenium oxide (RuO ₂ ), or strontium ruthenium oxide is in contact with the capacitive insulating film 20 on the upper surface of the capacitive insulating film 20. An upper electrode 21 made of (SrRuO ₃ ) or the like is deposited. Thus, the lower electrode 19, the capacitive insulating film 20, and the upper electrode 21 constitute a capacitive element 22 for storing information.

  As described above, according to the second embodiment, as in the first embodiment, the thickness of the capacitive insulating film 20 made of the ferroelectric of the capacitive element 22 having a three-dimensional structure is 12.5 nm or more and 100 nm or less. And the crystal grain size of the capacitor insulating film 20 is set to 12.5 nm or more and 200 nm or less, so that deterioration of the polarization characteristics of the capacitor insulating film 20 made of a ferroelectric can be suppressed.

In the second embodiment, SrBi ₂ (Ta _x Nb _1-x ) ₂ O ₉ is used as the ferroelectric as in the first embodiment. For example, bismuth lanthanum titanate ((B _{i x} In the case of using La _1-x ) ₄ Ti ₃ O ₁₂ ), the heat treatment conditions for determining the crystal grain size are changed as follows. That is, after the formation of the ferroelectric film serving as the capacitive insulating film 20, after performing a heat treatment for determining the crystal nucleus density in the range of 400 ° C. to 600 ° C., for example, the crystal is grown at 700 ° C. The diameter is set in the range of 12.5 nm to 200 nm.

The capacity in the ferroelectric material constituting the insulating film 20, instead of _{SrBi 2 (Ta x Nb 1-} x) 2 O 9 and _{(Bi x La 1-x)} 4 Ti 3 O 12, lead zirconium titanate ((Pb (Zr _x Ti _1-x ) O ₃ ) can be used.

  The capacitive element according to the present invention and the semiconductor memory device using the capacitive element can prevent deterioration of polarization characteristics of the capacitive insulating film made of a ferroelectric material, and thus have an effect of realizing good data retention characteristics. It is useful as a capacitive element having a three-dimensional structure provided with a capacitive insulating film made of a body, and a semiconductor memory device using the capacitive element.

It is a composition sectional view showing the important section of the capacity element which has a three-dimensional structure concerning a 1st embodiment of the present invention. 5 is a graph showing the dependence of residual polarization on the ferroelectric film thickness in the capacitive element according to the first embodiment of the present invention. 6 is a graph showing the dependence of the residual polarization on the ferroelectric crystal grain size in the capacitive element according to the first embodiment of the present invention. It is a graph which shows the applied electric field dependence of the polarization in the capacitive element which concerns on the 1st Embodiment of this invention. It is a composition sectional view showing the important section of the capacity element which has a solid structure concerning a 2nd embodiment of the present invention. It is a composition sectional view showing the important section of the capacitive element which has a three-dimensional structure concerning a conventional example. It is a graph showing the relationship between the leakage current and SiO ₂ in terms of effective thickness to the film thickness of the capacitor insulating film in the capacitor element having a three-dimensional structure according to the related art.

Explanation of symbols

11 Semiconductor substrate 12 Element isolation film 13 Gate insulation film 14 Gate electrode 15 Source / drain region 16 Memory cell transistor 17 Interlayer insulation film (first interlayer insulation film)
18 Plug (Plug contact)
19 Lower electrode 20 Capacitance insulating film 21 Upper electrode 27 Second interlayer insulating film 27a Hole

Claims (10)

A lower electrode having a three-dimensional shape;
An upper electrode formed to face the lower electrode;
A capacitive element formed between the lower electrode and the upper electrode and having a capacitive insulating film made of crystallized ferroelectric,
The capacitor element, wherein a thickness of the capacitor insulating film is set to 12.5 nm or more and 100 nm or less. The capacitive element according to claim 1,
The ferroelectric element has a polycrystalline structure, and a crystal grain size thereof is 12.5 nm or more and 200 nm or less. The capacitive element according to claim 1 or 2,
A voltage applied to the capacitor insulating film is 0.3 V or more and 2.5 V or less. The capacitive element according to claim 1 or 2,
The capacitor element, wherein an electric field applied to the capacitor insulating film is 250 kV / cm ² or more. The capacitive element according to claim 1 or 2,
The capacitor insulating _{film, SrBi 2 (Ta x Nb 1} -x) 2 O 9, Pb (Zr x Ti 1-x) O 3 and _{(Bi x La 1-x)} 4 Ti 3 O 12 ( where, x is 0 ≦ x ≦ 1)) is formed of one material selected from the above. The capacitive element according to claim 1 or 2,
The lower electrode has a convex cross-sectional shape, and a ratio of height to width (height / width) of the lower electrode is 1 or more. The capacitive element according to claim 6,
The capacitor element, wherein the width of the lower electrode is 0.2 μm or more and 1.0 μm or less. The capacitive element according to claim 1 or 2,
The lower electrode is formed along the bottom and side surfaces of a hole formed in the first interlayer insulating film, and the ratio of the depth and the diameter (depth / width) of the hole is 1 or more. A capacitive element. The capacitive element according to claim 8, wherein
The capacitor has a diameter of 0.2 μm or more and 0.8 μm or less. The capacitive element according to any one of claims 1 to 9,
A transistor having a source region and a drain region formed on a semiconductor substrate;
A second interlayer insulating film formed on the semiconductor substrate so as to cover the transistor;
A plug contact formed on the second interlayer insulating film so as to be electrically connected to a source region or a drain region of the transistor;
The semiconductor memory device, wherein the lower electrode of the capacitor element is formed so as to be connected to the plug contact.

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