JP2005101389A - Capacitor and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize a divercification for packaging a capacitor through a new application of a via electrode. <P>SOLUTION: Respective conducting between via electrodes 15a (a first and a second via electrode) from the surface of a capacitor to opposed internal electrodes 13a (a first and a second electrode layer) assures a function of the capacitor. At the same time, the via electodes 15a existing at a first repeating pitch of a first repeating pattern of the electrodes 13a are pitch-converted through internal electrodes 13b (a first and a second electrode layer for conducting) and conducted to via electrodes 15b (a first and a second via electrode for conducting) formed at a second repeating pitch scattered on the rear surface of the capacitor. Consequently the via electrodes 15a and the via electrodes 15b function as the conducting wire through the two side of the capaitor. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a capacitor in which a plurality of internal electrode layers and dielectric layers are alternately stacked, and more particularly to a multilayer capacitor in which a via electrode is used for conduction of the internal electrode layer and a manufacturing method thereof.

  In the multilayer capacitor as described above, the internal electrode layers are the first electrode layer and the second electrode layer facing each other with the dielectric layer in between, and a number of via electrodes that are electrically connected to these electrode layers are provided in the stacking direction. Such via electrodes include those connected to the first electrode layer (first via electrode) and those connected to the second electrode layer (second via electrode). Since it is sufficient that these via electrodes are electrically connected to the respective internal electrode layers, conventionally, the via electrodes have only reached the deepest internal electrode layer from the capacitor surface side (see, for example, Patent Document 1). reference).

JP 2002-359141 A JP 2003-158030 A

  In mounting such a capacitor on various integrated circuits, it is sufficient to mount another electronic device on the surface of the capacitor where the via electrode is exposed or to wire the via electrode on the surface of the capacitor.

  By the way, in recent years when miniaturization of electronic devices using integrated circuits is strongly demanded, it is widely used to use the front and back surfaces of devices as seen in mounting electronic devices on the front and back surfaces of printed circuit boards, for example. . However, in the capacitor proposed in the above publication, the actual situation is that no technical attention is paid to the mounting mode of the capacitor.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to diversify the mounting of capacitors through providing a new use of a via electrode.

In order to solve at least a part of the problems described above, the capacitor of the present invention includes:
A capacitor in which a plurality of internal electrode layers and dielectric layers are alternately laminated,
The internal electrodes are alternately provided as first electrode layers and second electrode layers facing the electrode layers on the capacitor surface side,
A plurality of first via electrodes formed to conduct commonly from the capacitor surface side to the first electrode layer, and a plurality of first via electrodes formed to conduct commonly from the capacitor surface side to the second electrode layer The second via electrodes are provided at a first repetition pitch,
On the back side of the capacitor, a first energizing electrode layer and a second energizing electrode layer that are laminated via the dielectric layer are provided,
Furthermore,
From the back side of the capacitor, a plurality of first energizing via electrodes that conduct to the first energizing electrode layer and a plurality of second energizing via electrodes that conduct to the second energizing electrode layer are connected to the energizing via. The electrode is repeatedly formed at a second repetition pitch interspersed on the capacitor back surface,
The first via electrode and the first energizing via electrode are at least partially connected through the first energizing electrode layer,
The gist of the second via electrode and the second energizing via electrode is that at least part of the second via electrode and the second energizing via electrode is conducted through the second energizing electrode layer.

  In this way, the first via electrode and the second via electrode that reach the internal electrode from the capacitor surface side are electrically connected to the first electrode layer and the second electrode layer, respectively, and can be charged in each electrode layer as a capacitor. Secure the functions of On the other hand, the first via electrode and the second via electrode that exist at the first repetition pitch are pitch-converted through the first conduction electrode layer and the second conduction electrode layer, and the second repetition pitch from the capacitor back side. The first energizing via electrode and the second energizing via electrode formed in the above are electrically connected. Therefore, the first via electrode and the first energization via electrode penetrate through the front and back of the capacitor, and the same applies to the second via electrode. As a result, according to the capacitor of the present invention, the via electrode, which has been assumed only for the purpose of charge charging, can be newly used as a conductive wire penetrating the front and back of the capacitor. It can be implemented and diversified. In this case, the pitch (second repetition pitch) of the first and second energizing electrode layers and the first and second energizing via electrodes, or the first and second electrode layers and the first and second vias is set. Various adjustments of the electrode pitch (first repetition pitch) can increase the degree of freedom of device mounting on the front and back of the capacitor.

  The capacitor of the present invention having the above configuration can take various forms. For example, the second repeated pitch of the current-carrying via electrodes existing in the formation region of the first current-carrying electrode layer and the second current-carrying electrode layer is the first via. It can be set to be equal to or more than the first repetition pitch of the electrode and the second via electrode.

  By doing so, via electrodes having different polarities do not come too close to each other in the formation region of the first energizing electrode layer and the second energizing electrode layer, that is, there is no fear of short-circuiting between different polarities. Reduction can be suppressed.

  Further, on the capacitor surface, surface side terminals to be terminals of the first and second via electrodes are formed for each via electrode, and on the capacitor back surface, terminals of the first and second energizing via electrodes are provided. It is also possible to form a back-side terminal for each via electrode. In this way, the lead connection to the via electrode via the terminal and the connection with the mounted product are facilitated.

  The capacitor of the present invention described above can take a form in which an electronic device or the like is already mounted in addition to the form alone. For example, the first via electrode and the second via electrode (surface side terminal) of the above capacitor A substrate having a semiconductor element connected to a semiconductor element, or a board having wiring including a power supply line and a ground line in each of the first and second current-carrying via electrodes (back surface side terminals). It can take the form of a connected board-integrated capacitor. A configuration in which a semiconductor and a substrate are provided on both sides of the capacitor is also possible.

In addition, the procedure adopted to manufacture the above capacitor is as follows:
A method of manufacturing a capacitor in which a plurality of internal electrode layers and dielectric layers are alternately laminated,
In order to form the internal electrode on the capacitor surface side, the internal electrode forming material to be the second electrode layer and the first electrode layer are alternately laminated with the dielectric material to be the dielectric layer interposed therebetween. (1) forming a first laminate in which the first electrode layer and the second electrode layer are repeated on the surface of the dielectric material at a first repetition pitch;
In the first laminated body, through-holes penetrating each of the laminated first electrode layers and the second electrode layers are formed at the first repetition pitch, and each through-hole is filled with a conductive paste. Step (2);
An electrode layer forming material of the first energizing electrode layer and the second energizing electrode layer is a second laminate in which the dielectric material is sandwiched between the first energizing electrode layer and the first energizing electrode layer. Holes reaching the second energizing electrode layer are provided at a second repetition pitch such that the holes are scattered from the surface of the second laminate, and the holes are filled with a conductive paste. Forming (3);
At least a part of the filled paste between the first electrode layers and the filled paste between the second electrode layers in the first laminate are the first and second energized electrodes in the second laminate. And a step (4) of superimposing the first and second laminated bodies filled with the paste so as to be bonded to a layer.

In addition, another procedure adopted for manufacturing the capacitor described above is:
A method of manufacturing a capacitor in which a plurality of internal electrode layers and dielectric layers are alternately laminated,
In order to form the internal electrode on the capacitor surface side, the internal electrode forming material to be the second electrode layer and the first electrode layer are alternately laminated with the dielectric material to be the dielectric layer interposed therebetween. A step (1) of forming a laminate;
Forming a through hole penetrating each of the laminated first electrode layers and the second electrode layers in the laminated body at a first repetition pitch, and filling each through hole with a conductive paste (2) When,
A first sheet using a dielectric material to be the dielectric, wherein the first sheet is provided with a through hole at a position overlapping at least a part of the through hole in the laminated body, and the through hole is filled with a conductive paste. A step (3) of stacking a sheet on the laminate;
A second sheet using a dielectric material to be the dielectric, wherein the second sheet has an electrode layer forming material for the first current-carrying electrode layer on the sheet surface, and is at least one of the through holes of the first sheet. A sheet in which a conductive paste is filled in through-holes provided at positions overlapping with a portion, and electrode layer arrival holes that are formed at a second repetition pitch and are scattered in the sheet and reach the first current-carrying electrode layer, And a step (4) of superimposing the second sheet on the first sheet.

  If a capacitor is manufactured through these steps, the first and second via electrodes from the capacitor surface side that cause charge charging to the first electrode layer and the second electrode layer are respectively connected to the first conductive electrode layer. Or through the first current-carrying electrode layer and the second current-carrying electrode layer, to the first current-carrying via electrode formed at the second repetition pitch from the back side of the capacitor, or to the first current-carrying electrode layer. A capacitor that is electrically connected to the conductive electrode layer and the second conductive via electrode can be easily manufactured.

In order to further clarify the configuration and operation of the present invention described above, embodiments of the present invention will be described in the following order.
A. Example:
A-1. Configuration of multilayer ceramic capacitor 10:
A-2. Manufacturing process of multilayer ceramic capacitor 10:
A-3. Effect:
B. Variation:

A. Example:
A-1. Configuration of multilayer ceramic capacitor 10:
FIG. 1 is an explanatory view showing an installation example of a multilayer ceramic capacitor 10 according to an embodiment of the present invention in a longitudinal section. In the installation example shown in FIG. 1, a package 50 on which an IC chip 30 is mounted and a wiring board 60 such as a mother board are connected via a multilayer ceramic capacitor 10.

  The IC chip 30 is a strip in which a large number of circuit elements such as transistors and resistors are formed on a single silicon substrate (wafer). The formed circuit elements are connected by a number of aluminum wirings. The aluminum wiring connected to the circuit element is drawn out to the lower surface of the IC chip 30 and connected to the pump-like pad 32. A large number of pads 32 are arranged in a lattice pattern on the lower surface of the IC chip 30 corresponding to the drawing position of the aluminum wiring.

  The package 50 is a container in which the IC chip 30 is mounted, and includes a lower layer 54 as an insulating layer on which the IC chip 30 is disposed. In this embodiment, the lower layer 54 is formed using an epoxy resin. Of course, the lower layer 54 can be formed of other insulating materials (for example, a resin material other than epoxy resin or ceramic). In addition to the lower layer 54, a configuration in which the upper layer 52 is provided as an insulating layer covering the IC chip 30 disposed in the lower layer 54 may be employed (see the two-dot chain line in FIG. 1). In this way, since the IC chip 30 is sealed in the insulating layer, the IC chip 30 can be effectively protected from the outside.

  The lower layer 54 is formed by laminating a number of epoxy resin plate-like bodies having a rectangular shape. The respective layers of the lower layer 54 are electrically connected by leads 56 formed of a copper plating layer or a copper foil. The lead 56 includes a bump 57 exposed on the upper surface (upper surface in FIG. 1) of the lower layer 54 and a terminal 58 exposed on the lower surface (lower surface in FIG. 1) of the lower layer 54. The bumps 57 are terminals connected to the IC chip 30, and many bumps 57 are arranged on the upper surface of the lower layer 54 in a lattice shape. The terminal 58 is connected to the surface side terminal 16 of the multilayer ceramic capacitor 10 using solder. In FIG. 1, leads 56, bumps 57, and terminals 58 (hereinafter referred to as leads 56+, bumps 57+, and terminals 58+) that are used as power supply lines are shown in black, and leads 56 (hereinafter referred to as ground lines). , Leads 56-, bumps 57-, and terminals 58-) are indicated by hatching, and the description of leads used as signal lines is omitted.

  The wiring board 60 is an epoxy resin multilayer board on which control wiring and components are mounted. As such a wiring board 60, a printed board such as a mother board can be considered. The respective layers of the wiring board 60 are electrically connected by leads 66 formed of a copper plating layer or a copper foil. The lead 66 includes a terminal 67 exposed on the upper surface (upper surface in FIG. 1) of the wiring board 60. This terminal 67 is connected to the back surface side terminal 17 of the multilayer ceramic capacitor 10 using solder. In FIG. 1, the lead 66 and the terminal 67 (hereinafter referred to as the lead 66+ and the terminal 67+) connected to the power supply line are shown using black fill, and the lead 66 and the terminal 67 (hereinafter referred to as the ground line) connected to the ground line. Lead 66- and terminal 67-) are shown using hatched hatching, and description of leads as signal lines is omitted.

  The multilayer ceramic capacitor 10 includes multilayered internal electrodes 13a on the capacitor upper surface side (capacitor surface side) shown in the figure, and includes a ceramic layer 14 as a dielectric between the electrodes. The ceramic layer 14 and the internal electrodes 13a Have a structure in which a large number of layers are alternately stacked (hereinafter referred to as a multilayer structure). On the capacitor lower surface side (capacitor rear surface side), another internal electrode 13b is laminated and opposed with the ceramic layer 14 interposed therebetween. That is, each ceramic layer 14 is sandwiched between the opposed internal electrodes 13a or internal electrodes 13b.

  Each of the internal electrodes 13a has a black positive charge electrode layer (for example, the first electrode) in the figure that is charged to a positive charge and a hatched negative charge electrode layer (for example, the second electrode) that is charged to a negative charge. ) Are alternately formed in a predetermined repeating pattern (first repeating pattern) and face each other. The internal electrode 13a is electrically connected to the via electrode 15a in common for each of the positive charge electrode layer and the negative charge electrode layer, and the via electrode 15a is connected to an external power source, a circuit, etc. via the surface side terminal 16. Connected to. The via electrode 15a is formed from the front surface 10a to the back surface 10b of the multilayer ceramic capacitor 10 until it reaches the lowermost positive charge electrode layer (for example, first energization electrode) and negative charge electrode layer (for example, second energization electrode). The formation pitch is the repetition pitch (first repetition pitch) of the first repetition pattern of the internal electrodes 13a.

  The internal electrodes 13b are alternately formed in a second repetitive pattern different from the first repetitive pattern of the internal electrodes 13a as a black first energizing electrode layer and a hatched second energizing electrode layer in the figure. opposite. The internal electrode 13b is electrically connected to the via electrode 15b in common for each of the first and second energizing electrode layers, and the via electrode 15b is connected to an external power source or circuit via the back surface side terminal 17. Connected to etc. The via electrode 15b is formed from the back surface 10b of the multilayer ceramic capacitor 10 to reach the first and second energization electrode layers at the deepest portion, and the formation pitch is as follows when the multilayer ceramic capacitor 10 is viewed in plan from the back surface 10b. The repeated pitch (second repeated pitch P2) is such that the via electrodes 15b are scattered on the back surface 10b of the multilayer ceramic capacitor 10.

  As described above, the multilayer ceramic capacitor 10 of this embodiment has the internal electrodes 13a and 13b in the dielectric, but the distance between the electrodes is short, and the multi-layer internal electrodes 13a are charged and function as a capacitor. That is, when the internal electrode 13a is connected to the via electrode 15a, positive and negative charges are charged in each of the opposing positive charge electrode layer and negative charge electrode layer to function as a multilayer capacitor. In the multilayer ceramic capacitor 10 having such a multilayer structure, a large number of portions where charges are accumulated are formed in a hierarchical manner, so that a small and large capacitance can be realized.

  As shown in the drawing, the via electrode 15a and the via electrode 15b have a front surface side terminal 16 and a back surface side terminal 17 on the capacitor surface side and back surface side, respectively.

  In the multilayer ceramic capacitor 10 of the present embodiment, as described above, the via electrode 15a and the via electrode 15b are respectively provided from the front and back sides of the capacitor, and both the via electrodes are subjected to pitch conversion in the internal electrode 13b. Conducted. Moreover, in order to achieve such conduction, at least a part of the via electrode 15a that is in conduction with the black internal electrode 13a (first electrode layer) in the figure is filled with the black first conduction of the internal electrode 13b. The via electrode 15b, which is electrically connected to the via electrode 15b which is electrically connected to the internal electrode layer, and the internal electrode 13a which is electrically connected to the hatched hatching (second electrode layer) in the figure, is at least partly hatched in the internal electrode 13b. The second conductive electrode layer is electrically connected to the via electrode 15b.

  This allows the via electrode 15a and the via electrode 15b to function as conductive lines through the front and back of the multilayer ceramic capacitor 10, so that the via electrode, which has been assumed only for charge charging in the past, can be passed through the capacitor front and back. Newly available as a line.

A-2. Manufacturing process of multilayer ceramic capacitor 10:
The multilayer ceramic capacitor 10 having the above-described configuration can be manufactured by the following manufacturing method. 2 is an explanatory diagram for explaining the outline of the production of the multilayer ceramic capacitor 10, FIG. 3 is an explanatory diagram for explaining the procedure of the production method employed in the embodiment, and FIG. 4 is for explaining the detailed contents of the production method. It is explanatory drawing of.

  As shown in FIG. 2, the multilayer ceramic capacitor 10 is manufactured by being divided into a first laminated body 11 in a portion including the internal electrode 13a and a second laminated body 12 in a portion including the internal electrode 13b. In the figure, reference numeral P1 indicates the bitch of the via electrode 15a in the multilayer ceramic capacitor 10 after completion, reference numeral P2 indicates the pitch of the via electrodes 15b, and reference numeral d indicates the via electrode diameters of the via electrodes 15a and 15b. Yes.

  As shown in FIG. 3, in the manufacturing method of a present Example, the following process is passed about each laminated body. First, the 1st laminated body 11 is demonstrated.

  In forming the first laminate 11, first, a ceramic slurry made of barium titanate or the like is uniformly and thinly applied to a long carrier film such as a PET (polyethylene terephthalate) film and dried. Thereby, a ceramic layer is formed on the carrier film (step S110). Next, a wiring layer is formed on the dried ceramic slurry by screen printing of an Ag electrode pattern (step S120). This wiring layer functions as the internal electrode 13a described above. Next, the ceramic layer and the carrier film are cut into a certain shape while the long carrier film on which the ceramic layer is formed is conveyed, and the carrier film is peeled off (steps S130 and S140). By such cutting and peeling, two types of ceramic sheets having different wiring layer formation positions are formed. Next, the first laminate 11 is formed by alternately laminating two types of ceramic sheets on a PET (polyethylene terephthalate) base sheet laid in advance (step S150). In the first laminated body 11 thus obtained, the internal electrodes 13a are alternately laminated in the first repetitive pattern as described above, and the respective electrodes face each other with the ceramic sheet interposed therebetween.

  Next, a conductive paste filling hole to be formed in the first laminate 11 is formed using a laser processing machine (step S160). When forming the filling hole in the first laminated body 11, as shown in FIG. 2, the filling hole for the via electrode 15a conducting through the via electrode 15b and the internal electrode 13b in the second laminated body 12 is formed in the first laminated body. 11 to penetrate through. On the other hand, the filling hole for the via electrode 15a that does not need to be electrically connected to the via electrode 15b may be any hole that reaches the lowermost internal electrode 13a, but in the present embodiment, this is a through hole.

  When forming the filling holes in the first stacked body 11, the filling holes are formed at the first repetition pitch (P1 in FIG. 2) of the first repetition pattern used to form the internal electrodes 13a. Hereinafter, this hole formation will be described.

  First, the diameter, number, range, and pitch between adjacent via electrodes after firing are determined. In the present embodiment, the diameter of each via electrode is set to a value that becomes a predetermined diameter d after a firing process described later, and the pitch between adjacent via electrodes is the first repetitive pitch P1 described above after the firing process described later. The value is such that Thereafter, through holes are formed by using a laser processing machine so as to satisfy the above determined specifications.

  Then, the 1st laminated body 11 is put in a pressurized container, the electrically conductive paste is pressure-filled to a filling hole (step S170), and it transfers to step S200 of FIG. The filled conductive paste functions as the above-described via electrode 15a. In this embodiment, paste-like Ag having a moderately high viscosity is used as the conductive paste. Further, the base sheet is peeled off when the paste is filled.

  The second laminated body 12 is also substantially the same as the first laminated body 11 described above, and after steps S110 to 170, the internal electrode 13b is opposed to the filling hole in the second repetitive pattern with the ceramic sheet interposed therebetween, and is electrically conductive in the filling hole. The second laminate 12 is filled with paste. As shown in FIG. 2, the second laminated body 12 is formed by laminating an upper laminated portion 12a having only a dielectric layer located on the upper surface side, an intermediate laminated portion 12b on the lower side, and a lower laminated portion 12c on the lowermost stage. Formed. And about the intermediate | middle laminated | stacked part 12b and the lower laminated part 12c, the internal electrode 13b is formed with a 2nd repeating pattern. As for the filling hole for filling the paste, in the upper laminated portion 12a, a filling hole for the via electrode 15a extending from the first laminated body 11 to the internal electrode 13b of the second laminated body 12 is formed to penetrate, and in the intermediate laminated portion 12b, A filling hole is formed through the via electrode 15a penetrating the second laminated body 12 and the via electrode 15a reaching the internal electrode 13b of the lower laminated portion 12c. In the lower laminated portion 12c, a via electrode 15a penetrating the second laminated body 12 and a filling hole for the via electrode 15a extending from the back side of the capacitor to the intermediate laminated portion 12b and the internal electrode 13b of the lower laminated portion 12c are formed to penetrate therethrough. Each laminated portion is put into a pressurized container, and a conductive paste is pressurized and filled in the filling hole. Thus, the filling hole is formed in advance, and the upper laminated portion 12a, the intermediate laminated portion 12b, and the lower laminated portion 12c in which the filling hole is filled with the conductive paste are laminated to form the second laminated body 12. It should be noted that each laminated portion in which the filling hole has been formed is laminated in advance, and the laminated state is put into a pressurized container, and the conductive paste is pressurized and filled in the filling hole. It can also be.

  In the completed multilayer ceramic capacitor 10, in the second multilayer body 12 shown in FIG. 2, the via electrode 15a and the via electrode 15b are mixed at the first repetition pitch P1 in the former and at the second repetition pitch P2. In each figure, it is represented by hatched hatching and black painting. The shaded hatch and the black-painted via electrode 15a and the via electrode 15b have the same polarity when the hatched hatch electrodes are used as capacitors, and the black-coated electrodes have the same polarity. Black electrodes have different polarities. In this embodiment, the via electrode pitch P3 between the via electrodes 15a and the via electrodes 15b having different polarities shown in FIG. 2 is set to be equal to or larger than the repeating pitch P1 of the via electrodes 15a with respect to the internal electrodes 13a. In FIG. 2, P3 is about 1.6 times P1.

  In addition, formation of the 1st laminated body 11 and the 2nd laminated body 12 (step S110-170) can be advanced simultaneously, and it can also be made to form each laminated body sequentially.

  When the first stacked body 11 and the second stacked body 12 are thus formed, both stacked bodies are joined (step S200). When the laminated body is joined, the conductive paste in the filling hole penetrating the laminated body in the first laminated body 11 is applied to the internal electrode 13b through the filled conductive paste on the upper surface of the second laminated body 12 in the drawing. Both laminated bodies are laminated so as to be joined.

  Next, the laminated body thus bonded is pressure-bonded by a high temperature / high pressure press (step S210), and then the front surface side terminal 16 and the back surface side terminal 17 are formed on the front and back surfaces of the capacitor (step S220). The pitch between the terminals of the front surface side terminal 16 and the rear surface side terminal 17 to be formed is generally the repetition pitch of P1 and P2 described above. Is formed in the exposed portion (the portion corresponding to the upper ends of the via electrode 15a and the via electrode 15b described above). Formation of the front surface side terminal 16 and the back surface side terminal 17 can be performed by a technique such as surface printing of a conductive material. In forming such terminals, the size and the pitch between the terminals are determined in consideration of the shrinkage ratio of the conductive paste due to firing described later. Next, a groove is formed in the multilayer body in accordance with the size of the multilayer ceramic capacitor 10 to be used, and the laminated body after the grooving is degreased and fired (step S230). After such firing, the multilayer ceramic capacitor 10 as shown in FIG. 1 is completed by singulation by breaks along the grooves.

  In addition, the manufacturing method of this multilayer capacitor is not limited to the process mentioned above, It can implement using arbitrary appropriate processes. For example, in the process up to step S160 described above, the carrier film peeling in step 140 and the sheet lamination in step 150 can be performed in reverse, or the sheet cutting in step S130 can be performed prior to the formation of the wiring layer in step S120. In the above-described embodiment, Ag is used as the conductive material constituting the via electrodes 15a and 15b. However, the present invention is not limited to this. For example, Pt, Pd, Ag-Pt, Ag- Pd, Cu, Au, Ni, etc. may be used. Which material is used may be determined in consideration of compatibility with the material of the ceramic layer and the like. Moreover, you may make it contain an inorganic material as needed.

A-3. Effect:
As described above, in the multilayer ceramic capacitor 10 of the present embodiment, as shown in FIG. 1, the dielectric is provided with the multi-layer internal electrode 13a with a short inter-electrode distance, and the internal electrode 13a includes the via electrode 15a. Through this voltage application, positive and negative charges are charged, and the function as a multilayer capacitor is realized. Moreover, the via electrode 15a from the surface 10a side of the capacitor is conducted to the via electrode 15b from the back surface 10b side of the capacitor through pitch conversion at the internal electrode 13b while realizing such a capacitor function. More specifically, in the drawing, at least part of the via electrode 15a electrically connected to the black internal electrode 13a (first electrode layer) is electrically connected to the black first conductive electrode layer in the internal electrode 13b. The via electrode 15a, which is electrically connected to the via electrode 15b and is connected to the hatched internal electrode 13a (second electrode layer) in the drawing, is at least partly used for the second energization of the hatched hatch in the internal electrode 13b. The via electrode 15b is electrically connected to the electrode layer.

  This allows the via electrode 15a and the via electrode 15b to function as conductive lines through the front and back of the multilayer ceramic capacitor 10, so that a via electrode, which has been assumed only for current application to the internal electrode layer, can be It can be newly used as a conductive wire that penetrates the front and back. For this reason, according to the multilayer ceramic capacitor 10, as shown in FIG. 1, it is possible to mount electronic devices (IC chip 30, package 50, wiring board 60, etc.) on the front and back of the capacitor. You can plan. In this case, the first repetitive pitch that defines the pitch of the surface side terminals 16 (via electrode 15a pitch) on the front surface 10a is adapted to the terminal pitch of the IC chip 30 or the package 50, or the back surface side terminal 17 (via electrode) on the back surface 10b. 15b pitch) can be adapted to the terminal pitch of the wiring board 60, so that the degree of freedom of device mounting on the front and back of the capacitor can be further increased.

  Further, in this embodiment, in the second multilayer body 12 when the multilayer ceramic capacitor 10 is manufactured, when the conduction between the via electrode 15a and the via electrode 15b is achieved as described above, the pitch P3 between the via electrodes having different polarities is set. The pitch of the via electrodes 15a is not less than the repeat pitch P1, specifically about 1.6 times. For this reason, since the via electrodes having different polarities do not come too close to each other, that is, the short-circuit between the different polarities does not occur, it is possible to suppress deterioration of the function as a capacitor.

  Further, the front surface side terminal 16 and the back surface side terminal 17 which are terminals of the via electrode 15a and the via electrode 15b are formed for each via electrode on the front and back surfaces of the capacitor. For this reason, the lead connection to the via electrode through the terminal and the connection between the mounted products are facilitated. Specifically, the terminal 58 of the package 50 can be easily and reliably connected to the surface side terminal 16 of the multilayer ceramic capacitor 10.

B. Variation:
In the above embodiment, the multilayer ceramic capacitor 10 is interposed between the package 50 and the wiring substrate 60 such as a mother board. However, the multilayer ceramic capacitor 10 may be interposed between other electronic devices. FIG. 5 is an explanatory view showing a modified example of the multilayer ceramic capacitor 10. The multilayer ceramic capacitor 10 shown in FIG. 5 is common to the configuration shown in FIG. 1 and the main part in the embodiment described above, and in FIG. The same numbers or letters as in FIG. 1 are used.

  In the modification shown in FIG. 5, the IC chip 130 and the package 150 are connected via the multilayer ceramic capacitor 110. In this embodiment, the package 150 including wiring including the lead 156 as a power supply line and a ground line is connected to the back surface side terminal 117 corresponding to the via electrode 115b of the multilayer ceramic capacitor 110. Further, the IC chip 130 is directly connected to the surface side terminal 116 corresponding to the via electrode 115 a of the multilayer ceramic capacitor 110 by the pad 132.

  Further, it is possible to adopt a form in which an IC chip, a package, and a wiring board are mounted in advance on the multilayer ceramic capacitors of the above-described embodiments and modifications. As such a form, a capacitor with an IC chip in which an IC chip is connected to the via electrode of the multilayer ceramic capacitor, a terminal having the via electrode of the multilayer ceramic capacitor or a package with a capacitor connected to the terminal, a via electrode of the multilayer ceramic capacitor A wiring board with a capacitor in which a wiring board is connected to a terminal of the IC, a structure in which an IC chip and a package are connected via the above-mentioned multilayer ceramic capacitor, and the like can be considered.

  In addition, the first and second repetitive pitches that define the pitches P1 and P2 of the via electrodes 15a and the via electrodes 15b and the first and second repetitive patterns that define the patterns of the internal electrodes 13a and the internal electrodes 13b are various ways. Can be prescribed. For example, the pitch P2 of the via electrodes 15b can be set to a positive multiple ratio of 1 or more than the pitch P1 of the via electrodes 15a, or a positive odd multiple ratio. Alternatively, the pitch P2 can be set to (1 / n.5) times the pitch P1 (where n is a natural number). Even if such a relationship is taken, it is preferable from the viewpoint of securing the capacitor function that the pitch P3 between via electrodes having different polarities shown in FIG.

  In particular, the pitch of the via electrodes 15b is not limited to a constant interval, and each via electrode 15b may be repeated so as to be scattered when viewed from the back surface of the capacitor. For example, the via electrode pitch is unequal. It may be a minute. Specifically, the interelectrode distance (pitch) from one via electrode 15b to the adjacent via electrode 15b is P0, but the interelectrode distance P1 to the next via electrode 15b is 2.1 times P0. It may be something that spreads out.

  Further, when the multilayer ceramic capacitor 10 is manufactured, the second multilayer body 12 shown in FIG. 2 may be stacked in the order of the upper multilayer portion 12a, the intermediate multilayer portion 12b, and the lower multilayer portion 12c. In this case, first, the upper laminated portion 12 a is overlaid on the first laminated body 11. Prior to this lamination, the upper laminated portion 12a is formed in advance. That is, a sheet is formed using a dielectric material that becomes a dielectric, and a through-hole is formed in the sheet at a position that overlaps at least a part of the through-hole for forming the via electrode 15a in the first stacked body 11, and the through-hole is formed. Is filled with a conductive paste. Then, the upper laminated portion 12a filled with paste is overlaid on the first laminated body 11 so that the filled paste (via electrode 15a) in the first laminated body 11 is bonded to the filled paste of the upper laminated portion 12a.

  In the lamination of the intermediate laminated portion 12b, a sheet is formed using a dielectric material serving as a dielectric, and the internal electrode 13b is formed on the surface of the sheet by a screen printing method or the like. In this sheet, a through hole is formed at a position overlapping with at least a part of the through hole of the upper laminated portion 12a, and electrode layer reaching holes reaching the internal electrode 13b are formed at a pitch that is scattered in the sheet. Fill with conductive paste. Then, the paste-filled intermediate laminated portion 12b is overlaid on the upper laminated portion 12a so that the filled paste in the intermediate laminated portion 12b is joined to the filled paste (via electrode 15a) in the upper laminated portion 12a.

  In the lamination of the lower laminated portion 12c, a sheet is formed using a dielectric material serving as a dielectric, and the internal electrode 13b is formed on the surface of the sheet by a screen printing method or the like. In this sheet, through-holes are formed at positions overlapping at least part of the through-holes / electrode layer arrival holes of the via electrode 15a and the via electrode 15b of the upper laminated portion 12a, and the internal electrodes 13b are arranged at a pitch that is scattered in the sheet. The electrode layer reaching hole is opened, and both holes are filled with a conductive paste. Then, the paste-filled lower laminated portion 12c is overlaid on the intermediate laminated portion 12b so that the filled paste (the via electrode 15a and the via electrode 15b) in the intermediate laminated portion 12b is joined to the filled paste in the lower laminated portion 12c. After that, the multilayer ceramic capacitor 10 can be manufactured by performing the processing after step S210 as described above. The electrode layer reaching holes in the intermediate laminated portion 12b and the lower laminated portion 12c may be through holes that penetrate the sheet.

  In this way, when sequentially laminating the respective laminated portions, the lower laminated portion 12c can be omitted. That is, in FIG. 2, the lower laminated portion 12c may not be provided. Even in this manner, the black via electrode 15a in the drawing of the first stacked body 11 is electrically connected to the via electrode 15b in the upper stacked portion 12a and the intermediate stacked portion 12b after being pitch-converted by the internal electrode 13b.

It is explanatory drawing which shows the example of installation of the multilayer ceramic capacitor 10 which is an Example of this invention in a longitudinal cross section. 3 is an explanatory diagram for explaining an outline of manufacturing the multilayer ceramic capacitor 10. FIG. It is explanatory drawing for demonstrating the procedure of the manufacturing method employ | adopted in the Example. It is explanatory drawing for demonstrating the detailed content of a manufacturing method. 6 is an explanatory view showing a modified example of the multilayer ceramic capacitor 10. FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Multilayer ceramic capacitor 10a ... Front surface 10b ... Back surface 11 ... 1st laminated body 12 ... 2nd laminated body 12a ... Upper laminated part 12b ... Intermediate laminated part 12c ... Lower laminated portion 13a ... Internal electrode 13b ... Internal electrode 14 ... Ceramic layer 15a ... Via electrode 15b ... Via electrode 16 ... Front side terminal 17 ... Back side terminal 30. IC chip 32 ... Pad 50 ... Package 52 ... Upper layer 54 ... Lower layer 56 ... Lead 57 ... Bump 58 ... Terminal 60 ... Wiring board 66 .. Lead 67 ... Terminal 110 ... Multilayer ceramic capacitor 115a ... Via electrode 115b ... Via electrode 116 ... Front side terminal 117 ... Back side terminal 132 ... Pad 150 ... Package 156 ... Lead

Claims (7)

A capacitor in which a plurality of internal electrode layers and dielectric layers are alternately laminated,
The internal electrodes are alternately provided as first electrode layers and second electrode layers facing the electrode layers on the capacitor surface side,
A plurality of first via electrodes formed to conduct commonly from the capacitor surface side to the first electrode layer, and a plurality of first via electrodes formed to conduct commonly from the capacitor surface side to the second electrode layer The second via electrodes are provided at a first repetition pitch,
On the back side of the capacitor, a first energizing electrode layer and a second energizing electrode layer that are laminated via the dielectric layer are provided,
Furthermore,
From the back side of the capacitor, a plurality of first energizing via electrodes that conduct to the first energizing electrode layer and a plurality of second energizing via electrodes that conduct to the second energizing electrode layer are connected to the energizing via. The electrode is repeatedly formed at a second repetition pitch interspersed on the capacitor back surface,
The first via electrode and the first energizing via electrode are at least partially connected through the first energizing electrode layer,
A capacitor in which at least a part of the second via electrode and the second energizing via electrode are conducted through the second energizing electrode layer. The capacitor of claim 1,
The second repeating pitch of the energizing via electrode existing in the formation region of the first energizing electrode layer and the second energizing electrode layer is greater than or equal to the first repeating pitch of the first via electrode and the second via electrode. Capacitor. The capacitor according to claim 1 or claim 2, wherein
A surface-side terminal formed on the capacitor surface for each via electrode so as to be a terminal of the first via electrode and the second via electrode;
A backside terminal formed on the backside of the capacitor for each via electrode so as to be a terminal for each of the first and second energization via electrodes.   A capacitor with a semiconductor element, comprising a semiconductor element connected to the first via electrode and the second via electrode of the capacitor according to claim 1.   5. A substrate-integrated capacitor, wherein a substrate having a wiring including a power supply line and a ground line is connected to each of the first and second energization via electrodes of the capacitor according to claim 1. A method of manufacturing a capacitor in which a plurality of internal electrode layers and dielectric layers are alternately laminated,
In order to form the internal electrode on the capacitor surface side, the internal electrode forming material to be the second electrode layer and the first electrode layer are alternately laminated with the dielectric material to be the dielectric layer interposed therebetween. A step (1) of forming a first laminate;
Forming through holes penetrating through the first electrode layers and the second electrode layers in the first laminated body at a first repetition pitch, and filling each through hole with a conductive paste; (2) and
An electrode layer forming material of the first energizing electrode layer and the second energizing electrode layer is a second laminate in which the dielectric material is sandwiched between the first energizing electrode layer and the first energizing electrode layer. Holes reaching the second energizing electrode layer are provided at a second repetition pitch such that the holes are scattered from the surface of the second laminate, and the holes are filled with a conductive paste. Forming (3);
At least a part of the filled paste between the first electrode layers and the filled paste between the second electrode layers in the first laminate are the first and second energized electrodes in the second laminate. And a step (4) of superimposing the first and second laminated bodies filled with the paste so as to be bonded to a layer. A method of manufacturing a capacitor in which a plurality of internal electrode layers and dielectric layers are alternately laminated,
In order to form the internal electrode on the capacitor surface side, the internal electrode forming material to be the second electrode layer and the first electrode layer are alternately laminated with the dielectric material to be the dielectric layer interposed therebetween. A step (1) of forming a laminate;
Forming a through hole penetrating each of the laminated first electrode layers and the second electrode layers in the laminated body at a first repetition pitch, and filling each through hole with a conductive paste (2) When,
A first sheet using a dielectric material to be the dielectric, wherein the first sheet is provided with a through hole at a position overlapping at least a part of the through hole in the laminated body, and the through hole is filled with a conductive paste. A step (3) of stacking a sheet on the laminate;
A second sheet using a dielectric material to be the dielectric, wherein the second sheet is provided with an electrode layer forming material for the first current-carrying electrode layer on the sheet surface, and at least one of the through holes of the first sheet A sheet in which a conductive paste is filled in through-holes provided at positions overlapping with a portion, and electrode layer arrival holes that are formed at a second repetition pitch and are scattered in the sheet and reach the first current-carrying electrode layer, And a step (4) of stacking a second sheet on the first sheet.

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