JP2005101162A - Semiconductor device and method of manufacturing thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a distorted Si channel MOS transistor which includes a partial SOI structure and does not arrange an insulating layer just under the channel. <P>SOLUTION: The semiconductor device includes a MOS transistor in which a source/drain region and a gate electrode are formed on a silicon substrate via an intermediate layer. The intermediate layer is formed of an SiGe (silicon germanium) layer and an insulating layer which are in contact with the silicon substrate. The SiGe layer and the insulating layer are substantially connected at the surface. The gate electrode is provided on a distorted Si (silicon) layer extended to the surface of the insulating film from the SiGe layer surface, while the source-drain region is formed at least partially in the region overlapping on the insulating film among the distorted Si layer. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention reduces junction leakage current and parasitic capacitance in a MOS transistor using a heterostructure of Si (silicon) and SiGe (silicon-germanium), and further fuses an SOI (silicon-on-insulator) structure and a strained channel structure. The present invention relates to a semiconductor device that avoids a self-heating effect and a floating body effect in a MOS transistor and a manufacturing method thereof.

  In recent years, in miniaturization of MOS transistors, there is an attempt to improve electron mobility and improve characteristics by using a strained Si layer in a channel portion. The strained Si layer refers to a Si layer in which a lattice constant is changed by applying a stress. There are various methods for forming such a strained Si channel. The most homogeneous and high strain can be obtained by epitaxially growing a Si layer on a lattice-relaxed SiGe layer. The strained Si layer lattice-matched on the SiGe layer receives tensile stress in the direction parallel to the interface and compressive stress in the vertical direction. This stress changes the Si band structure, changes the effective mass in the valence band, and increases the mobility in the interface parallel direction (channel direction). The advantage of the strained Si channel is that while the physical properties of the electronic material such as the mobility change, the physical properties of the material basically remain Si, so that the advantages of the Si MOS transistor can be enjoyed as they are. As described above, the strained Si channel MOS transistor can achieve a performance improvement relatively easily by using a lattice-relaxed SiGe substrate while using a normal Si MOS transistor manufacturing process. This is considered promising because there is a possibility that the characteristics of both MOS transistors can be improved.

  However, the strained Si channel MOS transistor basically has the same element structure as that of CMOS. Therefore, CMOS having short channel effect, parasitic capacitance, junction leakage current, etc. is confronted with MOS transistor having a gate length of 100 nm or less. It has the same difficulty as the problem.

A MOS transistor having an SOI structure has been proposed as a device structure capable of overcoming these problems. This structure uses an SOI substrate having a thin Si layer (SOI layer) on the surface and has a stacked structure of SiGe layer / SOI layer / SiO ₂ (silicon oxide) layer, so that the junction capacitance can be greatly reduced. The advantages of this SOI MOS transistor are combined with the high driving ability of strained Si.
However, as an essential problem in this structure, since the potential of the SOI layer is in a floating state, carriers generated by element operation accumulate, causing the substrate potential of the MOS transistor to fluctuate. As a result, the threshold voltage of the element is reduced. The so-called floating body effect that fluctuates is pointed out. In particular, in the n-type MOS transistor, the floating body effect becomes remarkable because the SOI layer as the channel layer exists on the insulating layer.
In the SOI device, the heat generated in the channel portion is generally directly under the channel by the SiO ₂ layer having low thermal conductivity, so the heat radiation to the lower side of the substrate is poor, and it is used only for heating the channel itself. The so-called self-heating effect is a problem. Particularly in the case of an n-type MOS transistor, the structure as disclosed in JP-A-9-219524 becomes prominent. A general SOI device is not suitable for a high-power element such as a high-frequency MOS transistor because of the self-heating effect.
Japanese Patent Laid-Open No. 9-219524 T.A. Tetsuka et al., VLSI sym. 2002

As described above, the strained Si channel MOS transistor having the SOI structure has a problem such as a floating body effect and a self-heating effect because the SiO ₂ layer is interposed as an insulating layer.

  An object of the present invention is to provide a strained Si channel MOS transistor having a partially SOI structure and having no insulating layer disposed immediately below the channel portion.

  In order to solve the above-described problems, the present invention is characterized by the following measures.

As a first means,
A semiconductor device having a MOS transistor in which a source / drain region and a gate electrode are formed on a silicon substrate via an intermediate layer, the intermediate layer comprising a SiGe (silicon germanium) layer in contact with the silicon substrate and an insulating film The SiGe layer and the insulating film are configured to be substantially continuous on the surface, and the gate electrode is provided on a strained Si (silicon) layer formed to extend from the SiGe layer surface to the insulating film surface, The source / drain region is a semiconductor device in which at least a part is formed in a region of the strained Si layer that overlaps with the insulating film.

According to the first means,
Since the strained Si layer serving as the channel extends from the surface of the SiGe layer to the surface of the insulating film, the junction leakage current from the impurity diffusion layer, which is a problem of the MOS transistor, is remarkably reduced. In addition, it is possible to reduce the junction capacitance between the source and drain regions, which is a parasitic capacitance.
Further, the SiGe layer is in contact with the channel and is also in contact with the silicon substrate, and the structure is such that no insulating layer is interposed between the channel and the silicon substrate. Accordingly, in the present invention, the heat generated in the channel is efficiently radiated to the substrate by the structure not passing through the insulating film such as SiO ₂ having low thermal conductivity, thereby preventing the decrease in electron mobility due to temperature rise, The semiconductor device is suitable for high-speed driving such as a MOS transistor.
As a second means,
The strained Si layer is a semiconductor device as a first means in which the strained Si layer exists in the transistor width direction only on the surface of the SiGe layer and does not have a region overlapping with the insulating film.

  According to the second means, there is provided a semiconductor device characterized in that the SiGe layer in contact with the strained Si layer in the first means is disposed at least in the entire channel width direction in the channel portion. According to the present invention, a sufficient active region can be obtained over the entire region in the transistor width direction.

As a third means,
A first etching step in which the SiGe layer is etched to a predetermined depth so that at least a portion to be a source / drain region in the transistor gate length direction is overhanged; and an insulating film is formed in the groove portion obtained in the first etching step And a step of embedding the semiconductor device.

According to the third means,
This is a first etching process in which the SiGe layer is etched so that at least the portions to be the source / drain regions in the transistor gate length direction overhang. Thereby, the semiconductor device by the first means can be manufactured.
As a fourth means,
A first etching step of etching the SiGe layer so that a portion to be a source / drain region in the transistor gate length direction is overhanged;
A second etching step for etching the SiGe layer in the transistor width direction;
A step of embedding an insulating film in the groove portion obtained by the first and second etchings;
The manufacturing method of the semiconductor device containing this.
According to the fourth means, first, as in the first means, the first etching for etching the SiGe layer so as to overhang only the portions that become the source / drain regions in the transistor gate length direction is performed. Next, in order to determine the transistor width direction, second etching for etching the SiGe layer is performed. In this second etching, the overhang portion formed by the first etching is protected so as not to be etched, and a trench is formed only in the transistor width direction, and etching is performed under the condition of anisotropic etching. The second etching is performed so that the entire region becomes the active region. An insulating film is embedded in the trenches obtained in the first and second etching steps to form a characteristic structure of the semiconductor device. Thereby, the semiconductor device according to the second means can be manufactured.

  As described above, according to the present invention, the insulating film is disposed so as to be in contact with all or part of the bottom surface of the source / drain region in the transistor width direction, and the insulating layer is not disposed immediately below the channel. By having a structure in contact with the substrate, only the source / drain region has a SOI structure.

According to the present invention, the impurity diffusion region in the source / drain portion is only a strained Si layer from the embodiment according to the present invention, which is very thin as compared with the prior art, and the insulating layer is in contact thereunder. Thus, the parasitic capacitance can be removed at the bottom portion of the strained Si. At the same time, the leakage current can be almost eliminated. Thereby, a MOSFET capable of higher frequency operation can be obtained.
Furthermore, in the conventional SOI structure, the heat dissipation of the heat generated in the channel is impaired due to the presence of the insulating film under the SiGe layer. The structure in which the SiGe layer is in direct contact with the Si substrate as in the present invention. As a result, the heat dissipation of the generated heat to the substrate is increased, and the electron mobility that has been saturated due to the self-heating effect and the floating body effect can be further improved, and the saturation current is about 10%. It becomes possible to improve. This effect shows a more remarkable improvement effect particularly when applied to an n-type MOSFET as disclosed in JP-A-9-219524.
Further, since the MOS transistor of the present invention can be applied to both n-type and p-type, the manufacturing process is simplified and the manufacturing cost can be reduced.

In the embodiments of the present invention, a strained Si channel MOS transistor having a partial SOI structure and having no insulating layer disposed immediately below the channel portion is provided to improve the self-heating effect and the floating body effect. I will explain it as a rule.

  A method of manufacturing a MOS transistor according to the present invention will be described in detail with reference to the drawings by taking an n-type MOS transistor as an example, but the present invention can also be applied to a p-type MOS transistor. Also add explanation.

  See FIG.

FIG. 1 is a cross-sectional view of a semiconductor device according to the first embodiment of the present invention after forming a SiGe layer and a strained Si layer. In FIG. 1, 1 is a silicon substrate, 2 is a SiGe layer, and 3 is a strained Si layer.
First, as shown in FIG. 1, LPCVD (low pressure chemical vapor deposition) or MBE is performed on a silicon substrate (a p-type substrate for an n-type MOS transistor and an n-type substrate for a p-type MOS transistor) 1. The SiGe layer 2 is epitaxially grown by vapor phase growth method such as (molecular beam epitaxial growth) method. In the case of the CVD method, SiH ₄ and GeH ₄ are used as the reaction gas, and for example, Si _0.7 Ge _0.3 having a high electron mobility is formed with a thickness of 2 μm. Since Ge (germanium) has a larger lattice constant than Si (silicon), the lattice constant increases as the Ge content increases. Subsequently, Si having a thickness of 20 nm is grown using SiH ₄ as a reaction gas. As a result, a strained Si layer 3 is formed on the lattice-relaxed SiGe layer 2 that is subjected to tensile stress in the direction parallel to the interface and compressive stress in the vertical direction. With this stress, the band structure of Si changes, the degeneration of the band in both the conduction band and the valence band is solved, and the effective mass also changes in the valence band, thereby increasing the mobility in the channel direction.
In the conventional SOI structure, after a SiO ₂ film is formed on a silicon substrate, the SiGe layer and the Si layer are stacked in this order, but in the present invention, a structure in which the SiGe layer is directly stacked on the silicon substrate is employed. The heat generated in the channel portion is efficiently radiated to the substrate as compared with the case of passing through the SiO ₂ film having low thermal conductivity, and the self-heating effect is reduced.

  See FIGS.

Next, the first etching process in the transistor gate length direction will be described with reference to FIGS.
2A is a top view of a MOS transistor according to the first embodiment of the present invention, and FIG. 2B is a cross-sectional view in the transistor gate length direction (AA ′ direction in FIG. 2A). . In FIG. 2, 1 is a silicon substrate, 2 is a SiGe layer, 3 is a strained Si layer, 4 is a nitride film, 5 is a photoresist, 6 is a transistor active region, and AA ′ is a transistor gate length direction.
The first etching step is performed by anisotropic etching and isotropic etching. First, a nitride film 4 (for example, a silicon nitride film) having a thickness of 0.3 μm is deposited on the strained Si layer 3 by LPCVD using SiH ₂ Cl ₂ and NH ₃ as reaction gases.
Next, a photoresist 5 is applied by spin coating to cover the portion that becomes the active region 6 of the MOS transistor, and the photoresist 5 is exposed and developed so that only the element isolation region on the source / drain end side in the transistor gate length direction is opened. To do. At this time, as shown in the drawing, the transistor width direction (BB ′ direction in FIG. 2A) is covered with the photoresist 5. That is, as will be described later, the transistor width direction can also be etched at the same time (described later), but here, a case will be described in which etching is performed in a separate process in order to further secure the transistor active region 6. Here, the transistor width direction is a direction perpendicular to the transistor gate length direction.

  FIG. 3 is a cross-sectional view of the semiconductor device according to the first embodiment of the present invention after anisotropic etching in the transistor gate length direction (AA ′ direction in FIG. 2A). In FIG. 3, 1 is a silicon substrate, 2 is a SiGe layer, 3 is a strained Si layer, 4 is a nitride film, and 5 is a photoresist.

As shown in FIG. 3, the photoresist 5 is used as a mask and the nitride film 4 is used as a reaction gas to remove it by anisotropic etching using a mixed gas of SF ₆ (sulfur hexafluoride) and Cl ₂ (chlorine). Then, the strained Si layer 3 and the SiGe layer 2 are continuously anisotropically etched to a depth of 0.2 μm, for example.

4 is a cross-sectional view of the semiconductor device according to the first embodiment of the present invention after isotropic etching in the transistor gate length direction (AA ′ direction in FIG. 2A). In FIG. 4, 1 is a silicon substrate, 2 is a SiGe layer, 3 is a strained Si layer, 4 is a nitride film, 5 is a photoresist, and 7 is an overhang.
In FIG. 4, an etching solution in which the selective ratio between the strained Si layer 3 and the SiGe layer 2 can be subsequently obtained (for example, HF (50%): H ₂ O ₂ : CH ₃ COOH = 1: 16: 24). The SiGe layer 2 is wet-etched so as to overhang 7 by, for example, about 0.1 to 0.2 μm with a liquid at a selection ratio of about 160. At this time, only the SiGe layer 2 is selectively etched, and the strained Si layer 3 is not etched and remains as a source / drain region, and an overhang 7 is formed on the bottom surface of the strained Si layer 3. Here, the wet etching method is used to form the overhang 7, but an RIE (Reactive Ion Etching) method using a chlorine-based gas (for example, Cl ₂ gas) may be used. At this time, etching is performed under conditions that are isotropic etching so that the overhang 7 can be formed. Finally, the photoresist 5 is removed, and the etching process in the transistor gate length direction is completed.

  See FIG.

  5A is a top view of the MOS transistor according to the first embodiment of the present invention, FIG. 5B is a cross-sectional view in the transistor gate length direction (direction AA ′ in FIG. 5A), FIG. FIG. 5C is a cross-sectional view in the transistor width direction (BB ′ direction in FIG. 5A). In FIG. 5, 1 is a silicon substrate, 2 is a SiGe layer, 3 is a strained Si layer, 4 is a nitride film, 6 is a transistor active region, 7 is an overhang, 8 is a photoresist, and AA ′ is a transistor gate length direction. BB ′ is the transistor width direction.

  Next, a second etching step in the width direction of the transistor will be described with reference to FIG. First, a photoresist 8 is applied by spin coating, and only an element isolation region in the transistor width direction is opened by exposure and development. At this time, the overhang 7 is protected by a photoresist so that it is not exposed to plasma during the next etching process.

Using the photoresist pattern 8 as a mask, the nitride film 4 is first removed by anisotropic etching, and then the strained Si layer 3 and SiGe layer 2 are successively etched to a depth of, for example, 0.4 μm. As the reaction gas, for example, a mixed gas of SF ₆ (sulfur hexafluoride) and Cl ₂ is used. At this time, the groove formed in the previous step is not etched further deeply with the photoresist 8 as a mask as shown in FIG. 5B. The etching in the transistor width direction in this step is anisotropic etching different from the etching in the transistor gate direction, and isotropic etching that causes overhang is not performed. Therefore, the SiGe layer 2 in contact with the strained Si layer 3 is at least Since the transistors are arranged in the entire region in the width direction of the transistor, a structure in which the activation region 6 can be sufficiently secured can be obtained. Finally, the photoresist 8 is removed, and the second etching process in the transistor width direction is completed.

  In this step, anisotropic etching is performed so as not to form the overhang 7 in the transistor width direction. However, when a predetermined specification of the semiconductor device can be satisfied without securing a sufficient activation region, it will be described with reference to FIG. Etching in the transistor width direction may be performed at the same time as etching in the transistor gate length direction, which is the previous process, by deleting the above process. As a result, the number of manufacturing steps can be reduced and the cost can be reduced.

  See FIG.

6A is a cross-sectional view in the transistor gate length direction (AA ′ direction in FIG. 5A), and FIG. 6B is a cross-sectional view in the transistor width direction (BB ′ direction in FIG. 5A). Indicates. In FIG. 6, 1 is a silicon substrate, 2 is a SiGe layer, 3 is a strained Si layer, 4 is a nitride film, and 9 is a SiO ₂ film.
A process of filling an overhang portion with an insulating film in a trench formed in the previous process will be described. As the insulating film, a silicon oxide film or a silicon nitride film is used. Here, the case where the SiO ₂ film 9 is used will be described. SiO ₂ film 9 by the LPCVD method, using a mixed gas of SiH ₄ and N ₂ O as reaction gases for forming the SiO ₂ film 9 on the entire surface. At this time, the overhang is completely filled with the SiO ₂ film 9. Thereafter, planarization is performed by a CMP (Chemical Mechanical Polishing) method. At this time, the nitride film 4 (for example, a silicon nitride film) serves as a polishing stop layer, and polishing with good flatness is possible. As a result, a structure in which the SiO ₂ film 9 is disposed instead of the impurity diffusion region which has been directly under the source / drain region in the past is obtained. That is, the junction leakage current from the diffusion region under the drain / source, which has been a problem in the prior art, can be remarkably reduced by the SOI structure formed only in the source / drain region according to the present invention.

  See FIG.

FIG. 7 is a sectional view in the transistor gate length direction according to the first embodiment of the present invention. In FIG. 7, 1 is a silicon substrate, 2 is a SiGe layer, 3 is a strained Si layer, 9 is a SiO ₂ film, 10 is a gate oxide film, and 11 is a gate electrode.
A method for forming a gate electrode will be described below with reference to FIG. After removal of the nitride film 4, a strained Si layer 3 surface in an oxygen atmosphere, for example, by thermal oxidation at a temperature of 800 ° C., for example by forming a SiO ₂ film having a thickness of 3nm gate oxide film 10 obtain. A polycrystalline Si layer having a thickness of 100 nm is deposited by LPCVD using SiH ₄ as a reaction gas, and a photoresist pattern to be a gate electrode is formed by a lithography process, and then anisotropic etching is performed using the photoresist pattern as a mask. Thus, the polycrystalline Si layer and the oxide film are etched to form, for example, a gate oxide film and a gate electrode 11 having a width of 80 nm.

FIG. 8 is a cross-sectional view in the transistor gate length direction according to the first embodiment of the present invention. In FIG. 8, 1 is a silicon substrate, 2 is a SiGe layer, 3 is a strained Si layer, 9 is a SiO ₂ film, 10 is a gate oxide film, 11 is a gate electrode, 12 is an As ion, and 13 is an n-type extension region. .
A method for forming a low concentration impurity region will be described with reference to FIG. Using the gate electrode 11 formed as a mask, for example, arsenic (As) ions or phosphorus (P) ions 12 are selectively ion-implanted into the n-type MOS transistor formation region, and n-type extension is applied to the source / drain. Region 13 is formed. In the case of a p-type MOS transistor, boron (B) or boron fluoride (BF ₂ ) is selectively ion-implanted as an ion species to form a p-type extension region at the source / drain. Next, rapid activation heat treatment (RTA: Rapid Thermal Annealing) is performed in a nitrogen atmosphere at 1000 ° C. for 10 seconds to activate the extension region 13. This region becomes a low concentration impurity region in an LDD (Lightly-doped drain) structure.

  See FIG.

FIG. 9 is a sectional view in the transistor gate length direction according to the first embodiment of the present invention. In FIG. 9, 1 is a silicon substrate, 2 is a SiGe layer, 9 is a SiO ₂ film, 11 is a gate electrode, 14 is a sidewall, 15 is an As ion, and 16 is an n ⁺ type source / drain region.
A method for manufacturing the n ⁺ -type source / drain region 16 to be a high concentration impurity region will be described with reference to this drawing. First, SiO ₂ is deposited on the entire surface by LPCVD using a mixed gas of SiH ₄ and N ₂ O as a reaction gas. Next, the entire surface of the SiO ₂ film is etched by anisotropic etching using a reactive gas containing a fluorine-based gas, for example, CHF ₃ or C ₂ F ₆ . As a result, sidewalls 14 are formed on the sidewalls of the gate electrode 11. By using this sidewall 14 as a mask, for example, arsenic (As) ions or phosphorus (P) ions 15 are selectively ion-implanted and, for example, RTA treatment is performed at 1000 ° C. for 10 seconds in a nitrogen atmosphere. N ⁺ type source / drain regions 16 which are high concentration impurity regions are formed. In order to obtain the p ⁺ type source / drain regions, for example, B (boron) ions may be implanted, and the p ⁺ type source / drain regions may be formed by performing a similar heat treatment at a predetermined temperature.

  See FIG.

FIG. 10 is a sectional view in the transistor gate length direction according to the first embodiment of the present invention. In FIG. 10, 1 is a silicon substrate, 2 is a SiGe layer, 9 is a SiO ₂ film, 11 is a gate electrode, 14 is a sidewall, and 17 is a CoSi ₂ layer.
The salicide technology will be described with reference to this figure. In the present invention, since the SiO ₂ film 9 is disposed immediately below the strained Si layer 3, the strained Si layer 3 in the source / drain region is a thin film, and the sheet resistance is increased. Therefore, in particular, the plug 18 (see FIG. 11). Therefore, it is necessary to reduce the resistance of the strained Si layer 3 by salicide. First, a cobalt (Co) layer is deposited on the entire surface by a sputtering method, for example, with a thickness of 10 nm. Thereafter, an RTA treatment is performed in a nitrogen atmosphere at a temperature of, for example, 550 ° C. for 30 seconds, so that the Co layer, the strained Si layer 3 in the n ⁺ -type source / drain region, and the polycrystal on the upper surface portion of the gate electrode 11 are formed. The CoSi ₂ layer 17 is formed by reacting with the Si layer. At this time, since the insulating film on the SiO ₂ film 9 and the side wall 14 are not silicided, the unreacted Co layer portion is selected by performing etching for 20 minutes with a mixed solution of ammonia peroxide water and sulfuric acid hydrogen peroxide solution. Etch away.

  See FIG.

FIG. 11 is a sectional view in the transistor gate length direction according to the first embodiment of the present invention. In FIG. 11, 1 is a silicon substrate, 2 is a SiGe layer, 9 is a SiO ₂ film, 17 is a CoSi ₂ layer, 18 is a plug, and 19 is an interlayer insulating film.
First, an interlayer insulating film 19 such as a SiO ₂ film is formed on the entire surface by LPCVD using a mixed gas of SiH ₄ and N ₂ O as a reaction gas, and then the source / drain of each MOS transistor is formed on the interlayer insulating layer 19. A contact hole for the region is opened by anisotropic etching using a fluorine-based gas such as CHF ₃ or C ₂ F ₆ . This contact hole is required to have a high aspect ratio as the miniaturization progresses, and the metal wiring coverage at the opening becomes stricter. For example, WF ₆ and SiH ₄ are used as reaction gases to form a film by the vapor phase growth method. Thereafter, a flattened plug 18 embedded in the opening by CMP can be formed, and the MOS transistor according to the first embodiment of the present invention is completed.

As a method for forming the plug, there is a method of forming by a damascene process using Cu. This is a method of forming a barrier metal and a seed layer after forming the contact hole, embedding Cu by a plating method, and further flattening by CMP. This is advantageous in terms of the depth of focus during exposure.
(Appendix 1) A semiconductor device having an n-type MOS transistor in which a source / drain region and a gate electrode are formed on a silicon substrate via an intermediate layer,
The intermediate layer includes a SiGe layer in contact with the silicon substrate and an insulating film, and is configured such that the SiGe layer and the insulating film are substantially continuous on the surface, and the gate electrode is formed from the surface of the SiGe layer. Provided on the strained Si layer that extends to the surface of the insulating film,
The source / drain region is an n-type MOS transistor in which at least a part is formed in a region of the strained Si layer overlapping the insulating film.
(Supplementary note 2) The n-type MOSFET according to supplementary note 1, wherein the strained Si layer is in the transistor width direction and exists only on the surface of the SiGe layer, and does not overlap with the insulating film.
(Supplementary Note 3) a first etching step of etching the SiGe layer to a predetermined depth so that at least a portion to be a source / drain region in the transistor gate length direction is overhanged;
A step of embedding an insulating film in the groove portion obtained in the first etching step;
A method for manufacturing an n-type MOSFET.
(Supplementary note 4) a first etching step of etching the SiGe layer to a predetermined depth so that the strained Si layer to be a source / drain region in the transistor gate length direction overhangs;
A second etching step of anisotropically etching the SiGe layer in the transistor width direction by a predetermined depth;
A step of embedding an insulating film in the groove portion obtained in the first and second etching steps;
A method for manufacturing an n-type MOSFET.

Sectional view of the semiconductor device according to the first embodiment of the present invention after forming the SiGe layer and the strained Si layer Semiconductor device (1) according to the first embodiment of the present invention for explaining a method for forming a transistor gate length direction A semiconductor device according to the first embodiment of the present invention for explaining a method for forming a transistor gate length direction (2) Semiconductor device according to the first embodiment of the present invention for explaining a transistor gate length direction forming method (3) Semiconductor device according to first embodiment of the present invention for explaining transistor width direction forming method Sectional view of the semiconductor device according to the first embodiment of the present invention for explaining a method of embedding an insulating film in the depression Sectional view of a semiconductor device according to the first embodiment of the present invention, illustrating a method of forming a gate electrode Sectional view of a semiconductor device according to the first embodiment of the present invention for explaining a method of forming a low concentration impurity region Sectional view of a semiconductor device according to the first embodiment of the present invention for explaining a method for forming a high concentration impurity region Cross-sectional view of a semiconductor device according to the first embodiment of the present invention for explaining a silicide formation method Sectional view of the semiconductor device according to the first embodiment of the present invention after the formation of the plug and the interlayer insulating layer

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 SiGe layer 3 Strained Si layer 4 Nitride film 5 Photoresist 6 Transistor active region 7 Overhang 8 Photoresist 9 SiO ₂ film 10 Gate oxide film 11 Gate electrode 12 As ion 13 n-type extension region 14 Side wall 15 As ion 16 n ⁺ type source / drain region 17 CoSi ₂
18 Plug 19 Interlayer insulation film AA ′ Transistor gate length direction BB ′ Transistor width direction

Claims (4)

A semiconductor device having a MOS transistor in which a source / drain region and a gate electrode are formed on a silicon substrate via an intermediate layer,
The intermediate layer includes a SiGe (silicon germanium) layer in contact with the silicon substrate and an insulating film, the SiGe layer and the insulating film are configured to be substantially continuous on the surface, and the gate electrode includes the gate electrode, Provided on a strained Si (silicon) layer formed to extend from the SiGe layer surface to the insulating film surface,
The source / drain region is a semiconductor device in which at least a part is formed in a region of the strained Si layer overlapping the insulating film. The semiconductor device according to claim 1, wherein the strained Si layer is in the transistor width direction and exists only on the surface of the SiGe layer, and there is no region overlapping with the insulating film. A first etching step of etching the SiGe layer to a predetermined depth so that at least a portion to be a source / drain region in the transistor gate length direction overhangs;
A step of embedding an insulating film in the groove portion obtained in the first etching step;
A method of manufacturing a semiconductor device including: A first etching step of etching the SiGe layer to a predetermined depth so that the strained Si layer serving as a source / drain region in the transistor gate length direction overhangs;
A second etching step of anisotropically etching the SiGe layer in the transistor width direction by a predetermined depth;
A step of embedding an insulating film in the groove portion obtained in the first and second etching steps;
A method of manufacturing a semiconductor device including:

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