JP2005097736A - 銅を覆う障壁物質を形成するための半導体処理方法及び組成物 - Google Patents

銅を覆う障壁物質を形成するための半導体処理方法及び組成物 Download PDF

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JP2005097736A
JP2005097736A JP2004242474A JP2004242474A JP2005097736A JP 2005097736 A JP2005097736 A JP 2005097736A JP 2004242474 A JP2004242474 A JP 2004242474A JP 2004242474 A JP2004242474 A JP 2004242474A JP 2005097736 A JP2005097736 A JP 2005097736A
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Prior art keywords
solution
compound
cobalt
composition
chelating agent
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JP2004242474A
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Japanese (ja)
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JP2005097736A5 (https=
Inventor
Varughese Mathew
マシュー ヴァルギーズ
Sam S Garcia
エス． ガルシア サム
Christopher M Prindle
エム． プリンドゥル クリストファー
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NXP USA Inc
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Freescale Semiconductor Inc
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Publication of JP2005097736A publication Critical patent/JP2005097736A/ja
Publication of JP2005097736A5 publication Critical patent/JP2005097736A5/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H10W20/037—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics the barrier, adhesion or liner layers being on top of a main fill metal
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/46—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a liquid
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/425—Barrier, adhesion or liner layers

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  • Chemically Coating (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
JP2004242474A 2003-08-27 2004-08-23 銅を覆う障壁物質を形成するための半導体処理方法及び組成物 Pending JP2005097736A (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/650,002 US6924232B2 (en) 2003-08-27 2003-08-27 Semiconductor process and composition for forming a barrier material overlying copper

Publications (2)

Publication Number Publication Date
JP2005097736A true JP2005097736A (ja) 2005-04-14
JP2005097736A5 JP2005097736A5 (https=) 2007-10-04

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JP2004242474A Pending JP2005097736A (ja) 2003-08-27 2004-08-23 銅を覆う障壁物質を形成するための半導体処理方法及び組成物

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Country Link
US (1) US6924232B2 (https=)
JP (1) JP2005097736A (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022153914A1 (ja) * 2021-01-18 2022-07-21 東京エレクトロン株式会社 めっき処理方法およびめっき処理装置

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US7205233B2 (en) * 2003-11-07 2007-04-17 Applied Materials, Inc. Method for forming CoWRe alloys by electroless deposition
US7268074B2 (en) * 2004-06-14 2007-09-11 Enthone, Inc. Capping of metal interconnects in integrated circuit electronic devices
JP4503401B2 (ja) * 2004-09-08 2010-07-14 株式会社荏原製作所 金属膜の成膜方法及び配線の形成方法
US7176133B2 (en) * 2004-11-22 2007-02-13 Freescale Semiconductor, Inc. Controlled electroless plating
US20080207005A1 (en) * 2005-02-15 2008-08-28 Freescale Semiconductor, Inc. Wafer Cleaning After Via-Etching
US20060280860A1 (en) * 2005-06-09 2006-12-14 Enthone Inc. Cobalt electroless plating in microelectronic devices
US20070049008A1 (en) * 2005-08-26 2007-03-01 Martin Gerald A Method for forming a capping layer on a semiconductor device
ATE543211T1 (de) * 2005-09-01 2012-02-15 Freescale Semiconductor Inc Kappschichtbildung auf einem doppel-damascene- verbindungselement
US7410899B2 (en) * 2005-09-20 2008-08-12 Enthone, Inc. Defectivity and process control of electroless deposition in microelectronics applications
WO2007087831A1 (en) * 2006-02-03 2007-08-09 Freescale Semiconductor, Inc. 'universal' barrier cmp slurry for use with low dielectric constant interlayer dielectrics
US20070184652A1 (en) * 2006-02-07 2007-08-09 Texas Instruments, Incorporated Method for preparing a metal feature surface prior to electroless metal deposition
US20070181653A1 (en) * 2006-02-08 2007-08-09 Michaelson Lynne M Magnetic alignment of integrated circuits to each other
US7803719B2 (en) * 2006-02-24 2010-09-28 Freescale Semiconductor, Inc. Semiconductor device including a coupled dielectric layer and metal layer, method of fabrication thereof, and passivating coupling material comprising multiple organic components for use in a semiconductor device
US20090301867A1 (en) * 2006-02-24 2009-12-10 Citibank N.A. Integrated system for semiconductor substrate processing using liquid phase metal deposition
US7378339B2 (en) * 2006-03-30 2008-05-27 Freescale Semiconductor, Inc. Barrier for use in 3-D integration of circuits
US7410544B2 (en) * 2006-04-21 2008-08-12 Freescale Semiconductor, Inc. Method for cleaning electroless process tank
US7772128B2 (en) * 2006-06-09 2010-08-10 Lam Research Corporation Semiconductor system with surface modification
US7572723B2 (en) * 2006-10-25 2009-08-11 Freescale Semiconductor, Inc. Micropad for bonding and a method therefor
US20080254205A1 (en) * 2007-04-13 2008-10-16 Enthone Inc. Self-initiated alkaline metal ion free electroless deposition composition for thin co-based and ni-based alloys
US7807572B2 (en) * 2008-01-04 2010-10-05 Freescale Semiconductor, Inc. Micropad formation for a semiconductor
JP2011510177A (ja) * 2008-01-24 2011-03-31 ビーエーエスエフ ソシエタス・ヨーロピア バリア層の無電解析出
US9551074B2 (en) * 2014-06-05 2017-01-24 Lam Research Corporation Electroless plating solution with at least two borane containing reducing agents
US10325876B2 (en) 2014-06-25 2019-06-18 Nxp Usa, Inc. Surface finish for wirebonding
US9786634B2 (en) * 2015-07-17 2017-10-10 National Taiwan University Interconnection structures and methods for making the same

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US5755859A (en) * 1995-08-24 1998-05-26 International Business Machines Corporation Cobalt-tin alloys and their applications for devices, chip interconnections and packaging
US5695810A (en) 1996-11-20 1997-12-09 Cornell Research Foundation, Inc. Use of cobalt tungsten phosphide as a barrier material for copper metallization
US6551856B1 (en) * 2000-08-11 2003-04-22 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming copper pad redistribution and device formed
US6605874B2 (en) 2001-12-19 2003-08-12 Intel Corporation Method of making semiconductor device using an interconnect
US6645567B2 (en) 2001-12-19 2003-11-11 Intel Corporation Electroless plating bath composition and method of using
US6528409B1 (en) 2002-04-29 2003-03-04 Advanced Micro Devices, Inc. Interconnect structure formed in porous dielectric material with minimized degradation and electromigration
US6797312B2 (en) * 2003-01-21 2004-09-28 Mattson Technology, Inc. Electroless plating solution and process

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022153914A1 (ja) * 2021-01-18 2022-07-21 東京エレクトロン株式会社 めっき処理方法およびめっき処理装置
JP7614232B2 (ja) 2021-01-18 2025-01-15 東京エレクトロン株式会社 めっき処理方法およびめっき処理装置

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US6924232B2 (en) 2005-08-02
US20050048773A1 (en) 2005-03-03

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