JP2005094427A - Semiconductor integrated circuit for communication - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent EVM and a transmission spectrum from being deteriorated by a change in the KV characteristics of an oscillation circuit for transmission following a temperature change, when incorporating the oscillation circuit for transmission into a semiconductor chip, and to prevent the decrease of communication quality and the increase of power consumption caused by a change in the output amplitude of the oscillation circuit for transmission following temperature variations. <P>SOLUTION: In a semiconductor integrated circuit (RF-IC) for communication having a phase control loop, a temperature compensation circuit (241) is provided. The temperature compensation circuit (241) compensates deviation in the KV characteristics (control voltage-oscillation frequency characteristics) of the oscillation circuit for transmission caused by the temperature change by changing the current (Icp) of a charge pump. Additionally, the oscillation circuit for transmission comprises a voltage controlled oscillator and an amplifier circuit for amplifying the output of the oscillator. The supply voltage of the amplifier circuit is changed according to temperature and a frequency so that the amplitude of an output signal in the amplifier circuit exists within a specified range. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a technique that is effective when applied to a semiconductor chip having a voltage controlled oscillation circuit (VCO) capable of switching an oscillation frequency, such as a mobile phone capable of transmitting and receiving signals of a plurality of bands. The present invention relates to a technique that is effectively used for a control loop of a transmission VCO in a high-frequency semiconductor integrated circuit that is used in a wireless communication apparatus to modulate or up-convert a transmission signal.

  One of the methods of wireless communication devices (mobile communication devices) such as mobile phones is a method called GSM (Global System for Mobile Communication). In this GSM system, a phase modulation system called GMSK (Gaussian Minimum Shift Keying) that shifts the phase of a carrier wave according to transmission data is used.

  By the way, in recent cellular phones such as the GSM system, in addition to the GMSK modulation mode, EDGE (Enhanced Data Rates for) having a 3π / 8 rotating 8-PSK (Phase Shift Keying) modulation mode for modulating the phase component and amplitude component of the carrier wave. A system called GMS Evolution) is being put into practical use. In contrast to GMSK modulation in which 1-bit information is transmitted per symbol, in 3π / 8 rotating 8-PSK (hereinafter referred to as 8-PSK) modulation, 3-bit information can be transmitted per symbol. Therefore, EDGE mode is changed to GMSK mode. Communication at a higher transmission rate (384 kbps) is possible.

  As a method of realizing a modulation method that gives information to the phase component and amplitude component of the transmission signal, the signal to be transmitted is separated into the phase component and the amplitude component, and then the feedback is controlled by the phase control loop and the amplitude control loop, respectively. After that, a method called a polar loop that is synthesized and output by an amplifier has been conventionally known (for example, ARTECH HOUSE, INC. Published in 1979 by “High Linearity RF Amplifier Design” by Kenington, Peter B. Page 162).

By the way, in recent years, in a wireless communication system, an effort has been made to incorporate as many circuits as possible into one or several semiconductor integrated circuits in order to reduce the number of components and reduce the size and cost of the system. One of them is an attempt to incorporate a transmission oscillator in a semiconductor integrated circuit (hereinafter referred to as a high frequency IC) having a modulation / demodulation function. For a high frequency IC constituting a GSM communication system, the transmission oscillator is turned on. A chip has been developed and proposed by the present applicant (Patent Document 1).
Japanese Patent Application No. 2003-048631 Japanese Patent Application No. 2001-119442

  The present inventors have studied a technique for incorporating a transmission oscillator in a high-frequency IC constituting an EDGE communication system. As a result, it became clear that there are the following problems. The polar loop method in the EDGE system examined by the present inventors is that the phase control loop detects the output of the transmission oscillator or the output of a high frequency power amplifier circuit (hereinafter referred to as a power amplifier) and compares it with a reference signal. This is fed back to the phase comparison circuit, and the amplitude control loop detects the output of the power amplifier and feeds it back to the amplitude comparison circuit for comparison with the reference signal. Such a polar loop system is disclosed in a patent application (Japanese Patent Application No. 2003-54042) proposed by the present applicant.

  By the way, conventional mobile phones include dual-band mobile phones that can handle signals in two frequency bands such as GSM of 880 to 915 MHz band and DCS (Digital Cellular System) of 1710 to 1785 MHz band. In addition, in such a dual-band mobile phone, two transmission oscillators (hereinafter referred to as transmission VCOs) corresponding to the respective frequency bands are provided, and the two systems can be handled by switching the transmission VCO. There is something that can be done.

  However, in recent years, in addition to GSM and DCS, there is a demand for a triple-band mobile phone that can handle, for example, a 1850 to 1910 MHz band PCS (Personal Communication System) signal. In addition, it is expected that mobile phones that are compatible with more systems will be required in the future. A transmission VCO used in a mobile phone that can handle such a plurality of systems needs to have a wide oscillation band (frequency range in which oscillation is possible).

  On the other hand, a major factor that determines the performance of a transmission VCO built in a semiconductor chip is the Q value of passive elements such as inductors. The Q value of a passive element is lower in an element formed on a semiconductor chip than in an element formed of discrete components in the current semiconductor manufacturing technology. Therefore, there are some which use an external element as an inductor. However, this does not sufficiently reduce the number of parts. Therefore, it is important to make it on-chip including the inductor.

  However, the oscillation band of the on-chip VCO has a disadvantage that it becomes narrower than the oscillation band of the oscillation module which is a discrete component because the Q value of the passive element is low. In order to solve this problem, the prior invention (Japanese Patent Application No. 2003-48631) has a configuration in which the capacity value of the VCO for transmission can be changed in stages, and any capacity value is set according to the frequency band used. A multiband transmission VCO that is selected to switch the oscillation frequency is employed.

  However, the invention of the prior application is limited to a technique for incorporating a transmission VCO in a high-frequency IC for a GSM system that supports only GMSK modulation. The present inventors have examined a technical problem that arises when a multi-band transmission VCO is built in a high-frequency IC for an EDGE system. As a result, when the capacitance value of the on-chip capacitive element constituting the transmission VCO changes due to temperature fluctuation, the KV characteristic (voltage-frequency sensitivity) of the transmission VCO deviates from the desired characteristic and the loop gain of the control loop changes. As a result, EVM (error vector magnitude) deteriorates and spectral regrowth (transmission spectrum), which means an attenuation of a signal level at a frequency 0.4 MHz away from the carrier frequency, deteriorates. As a result, it has been clarified that there are problems that the modulation accuracy is lowered and the amount of noise leakage to the adjacent channel is increased.

  Further, the output signal of the VCO for transmission is power amplified by a power amplifier configured as a separate semiconductor integrated circuit or module and output from the antenna. Conventionally, as a specification of the input range to this power amplifier, it is generally 5 dB. A range such as ± 2 dB was often required. In addition, from the viewpoint of improving communication quality and reducing power consumption, it is expected that strict conditions such as 5 dB ± 1 dB will be required in the future as specifications of the input range to the power amplifier.

  However, since the output amplitude of the transmission VCO changes depending on the power supply voltage, the oscillation frequency, and the temperature fluctuation, measures must be taken in advance so that the output amplitude of the transmission VCO does not change so much with respect to these fluctuation factors. There is a risk that the communication quality deteriorates or the power consumption increases and the maximum call time and the maximum standby time that can be performed by one charge are shortened. Note that there is one described in Document 2 as an invention in which the output amplitude of the transmission VCO is kept constant with respect to temperature fluctuations. However, the invention of the prior application is limited to a technique for keeping the output amplitude of the VCO for transmission constant with respect to temperature fluctuations in an ASK modulation circuit that performs only amplitude modulation.

SUMMARY OF THE INVENTION An object of the present invention is to provide a communication semiconductor capable of preventing deterioration of EVM and transmission spectrum due to a change in KV characteristics of a transmission oscillation circuit due to temperature fluctuation when a transmission oscillation circuit is built in a semiconductor chip. It is to provide an integrated circuit.
Another object of the present invention is to prevent a decrease in communication quality and an increase in power consumption due to a change in output amplitude of a transmission oscillation circuit due to a temperature change when the transmission oscillation circuit is built in a semiconductor chip. The object is to provide a semiconductor integrated circuit for communication.
Still another object of the present invention is to provide a technique which is effective when used in the case where a transmission oscillation circuit is built in a communication semiconductor integrated circuit constituting an EDGE system that performs phase modulation and amplitude modulation.
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

Outlines of representative ones of the inventions disclosed in the present application will be described as follows.
That is, the first invention of the present application is a transmission oscillation circuit that frequency-converts and outputs a phase-modulated signal, the phase of the output signal of the transmission oscillation circuit, and the phase of the phase-modulated and amplitude-modulated signal. A phase control loop for controlling the oscillation frequency of the oscillation circuit for transmission by using the voltage generated by the charge pump, the phase control circuit including a phase comparison circuit for comparing the output and a charge pump for generating a voltage according to the output of the phase comparison circuit The communication semiconductor integrated circuit is provided with a temperature compensation circuit that corrects a deviation of the KV characteristic (control voltage-oscillation frequency characteristic) of the transmission oscillation circuit due to a temperature change by changing a current of the charge pump. It is a thing.

  According to the above means, even if the KV characteristic of the transmission oscillation circuit deviates from a desired characteristic due to a temperature change, for example, the product Kv · Icp of the KV value Kv of the VCO and the current value Icp of the charge pump is within a predetermined range. By correcting the current of the charge pump so as to enter, stability of the phase control loop can be improved, and deterioration of the EVM and transmission spectrum can be prevented.

  Further, the second invention of the present application is for communication, comprising a voltage controlled oscillator and an amplifier circuit for amplifying the output of the oscillator, and comprising a transmission oscillation circuit for converting the frequency of the phase-modulated signal and outputting the signal. In the semiconductor integrated circuit, the power supply voltage of the amplifier circuit is changed according to the temperature so that the amplitude of the output signal of the amplifier circuit falls within a predetermined range.

  According to the above means, even if the amplitude of the output signal of the transmission oscillation circuit deviates from a desired range due to a temperature change, the power supply voltage of the amplifier circuit that amplifies the output of the oscillator is changed according to the temperature, and the gain Therefore, the amplitude of the output signal of the transmission oscillation circuit can be kept almost constant.

  Further, a third invention of the present application is for communication, comprising a voltage controlled oscillator and an amplifier circuit for amplifying the output of the oscillator, and comprising a transmission oscillation circuit for frequency-converting and outputting a phase-modulated signal In the semiconductor integrated circuit, the power supply voltage of the amplifier circuit is changed according to the frequency of the output signal of the voltage controlled oscillator so that the amplitude of the output signal of the amplifier circuit falls within a predetermined range.

  According to the above means, even if the amplitude of the output signal of the transmission oscillation circuit deviates from a desired range due to the change of the oscillation frequency, the power supply voltage of the amplifier circuit that amplifies the output of the oscillator changes according to the oscillation frequency. Since the gain is controlled, the amplitude of the output signal of the transmission oscillation circuit can be kept substantially constant.

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
That is, according to the first invention of the present application, even if the KV characteristic of the transmission oscillation circuit deviates from a desired characteristic due to a temperature change, the stability of the phase control loop is improved, and the EVM and the transmission spectrum are deteriorated. Can be prevented.

  According to the second invention of this application, when the transmission oscillation circuit is built in the semiconductor chip, even if the amplitude of the output signal of the transmission oscillation circuit deviates from a desired range due to a temperature change, the transmission oscillation The amplitude of the output signal of the circuit can be kept almost constant, thereby preventing communication quality deterioration and power consumption increase.

  Further, according to the third invention of the present application, when the transmission oscillation circuit is built in the semiconductor chip, even if the amplitude of the output signal of the transmission oscillation circuit is deviated from a desired range due to the change of the oscillation frequency, the transmission is not performed. The amplitude of the output signal of the trusted oscillation circuit can be kept substantially constant, thereby preventing communication quality deterioration and power consumption increase.

  Next, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a block diagram showing an embodiment of a communication semiconductor integrated circuit (high frequency IC) incorporating a transmission oscillation circuit according to the present invention and a radio communication system using the same. This embodiment is applied to an EDGE wireless communication system that performs 8-PSK modulation in a so-called polar loop system having a phase control loop and an amplitude control loop.

  The radio communication system shown in FIG. 1 includes an antenna 100 that transmits and receives signal radio waves, a switch 110 that switches between transmission and reception, a bandpass filter 120 that includes a SAW filter that removes unwanted waves from a received signal, and a high frequency that amplifies a transmission signal. A power amplifier circuit (power amplifier) 130; a high-frequency IC 200 that demodulates a received signal or modulates a transmission signal; a baseband circuit 300 that converts transmission data into I and Q signals and controls the high-frequency IC 200; Consists of. In this embodiment, the high frequency IC 200 and the baseband circuit 300 are each configured as a semiconductor integrated circuit on separate semiconductor chips.

  Although not particularly limited, the high-frequency IC 200 of this embodiment is configured to be able to modulate and demodulate signals by four communication systems of GSM850, GSM900, DCS1800, and PCS1900. In response to this, the band-pass filter 120 passes a GSM frequency band reception signal, a DCS1800 frequency band reception signal, and a PCS1900 frequency band reception signal. It consists of a filter.

  The high-frequency IC 200 according to the present embodiment is roughly composed of a reception system circuit, a transmission system circuit, and a control system circuit composed of other circuits common to the transmission / reception system such as a control circuit and a clock system circuit.

  The reception system circuit divides the oscillation signal φRF generated by the low noise amplifier 210 that amplifies the reception signal and the high-frequency oscillation circuit (RFVCO) 250 and generates an orthogonal signal that is 90 ° out of phase with each other. Demodulating circuits 212a and 212b composed of a phase circuit 211, a mixer for performing demodulation by synthesizing the orthogonal signal frequency-divided by the frequency-dividing phase-shifting circuit 211 with the reception signal amplified by the low noise amplifier 210, and demodulated It comprises high gain amplifying units (PGA) 220A, 220B, etc. that amplify the I and Q signals and output them to the baseband circuit 300, respectively.

  The transmission circuit divides the oscillation signal φIF generated by the oscillation circuit (IFVCO) 230 that generates an oscillation signal φIF of an intermediate frequency such as 640 MHz and the oscillation circuit 230 and is 90 ° out of phase with each other. Frequency-dividing phase shift circuit 232 that generates quadrature signals, modulation circuits 233a and 233b including mixers that modulate the generated quadrature signals with I and Q signals supplied from baseband circuit 300, and modulated signals , A transmission oscillation circuit (TXVCO) 240a, 240b for generating a transmission signal φTX having a predetermined frequency, a signal obtained by feeding back the transmission signal φTX output from the transmission oscillation circuits 240a, 240b, and a high frequency By synthesizing the signal φRF ′ obtained by dividing the oscillation signal φRF generated by the oscillation circuit (RFVCO) 250, the frequency thereof An offset mixer 253a that generates a signal having a frequency corresponding to the difference, and a phase comparison circuit 236 that compares the output of the offset mixer 253a with the modulation signal TXIF synthesized by the adder 234 to detect a frequency difference and a phase difference. And a charge pump & loop filter 237 that generates a voltage according to the output of the phase detection circuit 236, a signal obtained by feeding back the transmission output output from the high frequency power amplifier circuit 130, and a high frequency oscillation circuit (RFVCO) 250. A second offset mixer 253b that generates a signal having a frequency corresponding to the frequency difference by synthesizing the generated oscillation signal φRF, and an output of the offset mixer 253b and the modulation signal TXIF synthesized by the adder 234 And an amplitude comparison circuit 238 for detecting an amplitude difference and an electric power corresponding to the detected amplitude difference. And a like PA output control circuit 239 for generating a signal Vapc for controlling the gain of the high frequency power amplifier circuit 130 and an output level designation signal Vramp from the baseband IC300 and.

  One of the transmission oscillation circuits 240a and 240b is a circuit that generates a 850 to 900 MHz band signal for GSM, and the other is a circuit that generates a 1700 to 1900 MHz band signal for DCS and PCS. The loop filter is not particularly limited, but is composed of an external capacitor element and a resistor element with small manufacturing variations and temperature dependency.

  Further, on the chip of the high frequency IC 200 of this embodiment, a control circuit 260 for controlling the entire chip, an RF synthesizer 261 that constitutes an RF PLL circuit together with the high frequency oscillation circuit (RFVCO) 250, and the intermediate frequency An IF synthesizer 262 that constitutes an IF PLL circuit together with the oscillation circuit (IFVCO) 230, and a reference oscillation circuit (TCXO) 264 that generates a clock signal φref serving as a reference clock for the synthesizers 261 and 262 are provided. The synthesizers 261 and 262 are each composed of a phase comparison circuit, a charge pump, a loop filter, and the like.

  Since the reference oscillation signal φref is required to have high frequency accuracy, an external crystal oscillator Xtal is connected to the reference oscillation circuit 264. A frequency such as 26 MHz or 13 MHz is selected as the reference oscillation signal φref. This is because a crystal resonator having such a frequency is a general-purpose component and can be easily obtained.

  Control circuit 260 is provided with a control register, and this register is set based on a signal from baseband IC 300. Specifically, a clock signal CLK for synchronization, a data signal SDATA, and a load enable signal LEN as a control signal are supplied from the baseband IC 300 to the high frequency IC 200, and the control circuit 260 receives the load enable signal LEN. Is asserted to a valid level, the data signal SDATA transmitted from the baseband IC 300 is sequentially fetched in synchronization with the clock signal CLK and set in the control register. Although not particularly limited, the data signal SDATA is transmitted serially. The baseband IC 300 is composed of a microprocessor or the like.

  In this embodiment, a phase detection circuit 236, a charge pump & loop filter 237, transmission oscillation circuits (TXVCO) 240a and 240b, and an offset mixer 253a constitute a transmission PLL circuit (TXPLL) that performs frequency conversion. In the multiband wireless communication system of the present embodiment, for example, the control circuit 260 changes the frequency φRF of the oscillation signal of the high-frequency oscillation circuit 250 according to the channel to be used at the time of transmission / reception in response to a command from the baseband IC 300. Depending on the GSM mode or the DCS / PCS mode, the transmission frequency is switched by changing the frequency of the signal supplied to the offset mixers 253a and 253b.

  On the other hand, the oscillation frequency of the high-frequency oscillation circuit (RFVCO) 250 is set to a different value between the reception mode and the transmission mode. In the transmission mode, the oscillation frequency fRF of the high-frequency oscillation circuit (RFVCO) 250 is, for example, 3616-3716 MHz for GSM850, 3840-3980 MHz for GSM900, 3580-3730 MHz for DCS, and 3860--3 for PCS. The oscillation frequency fRF is set to 3980 MHz, and is divided into 1/4 in the case of GSM by a frequency divider, and is divided into 1/2 in the case of DCS and PCS and supplied to the offset mixers 253a and 253b. .

  The offset mixer 253a outputs a signal corresponding to the frequency difference (fRF−fTX) between the oscillation signal φRF from the RFVCO 250 and the transmission oscillation signal φTX from the transmission oscillation circuit (TXVCO) TXVCO 240a, 240b. The transmission PLL (TXPLL) operates so that the frequency matches the frequency of the modulation signal TXIF. In other words, the TXVCOs 240a and 240b are frequencies corresponding to the difference between the frequency of the oscillation signal φRF from the RFVCO 250 (fRF / 4 for GSM and fRF / 2 for DCS and PCS) and the frequency of the modulation signal TXIF. Controlled to oscillate.

  In this embodiment, in order to calibrate the frequencies of the TXVCOs 240a and 240b and select the band to be used, the output φTX of the TXVCOs 240a and 240b is supplied to the IF synthesizer 262 and controlled based on the frequency calibration data in the IF synthesizer. Band selection signals VB2 to VB0 from the circuit 260 are supplied to the TXVCOs 240a and 240b. A selection signal SEL for designating which VCO operates from the control circuit 260 to the TXVCOs 240a and 240b is configured.

  In the high frequency IC of the present embodiment, even if the KV value Kv (= oscillation frequency range / control voltage range) of the transmission VCO changes with temperature, the charge pump current Icp is changed according to the temperature to change Kv · Temperature compensation is performed so that Icp maintains a predetermined value so that the loop gain is kept constant. Specifically, as shown in FIG. 2 (A), the KV value Kv of the VCO increases substantially in proportion to the temperature as shown in FIG. 2 (A), and decreases as the temperature decreases. As shown in FIG. 2C, the charge pump current Icp decreases as the temperature increases, so that Kv · Icp is kept constant with respect to the temperature. Thereby, the loop gain of the phase control loop is stabilized, and even when the KV value Kv of the VCO changes due to temperature fluctuation, it is possible to prevent the deterioration of the EVM and the transmission spectrum.

  FIG. 3 shows a polar loop transmission PLL to which the present invention is applied, in which a phase control loop is extracted. In FIG. 3, the same circuits as those in FIG. In this embodiment, although not particularly limited, the loop filter is configured as a third order filter composed of resistors R1, R2 and capacitors C1, C2, C3. Further, the resistor R1 and the capacitors C1 and C2 are composed of an external capacitor element and a resistor element with small manufacturing variation and temperature dependency.

  In this embodiment, a reference current generation circuit with temperature compensation 241 is provided in association with the phase comparison circuit 236, and the reference current Iref supplied from the reference current generation circuit with temperature compensation 241 to the phase comparison circuit 236 is adjusted. As a result, the current value Icp of the current source of the charge pump CP provided at the output section of the phase comparison circuit 236 is kept constant even if the temperature changes as described above. It is configured.

  Further, in this embodiment, a selector 244 is provided for selecting an output signal of either the transmission oscillation circuit 240a or 240b and feeding it back to the offset mixer 253a. The selector 244 may be configured by a buffer having a selector function. Further, as shown in FIG. 3, the GSM transmission oscillation circuit 240a of FIG. 1 is composed of TXVCOa and a buffer BFFa, and the DCS / PCS transmission oscillation circuit 240b is composed of TXVCOb and a buffer BFFb. It is configured. The buffers BFFa and BFFb convert the differential outputs of TXVCOa and TXVCOb into single (single phase) signals and output them. By providing the buffers BFFa and BFFb, the outputs of the TXVCOa and TXVCOb can be amplified and supplied to the power amplifier, and fluctuations in the oscillation frequency and phase of the VCO due to fluctuations in the load of the power amplifier can be suppressed.

  FIG. 4 shows a specific circuit example of the reference current generating circuit 241 with temperature compensation, and FIG. 5 shows a specific circuit example of the phase comparison circuit 236.

  The reference current generating circuit 241 with temperature compensation of this embodiment includes a constant voltage circuit 411 such as a band gap reference circuit, a voltage-current conversion circuit 412, and a temperature compensation circuit 413. The band gap reference circuit includes NPN bipolar transistors (hereinafter simply referred to as transistors) Q1 and Q2 whose bases are commonly connected to each other. Q2 is a diode connection in which a base and a collector are coupled. A collector voltage is applied to the bases of Q1 and Q2, the emitter of the transistor Q1 is connected to the ground point GND through the resistor R3, the emitter of the transistor Q2 is directly connected to the ground point GND, and the collectors of Q1 and Q2 are connected to each other. The resistors R1 and R2 are connected to each other.

  In addition, a constant current source (which may be a resistor) CC0 and a transistor Q3 are connected in series between the power supply voltage Vcc and the ground point GND, and the collector voltage of the transistor Q1 is applied to the base of the transistor Q3. Yes. A transistor Q4 receiving the collector voltage of the transistor Q3 is provided. The emitter of Q4 is connected to the connection node N0 of the resistors R1 and R2, and the collector current is distributed to the transistors Q1 and Q2.

The constant voltage circuit 411 of this embodiment is a known band gap reference circuit called a wideler type. When the base-emitter voltage of the bipolar transistor is Vbe and the temperature is T, the potential V0 of the connection node N0 is as follows. Formula V0 = Vbe + (R2 / R3). (KT / q) .ln (R2 / R1)
It is represented by Here, the base-emitter voltage Vbe of the bipolar transistor has a negative temperature characteristic of −2 mV / ° C.

  In the above formula, Vbe in the first term has a negative temperature characteristic, and the second term includes the temperature T, and thus has a positive temperature characteristic. Therefore, by setting the values of the resistors R1, R2, and R3 of the second term so as to cancel the negative temperature characteristic of Vbe of the first term, the potential V0 of the connection node N0 is constant even if the temperature changes, that is, the temperature No dependency. This is the principle of operation of the Wideler type band gap reference circuit.

  The temperature compensated reference current generation circuit 241 of this embodiment includes a voltage-current conversion transistor Q6 that receives at the base the same potential Vc as the base potential of the transistor Q4 of the band gap reference circuit 411. If the density is adjusted to Q4, an emitter voltage equivalent to the band gap voltage can be generated, and a current I0 having no temperature dependence can be flowed. A resistor R6 is connected between the emitter of the transistor Q6 and the ground point, and a diode-connected PNP transistor Q7 and a resistor R7 are connected in series between the collector of Q6 and the power supply voltage terminal Vcc. ing.

  Here, the resistor R6 and the like have a positive temperature characteristic, but by using an appropriate manufacturing process, the change can be made small enough to be ignored compared to the temperature characteristic of the base-emitter voltage Vbe of the transistor. it can. Therefore, the current I0 flowing through the transistor Q6 can also be a current having no temperature dependence. Furthermore, a transistor Q7 that is supplied with the same current I0 as Q6 and a transistor Q10 that is current-mirror connected are provided, and a current that does not depend on temperature that is supplied to the transistor Q10 is output as the reference current Iref0.

  On the other hand, the voltage-current conversion circuit 412 is provided with transistors Q8 and Q9 connected to the base of the transistor Q4, and a voltage having no temperature dependency is supplied to the temperature compensation circuit 413 as with Q6. ing. The temperature compensation circuit 413 is provided with resistors R11 and R12 connected in series with the transistor Q8, a resistor R13 connected in series with Q9, and a diode-connected transistor Q11.

  Further, in the temperature compensation circuit 413, the potential V1 at the connection node of the resistors R11 and R12, and the potential V2 at the connection node of the resistor R13 and the transistor Q11 are respectively at levels formed by the MOS transistors M1 and M2 and the constant current source CC1. Bipolar transistors Q12 and Q13, which are input to the base terminal via the shift circuit and the emitter terminals are coupled via resistors R14 and R15, are connected between the collector terminals of Q12 and Q13 and the power supply voltage terminal Vcc. A differential circuit comprising active load transistors M3 and M4, constant current sources CC1 and CC2 connected between the connection node of the emitter resistors R14 and R15 and the ground point, and a changeover switch SW11 is provided.

  Here, the constant current source CC1 is for GSM, and CC2 is for DCS / PCS. In the high-frequency IC of the embodiment of FIG. 1, the TXVCO is switched between the GSM mode and the DCS or PCS mode, while the loop gain is changed by changing the current Icp using a common charge pump in the two modes. . Therefore, the correction amount by temperature compensation of the reference current Iref supplied to the charge pump is also changed depending on the mode.

  In the temperature compensation circuit 413, since the currents flowing through the resistors R11 and R12 are not temperature-dependent, even if the resistance values of the resistors R11 and R12 change with temperature, they are constant regardless of the temperature of the potential V1 of their coupling node. . On the other hand, the base-emitter voltage Vbe of the transistor Q11 has a negative temperature characteristic, and the change in resistance value accompanying the temperature change of the resistor R13 is negligibly small compared to the change in the base-emitter voltage Vbe of the transistor. The potential V2 at the connection node between the resistor R13 and the transistor Q11 changes according to the temperature.

  Therefore, the collector current of the differential bipolar transistor Q13 decreases as the temperature decreases, and the collector current of Q13 increases as the temperature increases. The drain currents of the load MOS transistors M3 and M4 show current increase / decrease opposite to Q13 so as to keep the constant current source CC1 constant. In this embodiment, the constants of the respective elements are set so that the collector currents of the differential bipolar transistors Q12 and Q13 are the same when the temperature is 25 ° C. That is, when the temperature is 25 ° C., no current flows out from the output node of the differential amplifier circuit, and no current is drawn.

  When the temperature is lower than 25 ° C., the collector current of Q13 is smaller than the collector current of Q12, and a part of the drain current of the load MOS transistor M4 flows out from the output node as the correction current Icomp, and is output from the transistor Q10. It is added to the constant current Iref0 and output as the reference current Iref. On the other hand, when the temperature is higher than 25 ° C., the collector current of Q13 becomes larger than the collector current of Q12 and the current Icomp is drawn from the output node, so that the constant current Iref0 from the transistor Q10 is subtracted and output as the reference current Iref. Is done. Therefore, the reference current Iref increases as the temperature decreases and decreases as the temperature increases. This reference current Iref is supplied to the phase comparison circuit 236 of FIG.

  The phase comparison circuit 236 shown in FIG. 5 includes a circuit called a Gilbert cell in which differential transistor pairs are vertically stacked, and includes a constant current transistor Q21 in a differential amplification stage of the Gilbert cell and a transistor Q20 connected in a current mirror manner. When the reference current Iref having temperature dependency is supplied from the temperature compensated reference current generation circuit 241 to the transistor Q20, the current supplied to the differential amplifier stage and the current supplied to the output stage are changed. It is comprised so that.

  Modulation signals TXIF and / TXIF from the modulation circuit are input to the lower differential transistor pair Q22 and Q23 of the phase comparison circuit 236, and the upper differential transistor pair Q24, Q25 and Q26 and Q27 are downed by the offset mixer 253a. The converted feedback signals φTX and / φTX are input. As a result, a current corresponding to the phase difference between TXIF, / TXIF and φTX, / φTX and the current value of the reference current Iref flows through the transistors Q30 and Q31 in the output stage. That is, if the phase difference is equal, the collector current of Q30 and Q31 increases as the current value of the reference current Iref increases, and the collector current of Q30 and Q31 decreases as the current value of the reference current Iref decreases. Here, since the reference current Iref is generated so as to have a negative temperature characteristic as described above, the collector currents of Q30 and Q31 also have a negative temperature characteristic.

  Further, the collector current of the transistor Q30 is turned back by the current mirror circuit composed of the transistors Q32 and Q33 and flows to the transistor Q33. As a result, the sum of the collector current flowing through Q31 and the collector current flowing through Q33 becomes a current proportional to the reference current Iref (the same current if the transistors have the same size). The transistor Q33 and the transistor Q31 are connected in series, and a loop filter is connected to the connection node. That is, the transistor Q31 functions as a current source for charging the charge pump, and the transistor Q33 functions as a current source for discharging the charge pump. As a result, when the collector current flowing through Q31 is larger than the collector current flowing through Q33, it flows into the loop filter as a charge current, and when the collector current flowing through Q31 is smaller than the collector current flowing through Q33, it is drawn from the loop filter as a discharge current. To work.

  Since the collector currents of the transistors Q31 and Q33 have a negative temperature characteristic in accordance with the reference current Iref from the temperature-compensated reference current generation circuit 241, the current Icp of the current source of the charge pump is as shown in FIG. The temperature is adjusted to decrease as the temperature increases. In addition, by providing a transistor having a size different from that of Q21 in parallel with the constant current transistor Q21 and switching with a switch, different currents are caused to flow in the differential circuit depending on the GSM mode and the DCS or PCS mode, so that the mode is changed. Accordingly, the current value of the current source of the charge pump is made different. In other words, the loop gain of the phase control loop can be changed by changing the frequency band of the loop filter depending on the mode, but in this embodiment, it can be handled by changing the current value of the current source of the charge pump. ing.

  As described above, the embodiment in which the deviation of the KV value of the TXVCO due to the temperature change is compensated by adjusting the current Icp of the current source of the charge pump has been described. However, the deviation of the KV characteristic of the TXVCO due to the manufacturing variation and the reference current generation circuit 241 Deviations in compensation characteristics can also be considered. In order to correct such a shift due to manufacturing variation, for example, a transistor having a different size in parallel with the transistors Q31 and Q33 in the output stage of the charge pump in FIG. 5, a switch that enables connection / separation of the transistor, and the switch A register for setting the on / off state of the charge pump may be provided so that the current Icp of the current source of the charge pump is adjusted in accordance with variation in characteristics.

  FIG. 6 shows a second embodiment of a transmission PLL to which the present invention is applied. Note that FIG. 6 also shows only the phase control loop of the polar-loop transmission PLL, as in FIG. 3, and the amplitude control loop is not shown.

  In this embodiment, a voltage regulator 242 is provided which generates a power supply voltage Vreg corresponding to the power supply voltage Vcc and the chip temperature and supplies it to the buffers BFFa and BFFb. The voltage regulator 242 is supplied with a mode selection signal MODE for designating a GSM mode or a DCS / PCS mode supplied from the band determination circuit 621 in the control circuit 260 to the oscillation circuits 240a and 240b. The generated voltage is adjusted according to the selection mode and is supplied to the buffer BFFa or BFFb. As for VCOa and VCOb, either GSM or DCS / PCS is set in an operating state according to the selection mode, and the other is stopped.

  The oscillation frequency band determination circuit 621 has a target oscillation frequency value TX (N, A) calculated based on the oscillation frequency designation information from the control circuit 260 and the frequency measured by the frequency measurement circuit and stored in the register 622 in advance. Bands to be used are determined from the values and band selection signals VB2 to VB0 are supplied to VCOa and VCOb.

  When it is desired to widen the frequency range to be covered by the VCO, if only the change in the capacitance value of the variable capacitance element due to the control voltage Vt is attempted, the Vt-fTF characteristic (control voltage-oscillation frequency characteristic) becomes steep, and the VCO The sensitivity, that is, the ratio (Δf / ΔVt) between the amount of change in frequency and the amount of change in control voltage becomes large and becomes weak against noise. That is, the oscillation frequency of the VCO changes greatly only by a slight noise on the control voltage Vt.

  In order to solve this problem, the VCOa and VCOb of this embodiment are provided with a plurality of capacitor elements constituting the LC resonance circuit in parallel, and the capacitor elements connected by the band switching signals VB2 to VB0 are switched in eight stages. By changing the value of C, as shown in FIG. 8, it is configured to be able to perform oscillation control according to the eight Vt-fTF characteristic lines BAND0 to BAND7. These characteristics are selected and operated.

FIG. 7 shows a configuration example of the transmission VCO used in this embodiment.
The transmission VCO of this embodiment is an LC resonance type oscillation circuit, and a pair of P-channel MOS transistors M41 and M42 whose sources are commonly connected and whose gates and drains are cross-coupled with each other, and common to the transistors M41 and M42. A constant current source I0 connected between the source and the power supply voltage terminal Vcc, inductors L1 and L2 respectively connected between the drains of the transistors M41 and M42 and the ground point GND, and the transistors M41 and M42 MOS varactors Mv1, Mv2 as variable capacitance elements connected in series between drain terminals, capacitance C11-switch MOS transistor M11-capacitance C12 similarly connected in series between drain terminals of transistors M41, M42, and C21-M12-C22 connected in parallel; C31-M1 And it is configured from the Metropolitan -C32. The MOS varactors Mv1 and Mv2 utilize the capacitance between the gate electrode and the substrate using the gate insulating film of the P channel MOS transistor as a dielectric. The switch MOS transistors M11 to M13 are configured by N-channel MOSFETs.

  In the oscillation circuit of this embodiment, the control voltage Vt from the charge pump & loop filter 237 is applied to the connection node N0 of the MOS varactors Mv1 and Mv2 to continuously change the oscillation frequency, while between the capacitors C11 and C12. When the switch MOS transistor M11, the switch MOS transistor M12 between the capacitors C21 and C22, and the switch MOS transistor M13 between the capacitors C31 and C32 are turned on or off by the band selection signals VB2 to VB0, the oscillation frequency is reduced. It is configured to change in stages.

  As the variable capacitance element, a varactor diode composed of a PN junction is generally used. However, by using a MOS varactor as in this embodiment, the oscillation level can be increased, and thereby the CN of the circuit can be increased. The ratio is good. Further, by adopting a circuit configuration in which the inductors L1 and L2 are connected to the ground point and the potential of each node in the circuit is determined based on the ground potential, there is an advantage that the power supply voltage dependency is reduced.

  The capacitors C11 and C12 have the same capacitance value, and C21 and C22 and C31 and C32 have the same capacitance value. However, the capacitance values of the capacitors C11, C21, and C31 are set to have a weight of 2 to the power of m (m is 2, 1, 0), respectively, and the capacitance values are 8 levels according to the combination of VB2 to VB0. The oscillation circuit is made to operate with any of the 8-band frequency characteristics BAND0 to BAND7 shown in FIG.

  Furthermore, in the TXVCO of the present embodiment, the resistors R11 are respectively connected between the inverters INV1 to INV3 that invert the band selection signals VB2 to VB0, and the output terminals of the inverters and the drain and source terminals of the switch MOS transistors M11 to M13. , R12 to R31, R32 are connected, and when the switch MOS transistors M11 to M13 are turned off, one terminal of the fixed capacitors C11 to C32 is fixed to the power supply voltage Vcc so as not to float. Further, a switch SW0 is provided in series with the constant current source I0, and the oscillation operation of the VCO can be stopped by turning off the switch SW0.

  In the LC resonance type oscillation circuit of this embodiment, the fixed capacitors C11 to C32 are constituted by a capacitor having a sandwich structure of metal film-insulating film-metal film formed on a semiconductor substrate. A desired capacitance ratio (2 m) can be obtained by the size ratio of the electrodes constituting the capacitors C11 to C32. Hereinafter, the capacitors C11 to C32 are referred to as band switching capacitors, and the MOS varactors Mv1 and Mv2 are referred to as variable capacitors. A varactor diode made of a PN junction may be used as the variable capacitor, and a capacitor between the gate electrode of the MOS transistor and the substrate may be used as the fixed capacitors C11 to C32. In this embodiment, the inductors L1 and L2 are on-chip elements made of an aluminum layer formed on a semiconductor substrate. This is to reduce the number of components, and external elements are not used. It is also possible to use it.

FIG. 9 shows the characteristics of the MOS varactors Mv1 and Mv2 as variable capacitors used in the LC resonance type oscillation circuit of FIG.
In FIG. 9, the horizontal axis represents the voltage between the terminals of the MOS varactors Mv1 and Mv2, that is, the control voltage applied to the connection node N0 when the potential of the connection node (= output node) between the inductors L1 and L2 is constant (= GND). Vt, the vertical axis represents the capacitance values of the MOS varactors Mv1, Mv2, and Vth represents the threshold voltage as a MOS transistor. From FIG. 9, when the voltage Vt is sufficiently higher than Vth, the capacitance values of the MOS varactors Mv1 and Mv2 are large, and when the voltage Vt is sufficiently lower than Vth, the capacitance value is small. Further, the capacitance values of the MOS varactors Mv1 and Mv2 change greatly in the vicinity of Vth, and a substantially constant value is shown in the portion excluding the transition region.

  As described above, the capacitance values of the MOS varactors Mv1 and Mv2 greatly change because the capacitance values of the MOS varactors Mv1 and Mv2 are in a gate parasitic state when the voltage Vt is lower than Vth. In contrast to the capacitance Coff alone, when the voltage Vt is higher than Vth, an inversion layer is formed under the gate electrode, so that the capacitance value is the size obtained by adding the MOS gate oxide film capacitance Cox to the parasitic capacitance Coff ( This is because Coff + Cox).

  Therefore, in the LC resonance type oscillation circuit of FIG. 6, the capacitance values of the MOS varactors Mv1 and Mv2 may vary depending on the output amplitude level and the oscillation output level. Specifically, the oscillation output changes in the form of a sine wave with an amplitude ± Va centered on GND, but at this time, the control voltage Vt applied to the MOS varactors Mv1 and Mv2 satisfies the condition of Vt <−Va + Vth. The capacitance values of the MOS varactors Mv1 and Mv2 are Coff (= constant).

  On the other hand, when the control voltage Vt satisfies the condition of Vt> + Va + Vth, the capacitance values of the MOS varactors Mv1 and Mv2 are Coff + Cox (= constant). On the other hand, when Vt satisfies the condition of (−Va + Vth) <Vt <(+ Va + Vth), the capacitance values of the MOS varactors Mv1 and Mv2 change according to Vt, and the on-time of the MOS transistor in the cycle It is expressed as a sum of values obtained by integrating (Coff + Cox) and Coff according to the ratio of ton and off time toff.

  Thus, when the capacitance values of the MOS varactors Mv1 and Mv2 vary according to the control voltage Vt, the oscillation frequency fvco of the LC resonance type oscillation circuit also changes. Conversely, it can be seen that the oscillation frequency changes if the output amplitude 2 · Va of the oscillation circuit changes even if the voltage Vt is constant. At this time, there is a correlation between the output amplitude 2 · Va and the oscillation frequency fvco.

  In the embodiment of FIG. 6, a mode selection signal is given to the voltage regulator 242, and the power supply voltage Vreg of the buffers BFFa and BFFb at the subsequent stage of the oscillation circuits VCOa and VCOb is changed according to the operation mode. The gain of the buffer is increased by increasing the voltage Vreg to be generated, and the gain V is decreased by decreasing the generated voltage Vreg as the oscillation frequency is lower. Instead of the mode selection signal, selection band information, that is, oscillation frequency information may be provided, and the power supply voltage Vreg of the buffers BFFa and BFFb may be changed according to the oscillation frequency.

  FIG. 10 shows the correlation between the control voltage Vt applied to the MOS varactors Mv1 and Mv2 and the oscillation frequency fvco of the VCO, and the correlation between these and the amplitude of the oscillation output. In FIG. 10, a voltage V0 in which the solid line corresponds to the intersection of the correlation lines of Vt and fvco corresponds to the threshold value Vth of the MOSFET.

  As can be seen from FIG. 10, when the control voltage Vt is lower than a certain value V1 (= −Va + Vth), the oscillation frequency fvco becomes a certain high substantially constant value f1, and when the voltage Vt is higher than V2 (= Va + Vth), i The oscillation frequency fvco is a certain low and substantially constant value f2. When the control voltage Vt is between V1 and V2, the oscillation frequency fvco changes almost linearly. The difference (V2−V1) between the values V1 and V2 of the control voltage Vt when the oscillation frequency fvco changes substantially corresponds to the amplitude 2 · Va of the oscillation output at that time. The straight lines with different slopes mean that the Vt-fvco characteristic (control voltage-oscillation frequency characteristic) changes greatly as the Q value of the VCO changes due to manufacturing variations or temperature changes. It can be seen from FIG. 10 that the output amplitude of the VCO becomes smaller as the Vt-fvco characteristic becomes steeper, and the amplitude becomes larger as the Vt-fvco characteristic becomes gentler. This is a feature of the VCO of FIG. 7 using a MOS varactor as a variable capacitance element.

  By the way, in the VCO of FIG. 7, when the Q value such as the resistance values of the varactors Mv1 and Mv2 changes due to a temperature change, the amplitude changes, thereby changing the KV value Kv of the VCO and changing the loop gain. Further, when the Vt-fvco characteristic becomes steep, the KV value Kv of the VCO increases. When the Vt-fvco characteristic becomes gentle, the KV value Kv of the VCO decreases. Therefore, the KV value Kv of the VCO increases as the amplitude 2 · Va decreases, and the KV value Kv of the VCO decreases as the amplitude increases. Specifically, the higher the temperature, the larger the KV value Kv of the VCO, and the lower the temperature, the smaller the KV value Kv of the VCO. That is, the higher the temperature, the smaller the amplitude 2 · Va of the VCO, and the lower the temperature, the larger the amplitude.

  Therefore, in order to stabilize the loop gain of the transmission PLL regardless of the temperature change, it is effective to change the current value Icp of the charge pump according to the temperature as in the first embodiment described above. In order to make the TXVCO amplitude constant regardless of the change, the gain of the TXVCO may be reduced at a low temperature and the gain may be increased at a high temperature according to the temperature change. In the second embodiment shown in FIG. 6, the voltage regulator 242 has a temperature compensation function, and the power supply voltage Vreg of the buffers BFFa and BFFb in the subsequent stage of the oscillation circuits VCOa and VCOb is changed according to the temperature, so that the temperature is low. Reduces the generated voltage Vreg to reduce the gain, and when the temperature is high, the generated voltage Vreg is increased to increase the gain.

FIG. 11 shows a specific circuit example of the voltage regulator 242 having a temperature compensation function.
As shown in FIG. 11, the voltage regulator 242 of this embodiment includes a reference voltage generation circuit 421 and the reference voltage Vref generated by the reference voltage generation circuit 421 as the gate input voltage of one differential transistor M31. And a temperature compensation circuit 423 that generates a voltage fed back to the gate terminal of the other differential transistor M32 of the differential amplifier circuit 422. As the reference voltage generation circuit 421, a circuit having the same configuration as that of the Wideler type bandgap reference circuit 411 shown in FIG. 4 can be used, or a circuit can also be used.

  The differential amplifier circuit 422 includes a pair of differential transistors M31 and M32 whose sources are coupled to each other, a constant current source CC3 connected between a common source and a ground point, collectors of M31 and M32, and a power supply voltage terminal. The active load transistors M33 and M34 are connected to Vcc, and the output transistor M35 has a gate terminal connected to the drain terminal of M31.

  The temperature compensation circuit 423 is provided in parallel with the resistor means RM1 and RM2 connected in series between the drain terminal of the output transistor M35, that is, the output terminal of the circuit, and the ground point, and the resistor means RM2, and the current value according to the temperature. Variable current means VC that changes. Among these, the resistance means RM1 includes a pair of parallel resistors RM11, RM12, RM13, and switches SW11, SW12, SW13 connected in series with the respective resistors RM11, RM12, RM13. The resistors RM11, RM12, and RM13 have different resistance values, and one of the switches SW11, SW12, and SW13 is turned on by a signal MODE indicating GSM mode, DCS mode, or PCS mode, and the other is turned off. To be.

  Thereby, the voltage Vreg generated by the voltage regulator 242 is different in the GSM mode, the DCS mode, and the PCS mode. Specifically, the resistance values of the resistors RM12 and RM13 are set so that the generated voltage Vreg (PCS) in the PCS mode is higher than the generated voltage Vreg (DCS) in the DCS mode having a low oscillation frequency.

  In this embodiment, the generated voltage Vreg is switched in three stages in the GSM mode, the DCS mode, or the PCS mode. However, as described above, the TXVCO oscillates in any of the eight frequency bands. A plurality of pairs of resistors and switches constituting the resistance means RM1 may be provided so that the generated voltage Vreg is switched in multiple stages according to the selected band. Note that this is a case where the voltage regulator 242 is configured as a circuit common to the two buffers BFFa and BFFb subsequent to VCOa and VCOb, and when separate voltage regulators are provided according to the buffers BFFa and BFFb, The generated voltage Vreg may be individually switched in multiple stages.

  In the voltage regulator of this embodiment, feedback is applied so that the gate voltage of the differential transistor M32 matches the reference voltage Vref which is the gate voltage of M31, and the resistor RM1, the resistor RM2, and the combined resistor Rc of the variable current source VC A voltage Vreg corresponding to the ratio is generated. For example, when the ratio of the resistor RM1 to the combined resistor Rc is 1: 1, a voltage half of Vreg is fed back to the gate terminal of the differential transistor M32, so that the generated voltage Vreg is 2 × Vref. .

  Further, in the voltage regulator of this embodiment, the variable current source VC of the temperature compensation circuit 423 includes a series resistor RM3 and a diode-connected bipolar transistor Q13. In this circuit, if the base-emitter voltage of the transistor Q13 is Vbe and the resistance value of the resistor RM3 is r3, the current I3 flowing through the resistor RM3 is expressed by I3 = (Vref−Vbe) / r3. Here, the base-emitter voltage Vbe has a negative temperature characteristic. Therefore, the current I3 flowing through the resistor R3 increases as the temperature increases. This is equivalent to a decrease in the combined resistance Rc of the resistor RM2 and the variable current source VC. As a result, the voltage drop amount of the resistor R1 increases and the gate voltage of the differential transistor M32 tends to decrease. However, the differential amplifier circuit 422 works to return the voltage to the reference voltage Vref and generates the generated voltage. Vreg is increased. Conversely, when the temperature is lowered, the generated voltage Vreg is lowered.

  As described above, the voltage regulator of this embodiment generates a voltage Vreg that increases as the temperature increases according to the temperature. Since the band gap reference circuit generates a constant voltage regardless of the power supply voltage Vcc, the voltage regulator of this embodiment does not change the generated voltage Vreg even if the power supply voltage Vcc varies. Further, a higher voltage Vreg is generated as the frequency is higher according to the oscillation frequency of the TXVCO. Since the voltage Vreg controlled in this way is supplied as a power supply voltage to the buffers BFFa and BFFb in the subsequent stage of the TXVCO, the output amplitude of the transmission oscillation circuits 240a and 240b is caused by a change in temperature, a fluctuation in the power supply voltage Vcc, It is kept almost constant with respect to switching of the oscillation frequency.

  FIG. 12 shows a circuit example of buffers BFFa and BFFb that operate in response to the voltage Vreg generated by the voltage regulator 242 configured as described above.

  As shown in FIG. 12, the buffers BFFa and BFFb have a first buffer 431 that does not have much gain and mainly has a function of converting the differential output of the TXVCO into a single signal, and a second buffer 432 mainly responsible for signal amplification. It consists of and. The first and second buffers are connected by a capacitor C40 in order to cut the DC voltage. The voltage Vreg generated by the voltage regulator 242 is supplied to the second buffer 432 at the subsequent stage. If the voltage Vreg generated by the voltage regulator 242 is supplied to all of the TXVCO, the first buffer 431, and the second buffer 432, the accuracy of the output amplitude becomes higher. However, the noise characteristics and the power conversion efficiency are not. This is because, if the power supply voltage of the second buffer 432 as the final stage is controlled, a considerably good accuracy can be obtained.

  The first buffer 431 includes differential MOS transistors M41 and M42 whose source terminals are coupled to each other by GND and the TXVCO differential output signals φTX and / φTX are input to the gate terminals, and drains of the differential MOS transistors M41 and M42. Active load transistors M43 and M44 connected to the side, and resistors R41 and R42 for providing a bias point, that is, an amplitude center of an input signal, to the gate terminals of the differential MOS transistors M41 and M42.

  The second buffer 432 is configured by a CMOS inverter in which a P-channel MOS transistor M45 and an N-channel MOS transistor M46 are connected in series, and the output signal of the first buffer 431 is input to each gate terminal. The resistor R43 is provided for self-biasing so as to fix the bias point (amplitude center) of the output signal to the center level (Vreg / 2) of the input signal.

  The invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Nor. For example, the first embodiment and the second embodiment may be combined to apply both. In the embodiment, the TXVCO output is fed back to the phase comparator 236 via the offset mixer 253a. However, the buffer output may be fed back.

  In the above-described embodiment, the case where the present invention is applied to a polar loop type radio communication system having a phase control loop and an amplitude control loop has been described. However, the present invention is applicable only to a phase control loop that performs phase modulation such as GMSK modulation. It is possible to apply to an offset PLL type high frequency IC having

  In the above description, the case where the invention made mainly by the present inventor is applied to a high frequency IC used in a wireless communication system of a mobile phone capable of communication using the EDGE system, which is a field of use behind the invention, has been described. The invention is not limited to an EDGE high frequency IC, but is a high frequency IC for wireless LAN that performs modulation such as 16QAM or 64QAM that requires phase modulation and amplitude modulation, and uses a phase control loop and amplitude as a modulation method. The present invention can also be applied to a transmission VCO of a high-frequency IC having a transmission system circuit that employs a so-called polar loop system having a control loop.

1 is a block diagram showing an embodiment of a communication semiconductor integrated circuit (high frequency IC) incorporating a transmission oscillation circuit according to the present invention and a radio communication system using the same. FIG. It is explanatory drawing which shows the control principle of the phase control loop in the semiconductor integrated circuit for communication which incorporated the oscillation circuit for transmission based on this invention. It is a block diagram which shows the detail of the phase control loop of the PLL for transmission of the polar loop system to which this invention is applied. It is a circuit diagram showing a specific circuit example of a reference current generation circuit with temperature compensation. It is a circuit diagram which shows the specific circuit example of a phase comparison circuit. It is a block diagram which shows the 2nd Example of PLL for transmission to which this invention is applied. It is a circuit diagram which shows the structural example of VCO for transmission used in a present Example. It is a characteristic view which shows the frequency characteristic of VCO for transmission of FIG. It is a characteristic view which shows the voltage-capacitance characteristic of the MOS varactor used for VCO for transmission of FIG. It is a correlation diagram showing the correlation between the control voltage Vt applied to the MOS varactor and the oscillation frequency fvco, and the correlation between these and the amplitude of the oscillation output. It is a circuit diagram which shows the specific circuit example of the voltage regulator which has a temperature compensation function. It is a circuit diagram which shows the circuit example of the buffer which receives and receives the voltage generated by the voltage regulator.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Transmission / reception antenna 110 Transmission / reception switching switch 120 Filter 130 High frequency power amplifier circuit 200 High frequency IC
210 Low noise amplifier 211, 232 Frequency division phase shift circuit 212a, 212b Demodulation mixer 220A, 220B High gain amplifier circuit 233a, 233b Modulation mixer 253a, 253b Frequency conversion mixer 230 Intermediate frequency oscillation circuit (IFVCO)
236 Phase comparison circuit 237a Transmission PLL charge pump 237b Transmission PLL loop filter 238 Amplitude comparison circuit 240a, 240b Transmission oscillation circuit (TXVCO)
241 Reference current generation circuit 242 Voltage regulator 244 Selector 250 High frequency oscillation circuit (Reception VCO, RFVCO)
261 Synthesizer circuit for RFPLL 262 Synthesizer circuit for IFPLL 264 Reference oscillation circuit 300 Baseband circuit 411 Constant voltage circuit 412 Voltage-current conversion circuit 413 Temperature compensation circuit 431 First buffer 432 Second buffer

Claims (16)

A transmission oscillation circuit for frequency-converting and outputting a phase-modulated signal, a phase comparison circuit for comparing the phase of the output signal of the transmission oscillation circuit with the phase of the modulated signal, and the output of the phase comparison circuit A phase control loop for controlling the oscillation frequency of the oscillation circuit for transmission by the voltage generated by the current of the charge pump, including a charge pump for generating a voltage according to
A temperature compensation circuit that corrects a deviation in control voltage-oscillation frequency characteristics of the transmission oscillation circuit due to a temperature change by changing a current of the charge pump; and
A semiconductor integrated circuit for communication, comprising:   The temperature compensation circuit is configured such that a product (Kv · Icp) of an oscillation frequency range / control voltage range value (Kv) of the transmission oscillation circuit and a current value (Icp) of the charge pump falls within a predetermined range. 2. The communication semiconductor integrated circuit according to claim 1, wherein a current of the charge pump is corrected.   An amplitude comparison circuit that compares the amplitude of the output signal of the power amplification circuit that amplifies the transmission signal and the amplitude of the modulated signal, and generates the voltage according to the amplitude difference detected by the amplitude comparison circuit to generate the power 3. The communication semiconductor integrated circuit according to claim 1, further comprising an amplitude control loop that outputs the output level control signal to the circuit.   The communication semiconductor integrated circuit according to claim 1, wherein the transmission oscillation circuit is configured to be capable of oscillating in a plurality of frequency bands.   The transmission oscillation circuit has a variable capacitance element using a capacitance existing between the gate and the substrate of a MOS transistor, and a voltage generated by the current of the charge pump is applied to one terminal of the variable capacitance element. 5. The communication semiconductor integrated circuit according to claim 1, wherein the communication semiconductor integrated circuit is configured to oscillate at a frequency corresponding to the applied voltage.   The transmission oscillation circuit includes a first oscillation circuit capable of oscillating in a first frequency band and a second oscillation circuit capable of oscillating in a second frequency band, and the charge pump includes the first oscillation circuit. And the second oscillation circuit are configured as a common circuit so that the current value of the charge pump is switched between when the first oscillation circuit is operated and when the second oscillation circuit is operated. 6. The communication semiconductor integrated circuit according to claim 1, wherein the communication semiconductor integrated circuit is configured as described above. Equipped with a transmission oscillation circuit that converts the frequency of the phase-modulated signal and outputs it.
The transmission oscillation circuit includes a voltage controlled oscillator and an amplification circuit that amplifies the output of the oscillator, and the power supply voltage of the amplification circuit depends on temperature so that the amplitude of the output signal of the amplification circuit falls within a predetermined range. A communication semiconductor integrated circuit characterized by being changed. Equipped with a transmission oscillation circuit that converts the frequency of the phase-modulated signal and outputs it.
The transmission oscillation circuit includes a voltage controlled oscillator and an amplification circuit that amplifies the output of the oscillator, and the frequency of the output signal of the voltage controlled oscillator is set so that the amplitude of the output signal of the amplification circuit falls within a predetermined range. In response, the power supply voltage of the amplifier circuit is changed. Equipped with a transmission oscillation circuit that converts the frequency of the phase-modulated signal and outputs it.
The transmission oscillation circuit includes a voltage controlled oscillator and an amplification circuit that amplifies the output of the oscillator, and the temperature and the output signal of the voltage controlled oscillator are adjusted so that the amplitude of the output signal of the amplification circuit falls within a predetermined range. A communication semiconductor integrated circuit in which a power supply voltage of the amplifier circuit is changed according to a frequency.   A voltage regulator that generates a voltage that is constant and changes according to temperature regardless of fluctuations in the power supply voltage is provided, and the voltage generated by the voltage regulator is supplied to the power supply voltage terminal of the amplifier circuit. 10. The semiconductor integrated circuit for communication according to claim 7, 8 or 9.   A phase comparison circuit that compares the phase of the output signal of the transmission oscillation circuit with the phase of the modulated signal, and generates a voltage corresponding to the phase difference detected by the phase comparison circuit to oscillate the transmission oscillation circuit 11. The communication semiconductor integrated circuit according to claim 10, further comprising a phase control loop for controlling the frequency.   An amplitude comparison circuit that compares the amplitude of the output signal of the power amplification circuit that amplifies the transmission signal and the amplitude of the modulated signal, and generates the voltage according to the amplitude difference detected by the amplitude comparison circuit to generate the power 12. The communication semiconductor integrated circuit according to claim 11, further comprising an amplitude control loop that outputs an output level control signal to the circuit.   The voltage controlled oscillator has a differential output, and the amplifier circuit converts a differential output signal of the voltage controlled oscillator into a single-phase signal, and a first buffer circuit that amplifies the output signal of the first buffer circuit. The voltage generated by the voltage regulator is supplied to a power supply voltage terminal of the second buffer circuit, and the second buffer circuit is supplied with the second buffer circuit. Semiconductor integrated circuit for communication.   The voltage controlled oscillator has a variable capacitance element using a capacitance existing between a gate and a substrate of a MOS transistor, and a voltage generated in the phase control loop is applied to one terminal of the variable capacitance element. 14. The communication semiconductor integrated circuit according to claim 11, wherein the oscillating operation is performed at a frequency corresponding to the applied voltage.   The transmission oscillation circuit includes a first oscillation circuit capable of oscillating in a first frequency band and a second oscillation circuit capable of oscillating in a second frequency band, and the voltage regulator includes the first oscillation circuit. And the second oscillation circuit are configured as a common circuit, and generate and supply different voltages when the first oscillation circuit is operated and when the second oscillation circuit is operated. The communication semiconductor integrated circuit according to claim 11, wherein the communication semiconductor integrated circuit is configured as described above. A transmission oscillation circuit that frequency-converts and outputs a phase-modulated signal, a phase comparison circuit that compares the phase of the output signal of the transmission oscillation circuit with the phase of the phase-modulated and amplitude-modulated signal, and the phase A phase control loop including a charge pump for generating a voltage according to the output of the comparison circuit and controlling the oscillation frequency of the oscillation circuit for transmission by the voltage generated by the current of the charge pump;
A temperature compensation circuit that corrects a deviation in control voltage-oscillation frequency characteristics of the transmission oscillation circuit due to a temperature change by changing a current of the charge pump; and
With
The transmission oscillation circuit includes a voltage controlled oscillator and an amplification circuit that amplifies the output of the oscillator,
A communication semiconductor integrated circuit in which a power supply voltage of the amplifier circuit is changed according to a temperature and a frequency of an output signal of the voltage controlled oscillator so that an amplitude of an output signal of the amplifier circuit falls within a predetermined range.

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