JP2005093776A - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
- Publication number
- JP2005093776A JP2005093776A JP2003325962A JP2003325962A JP2005093776A JP 2005093776 A JP2005093776 A JP 2005093776A JP 2003325962 A JP2003325962 A JP 2003325962A JP 2003325962 A JP2003325962 A JP 2003325962A JP 2005093776 A JP2005093776 A JP 2005093776A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor substrate
- resin
- forming
- semiconductor
- alignment mark
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Dicing (AREA)
Abstract
【解決手段】 半導体基板の表面に電子回路を形成し、この電子回路の電極端子を半導体基板上で配線を介して分散することによる再配置させた電極パッドを形成すると共に、半導体基板の外周部近傍に、半導体基板を切断分離する際、切断位置の基準となる位置合わせマークを形成する。この位置合わせマークを露出するとともに、樹脂や半導体基板の研磨時に、半導体基板の割れ、欠け、クラック等を防止するため半導体基板の外周方向の領域に樹脂層を形成する。
【選択図】 図11
Description
同時に、樹脂層の形成は少なくとも位置合わせマークを含む領域を開口しているので、この位置合わせマークを基準にして寸法精度の高い切断分離が可能となる。特に、この位置合わせマークを含む領域より半導体基板の外周方向の領域には樹脂層を形成しているため、半導体基板全面に樹脂層が形成された場合同様、半導体基板裏面の研磨時に半導体基板の割れ、欠け、クラック、樹脂の剥離等の発生がない。
Claims (1)
- 半導体基板の一主面に、電子回路を形成し、該電子回路の電極端子を前記半導体基板上で配線を介して分散することによる再配置させた電極パッドを形成すると共に、前記半導体基板一主面の外周部近傍に、前記半導体基板を切断分離する際、切断位置の基準となる位置合わせマークを形成する工程と、
前記電極パッド上にハンダコアを形成する工程と、
少なくとも前記位置合わせマークを含む領域を露出し、かつ該露出領域より半導体基板の外周方向の領域に樹脂層が形成されるように、前記ハンダコアを形成した前記半導体基板の一主面を印刷法により樹脂封止する工程と、
該封止樹脂及び前記ハンダコアを研磨し、前記ハンダコアの一部を露出させる工程と、
前記半導体基板の別の一主面を研磨した後、該別の一主面に樹脂層を形成する工程と、
前記露出したハンダコア上にハンダバンプを形成する工程と、
前記露出する位置合わせマークを基準として前記半導体基板を切断分離し、個々の半導体装置に分割する工程とを含むことを特徴とする半導体装置の製造方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003325962A JP4326891B2 (ja) | 2003-09-18 | 2003-09-18 | 半導体装置の製造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003325962A JP4326891B2 (ja) | 2003-09-18 | 2003-09-18 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005093776A true JP2005093776A (ja) | 2005-04-07 |
JP4326891B2 JP4326891B2 (ja) | 2009-09-09 |
Family
ID=34456272
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2003325962A Expired - Fee Related JP4326891B2 (ja) | 2003-09-18 | 2003-09-18 | 半導体装置の製造方法 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4326891B2 (ja) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007294610A (ja) * | 2006-04-24 | 2007-11-08 | Sony Corp | 半導体装置の製造方法 |
KR101059625B1 (ko) * | 2008-06-09 | 2011-08-25 | 삼성전기주식회사 | 웨이퍼 레벨 칩 스케일 패키지 및 그 제조방법 |
CN107195618A (zh) * | 2016-03-15 | 2017-09-22 | 台湾积体电路制造股份有限公司 | 重布线路结构 |
WO2023021888A1 (ja) * | 2021-08-20 | 2023-02-23 | 株式会社村田製作所 | 電子部品モジュール |
-
2003
- 2003-09-18 JP JP2003325962A patent/JP4326891B2/ja not_active Expired - Fee Related
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007294610A (ja) * | 2006-04-24 | 2007-11-08 | Sony Corp | 半導体装置の製造方法 |
KR101059625B1 (ko) * | 2008-06-09 | 2011-08-25 | 삼성전기주식회사 | 웨이퍼 레벨 칩 스케일 패키지 및 그 제조방법 |
CN107195618A (zh) * | 2016-03-15 | 2017-09-22 | 台湾积体电路制造股份有限公司 | 重布线路结构 |
WO2023021888A1 (ja) * | 2021-08-20 | 2023-02-23 | 株式会社村田製作所 | 電子部品モジュール |
Also Published As
Publication number | Publication date |
---|---|
JP4326891B2 (ja) | 2009-09-09 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR100319609B1 (ko) | 와이어 어래이드 칩 사이즈 패키지 및 그 제조방법 | |
US6232666B1 (en) | Interconnect for packaging semiconductor dice and fabricating BGA packages | |
US7163843B2 (en) | Semiconductor component of semiconductor chip size with flip-chip-like external contacts, and method of producing the same | |
US7863757B2 (en) | Methods and systems for packaging integrated circuits | |
JP3796016B2 (ja) | 半導体装置 | |
TWI733049B (zh) | 半導體封裝及其製造方法 | |
JP4452235B2 (ja) | パッケージ構造とその製造方法 | |
JP2000068401A (ja) | 半導体装置およびその製造方法 | |
KR20080081341A (ko) | 몰드형 어레이 패키지에 통합 무선 주파수 차폐물을제공하는 방법 및 시스템 | |
JPH10275875A (ja) | 半導体装置 | |
JP2006303482A (ja) | 固体撮像装置の製造方法 | |
JP2006222121A (ja) | 半導体装置の製造方法 | |
US11721654B2 (en) | Ultra-thin multichip power devices | |
JP2001160597A (ja) | 半導体装置、配線基板及び半導体装置の製造方法 | |
JP4326891B2 (ja) | 半導体装置の製造方法 | |
JP4073308B2 (ja) | 回路装置の製造方法 | |
JP2014165388A (ja) | 半導体装置の製造方法 | |
JP3881658B2 (ja) | 中継部材、中継部材を用いたマルチチップパッケージ、及びその製造方法 | |
JP2013065582A (ja) | 半導体ウエハ及び半導体装置並びに半導体装置の製造方法 | |
US6551855B1 (en) | Substrate strip and manufacturing method thereof | |
JPH0562980A (ja) | 半導体装置およびその製造方法 | |
JP2007059493A (ja) | 半導体装置およびその製造方法 | |
KR20090127742A (ko) | 웨이퍼 레벨 칩 스케일 패키지 및 그 제조방법 | |
JP3359824B2 (ja) | Bga型半導体装置の製造方法 | |
KR102365004B1 (ko) | 반도체 패키지 및 그 제조 방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20060724 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20071207 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20071218 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20080206 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20090526 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20090610 |
|
FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120619 Year of fee payment: 3 |
|
R150 | Certificate of patent (=grant) or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
LAPS | Cancellation because of no payment of annual fees |