JP2005092489A - Data transfer circuit and electronic device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data transfer circuit capable of reducing load of a CPU at low costs and with simple structure without using DMA transfer and performing data transfer at high speed between a small memory medium and an electronic device, when the CPU not having so high clock frequency for operation is used. <P>SOLUTION: A data transfer circuit 1 transfers data from the small memory medium 5 connecting to the electronic device to a main memory 3. The data transfer circuit 1 reads data from the small memory medium 5, and writes the data in one FIFO memory selected among a plurality of FIFO memories. The data transfer circuit 1 selects a FIFO memory except the one FIFO memory for reading data and generates an interrupt signal S<SB>IN2</SB>. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a data transfer circuit used for transferring data between a small storage medium such as a compact flash (registered trademark) and an electronic device such as a digital still camera or a pachinko machine, and such a data transfer circuit. The present invention relates to an electronic device including

  A conventional data transfer circuit includes a program input / output unit that accesses an input / output device and generates an interrupt when the access is completed, and an interrupt handler. The interrupt handler is executed by the CPU (Central Processing Unit) and responds to the interrupt. The interrupt handler executes a programmed input / output sequence control function and data management function, which are executed by repeatedly using a program input / output unit, an interrupt, and an interrupt handler. By cooperation of these components, a large number of CPU input / output sequences are executed as if program input / output is being executed by a dedicated input / output processor (see, for example, Patent Document 1). Hereinafter, this technique is referred to as a first conventional example.

  The conventional data transfer circuit includes a sequence controller, a bidirectional (FIFO) memory interposed between the storage medium and the main memory, a first register for storing a normal end value, The second register that stores the state value indicating the state of the storage medium, the transfer request signal is output when the state value stored in the second register matches the normal end value stored in the first register, and the error signal when the two do not match Some of them are provided with a comparison circuit that outputs and a counter that counts every time data transfer of each segment of the storage medium is completed. The sequence controller allows and continues data transfer for each segment in sequence while the transfer request signal is supplied, and issues an interrupt request to the CPU and stops data transfer when an abnormal signal is supplied. (For example, refer to Patent Document 2). Hereinafter, this technique is referred to as a second conventional example.

JP-A-9-26928 ([0024] to [0034], FIG. 1, FIG. 6, FIG. 7) JP 2002-202948 A ([0014], [0015], FIG. 2)

As described above, in the first conventional example, the program input / output unit and the interrupt handler cooperate with each other, so that the program input / output is performed by the dedicated input / output processor as if the input / output of the CPU is large. The sequence is being executed. However, in the first conventional example described above, since the interrupt handler itself is executed by the CPU, if the frequency of the CPU operation clock is not so high, the time between the CPU cycles becomes long. As a result, the data transfer rate is lowered. Also, the burden on the CPU is not reduced much.
In this regard, in the second conventional example described above, since a direct memory access controller (DMAC) is used for data transfer to and from the main memory, generally, the burden on the CPU is small and high speed is achieved. Data transfer can be performed.

  However, when transferring data from a small storage medium such as a Compact Flash (registered trademark) to an electronic device, the access speed of the small storage medium itself is low, so the data transfer speed from the FIFO memory to the main memory is increased using DMAC. Even so, there is a problem that the substantial data transfer rate is not improved. The reason is shown below. That is, for this type of small storage medium, a NAND (NAND) type flash memory that is relatively inexpensive is used for reasons such as high integration and single power supply operation. Although this NAND flash memory is accessed in units of sectors, it takes a long time to start reading data from another sector after reading data from one sector. The typical data transfer rate is not improved. In addition, when the CPU used in the electronic device shares the main bus with the DMAC, the overhead due to arbitration of the main bus and the increase in waiting time during DMA transfer affect the real-time processing by the CPU. There was a problem of giving. Furthermore, the use of DMAC increases the circuit scale of the electronic device, and thus there is a problem that the price of the electronic device is increased.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide an inexpensive and simple configuration without using DMA transfer even when using a CPU whose operating clock frequency is not high. Thus, it is possible to obtain a data transfer circuit and an electronic device that can reduce the burden on the CPU and perform high-speed data transfer between the small storage medium and the electronic device.

A data transfer circuit according to the present invention is for transferring data from a small storage medium connected to an electronic device to the inside of the electronic device. The data is read from the small storage medium and selected from a plurality of FIFO memories. In addition to writing to the one FIFO memory, the FIFO memory for reading the data from other than the one FIFO memory is selected to generate an interrupt signal.
According to the present invention, since the CPU is not involved in the data transfer from the small storage medium to the data transfer circuit, the DMA transfer is not used even when the CPU having a low operating clock frequency is used for the electronic device. It is inexpensive and has a simple configuration, and the burden on the CPU is small. Data can be transferred between a small storage medium and an electronic device at high speed.

A data transfer circuit according to the present invention is for transferring data from a small storage medium connected to an electronic device to the inside of the electronic device, and reads data from a plurality of FIFO memories from the small storage medium. A memory control circuit that selects one FIFO memory for writing the data and selects an FIFO memory for reading the data from other than the one FIFO memory to generate an interrupt signal; and the small storage medium And a cycle generation circuit for reading out the data from the memory and writing it into the one FIFO memory.
According to the present invention, the memory control circuit selects one FIFO memory for writing the data read from the small storage medium from among the plurality of FIFO memories, and the data from other than the one FIFO memory. The FIFO memory for reading is selected and an interrupt signal is generated. On the other hand, the cycle generation circuit reads the data from the small storage medium and writes it to the one FIFO memory. Therefore, since the CPU is not involved in data transfer from the small storage medium to the data transfer circuit, even if a CPU with a low operating clock frequency is used for the electronic device, it is inexpensive and simple without using DMA transfer. With a simple configuration, the burden on the CPU is small, and data can be transferred between the small storage medium and the electronic device at high speed.

In the data transfer circuit according to the present invention, the memory control circuit includes a plurality of FIFO memories and a first value indicating that the data is stored corresponding to the plurality of FIFO memories, A status register in which one of the second values indicating that data is not stored is stored, and a first number indicating a FIFO memory in which the data to be read next time is stored are stored in the first register. When reading of data from the FIFO memory of the number is completed, the value of the status register corresponding to the first number is set to the second value, 1 is incremented to the first number, and the first A first control circuit for generating the interrupt signal when the value of the status register corresponding to the number 1 is the first value; The second number indicating the FIFO memory to be written is held, and when the data writing to the FIFO memory with the second number is completed, the value of the status register corresponding to the second number is set to the first value. When the value of the status register corresponding to the second number is the second value, an empty signal indicating that there is no data is set. And a second control circuit for generating.
According to the present invention, the first control circuit sets the value of the status register corresponding to the first number when the data reading from the held first number FIFO memory is completed. And 1 is incremented to the first number. When the value of the status register corresponding to the first number is the first value, the interrupt signal is generated. On the other hand, the second control circuit sets the value of the status register corresponding to the second number to the first value when the data writing to the FIFO memory having the second number held is completed. In addition, 1 is incremented to the second number, and an empty signal is generated when the value of the status register corresponding to the second number is the second value. Therefore, since the CPU is not involved in data transfer from the small storage medium to the data transfer circuit, even if a CPU with a low operating clock frequency is used for the electronic device, it is inexpensive and simple without using DMA transfer. With a simple configuration, the burden on the CPU is small, and data can be transferred between the small storage medium and the electronic device at high speed.

In the data transfer circuit according to the present invention, the cycle generation circuit sets a count value of an internal counter to a predetermined value when an interrupt signal is supplied from the small storage medium, and the memory control circuit When the empty signal indicating the absence of the data is supplied, the predetermined value of the counter reads the data from the small storage medium and supplies the data to the memory control circuit at a predetermined data transfer rate. There is a burst cycle generation circuit that performs as much as.
According to the present invention, the burst cycle generation circuit sets the count value of the internal counter to a predetermined value when an interrupt signal is supplied from the small storage medium, and confirms that there is no data from the memory control circuit. When the signal shown is supplied, the data is read from the small storage medium and supplied to the memory control circuit at a predetermined data transfer rate by the predetermined value of the counter. Therefore, since the CPU is not involved in data transfer from the small storage medium to the data transfer circuit, even if a CPU with a low operating clock frequency is used for the electronic device, it is inexpensive and simple without using DMA transfer. With a simple configuration, the burden on the CPU is small, and data can be transferred between the small storage medium and the electronic device at high speed.

An electronic device according to the present invention includes any of the data transfer circuits described above.
According to the present invention, since the CPU is not involved in data transfer from the small storage medium to the data transfer circuit, even when a CPU having a high operation clock frequency is used, it is inexpensive and simple without using DMA transfer. With a simple configuration, the burden on the CPU is small, and data can be transferred between the small storage medium and the electronic device at high speed.

FIG. 1 is a block diagram showing a state in which a small storage medium 5 is connected to a main part of an electronic apparatus provided with a data transfer circuit 1 in an embodiment of the present invention.
The electronic apparatus in this example includes a data transfer circuit 1, a CPU 2, and a main memory 3, and the data transfer circuit 1, the CPU 2, and the main memory 3 are connected to each other via a main bus 4. Further, the electronic apparatus of this example is configured so that the small storage medium 5 can be connected. The data transfer circuit 1 supports data transfer performed between the small storage medium 5 and the CPU 2 in the operation mode set by the CPU 2. The CPU 2 executes various programs stored in the main memory 3 and controls each part of the electronic device using various registers and flags secured in the main memory 3. The main memory 3 is composed of a semiconductor memory such as a RAM, a ROM, or a flash memory, and stores various programs and various data to be executed by the CPU 2 and is used for work when these programs are executed. . The small storage medium 5 is formed of a compact flash (registered trademark) or the like, and has a NAND type flash memory.

  The data transfer circuit 1 includes a cycle generation circuit 6 and a memory control circuit 7. The cycle generation circuit 6 operates so that the CPU 2 can directly access the small storage medium 5 when the CPU 2 sets the PIO mode (Programmed Input / Output mode), and when the burst mode is set by the CPU 2. A cycle for reading data for one sector (512 bytes) from the small storage medium 5 at a data transfer speed close to the fastest timing in the PIO mode 4 is generated. Here, the PIO mode is a kind of data transfer method in ATA (AT Attachment) which is an official standard of IDE (Integrated Drive Electronics) interface. The IDE interface is a standard for connecting a personal computer and a hard disk, which is used by the American National Standards Institute (ANSI). PIO modes are defined from PIO modes 0 to 4, with data transfer rates of 3.3 Mbytes / sec, 5.2 Mbytes / sec, 8.3 Mbytes / sec, 11.1 Mbytes / sec, and 16.7 Mbytes / sec, respectively. Can transfer data. Most of recent compact flash (registered trademark) comply with PIO mode 4. On the other hand, the burst mode is a mode relating to burst transfer in which the data transfer operation from the small storage medium 5 to the data transfer circuit 1 is continuously performed without the CPU 2 being involved. The memory control circuit 7 performs data transfer between the plurality of FIFO memories and the small storage medium 5 via the cycle generation circuit 6 in the burst mode.

  Next, the configuration of the cycle generation circuit 6 will be described with reference to the block diagram shown in FIG. The cycle generation circuit 6 includes an interface circuit 11 to 13, a control register 14, a status polling circuit 15, a command circuit 16, a media cycle generation circuit 17, an interrupt detection circuit 18, and a burst cycle generation circuit 19. It is configured. The control register 14 includes an operation mode register 21, an LBA (Logical Block Address) register 22, a transfer sector number register 23, a command register 24, and a status register 25. The operation mode register 21 is supplied with and stores values corresponding to various operation modes such as a PIO mode and a burst mode set by the CPU 2 from the CPU 2. The LBA register 22 is supplied with the LBA address in the burst mode from the CPU 2 and stored therein. Here, LBA is originally one of addressing methods in a hard disk having a current general IDE interface, and a number is assigned in order to each unit block to be accessed, and the number is designated. And how to select an address. This LBA is also applied to a flash memory constituting the small storage medium 5. The LBA address is an address assigned based on the LBA. A hard disk having an IDE interface is divided into sectors each having 512 bytes as one sector, and LBA addresses are assigned in order from the head. Also in the small storage medium 5 of this example, as in the case of the hard disk, it is assumed that 512 bytes is divided into one sector and LBA addresses are assigned in order from the head.

  In the transfer sector number register 23, the total number of sectors to be transferred in the burst mode (hereinafter referred to as the transfer sector number) is supplied from the CPU 2 and stored. In the command register 24, a command that the CPU 2 desires to transfer to the small storage medium 5 is supplied from the CPU 2 and stored in the PIO mode. Further, the command register 24 is supplied with a read command for reading data from the small storage medium 5 in the burst mode and is stored therein. The status register 25 is supplied with status information indicating the current state of the small storage medium 5 from the small storage medium 5 and stored therein. The status information stored in the status register 25 is configured to be readable by the CPU 2.

The status polling circuit 15 reads the status information of the small storage medium 5 via the media cycle generation circuit 17 and the interface circuit 13, and when the status information indicates that the small storage medium 5 can be used, the command circuit 16 is supplied with a ready signal _SRE . On the other hand, when the status information indicates that the small storage medium 5 is unusable, the status polling circuit 15 periodically checks until the small storage medium 5 becomes usable or a preset time elapses. Thus, the status information of the small storage medium 5 is read through the media cycle generation circuit 17 and the interface circuit 13.

When the preparation completion signal S _RE is supplied from the status polling circuit 15, the command circuit 16 receives the LBA address and the transfer from the LBA register 22, the transfer sector number register 23, and the command register 24 that constitute the control register 14. The number of sectors and command are read, the number of transfer sectors is stored in the internal count register 26, and the LBA address as the address AD is set in the small storage medium 5 via the media cycle generation circuit 17 and the interface circuit 13, and "1" is set. After supplying the set number of transfer sectors, a command is supplied as a command CMD. The command circuit 16, the burst cycle generator 19, 1 if the sector sector read end signal S _SR indicating that the data transfer is completed in is supplied, the value "0 the count value of the count register 26 When the count value is “0”, the supply of the address AD, the number of transfer sectors set to “1”, and the command CMD to the small storage medium 5 is terminated. On the other hand, when the count value of the count register 26 when the sector read end signal _SSR is supplied from the burst cycle generation circuit 19 is not the value “0”, the command circuit 16 calculates the value “ After the number obtained by subtracting 1 ”is reset as a new count value in the count register 26, the address AD and the number of transfer sectors set to“ 1 ”are set in the small storage medium 5 via the media cycle generation circuit 17 and the interface circuit 13. Is supplied, then the command CMD is supplied.

  The media cycle generation circuit 17 supplies status information supplied from the small storage medium 5 via the interface circuit 13 to the status polling circuit 15 in response to a request from the status polling circuit 15, and LBA supplied from the command circuit 16. The address AD and the number of transfer sectors set to “1”, the command CMD, and the chip select signal CS are supplied to the small storage medium 5 via the interface circuit 13. In the burst mode, the media cycle generation circuit 17 supplies 16-bit parallel data DT supplied from the small storage medium 5 via the interface circuit 13 to the burst cycle generation circuit 19. Further, in the burst mode, the media cycle generation circuit 17 generates an address AD, a command CMD, and a chip select signal CS in order to synchronize the cycle generated internally and the cycle generated by the burst cycle generation circuit 19. This is supplied to the circuit 19.

Interrupt detection circuit 18 monitors whether an interrupt signal S _IN1 is supplied from the small storage medium 5 via the interface circuit 13, when the interrupt signal S _IN1 is supplied, the burst transfer supplying a burst signal S _BS for instructing the start to the burst cycle generation circuit 19. The burst cycle generation circuit 19 is enabled (activated) when the burst enable signal BE is supplied from the control register 14. When the burst signal _SBS is supplied, the burst cycle generation circuit 19 sets the count value of the internal cycle counter 27 to the value “255”. Also, the burst cycle generating circuit 19 which is enabled, a value indicating that the empty signal S _EM from the memory control circuit 7 is supplied via the interface circuit 12 is no data "1", and the media cycle generator When the address AD, command CMD, and chip select signal CS supplied from 17 are decoded and recognized as a data read cycle, a write signal WR for instructing data writing is generated in synchronism with the clock to generate a memory. A 16-bit parallel is supplied to the control circuit 7 via the interface circuit 12 and at a data transfer speed close to the fastest timing in the PIO mode 4 via the interface circuit 13 and the media cycle generation circuit 17 from the small storage medium 5. Data DT and the interface circuit 1 The supply of 16-bit parallel data DT to the memory control circuit 7 through the performed by the amount of the count value of the cycle counter 27 (256 times). Then, the burst cycle generation circuit 19, 1 if the sector of data transfer has been completed, supplies the sector read end signal S _SR indicating that the command circuit 16.

Next, the configuration of the memory control circuit 7 will be described with reference to the block diagram shown in FIG. The memory control circuit 7 includes interface circuits 31 and 32, FIFO memories 33 _{1 to} 33 _n (n is a natural number of 2 or more), a status register 34, control circuits 35 and 36, a CPU bus selector 37, and a media bus. And a selector 38. The FIFO memories 33 _{1 to} 33 _n each have a storage capacity of 512 bytes and are enabled (activated) by the corresponding write signals WR _{1 to} WR _n supplied from the media bus selector 38, and then synchronized with a certain clock. Similarly, the corresponding 16-bit parallel data DT _{1 to} DT _n supplied from the media bus selector 38 is stored in the first-in first. The FIFO memories 33 _{1 to} 33 _n are enabled (activated) by corresponding read signals RE _{1 to} RE _n supplied from the CPU bus selector 37 and then synchronized with a separate clock that is asynchronous with the clock. The parallel data stored therein is read out in advance, and supplied to the CPU bus selector 37 as data CDT _{1 to} CDT _n having the same bit width as the CPU 2 bus width (for example, 32 bits or 64 bits). The FIFO memories 33 _{1 to} 33 _n are collectively referred to as the FIFO memory 33.

The status register 34 has a bit width of n bits and indicates whether or not data is stored in the _n FIFO memories 33 _{1 to} 33 _n with a value “0” (a state where data is stored) (first state) Value) or “1” (a state in which no data is stored) (second value). Note that when the data transfer circuit 1 is reset, the status register 34 is initialized to all values “1” (a state in which no data is stored).

The control circuit 35 has a number (hereinafter referred to as a read block number) assigned to a FIFO memory 33 _i (1 ≦ i ≦ n) in which data to be read out next time by the CPU 2 is stored in its internal number register 39. .) I (first number) is stored, and the read block number i is supplied to the CPU bus selector 37. The control circuit 35 is read from the CPU bus selector 37, when the read end signal S _RED indicating that reads all the data from the FIFO memory 33 _i of the read block number i is supplied, the currently selected The value of the status register 34 corresponding to the block number i is set to a value “1” indicating that no data is stored, and 1 is incremented to the read block number i stored in the number register 39. When the read block number i stored in the number register 39 becomes the value “n + 1”, the read block number i is reset to the value “0”. Further, the control circuit 35 reads the value of the bit corresponding to the value of the read block number i from the status register 34, and if the value is the value “0” (a state where data is stored), the control circuit 35 interrupts. A signal S _IN2 is generated and supplied to the CPU ₂ . The interrupt signal S _IN2 can be returned to the inactive state when the CPU ₂ supplies a command.

The CPU bus selector 37 selects the FIFO memory 33 _i corresponding to the read block number i supplied from the control circuit 35 and supplies a read signal RE _i for enabling the FIFO memory 33 _i . It is connected to the main bus 4 (see FIG. 1) via the interface circuit 31. Further, CPU bus selector 37, when CPU2 monitors the reading data from the FIFO memory 33 _i, the reading of all the data from the FIFO memory 33 _i of the read block number i is completed, indicating that A read end signal S _RED is supplied to the control circuit 35.

The control circuit 36 has a number (hereinafter referred to as a write block) assigned to the FIFO memory 33 _j (1 ≦ j ≦ n, j ≠ i) to which the cycle generation circuit 6 is to write data next time in the internal number register 40. J (second number) is stored, and the write block number j is supplied to the media bus selector 38. When the write end signal S _WED indicating that all the data has been written is supplied from the media bus selector 38 to the FIFO memory 33 _j of the write block number j, the control circuit 36 writes the currently selected write. The value of the status register 34 corresponding to the block number j is set to a value “0” indicating that data is stored, and 1 is incremented to the write block number j stored in the number register 40. When the write block number j stored in the number register 40 reaches the value “n + 1”, the write block number j is reset to the value “0”. Further, the control circuit 36 reads the value of the bit corresponding to the value of the write block number j from the status register 34, and when the value is the value “1” (a state in which no data is stored), the data is supplies the cycle generation circuit 6 generates a empty signal S _EM value "1" indicating no.

When the write signal WR is supplied from the cycle generation circuit 6 via the interface circuit 32, the media bus selector 38 selects the FIFO memory 33 _j corresponding to the write block number j supplied from the control circuit 36 described above. Then, the write signal WR _j for enabling the FIFO memory 33 _j is supplied and connected to the bus connected to the cycle generation circuit 6. The media bus selector 38, when the cycle generation circuit 6 monitors the write data into the FIFO memory 33 _j, writing of all data in the FIFO memory 33 _j of the write block number j has been completed, the A write end signal S _WED indicating this is supplied to the control circuit 36.

  Next, the operation of the electronic apparatus having the above configuration will be described. The CPU 2 accesses the interface circuit 13 via the main bus 4, the interface circuit 11 and the control register 14 that constitute the cycle generation circuit 6. Further, the CPU 2 supplies a value corresponding to the PIO mode or the burst mode to the operation mode register 21 constituting the control register 14 via the main bus 4 and the interface circuit 11, whereby the data in the small storage medium 5 is stored in the PIO mode. Transfer in mode or burst mode. Note that the CPU 2 initializes each register constituting the control register 14 when the system is started up, such as when the electronic device is powered on, and then sets the small storage medium 5 to the PIO mode 4.

Next, the operation of the electronic device in the burst mode will be described. The CPU 2 supplies a burst enable signal BE from the control register 14 to the burst cycle generation circuit 19 by supplying a value corresponding to the burst mode to the operation mode register 21 of the control register 14 constituting the cycle generation circuit 6. After enabling the burst cycle generation circuit 19, the LBA address is supplied to the LBA register 22, the transfer sector number is supplied to the transfer sector number register 23, and the read command is supplied to the command register 24. As a result, the status polling circuit 15 reads the status information of the small storage medium 5 and supplies the ready signal S _RE to the command circuit 16 when the status information indicates that the small storage medium 5 is usable. To do. On the other hand, when the status information indicates that the small storage medium 5 is unusable, the status polling circuit 15 periodically checks until the small storage medium 5 becomes usable or a preset time elapses. Thus, the status information of the small storage medium 5 is read out.

When the completion signal S _RE is supplied from the status polling circuit 15, the command circuit 16 reads the LBA address from the LBA register 22, the transfer sector number from the transfer sector number register 23, and the read command from the command register 24. . Next, the command circuit 16 stores the number of transfer sectors in the internal count register 26, and stores the LBA address as the address AD and “1” in the small storage medium 5 via the media cycle generation circuit 17 and the interface circuit 13. After the number of transfer sectors set to "" is supplied, a read command is supplied. After the address AD, the number of transfer sectors set to “1”, and the read command are supplied to the small storage medium 5, the interrupt detection circuit 18 determines whether or not the interrupt signal S _IN1 is supplied from the small storage medium 5. or the monitoring, when the interrupt signal S _IN1 is supplied, supplies a burst signal S _BS to the burst cycle generation circuit 19. The media cycle generation circuit 17 supplies an address AD, a command CMD, and a chip select signal CS to the burst cycle generation circuit 19 in order to synchronize the cycle generated internally and the cycle generated by the burst cycle generation circuit 19. To do.

On the other hand, the control circuit 36 of the memory control circuit 7 supplies the write block number j stored in the internal number register 40 to the media bus selector 38 and corresponds to the value of the write block number j from the status register 34. the value of the bit in the case of the first value ( "1") supplies the empty signal S _EM value "1" indicating that there is no data in the cycle generator 6. The media bus selector 38 selects the FIFO memory 33 _j corresponding to the write block number j supplied from the control circuit 36 and connects it to the bus connected to the cycle generation circuit 6.

Accordingly, when the burst signal _SBS is supplied, the burst cycle generation circuit 19 of the enabled cycle generation circuit 6 sets the count value of the cycle counter 27 to the value “255” and then is supplied from the control circuit 36. When the empty signal _SEM is “1” and the address AD, the command CMD, and the chip select signal CS supplied from the media cycle generation circuit 17 are decoded and recognized as a data read cycle, the write signal WR is generated in synchronization with the clock, supplied to the memory control circuit 7 via the interface circuit 12, and 16-bit parallel data DT from the small storage medium 5 at a data transfer speed close to the fastest timing in the PIO mode 4 And 16-bit parallel data to the memory control circuit 7 T the supply of, performed by the amount of the count value of the cycle counter 27 (256 times). In the memory control circuit 7 to which the write signal WR is supplied from the cycle generation circuit 6, the media bus selector 38 selects the FIFO memory 33 _j corresponding to the write block number _j and supplies the write signal WR _j to the FIFO memory 33 _j. Therefore, 16-bit parallel data DT _i supplied from the cycle generation circuit 6 is sequentially stored in the FIFO memory 33 _j via the media bus selector 38. When the data transfer for one sector is completed, the burst cycle generation circuit 19 supplies a sector read end signal _SSR to the command circuit 16.

The command circuit 16 to which the sector read end signal _SSR is supplied compares the count value of the count register 26 with the value “0”, and when the count value is the value “0”, the address to the small storage medium 5 Supply of AD and the number of transfer sectors set to “1” and the read command is terminated. On the other hand, when the count value of the count register 26 when the sector read end signal _SSR is supplied from the burst cycle generation circuit 19 is not the value “0”, the command circuit 16 calculates the value “ After the number obtained by subtracting “1” is reset as a new count value in the count register 26, the address AD and the number of transfer sectors set to “1” are supplied to the small storage medium 5, and then the read command is supplied. .

On the other hand, the media bus selector 38 of the memory control circuit 7 monitors the data writing to the FIFO memory 33 _j by the cycle generation circuit 6, and when all the data has been written to the FIFO memory 33 _j of the write block number j. In this case, the write end signal S _WED is supplied to the control circuit 36. The control circuit 36 supplied with the write end signal S _WED sets the value of the status register 34 of the write block number j to the value “0” and sets 1 to the write block number j stored in the number register 40. Increment. Then, when the value of the bit corresponding to the value of the write block number j read from the status register 34 is the value “1”, the control circuit 36 sends the empty signal _SEM having the value “1” to the cycle generation circuit. 6 is supplied.

On the other hand, the control circuit 35 supplies the read block number i stored in the internal number register 39 to the CPU bus selector 37, and the value of the bit corresponding to the value of the read block number i is received from the status register 34. If it is the second value (value “0”), an interrupt signal S _IN2 is generated and supplied to the CPU ₂ . The CPU bus selector 37 selects the FIFO memory 33 _i corresponding to the read block number i supplied from the control circuit 35 and supplies the read signal RE _i to the FIFO memory 33 _i and also via the interface circuit 31. Connected to the main bus 4 (see FIG. 1).

Therefore, the CPU 2 reads data from the FIFO memory 33 _i of the read block number i via the main bus 4, the interface circuit 31, and the CPU bus selector 37, and sequentially stores them in the main memory 3 via the main bus 4. The CPU bus selector 37 monitors that the CPU 2 reads data from the FIFO memory 33 _{i of the} read block number i, and when reading of all data from the FIFO memory 33 _i of the read block number i is completed, A read end signal S _RED is supplied to the control circuit 35. The control circuit 35 to which the read end signal S _RED is supplied sets the value of the status register 34 of the read block number i to the value “1” and sets 1 to the read block number i stored in the number register 39. Increment. When the value of the bit corresponding to the value of the read block number i read from the status register 34 is the value “0”, the control circuit 35 generates an interrupt signal S _IN2 and supplies it to the CPU _2. .

The above-described data writing to the FIFO memory 33 _j corresponding to the write block number j and the data reading from the FIFO memory 33 _i corresponding to the read block number i are repeated separately and sequentially. Is called. When the data transfer in the burst mode corresponding to the number of transfer sectors requested by the CPU 2 is completed, the cycle generation circuit 6 stops its operation. Note that the operation of the electronic device in the PIO mode is substantially the same as in the conventional case, and a description thereof will be omitted.

  Next, a specific operation of the data transfer circuit 1 having the above configuration will be described with reference to a timing chart shown in FIG. The cycle generation circuit 6 generates each signal in synchronization with a clock CK having a frequency shown in FIG. 4A of 66.66 MHz (period: 15 nsec). FIG. 4B shows an address AD (for example, 3 bits A0 to A2) that the command circuit 16 supplies to the small storage medium 5 via the media cycle generation circuit 17 and the interface circuit 13, and its setup time is 30 nsec. (2 clocks CK). FIG. 4C shows a case where the CPU 2 sets a read command in the command register 24 in order to read the data DT stored in the small storage medium 5, thereby reading data supplied to the small storage medium 5 via the interface circuit 13. The signal RO (one of the command CMD) has a pulse width of 75 nsec (5 clocks CK). Therefore, the cycle time of the small storage medium 5 in this case is 120 nsec (equivalent to eight clocks of the clock CK), similarly to the cycle time of data reading in the PIO mode 4.

FIG. 4D shows 16-bit parallel data DT read from the small storage medium 5. FIG. 4E shows write data DT _j written in the FIFO memory 33 _j of a certain write block number j that constitutes the memory control circuit 7. FIG. 4F shows a write signal WR _j generated by the media bus selector 38 to write the write data DT _j into the FIFO memory 33 _j having the write block number j. The write signal WR _j becomes active at the rising edge of the first clock CK when the read signal RO shown in FIG. 4C becomes inactive, and the write signal WR _j corresponds to the required number of clocks CK (however, the small storage medium 5 After the cycle time, it becomes inactive.
The write data DT _j shown in FIG. 4 (e) is latched at the rising edge of the read signal RO shown in FIG. 4 (c) and then synchronized with the write signal WR _j shown in FIG. 4 (f). The data is sequentially written into the FIFO memory 33 _j with the number j.

As described above, according to the configuration of this example, the data writing to the FIFO memory 33 _j corresponding to the write block number j and the data reading from the FIFO memory 33 _i corresponding to the read block number i are: Each is repeated separately and sequentially. Therefore, the CPU 2 performs the data reading process from the FIFO memory 33 _i corresponding to the read block number i while the data writing process to the FIFO memory 33 _j corresponding to the write block number j is being performed. Since other processing can be executed, the burden is reduced. In the data writing process from the small storage medium 5 to the FIFO memory 33 of the memory control circuit 7, the timing is automatically generated by the cycle generation circuit 6 which is hardware, so that the frequency of the operation clock of the CPU is Even if it is not so high, data can be transferred at a higher speed than when the CPU 2 transfers data in the PIO mode.

In the data transfer according to the configuration of this example, since the CPU 2 performs the data reading process from the FIFO memory 33 _i corresponding to the read block number i, the CPU is completely involved in the data transfer as in the second conventional example. However, the CPU 2 is not involved in the data writing process to the FIFO memory 33 _j corresponding to the write block number j. Therefore, the data transfer according to the configuration of this example can be called a pseudo DMA transfer. However, in the data transfer according to the configuration of this example, since the DMAC is not used, the circuit scale of the electronic device can be reduced and the price thereof can be reduced. Since the bus 4 is not shared, there is no overhead due to arbitration for the exclusive use of the main bus 4 or an increase in waiting time during DMA transfer. Therefore, the real-time processing by the CPU 2 is not affected at all.

The embodiment has been described in detail with reference to the drawings. However, the specific configuration is not limited to the embodiment, and there are design changes and the like without departing from the scope of the invention. Are also included in the present invention.
For example, in the above-described embodiment, an example in which a compact flash (registered trademark) is used as the small storage medium 5 has been described, but the present invention is not limited to this. The small storage medium may be any medium that uses a NAND type flash memory. Examples of this type of small storage medium include Smart Media (registered trademark), SD (Secure Digital (registered trademark)) memory card, and Memory Stick (registered trademark). However, the interface specification of the data transfer circuit 1 needs to be an interface specification adapted to each small storage medium.

In the above-described embodiment, an example is shown in which data transfer is performed in the PIO mode 4 in the burst mode. However, the present invention is not limited to this, and any one of the PIO modes 0 to 4 can be selected by a program. Also good.
In the above-described embodiments, specific examples of electronic devices are not specifically shown. For example, pachinko machines, pachinko slot machines and other gaming machines, PDAs (Personal Digital Assistants), various FAs (factories)・ Automation) Industrial equipment such as instruments and various measuring instruments, consumer equipment such as DVD recorders and digital still cameras, and other relatively small electronic devices that handle a certain amount of data using a small storage medium Any thing is good.

In the above-described embodiment, specific examples of data to be transferred are not specifically shown. For example, still image data compressed in JPEG (joint photographic experts group) format or other formats, MPEG ( Moving Picture Expert Group) format and other compressed video data, OS and various driver program data, and data created by various application programs.
In the above-described embodiment, an example is shown in which the electronic device is configured so that only one small storage medium 5 can be connected. However, the present invention is not limited to this, and the electronic device has two small storage media 5. It may be configured to be connectable (two or more slots). In this case, the control register 14 constituting the cycle generation circuit 6 needs to be provided with a register for storing a drive number for identifying the small storage medium 5 inserted in each slot.

It is a block diagram which shows the state by which the small storage medium was connected to the principal part of the electronic device provided with the data transfer circuit in embodiment of this invention. It is a block diagram which shows the structure of the cycle generation circuit which comprises a data transfer circuit. It is a block diagram which shows the structure of the memory control circuit which comprises a data transfer circuit. 6 is a timing chart for explaining an example of the operation of the data transfer circuit.

Explanation of symbols

1 data transfer circuit, 2 CPU, 3 main memory, 4 main bus, 5 small storage medium, 6 cycle generation circuit, 7 memory control circuit, 11-13, 31, 32 interface circuit, 14 control register, 15 status polling circuit, 16 command circuit, 17 media cycle generation circuit, 18 interrupt detection circuit, 19 burst cycle generation circuit, 21 operation mode register, 22 LBA register, 23 transfer sector number register, 24 command register, 25 status register, 26 count register, 27 Cycle counter, 33, 33 _{1 to} 33 _n FIFO memory, 34 status register, 35 control circuit (first control circuit), 36 control circuit (second control circuit), 37 CPU bus selector, 38 media bus selector, 39 , 40 number Register.

Claims (5)

A data transfer circuit for transferring data from a small storage medium connected to an electronic device to the inside of the electronic device,
Reading the data from the small storage medium and writing it to one selected FIFO memory, and selecting an FIFO memory for reading the data from other than the one FIFO memory and generating an interrupt signal A data transfer circuit characterized by the above. A data transfer circuit for transferring data from a small storage medium connected to an electronic device to the inside of the electronic device,
One FIFO memory for writing the data read from the small storage medium is selected from among a plurality of FIFO memories, and a FIFO memory for reading the data from other than the one FIFO memory is selected and allocated. A memory control circuit for generating an embedded signal;
A data transfer circuit comprising: a cycle generation circuit that reads the data from the small storage medium and writes the data to the one FIFO memory. The memory control circuit includes:
The plurality of FIFO memories;
A status register that stores either a first value indicating that the data is stored or a second value indicating that the data is not stored, corresponding to the plurality of FIFO memories;
The status register corresponding to the first number is stored when the first number indicating the FIFO memory in which the data to be read next time is stored and data reading from the FIFO memory of the first number is completed Is set to the second value, 1 is incremented to the first number, and if the value of the status register corresponding to the first number is the first value, the A first control circuit for generating an embedded signal;
The second number indicating the FIFO memory to which the data is to be written next time is held, and when the data writing to the FIFO memory having the second number is completed, the value of the status register corresponding to the second number is set. Set to the first value, increment 1 to the second number, and if the value of the status register corresponding to the second number is the second value, there is no data The data transfer circuit according to claim 2, further comprising: a second control circuit that generates an empty signal indicating   The cycle generation circuit sets the count value of an internal counter to a predetermined value when an interrupt signal is supplied from the small storage medium, and an empty signal indicating that there is no data is supplied from the memory control circuit A burst cycle generating circuit for reading the data from the small storage medium and supplying the data to the memory control circuit by the predetermined value at a predetermined data transfer rate when 4. The data transfer circuit according to claim 2, wherein the data transfer circuit is provided. An electronic apparatus comprising the data transfer circuit according to claim 1.

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