JP2005091505A - Display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the power consumption of a liquid crystal display device by improving a precharge system for a panel. <P>SOLUTION: The display device consists of a panel wherein a pixel array section 2 and a peripheral circuit section for driving the pixel array section are formed on one and the same substrate 1. The pixel array section 2 comprises scanning lines X arranged in a row shape, signal lines Y arranged in a column shape, and pixels PXL arranged in matrix corresponding to the intersections of each scanning line X and signal line Y. The peripheral circuit section is provided with a vertical drive circuit 3 for successively scanning the scanning lines X and selecting pixel PXL for each row, a horizontal drive circuit 4 for writing an image signal on the pixel PXL of the selected row via the signal line Y to display an image, and a precharge circuit 5 for preliminarily impressing a precharge signal to the signal line Y before writing the image signal so as to improve the quality of the image. On the panel, a voltage holding/supplying circuit 6 including a capacitor that stores the voltage for the precharge signal, is formed and supplies the voltage for the precharge signal to the precharge circuit 5 inside the panel. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an active matrix type display device in which peripheral circuit portions are formed on the same substrate. More specifically, the present invention relates to a technique for improving a precharge circuit included in a peripheral circuit unit.

A conventional active matrix display device includes a panel in which a pixel array portion and a peripheral circuit portion for driving the pixel array portion are formed on the same substrate. The pixel array unit includes scanning lines arranged in rows, signal lines arranged in columns, and pixels arranged in a matrix (matrix shape) corresponding to the intersections of the scanning lines and the signal lines. It is configured. On the other hand, the peripheral circuit section sequentially scans the row-like scanning lines and selects the pixels for each row, and writes the video signal to the pixels in the selected row via the column-like signal lines. And a horizontal driving circuit for displaying. In recent years, a panel including a precharge circuit has been developed. The precharge circuit preliminarily applies a precharge signal to the columnar signal lines before writing the video signal in order to improve the image quality.
JP-A-8-69013

  Conventionally, a precharge signal is supplied to the panel from the outside in the same manner as a video signal. For example, when an LCD panel is used as a display for various devices, a precharge signal is supplied from the device body to the panel. For this reason, it has a structure in which current always flows from the device main body to the panel side. Since a high voltage such as a video signal (video signal) or a power supply voltage is input to the panel in addition to the precharge signal, a large current flows from the main body side to the panel, resulting in an increase in power consumption as a whole system.

  In view of the above-described problems of the conventional technology, an object of the present invention is to improve the precharge method of the panel and reduce the power consumption of the display device. The following measures were taken in order to achieve this purpose. That is, the pixel array unit and a peripheral circuit unit for driving the pixel array unit are formed on a same substrate, and the pixel array unit includes scanning lines arranged in rows and signal lines arranged in columns. A vertical driving circuit that includes pixels arranged in a matrix corresponding to the intersections of the scanning lines and the signal lines, and the peripheral circuit section sequentially scans the row-like scanning lines and selects the pixels for each row. A horizontal drive circuit for displaying an image by writing a video signal to the pixels in the selected row via a column-shaped signal line, and a column-shaped circuit before writing the video signal to improve the image quality of the image. In a display device including a precharge circuit that preliminarily applies a precharge signal to a signal line, a voltage holding and supply circuit including a capacitor that stores a voltage for the precharge signal is formed on the panel. The precharge times inside the panel The voltage for the precharge signal, characterized in that that can be supplied to.

  Preferably, the precharge circuit applies the precharge signal to each signal line during a blanking period other than a period for writing a video signal, and the voltage holding and supplying circuit charges and discharges the capacitor in accordance with the blanking period. To control. The pixel includes a liquid crystal cell, a thin film transistor connected to the scanning line and the signal line and writing a video signal to the liquid crystal cell, and a thin film capacitor holding the video signal written to the liquid crystal cell. Have the same layer structure as the thin film capacitor and are formed simultaneously.

  According to the present invention, a large-capacity precharge signal voltage holding and supplying circuit is built in the peripheral circuit portion of the panel constituting the active matrix display device. This voltage holding and supplying circuit includes a large-capacity thin film capacitor. A voltage obtained by periodically charging the large-capacity capacitor is used as a precharge signal. Thereby, reduction of the power consumption of a panel is realizable.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a schematic block diagram showing a preferred embodiment of a display device according to the present invention. As shown in the figure, this display device is composed of a panel in which a pixel array section 2 and a peripheral circuit section for driving the pixel array section 2 are formed on the same substrate 1. The pixel array unit 2 includes scanning lines X arranged in rows, signal lines Y arranged in columns, and pixels PXL arranged in a matrix corresponding to the intersections of the scanning lines X and the signal lines Y. It consists of and. On the other hand, the peripheral circuit portion is arranged so as to surround the central pixel array portion 2. The peripheral circuit unit includes a vertical drive circuit 3, a horizontal drive circuit 4, and a precharge circuit 5. The vertical drive circuit 3 sequentially scans the row-like scanning lines X and selects the pixels PXL for each row. In the present embodiment, the vertical drive circuits 3 are arranged on both the left and right sides of the substrate 1 and drive the row-shaped scanning lines X simultaneously from both sides. The horizontal drive circuit 4 writes an image signal to the pixels PXL in the selected row via the column-shaped signal line Y and displays an image. In the present embodiment, the horizontal drive circuit 4 is connected to the upper end side of the column-shaped signal line Y. The precharge circuit 5 preliminarily applies a precharge signal to the columnar signal lines Y before writing a video signal in order to improve the image quality of the image displayed on the pixel array unit 2. In the present embodiment, the precharge circuit 5 is connected to the lower end side of the column-shaped signal line Y. An external connection terminal 7 is also formed at the upper end of the substrate 1.

  As a feature of the present invention, a voltage holding and supply circuit 6 including a capacitor for storing a precharge signal voltage is formed in the panel, and the precharge signal voltage is supplied to the precharge circuit 5 inside the panel. doing. The large-capacitance capacitor included in the voltage holding and supplying circuit 6 can be appropriately formed in an empty portion of the peripheral circuit portion so as not to press the area occupied by the central pixel array portion 2. In the present embodiment, the precharge circuit 5 applies a precharge signal to each signal line Y during a blanking period other than a period during which a video signal is written. The voltage holding and supplying circuit 6 controls charging / discharging of the capacitor in accordance with the blanking period. The panel of the present embodiment is an LCD (liquid crystal display). That is, each pixel PXL includes a liquid crystal cell LC, a thin film transistor TFT that is connected to the scanning line X and the signal line Y and writes a video signal to the liquid crystal cell LC, and a thin film capacitor Cs that holds the video signal written in the liquid crystal cell LC. Consists of. On the other hand, the large-capacitance capacitor included in the voltage holding and supplying circuit 6 has the same layer configuration as the thin film capacitor Cs of the pixel and is formed at the same time.

  The gate electrode of the thin film transistor TFT is connected to the corresponding scanning line X. The source electrode of the TFT is connected to the corresponding signal line Y. The drain electrode of the TFT is connected to the pixel electrode of the corresponding liquid crystal cell LC. The liquid crystal cell LC is composed of liquid crystal held between the pixel electrode and the counter electrode. The counter electrode is formed on another substrate facing the substrate 1. The thin film capacitor Cs is also called an auxiliary capacitor, and one electrode thereof is connected to the drain electrode of the TFT, while the other electrode is connected to a predetermined potential.

  As is apparent from the above description, in the present invention, a large capacity capacitor for precharging is added inside the LCD panel to constitute a voltage holding and supplying circuit for precharging. The signal line is precharged using the voltage stored in the large capacitor. A large-capacitance capacitor used in the precharge voltage holding and supplying circuit formed in the peripheral circuit portion of the LCD panel can be formed by the same process as the auxiliary capacitor Cs formed in each pixel. Further, the other parts of the voltage holding and supplying circuit 6 can be formed simultaneously with the vertical driving circuit 3, the horizontal driving circuit 4 and the precharge circuit 5 by a normal process, so that the number of processes is not increased. By disposing the large-capacitance capacitor in the lower empty corner of the substrate 1, for example, the large-capacitance capacitor can be disposed so as not to overlap with the pixel array section 2 and other circuits included in the peripheral circuit section in the layout.

  FIG. 2 is a circuit diagram showing a specific configuration of the voltage holding and supplying circuit 6 shown in FIG. As shown in the figure, the voltage holding and supplying circuit 6 includes a constant resistor Rsw, a capacitor C, a resistor R, a switch SW, and the like. The constant resistance Rsw and the resistance R are connected in series between the power supply voltage level and the ground level via the switch SW. In this example, the power supply voltage VDD is 15 V, for example, and the ground voltage GND is 0 V, for example. The capacitor C is connected to both ends of the resistor R. The output voltage of the voltage holding and supplying circuit 6 is obtained from the connection point between the constant resistance Rsw and the resistance R. The output voltage is adjusted to a desired level by the capacitor C and the resistor R with the power supply voltage VDD as an input. This output voltage is held as a precharge signal by holding its potential by charging for a certain period by a holding circuit using a large-capacitance capacitor C. The charging period is set corresponding to the blanking period, and corresponds to both the horizontal scanning and vertical scanning blanking periods. According to this configuration, it is possible to reduce the steady current consumption by supplying the precharge signal input from the device main body (system) side in the panel. A reduction in power consumption can be realized with a steady reduction in current consumption.

  The precharge signal usually requires a plurality of potential levels. The voltage holding and supplying circuit shown in FIG. 2 is incorporated in the panel according to the number of necessary potential levels. In this case, the lower the output voltage is compared with the power supply voltage VDD, the more discharge through the resistor R. Therefore, the capacity of the capacitor C must be increased to compensate for this. Further, the longer the precharge period, the larger the capacitance of the capacitor C is required to supply a stable output voltage.

  FIG. 3 is a schematic diagram showing a cross-sectional structure of the TFT and the capacitor C shown in FIG. In the TFT, a semiconductor thin film 11 such as polycrystalline silicon formed on the substrate 1 is used as an element region, and a gate electrode G made of a semiconductor thin film 13 such as polycrystalline silicon is formed thereon via an insulating film 12. The TFT having such a structure is covered with a first interlayer insulating film 14, and a metal wiring 15 is formed thereon. One metal wiring 15 is connected to the drain D of the TFT through a contact hole formed in the first interlayer insulating film 14. The other metal wiring 15 is connected to the source S of the TFT through a contact hole formed in the first interlayer insulating film 14. The metal wiring 15 is a part of the signal line Y. A metal wiring 15 made of aluminum or the like is covered with a second interlayer insulating film 16, and a pixel electrode 17 is formed thereon. The pixel electrode 17 is connected to the metal wiring 15 on the drain side through a contact hole formed in the second interlayer insulating film 16.

  On the other hand, the large-capacitance capacitor C has a thin film structure like the thin film transistor TFT and can be formed simultaneously with the TFT. In the illustrated example, the large-capacitance capacitor C has a configuration in which the insulating film 12 in the same layer as the gate insulating film is a dielectric, and the upper and lower sides thereof are held by a pair of electrodes. The lower electrode is the same layer as the semiconductor thin film 11 constituting the element region of the TFT. The upper electrode is the same layer as the semiconductor thin film 13 constituting the gate electrode of the TFT. The lower electrode is connected to the ground potential GND through the metal wiring 15. The upper electrode is connected to the output terminal (OUT) via another metal wiring 15. Note that the auxiliary capacitor Cs formed in the pixel also has the same layer configuration as the large-capacitance capacitor C. In other words, the large-capacitance capacitor C has the same layer configuration as the thin film capacitor Cs of the pixel portion and is formed at the same time.

  FIG. 4 is a circuit diagram showing a part of the precharge circuit 5 shown in FIG. The precharge circuit receives supply of voltages PsigBH and PsigBL necessary for precharge from the voltage holding supply circuit 6. The precharge circuit includes a pair of transmission gate elements TG1 and TG2, and alternately selects PsigBH and PsigBL in accordance with a periodic signal FRP supplied from the outside and its inverted signal to obtain a synthesized signal PsigB. Yes.

  As shown in the waveform diagram, in PsigB, a high voltage level PsigBH and a low voltage level PsigBL appear alternately in a predetermined cycle. The predetermined cycle corresponds to a horizontal scanning period or a vertical scanning period. In general, the polarity of a video signal written in a liquid crystal display element is switched in one horizontal period or one vertical period. Accordingly, the polarity of the precharge signal also needs to be switched, and the precharge signal PsigB is obtained by combining PsigBH and PsigBL. The precharge signal PsigB is supplied in order to make the leak amount between the pixel electrode and the signal line separated by the TFT constant before writing the video signal in the pixel in advance. The precharge signal applied to the signal line for this purpose requires a voltage having a large absolute value for both positive polarity and negative polarity. In the case of a normally white mode display device, the level required for the precharge signal PsigB is a black level.

  As other precharge signals, PsigG is required in addition to PsigB. The precharge signal PsigG is set to an intermediate level (gray level) between the white level and the black level, and the uniformity of the image is improved by precharging the signal line with an intermediate level potential in advance. . PsigG also requires two levels of high and low in accordance with the polarity inversion of the video signal, and is supplied from the voltage holding and supplying circuit having the configuration shown in FIG.

  FIG. 5 is a circuit diagram showing another part of precharge circuit 5 shown in FIG. The illustrated circuit is controlled by the control signals PCG and PRG, and combines the gray level precharge signal PsigG and the black level precharge signal PsigB formed in the previous stage to generate a final precharge signal Psig. Supply to the wire. As shown in the figure, this circuit includes NAND gate elements NAND1 and NAND2, inverter elements INV1 and INV2, and transmission gate elements TG3 and TG4.

  FIG. 6 is a timing chart for explaining the operation of the precharge circuit shown in FIG. As described above, the horizontal drive circuit samples the video signal Vsig on each signal line, while the precharge circuit applies the precharge signal Psig to each signal line. As shown in the figure, the video signal Vsig is divided into a blanking period and a video period. Further, the polarity is inverted with respect to the center voltage (for example, 7.5 V) every predetermined period (for example, one horizontal period). The first control signal PCG is high level H during the blanking period and low level L during the video period. The control signal PCG controls the precharge circuit so as to execute precharge when it is high. The second control signal PRG is high level H in the first half of the blanking period and low level L in the second half. The control signal PRG switches between a black level precharge signal and a gray level precharge signal. When PRG is H, a black level precharge signal is selected. As described above, the precharge circuit in FIG. 5 is controlled according to the control signals PCG and PRG, and applies the final precharge signal Psig to the signal line for each blanking period. In accordance with the polarity inversion of the video signal Vsig, the polarity of Psig is also inverted. In the example shown in the figure, a positive potential PsigBH (for example, 12.5 V) is first applied at the black level during the first blanking period, and then a positive potential gray level potential PsigGH (for example, 10.0 V) is applied. In the next blanking period, a negative black level PsigBL (for example, 2.5 V) is first applied, and subsequently a negative gray level PsigGL (for example, 5.5 V) is applied. The waveform of the precharge signal Psig described above is merely an example, and the present invention is not limited to this.

  As described above, according to the present invention, a large-capacity precharge signal voltage holding and supplying circuit is incorporated in the panel. By generating the precharge signal inside the panel, steady current consumption can be reduced. Accordingly, the present invention can be used in display devices for the purpose of reducing power consumption.

It is a block diagram which shows the whole structure of the display apparatus which concerns on this invention. FIG. 2 is a circuit diagram illustrating a specific configuration example of a voltage holding and supplying circuit incorporated in the display device illustrated in FIG. 1. It is a typical fragmentary sectional view which shows the structure of the high capacity | capacitance capacitor | condenser incorporated in a voltage holding supply circuit. FIG. 2 is a circuit diagram showing a pre-stage portion of a precharge circuit incorporated in the display device shown in FIG. 1. It is a circuit diagram of the back | latter stage part integrated in a precharge circuit. 6 is a timing chart for explaining the operation of the precharge circuit shown in FIG. 5.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Substrate, 2 ... Pixel array part, 3 ... Vertical drive circuit, 4 ... Horizontal drive circuit, 5 ... Precharge circuit, 6 ... Voltage holding supply circuit, 7 ... ·Connecting terminal

Claims (3)

It consists of a panel in which the pixel array part and the peripheral circuit part that drives it are formed on the same substrate,
The pixel array unit includes scanning lines arranged in rows, signal lines arranged in columns, and pixels arranged in a matrix corresponding to intersections between the scanning lines and the signal lines.
The peripheral circuit section sequentially scans row-shaped scanning lines to select pixels for each row, and writes video signals to the pixels in the selected rows via column-shaped signal lines. In a display device comprising a horizontal driving circuit for displaying and a precharge circuit for preliminarily applying a precharge signal to a column-shaped signal line before writing the video signal in order to improve the image quality of the image,
The panel is provided with a voltage holding and supplying circuit including a capacitor for storing the voltage for the precharge signal, and the voltage for the precharge signal can be supplied to the precharge circuit inside the panel. Display device. The precharge circuit applies the precharge signal to each signal line during a blanking period other than a period for writing a video signal,
The display device according to claim 1, wherein the voltage holding and supplying circuit controls charging and discharging of the capacitor in accordance with the blanking period. The pixel includes a liquid crystal cell, a thin film transistor connected to the scanning line and the signal line and writing a video signal to the liquid crystal cell, and a thin film capacitor holding the video signal written to the liquid crystal cell,
The display device according to claim 1, wherein the capacitor has the same layer configuration as the thin film capacitor and is formed at the same time.

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