JP2005084999A - Device and method for controlling cache memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To increase process efficiency by reducing power consumption of a cache memory. <P>SOLUTION: When data to be read is being read from a processor, a cache memory control device 1 detects whether or not the data expected to be read subsequently is cached. When the data expected to be read subsequently is stored in the cache, it is stored in a look-ahead cache part 20; when it is not stored in the cache, it is read from an external memory and stored in the look-ahead cache part 20. Thereafter, when the address of the data actually read from the processor in a subsequent cycle matches the address of the data stored in the look-ahead cache part 20, the data is outputted from the look-ahead cache part 20 to the processor. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a cache memory control device and a cache memory control method provided for efficiently transferring data between a processor and a memory device.

Conventionally, a cache memory is used in order to speed up a process in which a processor reads data on a memory device such as a main memory.
The cache memory is configured by a storage element that can read data at high speed by a processor. The cache memory stores a part of data stored in the memory device (hereinafter referred to as “memory device data” as appropriate), and when the processor reads data from the memory device, the cache memory If the data is stored in the cache memory, the data can be read at high speed by reading from the cache memory.

Here, there are various cache memory systems, but the set associative system is common.
The set associative method is a method that can improve the hit rate by dividing the cache memory into a plurality of areas (way) and storing data of different addresses on the memory device in each way. It is.

FIG. 12 is a schematic diagram showing a configuration of a conventional set-associative cache memory 100. As shown in FIG.
In FIG. 12, the cache memory 100 includes a tag table 110, a data memory 120, a hit detection unit 130, and a multiplexer (MUX) 140. In the cache memory 100, a plurality of N elements can be stored in the storage area, and each of these elements is referred to as an “entry”. The cache memory 100 is a two-way set associative method, and each entry stores two memory device data (way A and way B data).

  The tag table 110 stores address information indicating at which address on the memory device the memory device data of the ways A and B in the data memory 120 is stored. The address information stored in the tag table 110 is referred to by a hit detection unit 130, which will be described later, and is used to determine whether or not the cache is hit.

The data memory 120 stores predetermined memory device data such as frequently accessed data. The data memory 120 can store memory device data corresponding to each of the ways A and B.
The hit detection unit 130 detects whether or not the memory device data stored in the cache memory 100 has hit in response to a read command from the processor. Specifically, the address information stored in the tag table 110 is referred to, and when the address information corresponding to the address indicated in the read command from the processor is detected, it is determined that the cache is hit. Then, the hit detection unit 130 outputs information indicating the hit way to the MUX 140.

The MUX 140 selects any memory device data output from the data memory 120 based on the information indicating the way input from the hit detection unit 130, and outputs data to the processor (data read by the processor). ).
In such a set associative method, when an entry address (an address for selecting one of the entries stored in the cache memory) is input from the processor, a tag is assigned to each of the plurality of ways in the cache memory 100. Access to table 110 and data memory 120 to detect if data hits.

For this reason, access to unnecessary portions in the cache memory 100 increases, and there is a problem that power consumption increases or processing efficiency decreases.
Here, various proposals have been made to solve the problems in the conventional cache memory including the cache memory 100 as described above.
Japanese Patent Laid-Open No. 11-39216 discloses a set associative cache memory having a plurality of ways in which a memory device is interleaved and accessed in order to reduce a delay until the output of the data memory is determined Is disclosed.

For the same purpose, Japanese Patent Laid-Open No. 2002-328839 discloses a method for predicting a way by associative memory. Furthermore, in Japanese Patent Laid-Open Nos. 2000-112820 and 2000-347934, as a technique for predicting cache hits in advance, when a processor reads instructions, the instructions are often read from consecutive addresses. A technique for predicting subsequent instructions using the above tendency is disclosed.
Japanese Patent Laid-Open No. 11-39216 JP 2002-328839 A JP 2000-112820 A JP 2000-347934 A

However, all of the techniques described in the above-mentioned publications are techniques for reducing an access delay with respect to read data.
That is, in the technique described in the above-mentioned publication, it is difficult to solve the problem of increasing power consumption or reducing processing efficiency due to an increase in access to unnecessary portions in the cache memory. Met.

  An object of the present invention is to reduce power consumption in a cache memory and improve processing efficiency.

In order to solve the above problems, the present invention provides:
A memory device storing data to be read by a processor (for example, an external memory in the best mode for carrying out the invention), and at least part of the stored data is divided into a plurality of ways (for example, the invention). In the best mode for implementing the above, a cache memory control device that is cached in a cache memory including ways A and B) and can supply the cached data to the processor, the data being read being read by the processor Cache determination means (for example, the access management unit 10 and the tag table 30 in FIG. 1) for determining whether or not the scheduled data that is expected to be read after is cached in any way of the cache memory; And the cache determination means causes the scheduled data to be sent to any way. When it is determined that the schedule data is cached, a prefetch cache means (for example, access management in FIG. 1) that accesses the way in which the schedule data is stored and reads and stores the schedule data. Unit 10 and a prefetch cache unit 20), wherein the prefetch cache means outputs the stored plan data to a processor when the plan data is read after the data being read. Yes.

  With such a configuration, data that is considered to be read after the data being read by the processor can be stored in advance in the prefetch cache means and output to the processor, and the data can be output from the cache memory. When reading, it is possible to prevent access to unnecessary ways. That is, it is possible to solve the problem that an increase in power consumption or a decrease in processing efficiency due to an increase in access to an unnecessary portion in the cache memory.

  Further, the cache memory includes address storage means for storing addresses of data cached for the plurality of ways, and data storage means for storing data corresponding to each of the addresses, The cache determination means determines whether or not the schedule data is cached according to whether or not the address of the schedule data is stored in any of the ways of the address storage means. Of the plurality of ways of the data storage means, the way corresponding to the way of the address storage means storing the address of the scheduled data is accessed.

  With such a configuration, it is possible to determine whether or not the scheduled data hits the cache by accessing the address storage means, so the data storage means is accessed when determining whether or not the cache hits the cache. By doing so, it is possible to reduce unnecessary power consumption. Further, since the data storage means can access only the way where the scheduled data is stored, it is possible to further reduce the power consumption.

The scheduled data is data that is expected to be read immediately after the data being read (for example, data at an address subsequent to the address of the data being read).
Therefore, only the data that is expected to be read next to the data being read only needs to be processed such as whether it is cached and stored in the prefetch cache means, so that the processing efficiency can be improved.

Further, the data to be read by the processor is configured as a block including a plurality of words, and whether or not the scheduled data is cached or the scheduled data is read in units of the block. It is said.
With this configuration, it is not necessary for the processor to execute a read command for each of a plurality of words, and the entire block can be read with a single read command, thus reducing power consumption and improving processing efficiency. It becomes possible to make it.

The cache determination means determines whether the scheduled data is cached in response to the processor instructing to read the last word among the plurality of words constituting the data being read. It is characterized by that.
In general, it is more likely that the scheduled data will be hit when it is predicted at the timing when the word after the data being read is read by the processor.

Therefore, with such a configuration, data read into the processor with higher probability can be prefetched as scheduled data.
The cache determination means determines whether the scheduled data is cached in response to the processor instructing to read the word preceding the last word among the plurality of words constituting the data being read. It is characterized by determining whether or not.

With such a configuration, it is possible to determine whether or not the scheduled data is cached at an earlier timing, so that the processing when it is not cached (for example, processing to read from the memory device) can be performed earlier, and the wait It is possible to prevent the occurrence of cycles or reduce the number of wait cycles that occur.
Further, the prefetch cache means, when the cache judgment means judges that the scheduled data is cached in any way, the processor reads the end of the plurality of words constituting the data being read. In response to the instruction to read the word, the way in which the schedule data is stored is accessed to read the schedule data.

  With such a configuration, even when it is determined whether the schedule data is cached at an earlier timing, the schedule data can be actually read at a timing when the probability that the schedule data is read is increased. Therefore, since the rate at which the scheduled data stored in the prefetch cache means is not read by the processor can be reduced, it is possible to prevent a reduction in processing efficiency.

Further, the present invention is characterized by further comprising a power consumption reduction means for operating a way not related to data reading among a plurality of ways in the cache memory with low power consumption.
With such a configuration, it is possible to reduce power consumption of unnecessary portions and further reduce power consumption of the cache memory control device.

Further, the low power consumption means is characterized by having a clock gating function for controlling so that a clock signal is not supplied to a way not related to data reading.
With such a configuration, unnecessary power consumption generated by supplying a clock signal to unnecessary portions can be reduced.

Further, the cache memory is a set associative cache memory.
With this configuration, in the set associative cache memory, consumption caused by unnecessary access to the address storage means (tag table) and data storage means (data memory) of each way included in the entry The power can be greatly reduced and the processing efficiency can be improved.

The prefetch cache unit accesses the memory device and reads the scheduled data when the cache determining unit determines that the scheduled data is not cached in any way of the cache memory. It is characterized by memorizing.
With this configuration, when the scheduled data is not cached, the process of reading the scheduled data from the memory device can be performed more quickly, so that the generation of wait cycles can be prevented or the generated wait cycles can be reduced. Is possible.

The present invention also provides:
A method for caching at least a part of stored data in a cache memory including a plurality of ways from a memory device storing data to be read by the processor and supplying the cached data to the processor A cache memory control method for determining whether or not scheduled data expected to be read after the data being read being read by the processor is cached in any way of the cache memory, In the cache determination step, when it is determined that the scheduled data is cached in any way, the way in which the scheduled data is stored is accessed from among the plurality of ways, and the scheduled data Read-ahead cache to read and store And step, by the processor, when the schedule data is read after the read in data, is characterized in that it comprises an output step of outputting the schedule data stored in the read-ahead cache step processor.

  Thus, according to the present invention, it is possible to reduce the power consumption in the cache memory and improve the processing efficiency.

Hereinafter, an embodiment of a cache memory control device according to the present invention will be described with reference to the drawings.
First, the configuration will be described.
FIG. 1 is a diagram showing a configuration of a cache memory control device 1 to which the present invention is applied.
In FIG. 1, the cache memory control device 1 includes an access management unit 10, a prefetch cache unit 20, a tag table 30, a data memory 40, a hit detection unit 50, and a MUX 60.

FIG. 2 is a diagram showing a configuration of data stored in the tag table 30 and the data memory 40. (a) is a configuration of data in the tag table 30, and (b) is a data memory 40. The structure of the data in is shown.
Hereinafter, the configuration of the cache memory control device 1 will be described with reference to FIG. 1, and FIG. 2 will be referred to as appropriate. Here, it is assumed that the cache memory control device 1 is a two-way (way A, B) set associative method.

The access management unit 10 controls the cache memory control device 1 as a whole, and operates the cache memory control device 1 in accordance with a state transition diagram to be described later.
For example, when the data at the address indicated in the read command is stored in the prefetch cache unit 20 based on the read command input from the processor, the access management unit 10 transmits the data corresponding to the address to the processor. The data to be continuously read is predicted, and the predicted data is stored in the processor prefetch buffer 22 of the prefetch cache unit 20.

  On the other hand, when the data at the address indicated in the read command is not stored in the prefetch cache unit 20, the access management unit 10 refers to the tag table 30. When the address is stored in the tag table 30, the access management unit 10 stores data corresponding to the address from the data memory 40 to the processor prefetch buffer 22.

When the address indicated in the read command is not stored in the tag table 30, the access management unit 10 accesses the external memory and stores data at the address in the external memory prefetch buffer 23 of the prefetch cache unit 20. Let
The prefetch cache unit 20 receives a read command input from the processor and outputs an address indicated by the read command to the access management unit 10. In addition, the prefetch cache unit 20 reads and stores data predicted to be read by the processor in advance from the data memory 40 or the external memory in accordance with an instruction from the access management unit 10, and when the data is actually read from the processor The data is output to the processor.

Specifically, the prefetch cache unit 20 includes an address control unit 21, a processor prefetch buffer 22, and an external memory prefetch buffer 23.
The address control unit 21 acquires the address of data to be read from the read command input from the processor, and outputs it to the access management unit 10. Further, the address control unit 21 outputs an address to be read to the tag table 30 and the data memory 40 when reading the data cached in the data memory 40, or is cached in the data memory 40. When reading out non-existing data from the external memory, the read target address is output to the external memory.

The address control unit 21 is instructed to read data (read ahead) from the access management unit 10 and stores the address of the data in the tag table 30. The address is output only to the way in which the data is stored.
As a result, the number of accesses to unnecessary ways can be reduced, power consumption can be reduced, and processing efficiency can be improved.

The processor prefetch buffer 22 receives the data read from the data memory 40 via the MUX 60 and stores it as data to be output to the processor.
The external memory prefetch buffer 23 receives data read from the external memory and stores it as data to be output to the processor. Further, the data stored in the external memory prefetch buffer 23 is stored in the data memory 40 at a clock timing at which processing is not performed in the cache memory control device 1.

  As shown in FIG. 2A, the tag table 30 has a cache hit for data stored in the data memory 40 for each entry (0 to 511, where the number of entries is N = 512). And a flag indicating whether or not, and an address on the external memory in which the data stored in the data memory 40 is stored. Each entry stores flags and addresses corresponding to the ways A and B. By referring to the address stored in the tag table 30, it is possible to determine whether or not the data in the data memory 40 has hit the cache.

  The data memory 40 stores predetermined memory device data for each entry. The data memory 40 treats 4 words as one block, and when reading data from the data memory 40, reads 4 words (w0 to w4) of any way included in the entry as one group. Is possible. However, it is also possible to read out some words (for example, words w1 to w3) in one block.

  The hit detection unit 50 determines whether or not the memory device data stored in the data memory 40 has been hit when the address indicated in the read command is input from the address control unit 21 to the tag table 30. Is detected. Specifically, each address stored in the tag table 30 is referred to, and when an address input from the address control unit 21 is detected, it is determined that the cache is hit. Then, the hit detection unit 50 outputs information indicating the hit way to the MUX 60.

The MUX 60 receives information indicating the hit way from the hit detection unit 50 and receives memory device data from the storage area of each way in the data memory 40. Then, the MUX 60 selects memory device data corresponding to the way input from the hit detection unit 50 and outputs it to the processor prefetch buffer 22.
Next, the operation will be described.

The cache memory control device 1 performs state transition corresponding to a predetermined operation mainly under the control of the access management unit 10.
First, the basic operation of the cache memory control device 1 will be described.
In the basic operation of the cache memory control device 1, it is expected that the address of the last word of the memory device data to be read is read with reference to the tag table 30 at the timing when it is output from the processor. Whether data (hereinafter referred to as “planned data”) hits the cache is detected (prefetched). Therefore, since the cache can be prefetched for data that is highly likely to be read, the data hit rate in the prefetch cache unit 20 can be improved.

FIG. 3 is a state transition diagram showing the basic operation of the cache memory control device 1.
In FIG. 3, the cache memory control device 1 transitions between states S1 to S4, and transition conditions C1 to C12 for transitioning between the states are defined.
In the state S1 (ST-PRC-NORMAL), when the scheduled data is stored in the processor prefetch buffer 22 (when the prefetch cache is hit), the data is output to the processor in units of blocks.

In the state S1, if the scheduled data is not stored in the processor prefetch buffer 22, the tag table 30 and the data memory 40 are accessed based on the read target address, and coincide with the address. The state shifts to a state of reading data from the data memory 40 (ST-PREREAD-ACTIVE).
Further, in the state S1, the cache reading (reading of the data memory 40) is not performed until the reading of the last word in the block of data read from the external memory is completed.

In the state S2 (ST-PREREAD-ACTIVE), based on the address of the scheduled data, only the tag table 30 is accessed, and when it matches the address stored in the tag table 30 (cache hit), that address Is read from the data memory 40.
In the state S3 (ST-CACHE-HIT-TEST), the tag table 30 and the data memory 40 are accessed, and it is detected whether or not the address of the scheduled data matches the address of the tag table 30. In the state S3, data corresponding to the address that matches the address of the scheduled data is read from the data memory 40.

  In the state S4 (ST-EXMEM-ACCESS), the state machine “sm-exmem-access” (see FIG. 4) for reading the external memory is activated to read the external memory. The timing of transition from the state S4 to another state is the time when reading of one word is completed, and the end of the operation of the state machine “sm-exmem-access” is not waited. That is, in other states, a wait cycle (wait-cycle) for waiting for reading from the external memory may occur.

In the transition condition C1 (CND-PRA-START), in the state S1, the address of the last word of the data to be read (the word with the end of the address expressed in hexadecimal number “C”) is input from the processor. It means that.
The transition condition C2 (CND-PRA-END) means that if no wait cycle occurs in the state S2, the state returns to the state S1 in the next cycle.

The transition condition C3 (CND-CHT-START) means a case where the scheduled data does not hit the prefetch cache (stored in the processor prefetch buffer 22) in the state S1.
The transition condition C4 (CND-CHT-CNT) is a condition for continuing the state S3. In other words, since the scheduled data is not stored in the prefetch cache unit 20, it is a condition for continuously checking the cache hit by accessing the tag table 30 and the data memory 40. For branch instructions, if the branch destination address is at the end of the block and is in state S3, the first word of the block is accessed in the next cycle, so the prefetch cache is not hit continuously. On the other hand, it is determined that the prefetch cache is a miss hit.

  The transition condition C5 (CND-CHT-PRA) is a condition for making a transition from the state S3 to the state S2. That is, since the scheduled data is not stored in the prefetch cache unit 20, only the tag table 30 is accessed and the cache hit is confirmed from the state where the cache hit is confirmed by accessing the tag table 30 and the data memory 40. It is a condition for making a transition to a state to perform. For the branch instruction, if the branch destination address is the second from the end of the block (the word expressed as a hexadecimal number with the end of the address “8”) and is in the state S3, in the next cycle Since the data at the end of the block is accessed, that is, the state transits to the state S2, the state directly transits to the state S2 without returning to the state S1.

In the transition condition C6 (CND-CHT-END), in the state S3, the branch destination address is the head and the second of the block (the word whose hexadecimal address ends with “0” or “4”). In this case, if the prefetch cache is hit, it means that the process returns to the state S1.
The transition condition C7 (CND-EMA-START) means a case in which no cache is hit in the state S3 (when data to be read is not stored in the data memory 40).

The transition condition C8 (CND-PRA-EMA) means a case where the cache is not hit in the state S2.
The transition condition C9 (CND-PRA-CHT) means a case where the prefetch cache is not hit in the state S2.
The transition condition C10 (CND-NORM-CNT) means a case where the prefetch cache is hit or an external memory is accessed in the state S1.

The transition condition C11 (CND-PRA-CNT) means a case where the prefetch process is continued in the state S2.
The transition condition C12 (CND-EMA-END) means a case where access to the external memory is completed in the state S4.
Next, the state machine “sm-exmem-access” for reading the external memory will be described.

FIG. 4 is a state transition diagram showing the operation of the state machine “sm-exmem-access” constructed on the cache memory control device 1.
In FIG. 4, the cache memory control device 1 transitions between states T1 to T6.
In state T1 (ST-WAIT), access to the external memory is stopped. In the state T1, the state transitions to the state T2 at a predetermined timing.

In the state T2 (ST-EXMEM-READ-1W-S), when the first word of the data to be read is read from the external memory and the reading process is completed, the process proceeds to the state T3.
In the state T3 (ST-EXMEM-READ-1W-E-2W-S), when the second word of the data to be read is read from the external memory and the reading process is completed, the process proceeds to the state T4.

In the state T4 (ST-EXMEM-READ-2W-E-3W-S), when the third word of the data to be read is read from the external memory and the reading process is completed, the process proceeds to the state T5.
In the state T5 (ST-EXMEM-READ-3W-E-4W-S), when the fourth word of the data to be read is read from the external memory and the reading process is completed, the process proceeds to the state T6.

In the state T6 (ST-EXMEM-READ-4W-E), the process returns to the state T1 in response to the completion of the process of reading the fourth word of the data to be read from the external memory.
As a result of transitioning between the states as shown in FIGS. 3 and 4, the cache memory control device 1 specifically performs the following operation according to the data read by the processor.
First, an example will be described in which data read by the processor continuously hits the prefetch cache.

FIG. 5 is a timing chart showing an operation example when data read by the processor hits the prefetch cache continuously.
FIG. 5 shows a case where data of consecutive addresses (data of addresses “A00 to A0C”, “A10 to A1C” and “A20 to A2C”) is read by the processor. Hereinafter, data indicated by addresses “A00 to A0C”, “A10 to A1C”, and “A20 to A2C” are referred to as first to third data, respectively.

In FIG. 5, the address of the last data in the first data (address “A0C”) is input from the processor (cycle “4”), and the address of the second data that is the scheduled data is the tag table 30. Is input to each way.
Then, at the next clock timing (cycle “5”), the addresses stored in the respective ways of the tag table 30 are output, and whether these addresses match the address of the second data or not. In this case, since they match, it is detected that the cache is hit (CACHE-HIT = 1). At this time, the address of the second data is assumed to be the way in which the second data of the data memory 40 is stored (here, the way A indicated by a solid line in FIG. 5). The way B in which the second data is not stored is indicated by a dotted line (the same applies hereinafter) (WAYA-DATA-ADRS, WAYB-DATA-ADRS).

  At the subsequent clock timing (cycle “6”), the data of the way storing the second data (WAYA-TAG-DATA, WAYB-TAG-DATA) is output from the data memory 40, and The hit detection unit 50 outputs information (WAY-SELECT) for selecting any way. As a result, the memory device data (data “D10”) of the selected way is output to the processor (PBUS-RDDATA).

That is, the cache memory control device 1 outputs the corresponding memory device data in cycle “6” in response to the read command from the processor executed in cycle “5”.
In addition, since the memory device data can be read in block units in the cache memory control device 1, by reading the data “D10”, other data (data “D14” to “D1C”) in the same block are also collected. Are read out and stored in the processor prefetch buffer 22. As a result, the three words following the data “D10” are output from the processor prefetch buffer 22 to the processor in succession to the data “D10” without accessing the tag table 30 and the data memory 40 to read each. Will be.

The cache memory control device 1 prefetches the third data by the process as described above while outputting the second data to the processor, and similarly outputs the third data to the processor.
Next, an example in which data read by the processor does not hit the prefetch cache will be described.
FIG. 6 is a timing chart showing an operation example when the data read by the processor does not hit the prefetch cache. The data names and signal names in FIG. 6 are the same as those in FIG.

In FIG. 6, the operation up to cycle “6” is almost the same as the operation up to cycle “6” shown in FIG. However, the first word of the second data read in cycle “5” is a branch instruction, and the instruction is executed in cycle “6”.
In cycle “7”, since the data of the branch destination address “A44” is not stored in the processor prefetch buffer 22, it is detected that the prefetch cache is not hit (PRC-HIT = 0). At this time, since the cache memory control device 1 supplies data without waiting, in order to output the memory device data “D44” corresponding to the address “A44” in the next cycle, the tag table 30 and the data memory The address of the block including the word of address “A44” (hereinafter referred to as “branch destination data”) is output to each of the 40 ways.

  In cycle “8”, the address (WAYA-TAG-DATA, WAYB-TAG-DATA) stored in each way is output from the tag table 30 and the data of each way is output from the data memory 40. (WAYA-TAG-DATA, WAYB-TAG-DATA) is output. At this time, since the address stored in each way of the tag table 30 matches the address of the branch destination data, it is detected that the cache is hit (CACHE-HIT = 1). Further, the hit detection unit 50 outputs information (WAY-SELECT) for selecting any way. As a result, the memory device data (data “D44”) of the selected way is output to the processor (PBUS-RDDATA).

That is, the cache memory control device 1 outputs the corresponding memory device data in cycle “8” in response to the branch destination read instruction from the processor executed in cycle “7”.
Here, since the branch destination address “A44” is the second word of the block, in the cache memory control device 1, the second to fourth words (address “A44˜ “A4C”) are read together and stored in the processor prefetch buffer 22.

Thereafter, the cache memory control device 1 prefetches the subsequent data and outputs it to the processor while outputting the branch destination data to the processor in the same manner as the processing in FIG.
Next, an example in which data read by the processor does not hit the prefetch cache or the cache will be described.
FIG. 7 is a timing chart showing an operation example when the data read by the processor does not hit the prefetch cache or the cache. The data names and signal names in FIG. 7 are the same as in FIG.

In FIG. 7, the operation up to the cycle “7” is the same as the operation up to the cycle “7” shown in FIG.
In cycle “8”, the address (WAYA-TAG-DATA, WAYB-TAG-DATA) stored in each way is output from the tag table 30 and the data of each way is output from the data memory 40. (WAYA-TAG-DATA, WAYB-TAG-DATA) is output. At this time, since the address stored in each way of the tag table 30 does not match the address of the branch destination data, it is detected that the cache is not hit (CACHE-HIT = 0).

Then, since the data at the address “A44” cannot be read, the cache memory control device 1 reads the data from the external memory. Therefore, a wait cycle is generated for three cycles until data can be taken from the external memory.
Note that the cache memory control device 1 sequentially stores the branch destination data fetched from the external memory in the external memory prefetch buffer 23. At this time, in order to fetch data from the external memory, two cycles are required for each word (data “D44 to D48”) unlike the case of the cache. Then, after storing the branch destination data in the external memory prefetch buffer 23, the cache memory control device 1 prefetches the subsequent data and outputs it to the processor in the same manner as in the processing in FIG. The branch destination data stored in the external memory prefetch buffer 23 is cached in the data memory 40 at a timing when the data memory 40 is not accessed. Further, when the data fetched from the external memory is stored in the external memory prefetch buffer 23 and a read command for the data is input from the processor, the data stored in the external memory prefetch buffer 23 is output to the processor. Is done.

Next, an example will be described in which the data read by the processor is data at consecutive addresses, but prefetching cannot be performed (the cache is not hit). In such a case, it is necessary to fetch the scheduled data from the external memory.
FIG. 8 is a timing chart showing an operation example when the data read by the processor does not hit the cache even though the data is continuous address data. Note that the data names and signal names in FIG. 8 are the same as those in FIG.

In FIG. 8, the operations of cycles “4 to 5” are substantially the same as the operations of cycles “6 to 7” shown in FIG. However, in the case of FIG. 8, access to the external memory is immediately started in cycle “5” in which it is detected that the cache is not hit.
Then, after three cycles after accessing the external memory (cycle “8”), each word of the scheduled data is sequentially fetched from the external memory.

That is, the data in the external memory is output to the processor after three cycles with respect to the cycle “5” in which the address (address “A10”) of the data to be read is input from the processor.
As a result, the data in the external memory can be fetched at a timing earlier by one cycle than in the conventional case where it is detected whether or not the cache hits after the address of the data to be read is input from the processor. It becomes possible. That is, in the conventional method, four cycles are required from when a read command is input from the processor to when data is output to the processor, but in FIG. 8, the number is shortened to three cycles.

  In the description of FIGS. 3 to 8, the timing of detecting whether or not the scheduled data hits the cache (prefetching), the address of the last word of the memory device data to be read is output from the processor. Although it has been described that it is timing, prefetching may be performed at the timing when the address of the first word of memory device data to be read is input from the processor. In this case, although the probability that the prefetched data is actually read from the processor is lowered, the penalty of the wait cycle can be reduced when the cache is not hit.

The operation when prefetching is performed at the timing when the address of the first word of the memory device data to be read is input from the processor (hereinafter referred to as “prefetching prefetch processing”) will be described.
FIG. 9 is a state transition diagram showing the operation of the prefetching process.
In FIG. 9, the cache memory control device 1 transitions between states P1 to P4 and states P5 and P6, and transition conditions G1 to G14 are defined for transitioning between the states.

Note that states P1 to P4 and transition conditions G2 to G12 in FIG. 9 are the same as states S1 to S4 and transition conditions C2 to C12 in FIG.
The state P5 (ST-PREREAD-IDLE) is an idle state for delaying the timing. That is, when prefetching is performed at the timing when the address of the first word of the block is input from the processor, in order to eliminate the “shift” in which the timing for fetching data to be read into the processor prefetch buffer 22 is too early, The idle state of the cycle is inserted.

In the state P6 (ST-PREREAD-EXE), data is transferred from the data memory 40 to the processor prefetch buffer 22.
The transition condition G1 (CND-PRA-F-START) indicates that in the state P1, the address of the first word of the data to be read (the word whose hexadecimal address ends with “0”) is read from the processor. It means that it is input.

In the transition condition G13 (CND-PRA-READ-START), in the state P5, the address of the last word of the data to be read (the word with the end of the address represented by the hexadecimal number “C”) is sent from the processor. It means that it is input.
The transition condition G14 (CND-PRA-READ-END) means that data transfer from the data memory 40 to the processor prefetch buffer 22 is completed.

As a result of the transition of each state as shown in FIG. 9, the cache memory control device 1 performs, for example, the operation corresponding to the above-described FIGS. In addition, description of specific operation | movement is abbreviate | omitted here.
As described above, the cache memory control device 1 according to the present embodiment determines whether data that is expected to be read subsequently is cached when the data to be read is read from the processor. (Whether or not it is stored in the data memory 40). If data that is expected to be read subsequently is stored in the cache, the data is stored in the prefetch cache unit 20, and if data that is expected to be read subsequently is not stored in the cache, the data is stored in the cache. Data is read from the external memory and stored in the prefetch cache unit 20. Thereafter, when the address of data actually read from the processor in the subsequent cycle matches the address of data stored in the prefetch cache unit 20, the data is output from the prefetch cache unit 20 to the processor. If the address of the data actually read from the processor in the subsequent cycle does not match the address of the data stored in the prefetch cache unit 20, the external memory is accessed at that time.

Therefore, when the address of the data to be read is input from the processor, it is not always necessary to access each way of the tag table 30 and the data memory 40, and the data to be read is stored in the data memory 40. Access only if it is remembered.
Therefore, access to an unnecessary part in the cache memory control device 1 can be prevented, and it becomes possible to reduce power consumption and improve processing efficiency.

Further, the cache memory control device 1 prefetches the scheduled data at the timing when the address of the last word of the data to be read is input.
Therefore, since data having a high probability of being read in the subsequent cycle can be stored in the prefetch cache unit 20, it is possible to reduce the situation of accessing useless data and to reduce power consumption.

On the other hand, the cache memory control device 1 can pre-read the scheduled data earlier than the timing at which the address of the last word is input, such as the timing at which the address of the first word of the data to be read is input. .
In this case, a cache hit is detected at an earlier timing, so that if the cache is not hit, the process of reading the data to be read from the external memory can be performed earlier and the occurrence of a wait cycle can be prevented. Alternatively, the number of wait cycles can be reduced.

Note that the cache memory control device 1 can further reduce power consumption by providing a clock gating function.
FIG. 10 is a diagram showing a configuration when the cache memory control device 1 has a clock gating function.
In FIG. 10, the cache memory control device 1 includes a power consumption control unit 70 in addition to the configuration shown in FIG. 1.

The power consumption control unit 70 has a function of stopping the supply of a clock signal to a portion that does not operate in the cache memory control device 1.
FIG. 11 is a diagram illustrating a configuration of the power consumption control unit 70.
In FIG. 11, the power consumption control unit 70 includes clock gating elements (hereinafter referred to as “CG elements”) 71-1 to 71-n corresponding to a plurality of n memories.

  These CG elements 71-1 to 71-n receive power consumption mode signals SG1 to SGn for switching whether or not to supply a clock signal from the access management unit 10, respectively. The access management unit 10 outputs a power consumption mode signal for stopping the supply of the clock signal to the memory determined to be unnecessary, and outputs the clock signal to the memory determined to be operated. A power consumption mode signal to be supplied is output.

  By adopting such a configuration, it becomes possible to supply a clock signal only to the way of the data memory 40 in which data to be read into the prefetch cache unit 20 is stored, and to further reduce power consumption. Can do.

It is a figure which shows the structure of the cache memory control apparatus 1 to which this invention is applied. FIG. 3 is a diagram illustrating a configuration of data stored in a tag table 30 and a data memory 40. FIG. 3 is a state transition diagram showing basic operations of the cache memory control device 1. FIG. 6 is a state transition diagram showing an operation of a state machine “sm-exmem-access” constructed on the cache memory control device 1. It is a timing chart which shows the operation example when the data read by a processor hits a prefetch cache continuously. It is a timing chart which shows the operation example when the data read by a processor does not hit a prefetch cache. It is a timing chart which shows the operation example when the data read by a processor do not hit neither a prefetch cache nor a cache. 7 is a timing chart illustrating an operation example in a case where data read by a processor is data at consecutive addresses and does not hit a cache. It is a state transition diagram which shows the operation | movement of a prefetching process. It is a figure which shows a structure in case the cache memory control apparatus 1 is provided with a clock gating function. 3 is a diagram illustrating a configuration of a power consumption control unit 70. FIG. 1 is a schematic diagram illustrating a configuration of a conventional set-associative cache memory 100. FIG.

Explanation of symbols

1 cache memory control device, 10 access management unit, 20 prefetch cache unit, 21 address control unit, 22 processor prefetch buffer, 23 external memory prefetch buffer, 30, 110 tag table, 40, 120 data memory, 50, 130 hit Detection unit, 60 MUX, 70 Power consumption control unit, 71 CG element, 100 Cache memory

Claims (12)

A cache capable of supplying at least a part of stored data to a cache memory including a plurality of ways from a memory device storing data to be read by the processor and supplying the cached data to the processor A memory control device,
Cache determination means for determining whether or not scheduled data expected to be read after the data being read being read by the processor is cached in any way of the cache memory;
When the cache determination means determines that the scheduled data is cached in any way, the way in which the scheduled data is stored is accessed from among the plurality of ways, and the scheduled data is Prefetch cache means for reading and storing;
Including
The cache memory control device, wherein the prefetch cache means outputs the stored plan data to a processor when the plan data is read after the data being read. The cache memory includes, for the plurality of ways, address storage means for storing cached data addresses, and data storage means for storing data corresponding to each of the addresses,
The cache determination means determines whether the schedule data is cached by determining whether the address of the schedule data is stored in any way of the address storage means,
2. The prefetch cache unit accesses a way corresponding to a way of the address storage unit storing an address of the scheduled data among a plurality of ways of the data storage unit. Cache memory controller.   3. The cache memory control device according to claim 1, wherein the scheduled data is data that is expected to be read immediately after the data being read.   Data to be read by the processor is configured as a block including a plurality of words, and the block is used as a unit to determine whether the scheduled data is cached or to read the scheduled data. The cache memory control device according to any one of claims 1 to 3.   The cache determination means determines whether the scheduled data is cached in response to the processor instructing to read the last word among the plurality of words constituting the data being read. 5. The cache memory control device according to claim 4, wherein:   The cache determination means determines whether or not the scheduled data is cached in response to the processor instructing to read the word preceding the last word among the plurality of words constituting the data being read. 5. The cache memory control device according to claim 4, wherein the determination is made.   The prefetch cache means, when the cache judgment means judges that the scheduled data is cached in any way, the processor is the last word among the plurality of words constituting the data being read. 7. The cache memory control device according to claim 6, wherein in response to instructing to read the data, the way in which the schedule data is stored is accessed to read the schedule data.   The power consumption reducing means for operating a way not related to data reading among a plurality of ways in the cache memory with low power consumption. Cache memory controller.   9. The cache memory control device according to claim 8, wherein the low power consumption means includes a clock gating function for controlling a way not related to data reading so as not to supply a clock signal.   The cache memory control device according to claim 1, wherein the cache memory is a set associative cache memory.   The prefetch cache means accesses the memory device to read and store the scheduled data when the cache judging means determines that the scheduled data is not cached in any way of the cache memory. 11. The cache memory control device according to claim 1, wherein the cache memory control device is a cache memory control device. A method for caching at least a part of stored data in a cache memory including a plurality of ways from a memory device storing data to be read by the processor and supplying the cached data to the processor A cache memory control method comprising:
A cache determination step of determining whether or not the scheduled data expected to be read after the data being read being read by the processor is cached in any of the ways of the cache memory;
In the cache determination step, when it is determined that the scheduled data is cached in any way, the way in which the scheduled data is stored is accessed from among the plurality of ways, and the scheduled data is A read-ahead cache step for reading and storing;
An output step of outputting the scheduled data stored in the prefetch cache step to the processor when the scheduled data is read after the data being read by the processor;
A cache memory control method comprising:

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