JP2005084763A - Memory-to-memory copy control device and memory-to-memory copy processing program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the time required for data copy between memory areas. <P>SOLUTION: A sub-copy size calculation means 11, a copy source address calculation means 13 and a copy destination address calculation means 14 are started to acquire a sub-copy size that is a data unit of copy processing, and a copy source address and copy destination address for this data unit. A reading request of data is transmitted to a request issuing means 15 with designation of the acquired sub-copy size and the copy source address to acquire the data concerned. A writing request of the read data is transmitted to the request issuing means 15 with designation of the sub-copy size and the copy destination address to copy the data. The sub-copy size is subtracted from the remaining copy size to update the copy size, and it is determined whether the copy processing is continued or ended based on the updated remaining copy size. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an inter-memory copy control device and an inter-memory copy processing program, and more particularly to an inter-memory copy control device and an inter-memory copy process that read data in a copy source memory area and write the read data in a copy destination memory area according to a copy instruction. Regarding the program.

  Conventionally, in a computer system, copying has been performed between memory areas in which memory contents written in a predetermined memory area are copied to another memory area under the control of software or DMA (Direct Memory Access). It has been a problem to shorten the copy processing time which increases in proportion to the memory area to be processed.

  Therefore, in some computer systems, etc., there is a computer system that determines whether or not copying is required for each predetermined memory space in order to increase the efficiency of copying the online memory contents to the standby side (see, for example, Patent Document 1). .)

  However, when copying, there is an access restriction called an alignment constraint. The alignment constraint is a constraint on the relationship between the access address and the access size that occurs when accessing the memory, such as reading and writing.

  FIG. 4 is a diagram showing alignment constraints. The figure shows an example of alignment constraints in a processor or DSP (Digital Signal Processor) having a 32-bit address and 64-bit data width. The address is expressed in hexadecimal.

  In the example shown in the figure, the maximum is a data width of 64 bits (8 bytes), and access is possible with a data width of 4 bytes, 2 bytes, and 1 byte. Generally, a multiple or a divisor of 8 based on 8 bytes is set as the data width. When the value of the least significant digit of the access address is 0 or 8, reading or writing with all data widths is possible. However, if the value of the least significant digit is 4 and c, it is 1, 2, 4 bytes, if it is 2 and e, it is 1, 2 bytes, otherwise it is only accessed with a data width of 1 byte. There is a restriction that it is possible. If the access size is 1 byte, all access addresses can be read / written. However, in 2 bytes, the least significant digit value is 0, 2, 4, 6, 8, a, c, e. In other words, it is possible to read / write only the value of the least significant digit of 0, 4, 8, and c in 4 bytes and the value of 0 and 8 of the least significant digit in 8 bytes.

  A memory-to-memory copying process procedure when there is such a conventional alignment constraint will be described. FIG. 5 is a flowchart showing a conventional inter-memory copying process procedure. Hereinafter, the processing unit will be described as 8 bytes.

When the copy process is started, alignment determination is performed based on the copy size and the access address (step S101), and the copy process is branched according to the determination (step S102). In the copying process, when the least significant digits of the access addresses of both the copy source and the copy destination are 0 and 8, 8-byte read and 8-byte write are copied (step S103). When the least significant digit of the access address is the copy sources 0 and 8 and the copy destinations 4 and c, the 8-byte read and 4-byte write are performed twice (step S104). On the contrary, when the least significant digit of the access address is 4 and c at the copy source and 0 and 8 at the copy destination, the copy processing is performed by reading 4 bytes twice and writing 8 bytes (step S105). Hereinafter, a copy process corresponding to the alignment constraint is selected. There are 16 types of copy processing only for copy processing in which the data width of at least one of read and write processing is 8 bytes. Subsequently, it is determined whether or not the copying process has been completed for all the memory areas by this copying process. If the copying process has not been completed, the process from step S101 is repeated (step S106).
JP-A-6-161903 (paragraph numbers [0006] to [0015], FIG. 1)

However, the conventional inter-memory copy control device and the inter-memory copy process have a problem that the copy process takes a long time due to alignment restrictions.
As described above, in order to meet alignment constraints when copying data between memory areas, a processing routine that satisfies the alignment constraints must be prepared for both the copy source and copy destination access addresses. For this reason, the number of processing routines increases and the number of determination conditions for branching also increases. For example, in the case of the alignment constraint shown in FIG. 4, it is necessary to prepare 16 processing routines with a data width of 8 bytes, 6 processings with 4 bytes, and 3 processing routines with 2 bytes. When processing routines are diversified, there arises a problem that processing for branching takes time.

  In addition, by having a processing routine for each alignment case in this way, the number of cases increases, so it becomes difficult to apply optimization for improving execution efficiency such as software pipeline, and the instruction code becomes enlarged, There is also a problem that the instruction cache hit rate decreases.

  Furthermore, there is a problem that the copying process itself takes time due to the alignment constraint. For example, a procedure for copying 8-byte data from the access address “00000001” to “00000002” in the memory-to-memory copy control apparatus capable of accessing the memory with an 8-byte data width will be described. First, in data reading, due to alignment restrictions, (1) 1 byte is read from “00000001”, (2) 2 bytes are read from “00000002”, (3) 4 bytes are read from “00000004”, (4) Four procedures of reading one byte from “00000008” are performed. In the subsequent writing, three procedures are performed: (1) writing 2 bytes from “00000002”, (2) writing 4 bytes from “00000024”, and (3) writing 2 bytes from “00000028”. In this way, even a device that can be accessed in units of 8 bytes cannot be read / written in a batch of 8 bytes due to alignment restrictions, so that the copying process takes time.

Even when determining whether or not copying is necessary, it is difficult to reduce the processing time during copying because copying is subject to the same restrictions.
Although the copying process by software has been described above, the same alignment constraint is also applied to the process by DMA. For this reason, it has been difficult to improve the performance of copy processing by DMA.

  The present invention has been made in view of these points, and an object thereof is to provide an inter-memory copy control device and an inter-memory copy processing program capable of reducing the time required for copying data between memory areas. To do.

  In order to solve the above problem, the present invention provides an inter-memory copy control apparatus as shown in FIG. The inter-memory copy control apparatus 1 according to the present invention stores a memory area in a predetermined copy source memory area 31 of the memory 3 via the memory access apparatus 2 that performs read or write control without alignment restrictions on the access address and the access size. The copied data is copied to the copy destination memory area 32.

  The inter-memory copy control device 1 includes a copy control means 10 for requesting data read from a copy source address and data write to a copy destination address based on a copy instruction inputted from the outside, and a copy control means 10 for controlling copy processing A sub-copy size calculating means 11 for calculating a sub-copy size as a processing unit according to the copy size, a copy-source address calculating means 13 for calculating a copy-source address indicating a copy-source memory area using the sub-copy size, and A copy address calculating unit 12 having a copy destination address calculating unit 14 for calculating a copy destination address indicating a copy destination memory area, and a request issuing unit 15 for issuing a data read request or a data write request to the memory access device 2. It comprises.

  According to such an inter-memory copy control device 1, when a copy instruction is input from the outside, the copy control means 10 initializes the remaining copy size, copy source address, and copy destination address to the values specified by the copy instruction. Turn into.

  Thereafter, the secondary copy size calculating means 11, the copy source address calculating means 13 and the copy destination address calculating means 14 constituting the copy address calculating means 12 are activated to acquire the secondary copy size, the copy source address and the copy destination address. Here, the sub-copy size refers to a processing unit of data size executed in one copy process. Usually, the maximum data width accessible at one time is determined for each memory, and in one copy process, a predetermined data size between a data size corresponding to the maximum data width and a data size corresponding to the minimum data width is determined. Processing is performed using the data size as a processing unit. The secondary copy size calculation unit 11 calculates the data size as a processing unit according to the remaining copy size, and sets it as the secondary copy size. Further, the copy source address calculation means 13 and the copy destination address calculation means 14 perform address calculation based on the sub-copy size. The copy control means 10 designates the sub-copy size and the copy source address calculated in this way, makes a data read request to the request issuing means 15, and acquires the corresponding data. Subsequently, the secondary copy size and the copy destination address are specified, and the request issuing means 15 is requested to write the read data, the data is copied to the target memory area, and the copy process is completed once. To do.

  Next, the sub-copy size is subtracted from the remaining copy size and updated, and it is determined whether to continue or end the copy process based on the updated remaining copy size. When continuing, the processing from the start of the secondary copy size calculation means 11, the copy source address calculation means 13 and the copy destination address calculation means 14 is performed.

  In this way, the copying process with the sub-copy size defined only by the remaining copy size as a processing unit is repeated, and the data in the copy source memory area 31 is copied to the copy destination memory area 32.

  In order to solve the above-described problem, an inter-memory copy processing program for causing a computer to execute the processing function of the inter-memory copy control device 1 shown in FIG. 1 is provided. The inter-memory copy processing program can cause a computer to execute the following processing procedure.

  When a copy instruction is input from the outside, the computer initializes the remaining copy size, copy source address, and copy destination address based on the copy instruction. Next, based on the initialized remaining copy size, the sub-copy size that is the first processing unit is calculated. Then, the secondary copy size and the copy source address are designated and a data read request is issued. Along with this, the memory access device 2 having no alignment constraint on the access address and the access size is activated, and data reading from the memory 3 is executed. Subsequently, a sub-copy size and a copy destination address are designated and a read request for the read data is issued. Along with this, the memory access device 2 copies the read data of the copy source address to the copy destination address. Next, the remaining copy size, copy source address, and copy destination address are updated using the secondary copy size. Then, the updated remaining copy size is checked to determine whether to continue or end the copy process. When continuing, the processing procedure from the sub-copy size calculation of the next processing unit based on the remaining copy size is repeated.

  In the present invention, since the copying process is performed based on the sub-copy size defined only by the remaining size, not only can the processing time required for branching the processing routine be reduced, but also the sub-copy size can be optimized. As a result, the processing time of copying itself can be shortened, and as a result, the copying process of the memory area is accelerated.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. First, the concept of the invention applied to the embodiment will be described, and then the specific contents of the embodiment will be described.
FIG. 1 is an explanatory diagram showing the operation principle of an inter-memory copy control device to which the present invention is applied.

  The inter-memory copy control device 1 to which the present invention is applied includes a memory 3 via a memory access device 2 that controls access to a memory area in response to a data read request or data write request issued by the inter-memory copy control device 1. Read / write data in a predetermined area. In the inter-memory copying process, the requested copying between memories is realized by repeatedly copying a predetermined processing unit (data width) accessible at one time.

  The memory access device 2 has no alignment restrictions, and there is no restriction on the relationship between the access address and the access size. That is, data reading and data writing from a memory area starting from an arbitrary address of the memory 3 can be performed without restriction on the access size.

The memory 3 is a predetermined storage device that stores various data, and the memory access device 2 reads and writes data.
The inter-memory copy control device 1 is a device that performs data copy processing, and includes a copy control means 10 that controls the copy processing, a sub-copy size calculation means 11 that calculates a sub-copy size as a processing unit, and a copy address calculation means 12. Copy source address calculating means 13 for calculating a copy source address for each processing unit, copy destination address calculating means 14 for calculating a copy destination address for each processing unit, and request issuing means for issuing a request to the memory access device 2 15.

  The copy control means 10 controls the execution of a series of copy processes in accordance with an external copy instruction. When a copy instruction is input from the outside, the copy source address indicating the copy source memory area 31 storing the original data, the copy destination address indicating the copy destination memory area 32 storing the copied data, and the amount of data to be copied Copy information including the indicated copy size is input, and initialization processing is performed. Since the copy information is set as an initial value, in the following description, the information instructed to copy from outside is the copy source address (initial value), the copy destination address (initial value), the copy size (initial value), respectively. write. In the initialization process, the copy source address (initial value) is set to the copy source address indicating the copy source for each processing unit, and the copy destination address (initial value) is set to the copy destination address indicating the copy destination for each processing unit. The In addition, a copy size (initial value) is set as the remaining copy size indicating the amount of data that has not been copied.

  When the initialization process is completed, the copying process for each processing unit is started. The secondary copy size calculation means 11, the copy source address calculation means 13 and the copy destination address calculation means 14 are activated to acquire the secondary copy size, the copy source address, and the copy destination address for each processing unit. Then, a data read request is made to the request issuing means 15 by designating the secondary copy size and the copy source address, and the read data of the processing unit (sub copy size) is acquired. Subsequently, a sub-copy size and a copy destination address are designated, and a data write request is made to the request issuing means 15 to write the read processing unit data. After writing is completed, the sub-copy size is subtracted from the remaining copy size, and the remaining copy size is updated. The updated remaining copy size is checked, and if the remaining copy size is 0, the copy process is terminated. If it is not 0, the process returns to the beginning of the copy process procedure for each process unit, and the copy process for the next process unit is started.

  The secondary copy size calculation unit 11 determines the secondary copy size according to the remaining copy size, and sets the data amount for each processing unit. Since the maximum data width that can be accessed at one time for each memory is determined, the secondary copy size is the largest accessible value that does not exceed the remaining copy size between the maximum data width and the minimum data width. Is set. For example, when the maximum data width is 8 bytes and the data size of accessible processing units is determined in advance, such as 8, 4, 2, 1, etc., the remaining copy size of these processing units is Select the largest processing unit that does not exceed.

The copy source address calculation means 13 calculates a copy source address indicating the copy source memory area in this processing unit.
The copy destination address calculation means 14 calculates a copy destination address indicating a copy destination memory area in this processing unit.

  When the request issuing means 15 inputs from the copy control means 10 an address (copy source address or copy destination address) indicating the memory area to be accessed, an access size (sub-copy size) and an instruction (read or write), the input information Based on the above, a read or write request is issued to the memory access device 2. The read data or response obtained from the memory access device 2 is transmitted to the copy control means 10.

The operation of the inter-memory copy control device 1 having such a configuration will be described.
A copy source address (initial value) indicating the copy source memory area 31, a copy destination address (initial value) indicating the copy destination memory area 32, and a copy size (initial A copy instruction including (value) is issued, and the process is started.

  Based on the copy instruction, the copy control unit 10 initializes a copy source address, a copy destination address, and a remaining copy size indicating an unfinished copy amount as a pointer in copy processing for each processing unit. At the end of initialization, the copy source address and copy destination address indicate the start address of the memory area instructed to copy, and the remaining copy size indicates the copy size instructed to copy.

  After the initialization, the copy process is started, and the copy control means 10 activates the secondary copy size calculation means 11, the copy source address calculation means 13, and the copy destination address calculation means 14. The secondary copy size calculation means 11 refers to the remaining copy size and selects the maximum data width not exceeding the remaining copy size as a processing unit. The copy source address calculating unit 13 and the copy destination address calculating unit 14 calculate a copy source address indicating the copy source memory area 31 and a copy destination address indicating the copy destination memory area 32 in this processing unit.

  The copy control means 10 makes a data read request to the request issuing means 15 by specifying the sub-copy size and the copy source address. The request issuing means 15 issues a data read request request to the memory access device 2 with the secondary copy size as the access size and the copy source address as the access address. Upon receiving the request, the memory access device 2 reads data in the designated memory area of the memory 3. The read data is sent to the copy control means 10 via the request issuing means 15. Subsequently, the copy control means 10 requests the request issuing means 15 to write the read data by specifying the sub-copy size and the copy destination address. The request issuing unit 15 issues a data write request request to the memory access device 2 using the secondary copy size as the access size and the copy destination address as the access address. The memory access device 2 that has received the request writes data in a specified memory area of the memory 3. A write end signal is sent to the copy control means 10 via the request issuing means 15, and the copy processing for each processing unit is completed.

  Subsequently, the copy control means 10 updates the remaining copy size using the sub-copy size, and determines whether to continue / end the copy process based on the updated remaining copy size. When continuing, the processes from the start of the secondary copy size calculating means 11, the copy source address calculating means 13 and the copy destination address calculating means 14 are repeated.

The process described above is repeated, the copy process is repeated with the maximum data width corresponding to the remaining copy size, and the inter-memory copy process of the memory area instructed to be copied is completed.
As described above, since the secondary copy size as a processing unit is determined only by the size of the remaining copy size, there is no need to perform complicated processing for determining restrictions on the copy source and destination addresses and the secondary copy size, and processing branch Can be shortened. Further, since only the number of copy processing routines to be branched needs to be prepared according to the type of data width, the instruction code is not enlarged. Furthermore, since the data width to be processed in accordance with the access address is not restricted, the copying process with the maximum data width can be performed, and the copying process itself can be shortened.

  As described above, according to the present invention, it is not necessary to perform processing for confirming and aligning the alignment of memory addresses, and the memory region can be copied at high speed. As a result, it is possible to improve the overall system performance accompanied by copying of the memory area.

  In the above description, the copy source address calculating unit 13 and the copy destination address calculating unit 14 are activated at the start of the copy process for each processing unit. However, when the remaining copy size is updated, the copy source address calculating unit 13 and the copy destination address calculating unit 14 are activated. The copy source address and the copy destination address may be updated.

  By the way, the inter-memory copy control device 1 has a data processing function for copying data between memory areas, and the entire device is controlled by a CPU (Central Processing Unit). A RAM (Random Access Memory) and a ROM (Read Only Memory) are connected to the CPU via a bus. Also, an external processor / DSP and a memory access device are connected via a bus. The ROM stores a program to be executed by the CPU. The RAM stores various data necessary for processing by the CPU. With such a hardware configuration, the processing functions of the present embodiment can be realized.

Note that the inter-memory copy control device 1 can also realize its processing function by hardware.
Next, an embodiment will be described by taking the case where the present invention is applied to a system having a 32-bit address and 64-bit (8-byte) data width as an example. In this case, the data width of the processing unit can be selected from four types of 8 bytes, 4 bytes, 2 bytes, and 1 byte.

FIG. 2 is a block diagram of the inter-memory copy control apparatus according to the embodiment of the present invention. The same components as those in FIG. 1 are denoted by the same reference numerals, and description thereof is omitted.
An inter-memory copy control apparatus 1 according to the present invention includes a copy control means 10, a sub copy size holding means 11a for holding a sub copy size, a copy source address holding means 13a for holding a copy source address, and an adder 13b. Address calculating means, copy destination address holding means 14a for holding the copy destination address and copy destination address calculating means having adder 14b, request issuing means 15, remaining copy size holding means 16a for holding the remaining copy size, and subtractor 16b It has.

  The copy control means 10 controls the copy process. The secondary copy size holding unit 11a, the copy source address holding unit 13a, the copy destination address holding unit 14a, and the remaining copy size holding unit 16a can read and write data held in the respective data holding units. Copy processing is performed with reference to the stored data. Here, it is assumed that the sub-copy size is calculated by the copy control means 10.

  The secondary copy size holding unit 11 a is a register that holds the value of the secondary copy size calculated by the copy control unit 10. Here, a data width value of 8 bytes, 4 bytes, 2 bytes, or 1 byte is held. If necessary, the held sub-copy size value is output to the adders 13b and 14b and the subtractor 16b.

  The copy source address holding unit 13a is a register that holds a copy source address indicating a copy source memory area in a processing unit. A copy source address (initial value) input from the outside is set by an initialization signal. Further, the value of the copy source address held according to the copy control means 10 is output to the adder 13b. The copy source address added by the adder 13b by the sub-copy size is stored in the copy source address holding unit 13a as a copy source address at the time of the next processing.

  The copy destination address holding unit 14a is a register that holds a copy destination address indicating a copy destination memory area in a processing unit. A copy destination address (initial value) input from the outside is set by an initialization signal. Further, the value of the copy destination address held according to the copy control means 10 is output to the adder 14b. The copy destination address added by the adder 14b by the size of the sub-copy size is stored in the copy destination address holding unit 14a as a copy destination address in the next processing.

  The remaining copy size holding means 16a is a register that holds the remaining copy size indicating the amount of unfinished copy data. The copy size (initial value) input from the outside is set by the initialization signal. Further, the value of the remaining copy size held according to the copy control means 10 is output to the subtracter 16b. When the copy processing for each processing unit is completed, the remaining copy size subtracted by the sub-copy size by the subtractor 16b is stored in the remaining copy size holding means 16a.

The operation of the inter-memory copy control device 1 having such a configuration will be described.
The inter-memory copy control device 1 inputs a copy instruction including a copy size (initial value), a copy source address (initial value), a copy destination address (initial value), and a copy start signal from an external device such as a processor / DSP. . In response to the initialization signal of the copy control means 10, the copy size (initial value) remains, the copy size holding means 16a, the copy source address (initial value) is the copy source address holding means 13a, and the copy destination address (initial value) is the copy destination address. It is stored in the holding means 14a, and the initialization process ends.

After the initialization is completed, the copying process is started.
The copy control means 10 reads the remaining copy size held in the remaining copy size holding means 16a, determines the execution / end of the copy process, and selects the sub-copy size for execution. If the remaining copy size is 0, a copy end signal is output to the outside and the copy process is terminated.

  On the other hand, if the remaining copy size is other than 0, copy processing is performed. If the remaining copy size is 1, 1 is set in the secondary copy size holding means 11a. When the remaining copy size is 2 or 3, 2 is set in the secondary copy size holding means 11a. When the remaining copy size is 4 to 7, 4 is set in the sub copy size holding means 11a. If the remaining copy size is 8 or more, 8 is set in the secondary copy size holding means 11a.

  Next, the copy control means 10 sends a request to the request issuing means 15 to read the data with the data width set in the secondary copy size holding means 11a from the copy source address held in the copy source address holding means 13a. Notify you to issue. As a result, the corresponding data α is read from the memory.

  Subsequently, the copy control means 10 sends a request to the request issuing means 15 to write the data α with the data width set in the secondary copy size holding means 11a from the copy destination address held in the copy destination address holding means 14a. Notify you to issue. As a result, the data α is written in the corresponding area of the memory.

  Next, the copy control means 10 subtracts the sub-copy size value held in the sub-copy size holding means 11a from the remaining copy size value held in the remaining copy size holding means 16a by the subtractor 16b and holds the remaining copy size. This is reflected in the means 16a. As a result, the amount of data that has been copied in units of processing is subtracted, and the remaining amount of data is stored in the remaining copy size holding means 16a. Further, the adder 13b adds the value of the sub-copy size to the value of the copy source address holding means 13a and reflects it to the copy source address holding means 13a. Similarly, the adder 14b adds the value of the sub-copy size to the value of the copy destination address holding unit 14a, and reflects it to the copy destination address holding unit 14a. As a result, the next copy source address and copy destination address of the memory area for which the copy processing for each processing unit has been completed are held in the holding means.

Since the preparation for the copy processing in the next processing unit is completed in this way, the processing from the determination of execution / end of the copy processing is performed.
As described above, the inter-memory copy control apparatus 1 according to the present invention can execute a copy process with a sub-copy size having the maximum data width according to the remaining copy size. For example, in the conventional memory-to-memory copy control device described above, when copying 8 bytes of data from the access address “00000001” to “00000002”, four readings of 1 byte, 2 bytes, 4 bytes, and 1 byte are performed. And writing of 3 times of 2 bytes, 4 bytes and 2 bytes was necessary. If this is executed by the memory-to-memory copy control apparatus according to the present invention, the copying process is completed by reading 8 bytes once and writing 8 bytes once.

As described above, according to the present invention, since the copying process can be performed using the maximum data width, the copying process can be speeded up.
Next, an inter-memory copy processing program according to the present invention will be described. The computer that executes the inter-memory copy processing program according to the present invention functions as an inter-memory copy control device. FIG. 3 is a flowchart showing a processing procedure by the inter-memory copy processing program according to the embodiment of the present invention.

When a copy instruction is input from the outside, the computer executes the following processing by the memory-to-memory copy processing program according to the present invention.
[Step S1] Using the copy source size (initial value), copy source address (initial value), and copy destination address (initial value) included in the copy instruction, the remaining copy size, copy source address for each processing unit, and copy destination Initialize the address.

  [Step S2] The remaining copy size is checked, and the process branches according to the amount of data. If the remaining copy size is 8 bytes or more, the process proceeds to step S3. If the remaining copy size is 7 bytes to 4 bytes, the process proceeds to step S4. If the remaining copy size is 3 bytes or 2 bytes, the process proceeds to step S5. If the remaining copy size is 1 byte, the process proceeds to step S6.

  [Step S3] If the remaining copy size is 8 bytes or more, 8-byte copy processing is performed with the data width (sub-copy size) set to 8 bytes. That is, 8-byte data reading and 8-byte data writing are performed.

  [Step S4] If the remaining copy size is 7 to 4 bytes, 4-byte copy processing is performed with the data width (sub-copy size) set to 4 bytes. That is, 4-byte data reading and 4-byte data writing are performed.

  [Step S5] If the remaining copy size is 3 or 2 bytes, 2-byte copy processing is performed with the data width (sub-copy size) set to 2 bytes. That is, 2-byte data reading and 2-byte data writing are performed.

  [Step S6] When the remaining copy size is 1 byte, 1-byte copy processing is performed with the data width (sub-copy size) set to 1 byte. That is, 1-byte data is read and 1-byte data is written.

  [Step S7] Copy processing with a predetermined data width (sub-copy size) ends, and the remaining copy size, copy source address, and copy destination address are updated. Then, the remaining copy size is checked, and it is determined whether the processing is continued or finished depending on whether the size is 0 or not. If it is 0, the process is terminated. If it is not 0, the process returns to step S2 to perform the next process.

  As described above, according to the present invention, there are four types of copy processing branch routines: 8-byte copy processing, 4-byte copy processing, 2-byte copy processing, and 1-byte copy processing. However, only the remaining copy size is compared with the data width. For this reason, the processing time for branch determination can be shortened, and the memory amount for the processing routine can be reduced. In addition, since the maximum data width is selected and the copying process is performed, the copying process can be speeded up.

  The above processing functions can be realized by a computer. In that case, a program describing the processing contents of the functions that the inter-memory copy control apparatus should have is provided. By executing the program on a computer, the above processing functions are realized on the computer. The program describing the processing contents can be recorded on a computer-readable recording medium. Examples of the computer-readable recording medium include a magnetic recording device, an optical disk, a magneto-optical recording medium, and a semiconductor memory. Examples of the magnetic recording device include a hard disk device (HDD), a flexible disk (FD), and a magnetic tape. Examples of the optical disc include a DVD (Digital Versatile Disc), a DVD-RAM (Random Access Memory), a CD-ROM (Compact Disc Read Only Memory), and a CD-R (Recordable) / RW (ReWritable). Magneto-optical recording media include MO (Magneto-Optical disk).

  When distributing the program, for example, portable recording media such as a DVD and a CD-ROM in which the program is recorded are sold. It is also possible to store the program in a storage device of a server computer and transfer the program from the server computer to another computer via a network.

  The computer that executes the program stores, for example, the program recorded on the portable recording medium or the program transferred from the server computer in its own storage device. Then, the computer reads the program from its own storage device and executes processing according to the program.

It is explanatory drawing which shows the operation principle of the copy control apparatus between memory to which this invention is applied. 1 is a configuration diagram of an inter-memory copy control device according to an embodiment of the present invention. FIG. It is the flowchart which showed the process sequence by the copy processing program between memory of embodiment of this invention. It is the figure shown about the alignment restrictions. It is the flowchart which showed the conventional copy processing procedure between memory.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Copy control apparatus between memory 2 Memory access apparatus 3 Memory 10 Copy control means 11 Sub copy size calculation means 11a Sub copy size holding means 12 Copy address calculation means 13 Copy source address calculation means 13a Copy source address holding means 13b Adder 14 Copy Destination address calculating means 14a Copy destination address holding means 14b Adder 15 Request issuing means 16a Remaining copy size holding means 16b Subtractor

Claims (4)

In a memory-to-memory copy control device that reads data in a copy source memory area according to a copy instruction and writes the data in a copy destination memory area.
Sub-copy size calculating means for calculating a sub-copy size as a processing unit according to the remaining copy size indicating the amount of unfinished data;
Copy address calculating means for calculating a copy source address indicating the copy source memory area and a copy destination address indicating the copy destination memory area for each process using the sub-copy size;
Request issuing means for issuing a read or write request to a memory access device that reads or writes a memory area of a predetermined storage device without restriction on an access address and an access size;
When the copy instruction is input from the outside, the remaining copy size, the copy source address, and the copy destination address are initialized, and the sub copy size calculating unit and the copy address calculating unit are operated to calculate the calculated A request to read data is requested to the request issuing means by designating a sub-copy size and the source address, and a request to write data read to the request issuing means is designated by designating the sub-copy size and the destination address. Copy control means for controlling copy processing, updating the remaining copy size using the sub-copy size, and determining continuation / termination of copy processing based on the remaining copy size;
An inter-memory copy control apparatus comprising: The sub-copy size calculating means
The remaining copy size is compared with the data size of a preset processing unit, and the largest data size of the processing unit not exceeding the remaining copy size is set as the sub-copy size.
The inter-memory copy control apparatus according to claim 1. The copy address calculating means includes:
A copy source address calculating unit having a copy source address holding unit for holding the value of the copy source address, and an adding unit for adding the value held by the copy source address holding unit and the value of the sub-copy size;
A copy destination address calculating means having a copy destination address holding means for holding the value of the copy destination address; and an adding means for adding the value held by the copy destination address holding means and the value of the sub-copy size;
The inter-memory copy control apparatus according to claim 1, further comprising: In an inter-memory copy processing program that reads data in a copy source memory area according to a copy instruction and performs a copy process between memory areas that writes the data in a copy destination memory area.
On the computer,
When the copy instruction is input from the outside, the remaining copy size indicating the unfinished data amount based on the copy instruction, the copy source address indicating the data read area, and the copy destination address indicating the data write area are initialized.
Calculate a secondary copy size as a processing unit according to the remaining copy size,
A memory access device that reads or writes a memory area of a predetermined storage device without restrictions on an access address and an access size, specifies the secondary copy size and the copy source address, requests data read, and reads data Get
Specifying the secondary copy size and the copy destination address, requesting the memory access device to write the read data, and performing a copy process for the secondary copy size,
Updating the remaining copy size, the copy source address and the copy destination address using the sub-copy size;
Determine whether to continue or end the copying process based on the updated remaining copy size,
When continuing, processing from the calculation of the sub-copy size according to the remaining copy size,
An inter-memory copy processing program characterized by causing a procedure to be executed.

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