JP2005079554A - Substrate with through electrode and manufacturing method of the same - Google Patents

Substrate with through electrode and manufacturing method of the same Download PDF

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JP2005079554A
JP2005079554A JP2003311919A JP2003311919A JP2005079554A JP 2005079554 A JP2005079554 A JP 2005079554A JP 2003311919 A JP2003311919 A JP 2003311919A JP 2003311919 A JP2003311919 A JP 2003311919A JP 2005079554 A JP2005079554 A JP 2005079554A
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substrate
bonding
electrode
hole
conductive portion
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Kazuhisa Itoi
和久 糸井
Tatsuo Suemasu
龍夫 末益
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Fujikura Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a substrate with a through electrode and a manufacturing method of the same capable of realizing a low-cost and mechanically and electrically stable connection. <P>SOLUTION: The manufacturing method of the substrate 29 with the through electrode that the substrate 1 having a through hole 5 and a bonding substrate 6 having a non-through hole 11 are used to position the substrate 1 and the bonding substrate 6 so as to allow the through hole 5 and the non-through hole 11 to be communicated, wherein a process for bonding the substrate 1 and the bonding substrate 6, a process for filling a base material of conductivity from an opening section 28 of the through hole 5 in the substrate 1, a process for removing the bonding substrate 6 are at least provided. This method allows the substrate 29 with the through electrode having the through electrode 27 comprising a conductive section 8 penetrating the substrate 1 in the thickness direction and a protrusion section 10 which protrudes from one surface of the substrate 1 and is integrated with the conductive section 8 to be manufactured. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、高密度3次元実装タイプの半導体装置などに用いられる貫通電極付き基板、及びその製造方法に関するものである。   The present invention relates to a substrate with a through electrode used for a high-density three-dimensional mounting type semiconductor device and the like, and a method for manufacturing the same.

近年、ICチップなどの半導体装置を、基板を介して3次元に設け、高密度に配線を行なう開発が進められている。
この技術では、基板の表裏に設けてなる半導体装置間を電気的に結ぶため、基板内を、その厚さ方向に貫通する導電部が用いられている(例えば、特許文献1参照。)。尚、特許文献1では、導電部を貫通電極と呼んでいる。
特開2003−86591号公報
In recent years, development has been advanced in which semiconductor devices such as IC chips are provided three-dimensionally via a substrate and wiring is performed at high density.
In this technique, in order to electrically connect the semiconductor devices provided on the front and back of the substrate, a conductive portion that penetrates the substrate in the thickness direction is used (for example, see Patent Document 1). In Patent Document 1, the conductive portion is called a through electrode.
JP 2003-86591 A

しかしながら、上記のような従来技術においては、基板の主面に対し垂直方向に形成された細孔に導電性物質を充填して貫通電極として機能する導電部を形成してなる貫通電極付き基板を用い、後付けで、貫通電極を、外の配線や回路、素子等へ繋げるために要する接点部を形成している。
この場合、導電部および接点部を形成するためには複数の工程が必要であり、貫通電極付き基板の製造工程が複雑になり、コスト高となる。
また、導電部と接点部との間に界面が生じたり、あるいは、その界面に酸化層が形成されて一体とならず、導電部と接点部との間で電気的不具合が生じる恐れがあった。
However, in the prior art as described above, a substrate with a through electrode formed by filling a conductive material into pores formed in a direction perpendicular to the main surface of the substrate to form a conductive portion functioning as a through electrode is provided. Used as a retrofit, a contact portion required to connect the through electrode to an external wiring, circuit, element or the like is formed.
In this case, in order to form the conductive portion and the contact portion, a plurality of steps are necessary, and the manufacturing process of the substrate with a through electrode becomes complicated and the cost is increased.
In addition, an interface may be formed between the conductive portion and the contact portion, or an oxide layer may be formed at the interface to be integrated, and there may be an electrical failure between the conductive portion and the contact portion. .

本発明は、上記課題を解決するものであり、低コストで、かつ、機械的および電気的に安定した接続を図ることが可能な貫通電極付き基板およびその製造方法を提供することを目的とする。   SUMMARY OF THE INVENTION The present invention solves the above-described problems, and an object thereof is to provide a substrate with a through electrode and a method for manufacturing the same that can achieve a low-cost and mechanically and electrically stable connection. .

上記目的を達成するため、本発明は、基板と、該基板内をその厚さ方向に貫通する導電部と、前記基板の一方の面から突出し、前記導電部と一体をなす突出部とを有し、前記導電部と前記突出部とで貫通電極を形成しており、前記導電部に前記突出部が重なる方向から見て、前記突出部は前記導電部より広い面積を有していることを特徴とする貫通電極付き基板である。   In order to achieve the above object, the present invention includes a substrate, a conductive portion that penetrates the substrate in the thickness direction, and a protruding portion that protrudes from one surface of the substrate and is integrated with the conductive portion. A through electrode is formed by the conductive portion and the protruding portion, and the protruding portion has a larger area than the conductive portion when viewed from the direction in which the protruding portion overlaps the conductive portion. It is the board | substrate with a penetration electrode characterized.

この構成によれば、突出部は導電部より広い面積を有しているので、突出部が、例えば、外の配線や回路、素子等の他部材と繋がる場合における機械的耐久性を向上でき、貫通電極における導電部と突出部とを界面がない一体構造とすれば、導電部と接点部との間で電気的不具合が生じる恐れを回避できる。   According to this configuration, since the protruding portion has a larger area than the conductive portion, the mechanical durability in the case where the protruding portion is connected to other members such as an external wiring, circuit, element, or the like can be improved. If the conductive portion and the protruding portion of the through electrode have an integrated structure with no interface, the risk of an electrical failure between the conductive portion and the contact portion can be avoided.

更に、本発明は、前記基板の断面方向から見て、前記突出部が前記導電部と接する部分において、前記突出部の幅は前記導電部の幅より大きくしても良い。
この構成によれば、突出部が、例えば、外の配線や回路、素子等の他部材と繋がる場合における機械的耐久性を向上できる。
Further, according to the present invention, the width of the protruding portion may be larger than the width of the conductive portion at a portion where the protruding portion is in contact with the conductive portion as viewed from the cross-sectional direction of the substrate.
According to this configuration, it is possible to improve the mechanical durability when the protruding portion is connected to other members such as an external wiring, a circuit, and an element, for example.

更に、本発明は、前記突出部の断面は、略半円状、台形状、方形状のうち何れかの形状であるようにしても良い。
この構成によれば、突出部の断面を略半円状とした場合には、突出部と他部材との繋ぎを様々な方向から行うことができる。突出部の断面を台形状とした場合には、突出部が平面を持つので他部材との繋ぎを容易に行うことができる。突出部の断面を方形状とした場合には、突出部が平面を持つので他部材との繋ぎを容易に行うことができる。特に、方形状の場合は、突出部厚さを大きくして他部材との繋ぎを容易に行うことができるとともに、複数の導電部との繋ぎを行いやすくなる。
Furthermore, according to the present invention, the cross section of the protruding portion may be any one of a substantially semicircular shape, a trapezoidal shape, and a rectangular shape.
According to this configuration, when the cross section of the protrusion is substantially semicircular, the protrusion and the other member can be connected from various directions. When the cross section of the protrusion is trapezoidal, since the protrusion has a flat surface, it can be easily connected to other members. When the cross section of the protrusion is rectangular, the protrusion has a flat surface, so that it can be easily connected to other members. In particular, in the case of a rectangular shape, it is possible to easily connect with other members by increasing the thickness of the protruding portion and to easily connect with a plurality of conductive portions.

更に、本発明は、複数の導電部に接してなる前記突出部が一体をなすものであっても良い。   Further, in the present invention, the projecting portions that are in contact with a plurality of conductive portions may be integrated.

また、本発明は、貫通孔を有する基板と非貫通孔を有する接合用基板とを用い、前記貫通孔と前記非貫通孔が連通するように前記基板と前記接合用基板との位置合せを行い、前記基板と前記接合用基板とを接合する工程と、前記基板の前記貫通孔の開口部から導電性を有する母材を充填する工程と、前記接合用基板を除去する工程と、を少なくとも具備することを特徴とする貫通電極付き基板の製造方法である。   Further, the present invention uses a substrate having a through hole and a bonding substrate having a non-through hole, and aligns the substrate and the bonding substrate so that the through hole and the non-through hole communicate with each other. And a step of bonding the substrate and the bonding substrate, a step of filling a conductive base material from an opening of the through hole of the substrate, and a step of removing the bonding substrate. A method for manufacturing a substrate with a through electrode.

この方法によれば、導電部と突出部とを同時に成形できるので、製造工程の簡略化が図れ、製造コストを低くすることができる。
また、導電部と突出部を一体として、同時に形成できるので、両者の間に界面が生じる恐れを回避できる。その結果、従来の問題点、すなわち、両者の界面に酸化層が形成されて一体とならず、導電部と突出部との間で電気的不具合が生じる恐れを回避できる。
According to this method, since the conductive portion and the protruding portion can be simultaneously formed, the manufacturing process can be simplified and the manufacturing cost can be reduced.
In addition, since the conductive portion and the protruding portion can be integrally formed at the same time, it is possible to avoid the possibility of an interface between the two. As a result, it is possible to avoid the conventional problem, that is, the possibility that an electrical failure occurs between the conductive portion and the protruding portion, because the oxide layer is formed at the interface between the two and is not integrated.

また、本発明において、前記位置合せは、光学的手法を用いても良い。
また、本発明において、前記接合用基板として、シリコン基板、又は、ガラス基板を用いても良い。
In the present invention, the alignment may be performed using an optical method.
In the present invention, a silicon substrate or a glass substrate may be used as the bonding substrate.

また、本発明において、前記接合用基板がシリコン基板の場合、前記光学的手法は、赤外域に波長を有する光を用いても良い。   In the present invention, when the bonding substrate is a silicon substrate, the optical method may use light having a wavelength in the infrared region.

また、本発明において、前記接合用基板がガラス基板の場合、前記光学的手法は、可視域に波長を有する光を用いても良い。   In the present invention, when the bonding substrate is a glass substrate, the optical technique may use light having a wavelength in the visible range.

以上、述べたように、本発明では、導電部と突出部とで貫通電極を形成しており、導電部に突出部が重なる方向から見て、突出部は導電部より広い面積を有しているので、突出部が、例えば、外の配線や回路、素子等の他部材と繋がる場合における機械的耐久性を向上でき、貫通電極における導電部と突出部とを界面がない一体構造とすれば、導電部と接点部との間で電気的不具合が生じる恐れを回避できる。   As described above, in the present invention, the through electrode is formed by the conductive portion and the protruding portion, and the protruding portion has a larger area than the conductive portion when viewed from the direction in which the protruding portion overlaps the conductive portion. Therefore, for example, if the projecting portion is connected to other members such as an external wiring, circuit, element, etc., the mechanical durability can be improved, and the conductive portion and the projecting portion in the through electrode have an integrated structure with no interface. The risk of an electrical failure occurring between the conductive portion and the contact portion can be avoided.

また、本発明では、貫通孔を有する基板と非貫通孔を有する接合用基板とを用い、前記貫通孔と前記非貫通孔が連通するように前記基板と前記接合用基板との位置合せを行い、前記基板と前記接合用基板とを接合する工程と、前記基板の前記貫通孔の開口部から導電性を有する母材を充填する工程と、前記接合用基板を除去する工程と、を少なくとも具備することを特徴とする貫通電極付き基板の製造方法であり、導電部と突出部とを同時に成形できるので、製造工程の簡略化が図れ、製造コストを低くすることができる。
また、本発明によれば、導電部と突出部とを同時に成形できるので、両者の間に界面が発生しにくくなり、また、両者間に酸化層が形成されない。よって、導電部と突出部との間で電気的不具合が生じる恐れを回避できる。
In the present invention, a substrate having a through hole and a bonding substrate having a non-through hole are used, and the substrate and the bonding substrate are aligned so that the through hole and the non-through hole communicate with each other. And a step of bonding the substrate and the bonding substrate, a step of filling a conductive base material from an opening of the through hole of the substrate, and a step of removing the bonding substrate. In the method of manufacturing a substrate with a through electrode, which is characterized in that the conductive portion and the protruding portion can be simultaneously formed, the manufacturing process can be simplified and the manufacturing cost can be reduced.
In addition, according to the present invention, since the conductive portion and the protruding portion can be formed at the same time, an interface is hardly generated between them, and an oxide layer is not formed between them. Therefore, it is possible to avoid the possibility of an electrical failure between the conductive portion and the protruding portion.

以下、本発明の実施の形態を、図面を参照にして説明する。
図1は、本発明の実施の形態による貫通電極付き基板29の製造方法を示しており、工程1〜工程6からなる。
図1は、基板の断面を示した図である。図1において、符号1は基板、符号1aは基板1の表面、符号1bは基板1の裏面である。表面加工前の基板1は表裏の区別はなく、本明細書では、微細孔を形成するために最初に穿孔する面を表面1aとし、その反対の面を裏面1bとする。符号2は保護層(表面絶縁層)、符号5は貫通微細孔(貫通孔)、符号6は接合用基板、符号7は壁面絶縁層、符号8は導電部、符号10は突出部、符号27は貫通電極である。
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 shows a method of manufacturing a substrate 29 with a through electrode according to an embodiment of the present invention, and includes steps 1 to 6.
FIG. 1 is a view showing a cross section of a substrate. In FIG. 1, reference numeral 1 is a substrate, reference numeral 1 a is a front surface of the substrate 1, and reference numeral 1 b is a back surface of the substrate 1. There is no distinction between the front and back surfaces of the substrate 1 before the surface processing, and in this specification, the surface that is first drilled to form the microholes is the surface 1a, and the opposite surface is the back surface 1b. Reference numeral 2 is a protective layer (surface insulating layer), reference numeral 5 is a through fine hole (through hole), reference numeral 6 is a bonding substrate, reference numeral 7 is a wall insulating layer, reference numeral 8 is a conductive portion, reference numeral 10 is a protruding portion, reference numeral 27. Is a through electrode.

(工程1)
基板1は、以下の説明ではシリコン基板を例として説明するが、材質はシリコンに限定されるものではない。工程1において、基板1の表面1aに保護層2を形成後、電極パターンをリソグラフィ技術により保護層2上に転写する。次いで、ウェットエッチング等により電極部位にある保護層2を除去して基板表面1aを部分的に露出させる。
(Process 1)
In the following description, the substrate 1 will be described using a silicon substrate as an example, but the material is not limited to silicon. In step 1, after forming the protective layer 2 on the surface 1a of the substrate 1, the electrode pattern is transferred onto the protective layer 2 by lithography. Next, the protective layer 2 at the electrode site is removed by wet etching or the like to partially expose the substrate surface 1a.

基板1の厚さは、例えば300〜600μm程度である。また保護層2は、熱酸化法によって形成される酸化膜(SiO)等が用いられる。貫通微細孔5の口径は通常、基板厚さより小さく、例えば5〜200μm程度である。また、貫通微細孔5の開口形状、配置、個数は、形成する電極パターンにより任意に設計可能である。
また、場合により、基板裏面1bに対しても保護層(図示せず)を形成しても良い。
The thickness of the substrate 1 is, for example, about 300 to 600 μm. The protective layer 2 is made of an oxide film (SiO 2 ) formed by a thermal oxidation method. The diameter of the through minute hole 5 is usually smaller than the substrate thickness, for example, about 5 to 200 μm. Moreover, the opening shape, arrangement | positioning, and number of through-microholes 5 can be arbitrarily designed by the electrode pattern to form.
In some cases, a protective layer (not shown) may be formed on the back surface 1b of the substrate.

(工程2)
工程2においてエッチング技術により基板表面1aの電極部位を穿孔し、貫通微細孔5を形成する。孔径が数十μmであり、深さが数百μm以上である高アスペクト比(微細孔の孔径と深さの比)を有する貫通微細孔5を形成する方法としては、ICP−RIE(Inductively Coupled Plasma−Reactive Ion Etching)、PAECE、レーザー法、マイクロドリル法などがあるが、多数の貫通微細孔5を短時間で一括穿孔するためにはマイクロドリル法は効率が悪く、またレーザー穿孔装置は高価であるところから、シリコン等の基板1の電極用微細孔形成にはICP−RIEが多く用いられている。
(Process 2)
In step 2, the electrode portion of the substrate surface 1a is drilled by an etching technique to form the through-hole 5. ICP-RIE (Inductively Coupled) is used as a method of forming the through-hole 5 having a high aspect ratio (ratio of hole diameter to depth) having a hole diameter of several tens of μm and a depth of several hundred μm or more. Plasma-Reactive Ion Etching), PAECE, laser method, micro-drill method, etc., but micro-drill method is inefficient to drill many through-holes 5 in a short time, and laser drilling equipment is expensive. Therefore, ICP-RIE is often used for forming microholes for electrodes of the substrate 1 such as silicon.

また、基板穿孔においては、エッチング深さが数百μmに及ぶため、シリコンとエッチングマスクの選択比(エッチンググレートの比)を大きくし、厚いエッチングマスクを用いる必要がある。そのため、工程1の保護層2をパターンニングするために、保護層2の上層としてレジスト(図示せず)を設け、レジストと保護層2の二層を工程2における貫通微細孔5を形成するためのエッチングマスクとして用いても良い。   Further, in the substrate drilling, since the etching depth reaches several hundred μm, it is necessary to increase the selection ratio (etching ratio) between silicon and the etching mask and use a thick etching mask. Therefore, in order to pattern the protective layer 2 in the step 1, a resist (not shown) is provided as an upper layer of the protective layer 2, and the two layers of the resist and the protective layer 2 are formed to form the through micropores 5 in the step 2. It may be used as an etching mask.

もちろん、貫通微細孔5形成に用いられるエッチングマスクの構造として、フォトレジスト等のレジスト、あるいは、酸化膜や窒化膜等をそれぞれ単独でエッチングマスクとして用いることの何れも採用可能である。
エッチングにおいて、保護層2がSiOであり、基板1がシリコンである場合、ICP−RIEにおけるシリコンとSiOの選択比(エッチンググレートの比)は、1:100〜200程度である。
Of course, as the structure of the etching mask used for forming the through-hole 5, either a resist such as a photoresist, or an oxide film, a nitride film, or the like can be used alone as an etching mask.
In the etching, when the protective layer 2 is made of SiO 2 and the substrate 1 is made of silicon, the selection ratio (etching rate ratio) between silicon and SiO 2 in ICP-RIE is about 1: 100 to 200.

数百μm以上の厚さを有するシリコン基板に貫通微細孔5を形成するためには、基板1の厚さと、前記選択比の値から保護層2の膜厚を適宜決定すればよい。
また、基板1の中心部と周辺部ではエッチンググレートに差が生ずるので、エッチンググレートの遅い中心部が貫通するために必要なエッチング時間に対応したエッチングマスクの厚さを設定しておくことが必要である。
In order to form the through micropores 5 in a silicon substrate having a thickness of several hundred μm or more, the thickness of the protective layer 2 may be appropriately determined from the thickness of the substrate 1 and the value of the selection ratio.
Further, since there is a difference in the etching rate between the central part and the peripheral part of the substrate 1, it is necessary to set the thickness of the etching mask corresponding to the etching time necessary for the central part having a slow etching rate to penetrate. It is.

また、Si0等の酸化膜を保護膜2として機能させるためには、0.5〜3μm程度の厚さが必要であるが、貫通微細孔5作成終了時に、前記の厚さに達しない場合でも、次工程である内壁絶縁層7形成において、基板表面1aも同時に膜形成作用を受けるように露出させておけば、微細孔壁面9と基板表面1aに同時に絶縁層を形成することができる。
このように貫通微細孔5を形成することにより、目視により基板1上の微細孔が全てエッチングされ、貫通したことを確認することが可能となる。
Further, if in order to function oxide film such as Si0 2 as the protective layer 2, it is necessary thickness of about 0.5 to 3 [mu] m, the through micropores 5 creates at the end, which does not reach the thickness of the However, in the formation of the inner wall insulating layer 7 as the next step, if the substrate surface 1a is also exposed so as to be subjected to the film forming action at the same time, the insulating layer can be formed simultaneously on the fine hole wall surface 9 and the substrate surface 1a.
By forming the through-holes 5 in this way, it is possible to confirm that all the fine holes on the substrate 1 have been etched and penetrated.

また、シリコン基板裏面側1bに保護層を形成した場合、この保護層は、シリコン基板1と比較して、エッチング速度が遅いため(保護層が酸化膜の場合は選択比で、1:100〜200程度、保護層がレジストの場合は選択比で、1:50〜100程度)、外周部の孔が貫通した後も、内周部の孔が貫通するまでエッチングを継続することが可能となる。よって、深さが整った貫通微細孔5を形成することができ、貫通微細孔5の深さは基板1の厚さで規定される。   Further, when a protective layer is formed on the back side 1b of the silicon substrate, the protective layer has a slower etching rate than the silicon substrate 1 (when the protective layer is an oxide film, the selectivity is 1: 100 to When the protective layer is a resist of about 200, the selection ratio is about 1:50 to 100), and even after the outer peripheral hole has penetrated, the etching can be continued until the inner peripheral hole penetrates. . Therefore, it is possible to form the through-hole 5 having a uniform depth, and the depth of the through-hole 5 is defined by the thickness of the substrate 1.

(工程3)
次に、工程3において、貫通微細孔5を形成済みの基板1に、非貫通孔11が形成された接合用基板6を接合する。
接合用基板6には、シリコン基板またはガラス基板を用いる。接合用基板6の接合方法、および、接合し電極用金属を充填した後の除去方法は、接合用基板6の材質によって異なる。
(Process 3)
Next, in step 3, the bonding substrate 6 in which the non-through holes 11 are formed is bonded to the substrate 1 in which the through micro holes 5 have been formed.
As the bonding substrate 6, a silicon substrate or a glass substrate is used. The joining method of the joining substrate 6 and the removing method after joining and filling the electrode metal differ depending on the material of the joining substrate 6.

まず、接合用基板6がシリコン基板である場合を説明する。シリコン基板は、例えば厚さが100〜300μm程度が望ましい。接合用基板6の外周全体に酸化膜等の絶縁膜12が形成された状態で、後述の方法により、非貫通孔11が形成されている。基板1の接合方法は、熱接合または、フォトレジスト等の樹脂による接合が使用される。以下に、これらの接合方法を説明する。   First, the case where the bonding substrate 6 is a silicon substrate will be described. The silicon substrate preferably has a thickness of about 100 to 300 μm, for example. With the insulating film 12 such as an oxide film formed on the entire outer periphery of the bonding substrate 6, the non-through hole 11 is formed by the method described later. As a bonding method of the substrate 1, thermal bonding or bonding with a resin such as a photoresist is used. Below, these joining methods are demonstrated.

接合用基板6がシリコン基板である場合は、基板1と接合用基板6を接合する際、両者の位置合せは、光学的手法を用いて行い、光学的手法は、赤外域に波長を有する光を用いる。
熱接合においては、貫通微細孔5を有する基板1および非貫通孔11を有する接合用基板6をアンモニアと過酸化水素の混合水溶液で洗浄することにより親水化処理を行ってから、両者を貼り合せる。その後、酸素雰囲気、または窒素雰囲気、または窒素と酸素の混合雰囲気により、加熱処理することによって接合が完了する。加熱処理における温度は800から1200℃、時間は30分〜12時間の間が望ましい。この場合、加熱処理中に、シリコン基板1の表面1aおよび貫通微細孔5および非貫通孔11の内壁に熱酸化反応により酸化膜が形成されるため、後に述べる工程4における壁面絶縁層7の形成は不要となる。
In the case where the bonding substrate 6 is a silicon substrate, when bonding the substrate 1 and the bonding substrate 6, both are aligned using an optical method, and the optical method is a light having a wavelength in the infrared region. Is used.
In thermal bonding, the substrate 1 having the through-holes 5 and the bonding substrate 6 having the non-through-holes 11 are washed with a mixed aqueous solution of ammonia and hydrogen peroxide, and then bonded together. . Thereafter, the bonding is completed by heat treatment in an oxygen atmosphere, a nitrogen atmosphere, or a mixed atmosphere of nitrogen and oxygen. The temperature in the heat treatment is desirably 800 to 1200 ° C., and the time is preferably 30 minutes to 12 hours. In this case, during the heat treatment, an oxide film is formed on the inner wall of the surface 1a of the silicon substrate 1 and the through-holes 5 and the non-through-holes 11 by a thermal oxidation reaction. Is no longer necessary.

また、樹脂による接合においては、フォトレジストを、例えば、0.5〜50μm程度の厚さで接合用基板6の片面に均一に塗布し、基板1に貼り合せる。その後、加熱処理することによって両基板1、6の接合が完了する。温度は、80〜200℃、時間は30分〜2時間の間が望ましい。
次に、接合用基板6がガラス基板である場合における接合を説明する。この場合、接合用基板6の厚さは100〜500μmが望ましい。接合方法は、陽極接合または樹脂による接合が行われる。以下に接合方法を説明する。
Further, in the bonding with the resin, the photoresist is uniformly applied to one surface of the bonding substrate 6 with a thickness of, for example, about 0.5 to 50 μm and bonded to the substrate 1. Then, joining of both the substrates 1 and 6 is completed by heat-processing. The temperature is preferably 80 to 200 ° C. and the time is preferably 30 minutes to 2 hours.
Next, joining in the case where the joining substrate 6 is a glass substrate will be described. In this case, the thickness of the bonding substrate 6 is preferably 100 to 500 μm. As a bonding method, anodic bonding or resin bonding is performed. The joining method will be described below.

接合用基板6がガラス基板である場合は、基板1と接合用基板6を接合する際、両者の位置合せは、光学的手法を用いて行い、光学的手法は、可視域に波長を有する光を用いる。
陽極接合法の場合は、基板1とガラスである接合基板6を貼り合せ、基板1を陽極側に、接合用基板6を陰極側に接続し、電圧を印加しながら加熱処理を行うことにより接合する。印加電圧600V、加熱温度は400〜500℃、加熱時間は1〜2時間が望ましい。また、樹脂による接合の方法は、接合用基板6がシリコンである場合に同様である。
When the bonding substrate 6 is a glass substrate, when the substrate 1 and the bonding substrate 6 are bonded, the alignment between the two is performed using an optical method, and the optical method is a light having a wavelength in the visible range. Is used.
In the case of the anodic bonding method, the substrate 1 and the bonding substrate 6 made of glass are bonded together, the substrate 1 is connected to the anode side, the bonding substrate 6 is connected to the cathode side, and the heat treatment is performed while applying voltage. To do. The applied voltage is 600 V, the heating temperature is 400 to 500 ° C., and the heating time is preferably 1 to 2 hours. The bonding method using resin is the same when the bonding substrate 6 is silicon.

次に、接合用基板6に、非貫通孔11を形成する方法について、図面を参照にして説明する。
接合用基板6がシリコン基板である場合、図2(a)におけるように、断面形状が半円状13である非貫通孔11(ここでは等方性の非貫通孔という)を形成するため、ウェットエッチングにより形成する際は、フッ酸、硝酸、酢酸の混合液を使用し、ドライエッチングでは、SF6ガス、CF4ガス、酸素ガス、又は、これらの混合ガスを使用する。また、図2(b)におけるように、断面形状が、角度の異なる複数の平面14、15、16を有する台形状である非貫通孔11(ここでは異方性の非貫通孔という)を形成するため、KOH(水酸化カリウム)、または、TMAH(水酸化テトラメチルアンモニウム)を使用したウェットエッチング、または、ドライエッチングを行う。また、図2(c)におけるように、断面形状が垂直の側面17を有する長方形状である非貫通孔11(ここでは垂直性の非貫通孔という)を形成するため、例えば、Deep-RIE法(シリコン基板を垂直に、深くエッチングするドライエッチング方法で、エッチングガスとしては一般にSF6ガスとC4F8ガスを用いる。SF6はシリコンをエッチングする役割、C4F8はエッチング穴の側壁にポリマーの保護膜を形成する役目を担い、エッチングと保護膜形成プロセスを交互い行いながら垂直に且つ深くシリコンをエッチングする)を用いる。
Next, a method for forming the non-through holes 11 in the bonding substrate 6 will be described with reference to the drawings.
When the bonding substrate 6 is a silicon substrate, as shown in FIG. 2A, in order to form a non-through hole 11 having a semicircular cross-sectional shape 13 (referred to as an isotropic non-through hole here), When forming by wet etching, a mixed solution of hydrofluoric acid, nitric acid, and acetic acid is used, and in dry etching, SF6 gas, CF4 gas, oxygen gas, or a mixed gas thereof is used. Further, as shown in FIG. 2B, a non-through-hole 11 (here, referred to as an anisotropic non-through-hole) having a trapezoidal shape having a plurality of planes 14, 15, 16 having different cross-sectional shapes is formed. Therefore, wet etching using KOH (potassium hydroxide) or TMAH (tetramethylammonium hydroxide) or dry etching is performed. Further, as shown in FIG. 2C, in order to form a non-through hole 11 having a rectangular cross section having a vertical side surface 17 (herein referred to as a vertical non-through hole), for example, the Deep-RIE method (This is a dry etching method that etches the silicon substrate vertically and deeply. As the etching gas, SF6 gas and C4F8 gas are generally used. SF6 plays the role of etching silicon, and C4F8 forms a polymer protective film on the sidewall of the etching hole. The silicon is etched vertically and deeply while alternately performing the etching and the protective film forming process.

シリコン基板に非貫通孔11を形成する場合、非貫通孔11の深さは、例えば10〜100μm、非貫通孔11の幅は、例えば30μmから100μmとなるようにする。
接合用基板6がガラス基板である場合、等方性の非貫通孔11を形成する場合、ウェットエッチングでは、フッ酸、硝酸、酢酸の混合液、ドライエッチングでは、SF6ガス、CF4ガス、酸素ガス、又は、これらの混合ガスを使用する。ガラスでは、等方性の非貫通孔11のみが形成可能となっており、非貫通孔11の深さは、例えば10〜100μm、非貫通孔11の幅は、例えば30μmから100μmとなるようにする。
When the non-through hole 11 is formed in the silicon substrate, the depth of the non-through hole 11 is, for example, 10 to 100 μm, and the width of the non-through hole 11 is, for example, 30 μm to 100 μm.
When the bonding substrate 6 is a glass substrate, when the isotropic non-through hole 11 is formed, a hydrofluoric acid, nitric acid, acetic acid mixed solution is used in wet etching, and SF6 gas, CF4 gas, oxygen gas is used in dry etching. Alternatively, a mixed gas of these is used. In glass, only the isotropic non-through hole 11 can be formed. The depth of the non-through hole 11 is, for example, 10 to 100 μm, and the width of the non-through hole 11 is, for example, 30 μm to 100 μm. To do.

(工程4)
図1に戻って説明すると、工程4において、貫通微細孔5の内壁および接合用基板6に形成された非貫通孔の内壁に壁面絶縁層7を形成する。基板1は、シリコン基板であり、導電性を有するため、基板1と貫通電極27との間に絶縁性部分を設ける必要があるため、壁面絶縁層7を形成する。壁面絶縁層7はSiO等の酸化膜であり、形成方法は、熱酸化法、PE−CVD法、陽極酸化法などである。基板接合において熱接合を行った場合は、この工程は不要である。
(Process 4)
Referring back to FIG. 1, in step 4, the wall surface insulating layer 7 is formed on the inner wall of the through microhole 5 and the inner wall of the non-through hole formed in the bonding substrate 6. Since the substrate 1 is a silicon substrate and has conductivity, it is necessary to provide an insulating portion between the substrate 1 and the through electrode 27, and thus the wall surface insulating layer 7 is formed. The wall surface insulating layer 7 is an oxide film such as SiO 2 , and the formation method is a thermal oxidation method, a PE-CVD method, an anodic oxidation method, or the like. This step is not necessary when thermal bonding is performed in the substrate bonding.

(工程5)
工程5において、壁面絶縁層7を形成した貫通微細孔5および非貫通孔11に、開口部28から貫通電極用の金属を充填し、導電部8および、バンプや配線となる突出部10からなる貫通電極27を形成する。貫通電極27は、導電部8と突出部10とが同時に成形され、導電部8と突出部10との間に界面のない一体構造となる。一体構造であるため、導電部8と突出部10との間に、酸化層は検出されない。又、導電部8に突出部10が重なる方向から見て、突出部10は、導電部8よりも広い面積を有しており、特に、基板1の断面方向から見て、突出部10が導電部8に接する部分において、突出部10の幅は導電部8の幅より大きいものとなっている。充填方法として、溶融金属吸引法、印刷法、CVD法などが使用される。
(Process 5)
In step 5, the through-holes 5 and the non-through-holes 11 in which the wall surface insulating layer 7 is formed are filled with the metal for the through-electrodes from the openings 28, and the conductive portions 8 and the protruding portions 10 that become bumps and wirings are formed. A through electrode 27 is formed. In the through electrode 27, the conductive portion 8 and the protruding portion 10 are formed at the same time, and an integrated structure without an interface between the conductive portion 8 and the protruding portion 10 is formed. Because of the integral structure, no oxide layer is detected between the conductive portion 8 and the protruding portion 10. In addition, the protrusion 10 has a larger area than the conductive portion 8 when viewed from the direction in which the protrusion 10 overlaps the conductive portion 8. In particular, the protrusion 10 is electrically conductive when viewed from the cross-sectional direction of the substrate 1. In the portion in contact with the portion 8, the width of the protruding portion 10 is larger than the width of the conductive portion 8. As a filling method, a molten metal suction method, a printing method, a CVD method, or the like is used.

溶融金属吸引法は、高アスペクト比の微細孔に金属を充填する場合に用いられる方法であって、まず、減圧した気密容器内において微細孔を形成した基板を加熱溶融した金属に挿入する。次いで容器内を加圧することにより、微細孔内部と気密容器内部の気圧差を利用して微細孔内部および突出部に溶融金属を充填した後、基板を溶融金属から取り出して冷却することにより、微細孔および突出部に金属を充填する。   The molten metal suction method is a method used when a high-aspect-ratio fine hole is filled with a metal. First, a substrate in which a fine hole is formed is inserted into a heat-melted metal in a vacuum-tight airtight container. Then, by pressurizing the inside of the container, the inside of the microhole and the protruding portion are filled with the molten metal using the pressure difference between the inside of the microhole and the inside of the airtight container, and then the substrate is taken out from the molten metal and cooled. Fill holes and protrusions with metal.

(工程6)
工程6において、接合用基板6を、研磨もしくはエッチングにより除去する。エッチングは、ドライエッチング、ウェットエッチングのどちらも適用可能である。ドライエッチングの場合は、SF6ガス、CF4ガス、酸素ガス、又はこれらの混合ガスを用い、ウェットエッチングの場合は、フッ酸、硝酸、酢酸の混合液あるいは、水酸化カリウム水溶液などが用いられる。
エッチングまたは研磨によって除去する接合用基板6の厚さは、接合用基板6の材質によって異なる。接合用基板6がシリコンである場合は、すでに基板1と接合用基板6の間に裏面絶縁層4が形成されているため、接合用基板6の厚さに等しい厚さを研磨もしくはエッチングして除去すれば、裏面絶縁層4が露出する状態となり、この状態で、突出部10が露出する。よって、従来技術のように、コンタクトホールを形成する必要はない。つまり、突出部10が形成された状態で、絶縁層部分7が除去されるため、導電部8と絶縁層部分7との間の隙間が生じるという問題は生じない。
(Step 6)
In step 6, the bonding substrate 6 is removed by polishing or etching. As the etching, either dry etching or wet etching can be applied. In the case of dry etching, SF6 gas, CF4 gas, oxygen gas, or a mixed gas thereof is used. In the case of wet etching, a mixed solution of hydrofluoric acid, nitric acid, and acetic acid, an aqueous potassium hydroxide solution, or the like is used.
The thickness of the bonding substrate 6 removed by etching or polishing varies depending on the material of the bonding substrate 6. When the bonding substrate 6 is silicon, the back insulating layer 4 has already been formed between the substrate 1 and the bonding substrate 6, so that the thickness equal to the thickness of the bonding substrate 6 is polished or etched. If it removes, it will be in the state which the back surface insulating layer 4 will be exposed, and the protrusion part 10 will be exposed in this state. Therefore, it is not necessary to form a contact hole as in the prior art. That is, since the insulating layer portion 7 is removed in the state where the protruding portion 10 is formed, there is no problem that a gap is generated between the conductive portion 8 and the insulating layer portion 7.

一方、接合用基板6がガラス基板の場合は、基板1と接合用基板6との間に裏面絶縁層4がないため、ガラスである接合用基板5を、その厚さが数μm程度残るところで除去を中止し、残存したガラス層を裏面絶縁層4として絶縁および表面保護に用いる。
いずれの接合用基板除去方法においても、基板1はその厚さが変化することはないので、貫通微細孔5の深さは一定であり、基板1の厚さに等しい。従って、貫通電極27作成後の基板1の厚さは、高い精度で一定となり、厚さ再現性の高い貫通電極付き基板の製造が可能である。
On the other hand, when the bonding substrate 6 is a glass substrate, there is no back surface insulating layer 4 between the substrate 1 and the bonding substrate 6, so that the bonding substrate 5 made of glass remains at a thickness of about several μm. The removal is stopped, and the remaining glass layer is used as the back insulating layer 4 for insulation and surface protection.
In any bonding substrate removing method, since the thickness of the substrate 1 does not change, the depth of the through microhole 5 is constant and equal to the thickness of the substrate 1. Therefore, the thickness of the substrate 1 after the through electrode 27 is formed is constant with high accuracy, and a substrate with a through electrode with high thickness reproducibility can be manufactured.

尚、図2(a)、(b)、(c)における、接合用基板6の非貫通孔11の形状に応じた突出部10が形成される。特に、図2(c)における接合用基板6を用いた場合、複数の導電部8に接してなる突出部10が一体をなし、突出部10が、複数の導電部8と電気的に連通するものとなる。   In addition, the protrusion part 10 according to the shape of the non-through-hole 11 of the board | substrate 6 for joining in FIG. 2 (a), (b), (c) is formed. In particular, when the bonding substrate 6 in FIG. 2C is used, the protrusions 10 in contact with the plurality of conductive portions 8 are integrated, and the protrusions 10 are in electrical communication with the plurality of conductive portions 8. It will be a thing.

次に、本発明の実施例について説明する。直径が2インチであり、厚さが400μmであるシリコン基板を用意し、シリコン基板の表面に熱酸化法により保護膜としてのSiO膜を形成後、フォトリソグラフィ技術により電極パターンを保護膜上に転写し、ウェットエッチングにより電極部位となるシリコン基板上の保護膜を除去した。
転写した電極パターンは、孔径が60μmの円形孔が、2000個整列したパターンである。また、ウェットエッチング後のSiO膜厚は1μmであり、これを次の貫通微細孔形成用エッチングのマスクとした。
Next, examples of the present invention will be described. A silicon substrate having a diameter of 2 inches and a thickness of 400 μm is prepared. After forming a SiO 2 film as a protective film on the surface of the silicon substrate by a thermal oxidation method, an electrode pattern is formed on the protective film by a photolithography technique. The protective film on the silicon substrate which becomes the electrode part was removed by transfer and wet etching.
The transferred electrode pattern is a pattern in which 2000 circular holes having a hole diameter of 60 μm are arranged. The SiO 2 film thickness after wet etching was 1 μm, and this was used as a mask for the next etching for forming through-microholes.

貫通微細孔は、ICP−RIEにより形成した。次に、基板接合を行った。接合する基板は、直径が2インチであり、厚さが200μmのシリコン基板であって、所定形状の非貫通孔が設けられている。両方の基板をアンモニアと過酸化水素の混合水溶液で洗浄することにより親水化処理を行ったのち、貼り合わせた。
貼り合わせた基板を、酸素雰囲気中で1100℃、3時間の加熱処理を行った。この例においては、熱接合法をもちいたため、接合工程において壁面絶縁層が形成され、新たに壁面絶縁層形成を行う必要はなかった。
The through micropores were formed by ICP-RIE. Next, substrate bonding was performed. The substrate to be joined is a silicon substrate having a diameter of 2 inches and a thickness of 200 μm, and is provided with a non-through hole having a predetermined shape. Both substrates were subjected to a hydrophilic treatment by washing with a mixed aqueous solution of ammonia and hydrogen peroxide, and then bonded together.
The bonded substrates were subjected to heat treatment at 1100 ° C. for 3 hours in an oxygen atmosphere. In this example, since a thermal bonding method was used, a wall surface insulating layer was formed in the bonding step, and it was not necessary to newly form a wall surface insulating layer.

次いで、溶融金属法によって微細孔および非貫通孔中に電極となる金属を注入し、接合した基板を研磨によって除去した。研磨量は200μmであり、接合した基板の厚さに等しい。
このようにして、出発基板の厚さと実質的に同じ厚さを有するとともに、バンプや配線となる突出部を有する貫通電極付き基板を得ることができた。
Next, a metal serving as an electrode was injected into the fine holes and the non-through holes by a molten metal method, and the bonded substrate was removed by polishing. The polishing amount is 200 μm, which is equal to the thickness of the bonded substrates.
In this way, it was possible to obtain a substrate with a through electrode having a thickness substantially the same as the thickness of the starting substrate and having protrusions serving as bumps and wiring.

本発明の実施の形態による貫通電極付き基板の製造方法である。It is a manufacturing method of the board | substrate with a penetration electrode by embodiment of this invention. 本発明の実施の形態による接合用基板を示す図である。It is a figure which shows the board | substrate for joining by embodiment of this invention.

符号の説明Explanation of symbols

1‥‥基板、2‥‥保護層、5‥‥貫通微細孔(微細孔)、6‥‥接合用基板、7‥‥壁面絶縁層、8‥‥導電部、10‥‥突出部、11‥‥非貫通孔、27‥‥貫通電極、28‥‥開口部、29‥‥貫通電極付き基板

DESCRIPTION OF SYMBOLS 1 ... Board | substrate, 2 ... Protective layer, 5 ... Through-micro hole (micro hole), 6 ... Bonding board, 7 ... Wall insulation layer, 8 ... Conductive part, 10 ... Projection part, 11 ... ······································ Non-through hole, 27 ·············

Claims (9)

基板と、該基板内をその厚さ方向に貫通する導電部と、前記基板の一方の面から突出し、前記導電部と一体をなす突出部とを有し、前記導電部と前記突出部とで貫通電極を形成しており、前記導電部に前記突出部が重なる方向から見て、前記突出部は前記導電部より広い面積を有していることを特徴とする貫通電極付き基板。 A substrate, a conductive portion that penetrates the substrate in the thickness direction, and a protruding portion that protrudes from one surface of the substrate and is integrated with the conductive portion, and the conductive portion and the protruding portion A substrate with a through electrode, wherein a through electrode is formed, and the protrusion has a larger area than the conductive portion when viewed from a direction in which the protrusion overlaps the conductive portion. 前記基板の断面方向から見て、前記突出部が前記導電部と接する部分において、前記突出部の幅は前記導電部の幅より大きいことを特徴とする請求項1に記載の貫通電極付き基板。 2. The substrate with through electrodes according to claim 1, wherein a width of the protruding portion is larger than a width of the conductive portion at a portion where the protruding portion is in contact with the conductive portion when viewed from a cross-sectional direction of the substrate. 前記突出部の断面は、略半円状、台形状、方形状のうち何れかの形状であることを特徴とする請求項1又は2に記載の貫通電極付き基板。 3. The substrate with a through electrode according to claim 1, wherein a cross section of the projecting portion has any one of a substantially semicircular shape, a trapezoidal shape, and a square shape. 複数の導電部に接してなる前記突出部が一体をなすことを特徴とする請求項1〜3の何れかに記載の貫通電極付き基板。 The board | substrate with a penetration electrode in any one of Claims 1-3 in which the said protrusion part formed in contact with several electroconductive part makes integral. 貫通孔を有する基板と非貫通孔を有する接合用基板とを用い、前記貫通孔と前記非貫通孔が連通するように前記基板と前記接合用基板との位置合せを行い、前記基板と前記接合用基板とを接合する工程と、
前記基板の前記貫通孔の開口部から導電性を有する母材を充填する工程と、
前記接合用基板を除去する工程と、を少なくとも具備することを特徴とする貫通電極付き基板の製造方法。
Using a substrate having a through hole and a bonding substrate having a non-through hole, the substrate and the bonding substrate are aligned so that the through hole and the non-through hole communicate with each other. Bonding the substrate to the substrate,
Filling a conductive base material from the opening of the through hole of the substrate;
And a step of removing the bonding substrate. A method of manufacturing a substrate with a through electrode, comprising: a step of removing the bonding substrate.
前記位置合せは、光学的手法を用いることを特徴とする請求項5に記載の貫通電極付き基板の製造方法。 The method for manufacturing a substrate with a through electrode according to claim 5, wherein the alignment uses an optical method. 前記接合用基板として、シリコン基板、又は、ガラス基板を用いることを特徴とする請求項5又は6に記載の貫通電極付き基板の製造方法。 The method for manufacturing a substrate with a through electrode according to claim 5 or 6, wherein a silicon substrate or a glass substrate is used as the bonding substrate. 前記接合用基板がシリコン基板の場合、前記光学的手法は、赤外域に波長を有する光を用いることを特徴とする請求項6に記載の貫通電極付き基板の製造方法。 When the said board | substrate for joining is a silicon substrate, the said optical method uses the light which has a wavelength in an infrared region, The manufacturing method of the board | substrate with a penetration electrode of Claim 6 characterized by the above-mentioned. 前記接合用基板がガラス基板の場合、前記光学的手法は、可視域に波長を有する光を用いることを特徴とする請求項6に記載の貫通電極付き基板の製造方法。

When the said board | substrate for joining is a glass substrate, the said optical method uses the light which has a wavelength in a visible region, The manufacturing method of the board | substrate with a penetration electrode of Claim 6 characterized by the above-mentioned.

JP2003311919A 2003-09-03 2003-09-03 Substrate with through electrode and manufacturing method of the same Withdrawn JP2005079554A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101152267B1 (en) 2010-05-19 2012-06-08 성균관대학교산학협력단 Method for manufacturing silicon interposer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101152267B1 (en) 2010-05-19 2012-06-08 성균관대학교산학협력단 Method for manufacturing silicon interposer

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