JP2005079491A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device by which the repair of a defect of a wiring pattern can be made efficiently. <P>SOLUTION: A wiring pattern is formed on a semiconductor wafer (S101). Subsequently, visual inspection on the formed wiring pattern is carried out (S102). The visual inspection is performed by comparing wiring patterns between neighboring cells. Next, the kind of the defect detected by the visual inspection is discriminated (S103). The discrimination of the kind of the defect is carried out in such a way that a designed layout pattern and an actual wiring pattern are subdivided, and whether the defect is a short-circuit defect or a disconnection defect is discriminated by comparing whether a pattern exists or not in a subdivided region of the layout pattern and whether a pattern exists or not in the corresponding subdivided region of the wiring pattern. Then, the discriminated defect of the short-circuit type or the disconnection type is repaired as required. The repair is carried out by a photolithography technology using an electron-beam exposure apparatus and an etching technology. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device manufacturing technique, and more particularly to a technique effective when applied to a semiconductor device manufacturing technique in which it is difficult to relieve defects by a redundant circuit.

  The semiconductor device manufacturing process includes a substrate process for forming a transistor on a semiconductor wafer and a wiring process for forming a wiring pattern via an interlayer insulating film on the semiconductor wafer on which the transistor is formed. In the wiring process, a wiring pattern is formed over multiple layers. After the wiring pattern is formed on each layer, a normal appearance inspection is performed. The appearance inspection is for inspecting whether there is a defect in the wiring pattern formed in the wiring process, and is used for process QC (Quality Control) and defect analysis.

  As a technique for repairing a defect detected by an appearance inspection, for example, there is a technique shown below. In JP-A-7-326613 (Patent Document 1), the etching gas is caused to react with the metal constituting the short-circuit defect portion by irradiating the short-circuit defect portion of the wiring pattern with laser light in the etching gas. A technique for removing short-circuit defects is described.

  Japanese Patent Laid-Open No. 7-029982 (Patent Document 2) drops a solution containing a metal complex on a disconnection defect portion of a wiring pattern, and irradiates the solution with laser light to deposit metal on the disconnection defect portion. A technique for making electrical connections is described.

Furthermore, Japanese Patent Application Laid-Open No. 10-294313 (Patent Document 3) describes a technique in which a voltage is applied to a wiring pattern in an organic metal gas to deposit a metal at a disconnection defect portion and make an electrical connection. .
Japanese Patent Laid-Open No. 7-326613 (pages 2 to 3, FIG. 2) JP-A-7-029982 (pages 3 to 4, FIG. 2) Japanese Patent Laid-Open No. 10-294313 (second page, FIG. 1)

  However, although the above-described appearance inspection process can specify the position coordinates where the defect exists, it cannot specify the type of the detected defect. For this reason, after the appearance inspection is performed, the type of the defect is manually identified and the defect is corrected. That is, since it is impossible to automatically determine whether the type of defect detected in the appearance inspection process is a short-circuit defect or a disconnection defect, TAT (turn around time) for defect correction cannot be reduced. There is a point.

  In addition, the above-mentioned technologies are used to correct short-circuit defects and disconnection defects that occur in wiring patterns. These technologies are dedicated technologies for correcting defects, and capital investment is required for their introduction. In addition to this, the development of facilities becomes difficult. In particular, the technology for correcting the disconnection defect and the technology for correcting the short-circuit defect are different from each other, and both devices need to be newly introduced in order to be able to correct both defects. Therefore, there is a problem that further capital investment is required and the development of the facility becomes difficult.

  An object of the present invention is to provide a semiconductor device manufacturing technique capable of improving the efficiency of defect correction of a wiring pattern.

  Another object of the present invention is to provide a semiconductor device manufacturing technique capable of suppressing an increase in equipment investment and reducing equipment development.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  A method of manufacturing a semiconductor device according to the present invention includes: (a) a step of forming a wiring pattern; and (b) a step of correcting a short-circuit defect generated when forming the wiring pattern after the step (a). The step (b) includes (b1) a step of forming a resist film opened on the short-circuit defect, and (b2) a step of removing the short-circuit defect by etching using the resist film as a mask. It is characterized by.

  The method for manufacturing a semiconductor device according to the present invention includes (a) a step of forming a wiring pattern, and (b) a step of correcting a disconnection defect generated when forming the wiring pattern after the step (a). The step (b) includes: (b1) a step of forming an insulating film on the region including the disconnection defect; and (b2) a step of forming a resist film having an opening on the disconnection defect on the insulating film. (B3) removing the insulating film formed in the disconnection defect by etching the insulating film using the resist film as a mask; and (b4) in the disconnection defect and in the insulating film. And (b5) a step of removing the conductor film formed on the insulating film.

  Further, the method of manufacturing a semiconductor device according to the present invention includes (a) a step of forming a wiring pattern, (b) a step of detecting a defect existing in the wiring pattern, and (c) a type of the detected defect automatically. A step of determining, and (d) a step of correcting the detected defect.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  The efficiency of wiring pattern defect correction can be improved.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

  A method for manufacturing a semiconductor device in the present embodiment will be described with reference to the drawings. FIG. 1 is a flowchart showing a flow of a method for manufacturing a semiconductor device in the present embodiment. The flow of this embodiment will be briefly described using this flowchart.

  First, in the method of manufacturing a semiconductor device in the present embodiment, a semiconductor element is formed on a semiconductor wafer using a normal semiconductor manufacturing technique, and then a wiring pattern is formed through an interlayer insulating film (S101).

  Subsequently, an appearance inspection is performed to check whether the formed wiring pattern has a defect (S102). This appearance inspection detects the presence or absence of a defect, and cannot identify the type of defect.

  Next, the type of defect detected by appearance inspection is determined (S103). For example, in this step, it is determined whether the defect detected by the appearance inspection is a short-circuit defect that short-circuits the wirings or a disconnection defect that disconnects the wirings.

  Subsequently, it is determined based on a predetermined condition whether the defect generated in the wiring pattern is to be corrected (S104). At this time, for example, (a) no correction is performed, (b) only short-circuit defects are corrected, (c) only disconnection defects are corrected, and (d) both short-circuit defects and disconnection defects are corrected. Thus, it can be divided into four results.

  In order to divide into four types of results, for example, the defect is first corrected by determining whether or not the defect should be corrected, and the case where the defect is not corrected and is left as it is. When correcting the defect, it is next determined whether to correct both the short-circuit defect and the disconnection defect (S105). This S105 can be divided into a case where both the short-circuit defect and the disconnection defect are corrected (S106) and a case where it is not. When both the short-circuit defect and the disconnection defect are not corrected, it is determined whether or not the short-circuit defect is corrected next (S107). This S107 is divided into a case where only the short-circuit defect is corrected (S108) and a case where only the disconnection defect is corrected (S109). In this way, the above four results can be divided.

  Subsequently, predetermined processing is performed in accordance with the above four determination results. That is, when only the short-circuit defect is corrected, the short-circuit defect is corrected. When only the disconnection defect is corrected, the disconnection defect is corrected. When correcting both the short-circuit defect and the disconnection defect, first, one defect such as a short-circuit defect is corrected, and the next other defect such as a disconnection defect is corrected. When the same wafer has a region for correcting both the short-circuit defect and the disconnection defect and a region for correcting only the short-circuit defect, the disconnection defect is corrected after correcting the short-circuit defect. Further, when there is a region for correcting both the short-circuit defect and the disconnection defect and a region for correcting only the disconnection defect, the disconnection defect is corrected after correcting the short-circuit defect. When the defect is not corrected, the defect is left as it is.

  Thereafter, an interlayer insulating film is formed on the wiring pattern, and a new wiring pattern is formed on the interlayer insulating film. After a new wiring pattern is formed on the upper layer, the above steps are repeated. In this way, defects existing in the wiring pattern can be corrected as necessary.

  Below, the detail of each above-mentioned process is demonstrated, referring drawings. First, the step of forming wiring (S101) will be described. FIG. 2 is a plan view showing a state in which the wiring 2 and the wiring 3 are formed on the predetermined region of the semiconductor wafer via the interlayer insulating film 1, and FIG. 3 is a cross-sectional view taken along the line AA of FIG. . In FIG. 3, the structure below the interlayer insulating film 1 is not shown.

  As shown in FIG. 2, the wiring 2 and the wiring 3 are formed in parallel to each other in a predetermined region of the semiconductor wafer, and a wiring pattern is formed by the wiring 2 and the wiring 3. Here, the semiconductor wafer has a plurality of chip formation regions, and a similar wiring pattern is formed in each chip formation region. In FIG. 2, a part of one chip region is shown enlarged, and a wiring pattern is formed by the wiring 2 and the wiring 3 in this enlarged region.

  The wiring 2 and the wiring 3 are formed on the interlayer insulating film 1 as shown in FIG. 3, and are each formed of a laminated film of a titanium / titanium nitride film 2a, an aluminum film 2b, and a titanium / titanium nitride film 2c. . Such wiring 2 and wiring 3 are formed as follows.

  First, as shown in FIG. 3, an interlayer insulating film 1 is formed on a semiconductor wafer (not shown). The interlayer insulating film 1 is made of, for example, a silicon oxide film, and can be formed using, for example, a CVD (Chemical Vapor Deposition) method.

  Next, as shown in FIG. 3, a titanium / titanium nitride film 2a, an aluminum film 2b, and a titanium / titanium nitride film 2c are sequentially formed on the interlayer insulating film 1. These films can be formed using, for example, a sputtering method. Subsequently, a resist film having photosensitivity is applied on these laminated films, and then the resist film is patterned by exposing and developing. The patterning is performed so that the resist film remains only in the region where the wirings 2 and 3 are to be formed. Thereafter, the wiring 2 and the wiring 3 are formed by etching using the patterned resist film as a mask, and a wiring pattern including the wiring 2 and the wiring 3 is formed.

  Next, an appearance inspection process (S102) for inspecting whether the wiring pattern formed in the wiring forming process (S101) is normally formed will be described.

  4 is a plan view showing a state in which the wiring pattern is normally formed, while FIGS. 5 and 6 show a state in which the defect is formed without the wiring pattern being normally formed. It is a top view. That is, FIG. 5 is a diagram showing a state in which the wiring 2 and the wiring 3 are connected by the short-circuit defect 4, and FIG. 6 shows a state in which the disconnection defect 5 is formed in the wiring 2. It is a figure.

  Normally, if the process of forming the wiring is performed normally, a normal wiring pattern is formed as shown in FIG. 4, but if the wiring formation is not performed normally, the state shown in FIGS. Become. For example, as described above, a patterned resist film is formed on the laminated film composed of the titanium / titanium nitride film 2a, the aluminum film 2b, and the titanium / titanium nitride film 2c. However, the resist film is originally removed due to a patterning deviation or the like. The resist film may remain in the power region. Then, in the subsequent etching of the laminated film, the laminated film to be etched remains without being removed, and for example, a short-circuit defect 4 as shown in FIG. 5 is formed. On the contrary, if the resist film does not remain in the region where the resist film is originally formed, the laminated film that should not be removed is etched when the laminated film is etched, and a disconnection defect 5 as shown in FIG. 6 is formed. It will be. It is an appearance inspection process that detects such a defect.

  In the appearance inspection process, for example, the wiring patterns are compared between adjacent cell regions, and the presence or absence of a defect is detected by detecting a difference in the wiring patterns. If a normal wiring pattern is formed in the adjacent cell region, it can be determined that no defect exists because no difference is detected in the wiring pattern. On the other hand, if there is a defect in one of the adjacent cell regions, a difference occurs in the wiring pattern, so that the presence of the defect can be detected. At this time, since it is possible to detect in which part the pattern is different, the position coordinates of the defect can be specified. However, this appearance inspection process simply detects defects based on the difference in wiring patterns, and does not detect how the wiring patterns are different. However, the type of defect has not been identified. Since it is only necessary to be able to compare in units in which the same wiring pattern is formed, the wiring patterns are not compared between adjacent cell regions, for example, the wiring patterns are compared between adjacent chip regions. Also good. In addition, since defects may exist in adjacent cell regions, for example, a defect may be detected using a wiring pattern that is known to be normal in advance.

  Next, the step (S103) of determining the type of defect detected in the appearance inspection step will be described. In the appearance inspection process, a defect is detected and a position coordinate where the defect exists is specified. Therefore, in the process of determining the type of defect, the actual wiring pattern (image data) and the layout pattern (image data) indicating the designed normal wiring pattern are subdivided near the position coordinates where the defect exists. The type of the defect is specified by comparing them.

  Specifically, an actual wiring pattern in the vicinity of the position coordinate where the defect exists is subdivided into a plurality of areas, and the layout pattern is also subdivided in the vicinity of the position coordinate of the defect. FIG. 7 shows a state in which the designed normal layout pattern is subdivided into a plurality of regions. Similarly, FIG. 8 shows a state where an actual wiring pattern in which the short-circuit defect 4 exists is subdivided in the vicinity of the short-circuit defect 4, and FIG. 9 shows an actual wiring pattern in which the disconnection defect 5 exists in the vicinity of the disconnection defect 5. Shows a subdivision.

  This subdivision is performed in the same way for the layout pattern and the actual wiring pattern. That is, the number of subdivided areas is the same in the layout pattern and the actual wiring pattern, and the area of each subdivided area and the position coordinates of each area are the same in the layout pattern and the actual wiring pattern. Done.

  Next, the presence or absence of the pattern is recognized for each individual area of the actual wiring pattern. This recognition is performed by comparing the amount of light of the captured image (brightness and darkness on the screen) with a preset threshold value.

  Next, the presence or absence of a pattern is compared for each subdivided area. For example, when comparing FIG. 7 showing a layout pattern and FIG. 8 showing an example of an actual wiring pattern, the presence / absence of the pattern is compared in the region 6a of FIG. 7 and the region 6b of FIG. The That is, the pattern presence / absence is compared between the region 6a and the region 6b corresponding to the region 6a. Such comparison is performed for all subdivided areas.

  When the actual wiring pattern is normal, the pattern matches in the layout pattern region and the corresponding wiring pattern region. However, when the short-circuit defect 4 that short-circuits the wiring 2 and the wiring 3 exists as shown in FIG. 8, in the region on the short-circuit defect 4, the layout pattern region and the corresponding actual wiring pattern region With or without pattern. For example, when comparing the region 6a in FIG. 7 with the region 6b in FIG. 8, the region 6a in FIG. 7 is a region that should not have a pattern from the layout data, whereas the region 6b in FIG. The amount of light corresponding to (the same material as the wirings 2 and 3) is detected and recognized as having a pattern. Such a pattern difference occurs in a region on the short-circuit defect 4.

  It can be seen from the layout data that the region 6a in FIG. 7 is a region where no wiring is formed (a region where the interlayer insulating film 1 is formed). As described above, the pattern of this region 6a and FIG. There is a difference between the pattern of the region 6b shown in FIG. Therefore, it can be seen that the wiring is formed in the region 6b in the actual wiring pattern. That is, a wiring that should not be formed is formed in the region 6b.

  In this way, it is possible to determine that the defect is the short-circuit defect 4 connecting the wiring 2 and the wiring 3 by comparing the presence or absence of the pattern in all the subdivided regions.

  Similarly, by comparing the layout pattern shown in FIG. 7 with the actual wiring pattern shown in FIG. 9, it is possible to determine that the disconnection defect 5 is formed in the actual wiring pattern. That is, when there is a disconnection defect 5 that disconnects the wiring 2 as shown in FIG. 9, the pattern on the area on the disconnection defect 5 is different between the area of the layout pattern and the area of the actual wiring pattern corresponding thereto. For example, when the pattern presence / absence is compared between the region 7a in FIG. 7 and the corresponding region 7b in FIG. 9, the region 7a in FIG. 7 is a region that should have a pattern from the layout data. From the region 7b of 9, the light quantity corresponding to the interlayer insulating film 1 is detected, and it is recognized that there is no wiring pattern. Such a difference in the presence / absence of the pattern occurs in a region on the disconnection defect 5 of the wiring 2 among the regions obtained by subdividing the wiring pattern.

  From the layout data, it can be seen that the region 7a in FIG. 7 is a region where the wiring 2 is to be formed, while the region 7b in FIG. 9 is that the wiring 2 is not formed. Accordingly, it can be seen that the wiring 2 is not formed on the interlayer insulating film 1 in the region 7b of the actual wiring pattern. By performing the comparison of the pattern presence / absence for all the subdivided regions, for example, in the case of FIG. 9, it is possible to determine that the defect detected by the appearance inspection is the disconnection defect 5.

  As described above, the type of defect detected in the appearance inspection process (S102) can be automatically determined. In the above description, the case where the designed layout pattern is used has been described. For example, instead of the layout pattern, a wiring pattern that has been found to be normal may be used as a comparison target.

  Next, the process of determining defect correction (S104, S105, S107) will be described.

  As described above, the defect whose position coordinates are specified is detected in the appearance inspection step (S102), and the detected defect type is automatically determined in the defect type determination step (S103). Therefore, all the detected defects can be corrected in the subsequent process.

  However, it may not be efficient to correct all detected defects. For example, when the number of detected defects is within an allowable range, the manufacturing process can be simplified by leaving the defects without correction. Moreover, TAT can be shortened. On the other hand, even when the number of defects exceeds a predetermined number, it may be better to make a defective product than to correct all the defects.

  In general, the correction method differs depending on the type of defect, and the time required for correction also differs. Therefore, it is possible to further improve the efficiency of the manufacturing process and shorten the TAT by determining whether or not to correct the defect according to the type of defect.

  Therefore, in the method of manufacturing a semiconductor device according to the present embodiment, a step of determining whether or not to correct a defect is provided. For example, in the method of manufacturing a semiconductor device according to the present embodiment, as a determination result, (a) no correction is performed, (b) only a short-circuit defect is corrected, (c) only a disconnection defect is corrected, (d) a short circuit. The results are divided into four results, such as correcting both defects and disconnection defects.

  As a method of dividing into four determination results in this way, it is first determined whether or not to correct a defect based on a predetermined condition (S104). As the predetermined condition, for example, data such as the allowable number of defects that are allowed without correction or the number of defects that are out of limits that are not corrected are input in advance, and the input data is detected. Comparing the number of defects can be a condition.

  That is, when the number of detected defects is within the allowable number of defects input in advance, it is determined that the defect is not corrected. Also, it is determined that the defect is not corrected when the number of detected defects exceeds the number of defects that has been input in advance. On the other hand, when the number of detected defects exceeds the allowable number of defects and falls below the limit number of defects, it is determined that the defect is corrected.

  If the defect is to be corrected, it is next determined whether to correct both the short-circuit defect and the disconnection defect (S105). As a condition for determining whether to correct both the short-circuit defect and the disconnection defect, for example, when the ratio of the number of short-circuit defects and the number of disconnection defects is substantially equal among the detected defects, both the short-circuit defect and the disconnection defect are corrected. Yes (S106). On the other hand, when the number of short-circuit defects and the number of disconnection defects are extremely different, for example, about 8 to 2, both the short-circuit defect and the disconnection defect are not corrected. In this way, by dividing the case where both are corrected and the case where both are not corrected depending on the number of short-circuit defects and the number of disconnection defects, efficient correction can be performed without performing unnecessary correction.

  The condition for determining to correct both the short-circuit defect and the disconnection defect is that the number of short-circuit defects and the number of disconnection defects are approximately equal, but not limited to this, for example, the number of short-circuit defects and the number of disconnection defects Even when the ratio is about 6 to 4 or about 4 to 6, both the short-circuit defect and the disconnection defect may be corrected. That is, it is possible to arbitrarily set the conditions for correcting both the short-circuit defect and the disconnection defect so that the manufacturing process of the semiconductor device can be improved.

  When both the short-circuit defect and the disconnection defect are not corrected, it is subsequently determined whether only the short-circuit defect is corrected (S107). As a condition for determining whether to correct only the short-circuit defect, for example, it can be set as a condition whether the number of short-circuit defects is considerably larger than the number of disconnection defects. If the number of short-circuit defects is considerably larger than the number of open-circuit defects, only a large number of short-circuit defects are corrected (S108). On the other hand, when the number of disconnection defects is considerably larger than the number of short-circuit defects, only the large number of disconnection defects are corrected without correcting the short-circuit defects (S109).

  In the present embodiment, the case where the number of defects is used as a condition has been described. However, the present invention is not limited to this. For example, a continuity distribution of position coordinates where defects exist may be used as a condition. That is, when the position coordinates where the defect exists are continuous, it is considered that the defect is concentrated in a specific chip region in the semiconductor wafer. Therefore, when the position coordinates of the defect are continuous more than a predetermined value, the specific chip area where the defect is concentrated is determined to be defective, and the defect in the chip area is not corrected, but the position coordinates are not continuous. You may make it correct about a defect. Furthermore, a condition that combines the number of defects and the continuity of the position coordinates of the defects may be used.

  In the present embodiment, four determination results are obtained. However, the present invention is not limited to this. For example, two determination results indicating that a defect is corrected or a defect is not corrected are obtained. May be.

  Next, a correction method for correcting a short-circuit defect will be described with reference to the drawings.

  FIG. 10 is a plan view showing a state in which a wiring pattern composed of the wiring 2 and the wiring 3 is formed on a predetermined region of the semiconductor wafer via the interlayer insulating film 1, and FIG. It is sectional drawing in a cross section. In FIG. 11, the illustration of the structure below the interlayer insulating film 1 is omitted.

  In FIG. 10, a short-circuit defect 4 that short-circuits the wiring 2 and the wiring 3 is formed between the wiring 2 and the wiring 3. As shown in FIG. 11, the wiring 2, the wiring 3, and the short-circuit defect 4 are formed of a laminated film composed of a titanium / titanium nitride film 2a, an aluminum film 2b, and a titanium / titanium nitride film 2c.

  The short-circuit defect 4 is detected in the above-described appearance inspection step (S102), and the position coordinate is specified. Further, it is determined that the defect is a short-circuit defect in the step of determining the defect type (S103). A method for correcting the short-circuit defect 4 will be described below.

  First, the position coordinates are specified in the appearance inspection process, and the position coordinates of the short-circuit defect 4 determined as the short-circuit defect in the process of determining the defect type are directly input to the electron beam exposure apparatus. Subsequently, a photosensitive resist film 8 is applied on the semiconductor wafer. That is, a resist film 8 is applied on the interlayer insulating film 1, the wiring pattern composed of the wirings 2 and 3, and the short-circuit defect 4 shown in FIG. For application of the resist film 8, for example, a spin coating method is used.

  Next, the semiconductor wafer coated with the resist film 8 is carried into an electron beam exposure apparatus and exposed. The electron beam exposure apparatus is an apparatus that exposes the resist film 8 by scanning an electron beam, and can expose a predetermined region at a pinpoint. Therefore, by using the electron beam exposure apparatus in which the position coordinates of the short-circuit defect 4 are input, the resist film 8 formed on the short-circuit defect 4 is exposed pinpoint based on the input position coordinates. Can do.

  Here, there are usually short-circuit defects to be corrected in addition to the short-circuit defects 4 on the semiconductor wafer, and the position coordinates of these short-circuit defects are also input to the electron beam exposure apparatus. Therefore, the resist film 8 formed on the short-circuit defect other than the short-circuit defect 4 is also exposed pinpoint.

  Thereafter, by developing, a resist film 8 having an opening on the short-circuit defect 4 can be formed as shown in FIGS. That is, the resist film 8 having an opening on the short-circuit defect 4 can be formed by a photolithography technique using an electron beam exposure apparatus. 12 shows a plan view in which an opening for opening the short-circuit defect 4 is formed in the resist film 8, and FIG. 13 shows a cross-sectional view taken along the line AA in FIG.

  Here, it is desirable that the size of the opening formed on the short-circuit defect 4 is slightly larger than the size of the short-circuit defect 4 from the viewpoint of completely removing the short-circuit defect 4 as shown in FIGS. The dimension of the opening is determined in consideration of the alignment accuracy of the electron beam exposure apparatus and the etching dimension shift amount of etching performed when the short-circuit defect 4 in the opening is removed. The alignment accuracy of the electron beam exposure apparatus means that, for example, when an opening is formed in the resist film 8 on the short-circuit defect 4, the opening is not formed directly above the short-circuit defect 4, but is formed slightly shifted. “Position shift” is shown. The etching dimension shift amount means that, for example, when the inside of the opening is etched using the resist film 8 having the opening as a mask, not all the regions in the opening are etched, but only the region narrower than the inside of the opening is etched. It shows that. That is, the amount of etching residue formed in the peripheral region of the opening is shown.

  For example, when an etching residue is generated in a region that is a maximum of +5 nm (one side) from the boundary line of the opening (etching dimension shift amount) and the alignment accuracy of the electron beam exposure apparatus is a maximum of ± 45 nm, one side 45 + 5 = 50 nm The opening is made larger than the dimension of the short-circuit defect 4 by (100 nm on both sides).

  Subsequently, as shown in FIGS. 14 and 15, the short-circuit defect 4 made of metal is removed by dry etching using the resist film 8 opened on the short-circuit defect 4 as a mask. Next, as shown in FIGS. 16 and 17, the patterned resist film 8 is removed. In this way, the short-circuit defect 4 can be corrected.

  Next, a correction method for correcting a disconnection defect will be described with reference to the drawings.

  FIG. 18 is a plan view showing a state in which a wiring pattern composed of the wiring 11 and the wiring 12 is formed on a predetermined region of the semiconductor wafer via the interlayer insulating film 10, and FIG. It is sectional drawing in a cross section. In FIG. 19, the illustration of the structure below the interlayer insulating film 10 is omitted.

  In FIG. 18, a disconnection defect 13 that disconnects the interconnect 12 is formed in the interconnect 12. Further, as shown in FIG. 19, the wiring 12 is formed of a laminated film composed of a titanium / titanium nitride film 12a, an aluminum film 12b, and a titanium / titanium nitride film 12c.

  First, as shown in FIG. 21, a silicon oxide film 14 is formed on the interlayer insulating film 10, the wiring pattern composed of the wiring 11 and the wiring 12, and the disconnection defect 13. The silicon oxide film 14 can be formed using, for example, HDP (High Density Plasma) -CVD. This high density plasma CVD (HDP-CVD) method is suitable for filling a fine region such as the disconnection defect 13.

  Subsequently, as shown in FIGS. 20 and 21, a silicon oxide film 15 is formed on the silicon oxide film 14. The silicon oxide film 15 can be formed by, for example, a CVD method using oxygen gas and TEOS (Tetra Ethyl Ortho Silicate) as raw materials. In this way, a film (insulating film) made of the silicon oxide film 14 and the silicon oxide film 15 can be formed. In this embodiment, both the silicon oxide film 14 and the silicon oxide film 15 are formed. However, only the silicon oxide film 14 may be formed, or only the silicon oxide film 15 may be formed.

  Next, as shown in FIGS. 22 and 23, the surface of the insulating film made of the silicon oxide film 14 and the silicon oxide film 15 is planarized. As a method for planarizing the surface, for example, a CMP (Chemical Mechanical Polishing) method can be used. Note that the thickness of the insulating film including the silicon oxide film 14 and the silicon oxide film 15 is as thin as possible because the capacitance between the wiring 11 and the wiring 12 and the wiring formed in the upper layer of these wirings is not changed. It is desirable to form. From such a viewpoint, for example, the thickness of the insulating film including the silicon oxide film 14 and the silicon oxide film 15 can be set to about 100 nm.

  Next, the position coordinates are specified in the appearance inspection process, and the position coordinates of the disconnection defect 13 determined as the disconnection defect in the defect type determination process are directly input to the electron beam exposure apparatus. Subsequently, a resist film 16 is applied on the insulating film made of the silicon oxide film 14 and the silicon oxide film 15. The resist film 16 can be applied using, for example, a spin coating method. Then, by using an electron beam exposure apparatus in which the position coordinates of the disconnection defect 13 are input, the resist film 16 formed on the disconnection defect 13 is exposed at a pinpoint based on the input position coordinates. Similar to the correction of the short-circuit defect 4, the position coordinates of the disconnection defects other than the disconnection defect 13 on the semiconductor wafer are input to the electron beam exposure apparatus. For this reason, the resist film 16 formed on the disconnection defect other than the disconnection defect 13 is also pinpointed.

  Subsequently, by developing, as shown in FIGS. 24 and 25, the resist film 16 formed on the disconnection defect 13 is removed through the silicon oxide film 14 and the silicon oxide film 15 to form an opening. To do. At this time, the dimension of the opening formed in the resist film 16 is made larger than the dimension of the disconnection defect 13 in order to completely electrically connect the disconnection defect 13.

  Next, as shown in FIGS. 26 and 27, the silicon oxide film 14 and the silicon oxide film 15 formed in the opening are removed by dry etching using the resist film 16 in which the opening is formed as a mask. At this time, in order to completely electrically connect the disconnection defect 13, it is desirable to expose a part of the wiring 12 when the silicon oxide film 14 and the silicon oxide film 15 in the opening are removed. That is, it is desirable that the size of the opening formed by removing the silicon oxide film 14 and the silicon oxide film 15 is larger than the size of the disconnection defect 13.

  Subsequently, the resist film 16 is removed as shown in FIGS. Then, as shown in FIGS. 30 and 31, a metal film 17 is formed on the semiconductor wafer so as to fill the disconnection defect 13. The metal film 17 can be formed by, for example, a sputtering method, a plating method, or a CVD method. As an example of the metal film 17, it can form from an aluminum film, for example.

  Next, as shown in FIGS. 32 and 33, the metal film 17 formed on the silicon oxide film 14 is removed, and the metal film 17 is only in the disconnection defect 13 and the opening formed in the silicon oxide film 14. Leave. For removal of the metal film 17 formed on the silicon oxide film 14, for example, polishing by a CMP method can be used. In this way, the disconnection defect 13 can be corrected.

  Although the process of correcting the short-circuit defect and the process of correcting the disconnection defect have been described based on the determination result, there is also a process of leaving the defect without correcting it. After correcting the defect or leaving it without correcting the defect, an interlayer insulating film is formed on the wiring pattern, and a new wiring pattern is formed above the interlayer insulating film. Then, the above process is repeated for this new wiring pattern. In this way, the presence or absence of defects in the wiring pattern formed in multiple layers can be checked for each layer, and the defects can be corrected as necessary.

  Note that when the disconnection defect is corrected, the thickness is increased by the amount of the silicon oxide film remaining on the semiconductor wafer as compared with the case where the short-circuit defect is corrected or the case where the defect is left without correcting the defect. Therefore, the thickness of the interlayer insulating film is adjusted so as not to differ between the semiconductor wafer in which the disconnection defect is corrected and the semiconductor wafer in which the disconnection defect is not corrected.

  As described above, according to the method of manufacturing a semiconductor device in the present embodiment, the type of defect detected in the appearance inspection process can be automatically determined, compared to the case of manually determining the type of defect. Therefore, the efficiency of the semiconductor device manufacturing process can be improved, and the TAT can be shortened.

  In addition, according to the method for manufacturing a semiconductor device in the present embodiment, it is possible to make an efficient correction because a defect is not corrected by determining whether the defect should be corrected. Therefore, the cost of the semiconductor product can be reduced.

  Furthermore, in the present embodiment, defects are corrected as necessary, so that the product yield can be improved. In particular, it is possible to improve the product yield in the manufacturing process of a semiconductor device in which it is difficult to repair a defect by a redundant circuit such as a CMOS image sensor or a CCD image sensor.

  According to the semiconductor device manufacturing method of the present embodiment, since the position coordinates of the defect to be corrected whose type has been automatically determined are directly input to the electron beam exposure apparatus, the time for specifying the position coordinates of the defect to be corrected is determined. It can be shortened. That is, since the position coordinates of the defect to be corrected are not specified manually, the time for specifying the position coordinates of the defect to be corrected can be shortened. Further, the alignment accuracy in the electron beam exposure apparatus can be ensured for all defects to be corrected. In other words, the position coordinates of the defect to be corrected whose type has been automatically determined is input to the electron beam exposure apparatus without human intervention. Therefore, for example, when the position coordinates of the defect to be corrected are specified manually, it may be possible that there is a deviation in the specification of the position coordinates of the defect to be corrected. However, in this embodiment, correction should be performed with the type automatically determined. Since the position coordinates of the defect are directly input to the electron beam exposure apparatus without human intervention, such a situation does not occur, and alignment accuracy can be ensured for the defect to be corrected.

  According to the method for manufacturing a semiconductor device in the present embodiment, as a technique for correcting the short-circuit defect 4 and the disconnection defect 13, a photolithography technique using an electron beam exposure apparatus and an etching technique are used. Therefore, the manufacturing method of the semiconductor device in the present embodiment can be realized by an existing semiconductor manufacturing apparatus (electron beam exposure apparatus or etching apparatus) and a process normally used in the manufacturing process of the semiconductor device. For this reason, defect correction can be realized without investing in new facilities or developing facilities.

  Note that this embodiment can be widely applied to a method of manufacturing a semiconductor device in which wiring is formed on a semiconductor wafer, and in particular, a semiconductor that does not perform repair by a redundant circuit, such as a CMOS image sensor, a CCD image sensor, or a microprocessor. The present invention can be applied to a device manufacturing method.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  In the above embodiment, an example using an exposure apparatus using an electron beam has been described. However, the present invention is not limited to this, and an exposure apparatus using an excimer laser, for example, may be used.

  In the above-described embodiment, the wiring using an aluminum film as a material has been described as an example. However, the present invention is not limited to this. For example, the present invention can be applied to a wiring using a tungsten film as a material.

  The semiconductor device manufacturing method of the present invention is used in a manufacturing industry that manufactures, for example, a CMOS image sensor, a CCD image sensor, and the like.

It is a flowchart which shows the manufacturing process of the semiconductor device which is one embodiment of this invention. It is a top view which shows a mode that the wiring pattern was formed on the interlayer insulation film. It is sectional drawing cut | disconnected by the AA cross section of FIG. It is a top view which shows a normal wiring pattern. It is the top view which showed the wiring pattern with a short circuit defect. It is the top view which showed the wiring pattern with a disconnection defect. It is a figure which shows a mode that the layout pattern was subdivided. It is a figure which shows a mode that the wiring pattern with a short circuit defect was subdivided. It is a figure which shows a mode that the wiring pattern with a disconnection defect was subdivided. It is the top view which showed the wiring pattern in which the short circuit defect was formed. It is sectional drawing cut | disconnected by the AA cross section of FIG. FIG. 11 is a plan view illustrating a manufacturing step of the semiconductor device following that of FIG. 10; It is sectional drawing cut | disconnected by the AA cross section of FIG. FIG. 13 is a plan view illustrating a manufacturing step of the semiconductor device following that of FIG. 12; It is sectional drawing cut | disconnected by the AA cross section of FIG. FIG. 15 is a plan view illustrating a manufacturing step of the semiconductor device following that of FIG. 14; It is sectional drawing cut | disconnected by the AA cross section of FIG. It is the top view which showed the wiring pattern in which the disconnection defect was formed. It is sectional drawing cut | disconnected by the AA cross section of FIG. FIG. 19 is a plan view illustrating a manufacturing step of the semiconductor device following that of FIG. 18; It is sectional drawing cut | disconnected by the AA cross section of FIG. FIG. 21 is a plan view illustrating a manufacturing step of the semiconductor device following that of FIG. 20; It is sectional drawing cut | disconnected by the AA cross section of FIG. FIG. 23 is a plan view showing a manufacturing step of the semiconductor device following that of FIG. 22; It is sectional drawing cut | disconnected by the AA cross section of FIG. FIG. 25 is a plan view illustrating a manufacturing step of the semiconductor device following that of FIG. 24; It is sectional drawing cut | disconnected by the AA cross section of FIG. FIG. 27 is a plan view showing a manufacturing step of the semiconductor device following that of FIG. 26; It is sectional drawing cut | disconnected by the AA cross section of FIG. FIG. 29 is a plan view showing a manufacturing step of the semiconductor device following that of FIG. 28; It is sectional drawing cut | disconnected by the AA cross section of FIG. FIG. 31 is a plan view illustrating a manufacturing step of the semiconductor device following that of FIG. 30; It is sectional drawing cut | disconnected by the AA cross section of FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Interlayer insulating film 2 Wiring 2a Titanium / titanium nitride film 2b Aluminum film 2c Titanium / titanium nitride film 3 Wiring 4 Short-circuit defect 5 Disconnection defect 6a Area 6b Area 7a Area 7b Area 8 Resist film 10 Interlayer insulating film 11 Wiring 12 Wiring 12a Titanium / Titanium nitride film 12b aluminum film 12c titanium / titanium nitride film 13 disconnection defect 14 silicon oxide film 15 silicon oxide film 16 resist film 17 metal film

Claims (10)

(A) forming a wiring pattern;
(B) a step of correcting a short-circuit defect generated when forming the wiring pattern after the step (a),
The step (b)
(B1) forming a resist film having an opening on the short-circuit defect;
(B2) A method of manufacturing a semiconductor device, comprising: removing the short-circuit defects by etching using the resist film as a mask. (A) forming a wiring pattern;
(B) a step of correcting a disconnection defect generated when forming the wiring pattern after the step (a),
The step (b)
(B1) forming an insulating film on the region including the disconnection defect;
(B2) forming a resist film having an opening on the disconnection defect on the insulating film;
(B3) removing the insulating film formed in the disconnection defect by etching the insulating film using the resist film as a mask;
(B4) forming a conductor film in the disconnection defect and on the insulating film;
(B5) removing the conductor film formed on the insulating film. A method for manufacturing a semiconductor device, comprising: (A) forming a wiring pattern;
(B) detecting a defect present in the wiring pattern;
(C) automatically determining the type of the detected defect;
And (d) a step of correcting the defect whose type has been discriminated, and a method for manufacturing a semiconductor device. A method of manufacturing a semiconductor device according to claim 3,
In the step (c), it is determined whether the detected defect is a short-circuit defect that short-circuits the wirings or a disconnection defect that disconnects the wirings. A method of manufacturing a semiconductor device according to claim 3,
In the step (c), the designed layout pattern and the actually formed wiring pattern are compared to determine whether it is a short-circuit defect or a disconnection defect. Manufacturing method. A method of manufacturing a semiconductor device according to claim 3,
The step (b) specifies the position coordinates of the detected defect,
The step (c) subdivides the designed layout pattern and the actually formed wiring pattern into a plurality of regions, respectively, in the vicinity of the position coordinates of the defect specified in the step (b), A semiconductor characterized by determining whether it is a short-circuit defect or a disconnection defect by comparing the presence / absence of a pattern in a subdivision of a layout pattern with the presence / absence of a pattern in a subdivision of the wiring pattern Device manufacturing method. A method of manufacturing a semiconductor device according to claim 3,
A method of manufacturing a semiconductor device comprising a step of determining whether or not the detected defect is to be corrected between the step (c) and the step (d). A method of manufacturing a semiconductor device according to claim 3,
The step (b) specifies the position coordinates of the detected defect,
Between the step (c) and the step (d),
(E) comprising a step of determining whether to correct the detected defect;
In the step (e), it is determined whether or not to correct the defect based on the number of the detected defects or the continuity of the position coordinates where the defects exist. A method of manufacturing a semiconductor device according to claim 3,
In the step (d), a photolithography technique using an electron beam or an excimer laser is used. A method of manufacturing a semiconductor device according to claim 3,
The step (b) specifies the position coordinates of the detected defect,
The step (d)
(D1) inputting the determined position coordinates of the specific type of the defect into an exposure apparatus using an electron beam or an excimer laser;
(D2) forming a resist film on the wiring pattern;
(D3) performing a patterning on the resist film by opening the defect by the exposure apparatus that has input the position coordinates of the defect;
And (d4) a step of correcting the defect using the patterned resist film.

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