JP2005079432A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2005079432A
JP2005079432A JP2003309881A JP2003309881A JP2005079432A JP 2005079432 A JP2005079432 A JP 2005079432A JP 2003309881 A JP2003309881 A JP 2003309881A JP 2003309881 A JP2003309881 A JP 2003309881A JP 2005079432 A JP2005079432 A JP 2005079432A
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electrode
layer
wiring
dielectric constant
low dielectric
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Atsuhito Mizutani
篤人 水谷
Takeshi Hamaya
毅 濱谷
Masaji Funakoshi
正司 舩越
Kazuhiko Matsushita
和彦 松下
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To suppress cracks generated on an interlayer insulation film between wiring by an impact at the time of wire bonding. <P>SOLUTION: A semiconductor device is provided with an electrode 4 composed of a conductive layer, an external terminal 8 composed of the conductive layer formed on the electrode 4 and the wiring layer 3 of a different potential holding an insulation layer 5 therebetween on the lower part of the electrode 4, and a low dielectric constant film layer 12 is embedded in the electrode 4. Thus, stress applied to the lower part of the external terminal 8 is dispersed by the low dielectric constant film layer 12 formed in the electrode for the impact of wire bonding to the external terminal 8. Thus, in the case of forming the wiring of different potential below the external terminal 8 in a semiconductor assembling process, the cracks generated in the insulation film 5 formed between the electrode 4 of an upper layer and the wiring layer 3 of a lower layer by the stress at the time of wire bonding are suppressed. As a result, leakage between the electrode 4 of the upper layer and the wiring layer 3 of the lower layer is prevented from occurring. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

この発明は、ボンディングパッドを有する半導体装置に関するものである。   The present invention relates to a semiconductor device having a bonding pad.

近年コンピュータや通信機器を中心とした電子機器の小型化と高機能化に伴い、半導体装置の小型化、高密度化及び高速化への要求がますます強くなってきている。しかし半導体の高速化の大きな妨げになるのが、ＭＯＳトランジスタ自体の遅延及び配線遅延である。従来は微細加工技術によりゲート長を短くすることでＭＯＳトランジスタ自体の遅延を低減してきた。一方、微細加工技術進展によるＭＯＳトランジスタ自体の遅延が小さくなるに従い配線遅延の問題が顕著になってきた。そこで配線遅延を小さくするため従来のＡｌ配線に代わりＣｕ配線が採用されるとともに、配線間に挟まれる絶縁膜に誘電率３.０以下の材料（低誘電率膜）が採用されつつある。   In recent years, with the miniaturization and high functionality of electronic devices such as computers and communication devices, there is an increasing demand for miniaturization, high density and high speed of semiconductor devices. However, it is the delay and wiring delay of the MOS transistor itself that greatly hinders the speeding up of the semiconductor. Conventionally, the delay of the MOS transistor itself has been reduced by shortening the gate length by microfabrication technology. On the other hand, the problem of wiring delay has become more prominent as the delay of the MOS transistor itself due to the progress of microfabrication technology becomes smaller. Therefore, in order to reduce the wiring delay, Cu wiring is adopted instead of the conventional Al wiring, and a material having a dielectric constant of 3.0 or less (low dielectric constant film) is being adopted for the insulating film sandwiched between the wirings.

こうした半導体装置の製造において半導体チップの電極パッドと外部の接続リードを金属細線で接続する或いは電極パッドにバンプ形成するために、汎用性に優れるＡｕ線を用いたボールボンディングが広く一般に普及している。   In the manufacture of such a semiconductor device, ball bonding using Au wire, which is excellent in versatility, is widely used in order to connect an electrode pad of a semiconductor chip and an external connection lead with a fine metal wire or to form a bump on the electrode pad. .

以下、図４を参照しながら、従来の半導体製造装置ついて説明する。   Hereinafter, a conventional semiconductor manufacturing apparatus will be described with reference to FIG.

図４（ａ）は従来の半導体製造装置のボンディングパッドを示す断面図、（ｂ）そのＡ−Ａ'断面図である。図４において、１は第１の層間絶縁膜、２は第１の配線間絶縁膜、３は下層メタル、４は最上層メタル、５は第２の層間絶縁膜、６は第２の配線間絶縁膜、７は第１の保護膜、８は外部端子、９は第２の保護膜、１０はボンディングワイヤである。   4A is a cross-sectional view showing a bonding pad of a conventional semiconductor manufacturing apparatus, and FIG. 4B is a cross-sectional view taken along line AA ′. In FIG. 4, 1 is the first interlayer insulating film, 2 is the first inter-wiring insulating film, 3 is the lower metal, 4 is the uppermost metal, 5 is the second inter-layer insulating film, and 6 is the second inter-wiring film. An insulating film, 7 is a first protective film, 8 is an external terminal, 9 is a second protective film, and 10 is a bonding wire.

図４に示すように、従来は第１の層間絶縁膜１の上に第1の配線間絶縁膜２及び下層メタル３を形成する。第1の配線間絶縁膜２及び下層メタル３の上に下層メタル３と最上層メタル４の間を絶縁する目的で第２の層間絶縁膜５を形成し、第２の層間絶縁膜５の上に第２の配線間絶縁膜６及び最上層メタル４を形成する。第２の配線間絶縁膜６及び最上層メタル４の上に第1の保護膜７を形成した後、外部端子８との接続部を開口する。開口部の上に外部端子８をＡｌ系材料で形成する。外部端子８の上に第２の保護膜９を形成した後に開口する。   As shown in FIG. 4, a first inter-wiring insulating film 2 and a lower layer metal 3 are conventionally formed on a first interlayer insulating film 1. A second interlayer insulating film 5 is formed on the first inter-wiring insulating film 2 and the lower layer metal 3 for the purpose of insulating between the lower layer metal 3 and the uppermost layer metal 4. Then, the second inter-wiring insulating film 6 and the uppermost metal 4 are formed. After the first protective film 7 is formed on the second inter-wiring insulating film 6 and the uppermost metal layer 4, a connection portion with the external terminal 8 is opened. The external terminal 8 is formed of an Al-based material on the opening. An opening is formed after the second protective film 9 is formed on the external terminal 8.

上記ウェーハプロセス後、ダイシング、ダイボンドを行い、外部端子８にボンディングワイヤ１０を押圧し、超音波をかけながらボンディングワイヤ１０と外部端子８を接合させる。
特開平１０−１９９９２５号公報 After the wafer process, dicing and die bonding are performed, the bonding wire 10 is pressed against the external terminal 8, and the bonding wire 10 and the external terminal 8 are joined while applying ultrasonic waves.
JP-A-10-199925

しかしながら、図４に示すような上記従来のボンディングパッド構造ではボンディングワイヤ１０を用いてボールボンディングする際に加えられる衝撃荷重、超音波及び圧力により第２の層間絶縁膜５がダメージを受けてクラックが生じ、最上層メタル４と下層メタル３が異電位の場合、配線間でのリークが発生するという課題が存在する。特に、超音波の振幅と垂直方向かつボンディングワイヤ１０の接合部エッジ下部に応力が集中してクラックが発生しやすい。また第２の層間絶縁膜５に機械的強度の低い低誘電率膜を採用した場合、その傾向が顕著になる。   However, in the conventional bonding pad structure as shown in FIG. 4, the second interlayer insulating film 5 is damaged by the impact load, ultrasonic wave and pressure applied when ball bonding is performed using the bonding wire 10, and cracks are generated. As a result, when the uppermost metal 4 and the lower metal 3 have different potentials, there is a problem that leakage occurs between wirings. In particular, cracks are likely to occur due to stress concentration in the direction perpendicular to the amplitude of the ultrasonic waves and below the joint edge of the bonding wire 10. In addition, when a low dielectric constant film having low mechanical strength is adopted for the second interlayer insulating film 5, the tendency becomes remarkable.

したがって、この発明の目的は、以上の課題を解決するために、ボンディングパッドを有する半導体製造装置におけるボンディングワイヤを用いたボールボンディング時に発生する配線間の層間絶縁膜に生じるクラックを抑制することができるボンディングパッド構造を有する半導体装置を提供することである。   Accordingly, in order to solve the above-described problems, an object of the present invention can suppress cracks generated in an interlayer insulating film between wirings generated during ball bonding using a bonding wire in a semiconductor manufacturing apparatus having a bonding pad. A semiconductor device having a bonding pad structure is provided.

上記目的を達成するためにこの発明の請求項１記載の半導体装置は、導電層からなる電極と、前記電極上に形成された導電層からなる外部端子と、前記電極の下部に絶縁層を挟んで異電位の配線層とを備えた半導体装置であって、前記電極に低誘電率膜層が埋設されている。   In order to achieve the above object, a semiconductor device according to claim 1 of the present invention includes an electrode made of a conductive layer, an external terminal made of a conductive layer formed on the electrode, and an insulating layer sandwiched below the electrode. In the semiconductor device having a wiring layer having a different potential, a low dielectric constant film layer is embedded in the electrode.

請求項２記載の半導体装置は、請求項１記載の半導体装置において、前記電極の導電材料は銅からなり、前記外部端子の導電材料はアルミニウムからなる。   The semiconductor device according to claim 2 is the semiconductor device according to claim 1, wherein the conductive material of the electrode is made of copper, and the conductive material of the external terminal is made of aluminum.

請求項３記載の半導体装置は、請求項１記載の半導体装置において、前記電極に埋設された低誘電率膜層を円柱状とし、前記低誘電率膜層中に前記電極と同一材料からなる円柱状の導電層を設け、前記電極と前記円柱状の導電層とを、前記電極と同一材料で前記円柱状の導電層を中心として相互に等角度をなすように形成された配線で４方向を繋いでいる。   The semiconductor device according to claim 3 is the semiconductor device according to claim 1, wherein the low dielectric constant film layer embedded in the electrode is formed in a columnar shape, and a circle made of the same material as the electrode is formed in the low dielectric constant film layer. A columnar conductive layer is provided, and the electrode and the columnar conductive layer are made of the same material as the electrode with wiring formed so as to be equiangular with each other around the columnar conductive layer. Are connected.

この発明の請求項１記載の半導体装置によれば、導電層からなる電極と、電極上に形成された導電層からなる外部端子と、電極の下部に絶縁層を挟んで異電位の配線層とを備え、電極に低誘電率膜層が埋設されているので、外部端子に対するワイヤボンドの衝撃に対して電極中に設けた低誘電率膜層によって外部端子下部へかかる応力を分散する。このため、半導体組立プロセスにおいて外部端子下に異電位の配線を有する場合、ワイヤボンド時の応力により発生する上層の電極と下層の配線層の層間にある絶縁膜中に発生するクラックを抑制することが可能である。その結果、上層の電極と下層の配線層間でのリーク発生防止を実現できる。   According to the semiconductor device of the first aspect of the present invention, the electrode composed of the conductive layer, the external terminal composed of the conductive layer formed on the electrode, the wiring layer having a different potential with the insulating layer sandwiched between the electrodes, Since the low dielectric constant film layer is embedded in the electrode, the stress applied to the lower portion of the external terminal is dispersed by the low dielectric constant film layer provided in the electrode against the impact of the wire bond to the external terminal. For this reason, in the semiconductor assembly process, when wiring with a different potential is provided under the external terminal, cracks generated in the insulating film between the upper electrode layer and the lower wiring layer caused by stress during wire bonding are suppressed. Is possible. As a result, it is possible to prevent leakage between the upper electrode and the lower wiring layer.

請求項２では、電極の導電材料は銅からなり、外部端子の導電材料はアルミニウムからなるので、配線遅延を小さくするため銅配線が採用された半導体装置において汎用性に優れるボールボンディングに適したボンディングパッド構造を実現できる。   According to the second aspect of the present invention, since the conductive material of the electrode is made of copper and the conductive material of the external terminal is made of aluminum, bonding suitable for ball bonding having excellent versatility in a semiconductor device employing copper wiring to reduce wiring delay. A pad structure can be realized.

請求項３では、電極に埋設された低誘電率膜層を円柱状とし、低誘電率膜層中に電極と同一材料からなる円柱状の導電層を設け、電極と円柱状の導電層とを、電極と同一材料で円柱状の導電層を中心として相互に等角度をなすように形成された配線で４方向を繋いでいるので、超音波の振幅方向に対して垂直及びクラックの発生しやすいボンディングワイヤの接合部エッジの下部の上層の電極中に設けた低誘電率層が割れることで応力を分散させ、上層の電極と下層の配線間の絶縁膜に至るクラックの発生を抑制することができる。また、低誘電率層は４方向にスリット状の配線が存在するので、半導体装置の方向が９０度回転しても問題なく対応することが可能である。   According to a third aspect of the present invention, the low dielectric constant film layer embedded in the electrode is formed into a columnar shape, a columnar conductive layer made of the same material as the electrode is provided in the low dielectric constant film layer, and the electrode and the columnar conductive layer are Since the four directions are connected by wirings formed at the same angle around the cylindrical conductive layer made of the same material as the electrode, it is easy to generate vertical and cracks with respect to the ultrasonic amplitude direction. The low dielectric constant layer provided in the upper layer electrode under the bonding edge of the bonding wire breaks down to disperse the stress and suppress the generation of cracks reaching the insulating film between the upper layer electrode and the lower layer wiring. it can. In addition, since the low dielectric constant layer has slit-like wirings in four directions, even if the direction of the semiconductor device is rotated by 90 degrees, it is possible to cope with it without any problem.

この発明の第１の実施の形態を図１および図２に基づいて説明する。図１（ａ）は本発明の第１の実施形態の半導体装置のボンディングパッドを示す断面図、（ｂ）はそのＡ−Ａ'断面図である。   A first embodiment of the present invention will be described with reference to FIGS. FIG. 1A is a sectional view showing a bonding pad of the semiconductor device according to the first embodiment of the present invention, and FIG. 1B is a sectional view taken along the line AA ′.

図１において、１は第1の層間絶縁膜、２は第1の配線間絶縁膜、３は下層メタル（配線層）、４は最上層メタル（電極）、５は第２の層間絶縁膜、６は第２の配線間絶縁膜、７は第1の保護膜、８は外部端子、９は第２の保護膜、１０はボンディングワイヤ、１１はクラック、１２は低誘電率膜パターンである。   In FIG. 1, 1 is a first interlayer insulating film, 2 is a first inter-wiring insulating film, 3 is a lower metal (wiring layer), 4 is an uppermost metal (electrode), 5 is a second interlayer insulating film, 6 is a second inter-wiring insulating film, 7 is a first protective film, 8 is an external terminal, 9 is a second protective film, 10 is a bonding wire, 11 is a crack, and 12 is a low dielectric constant film pattern.

図１に示すように、銅等の導電層からなる電極４と、電極４上に形成されたアルミニウム等の導電層からなる外部端子８と、電極４の下部に絶縁層５を挟んで異電位の配線層３とを備え、電極４に低誘電率膜層１２が埋設されている。この場合、第２の層間絶縁膜５を低誘電率膜とし、この上の最上層メタル４中に第２の配線間絶縁膜６と同種材料の低誘電率膜パターン１２を円柱状に形成する。低誘電率膜パターン１２の円の直径はボンディングワイヤ１０のボール圧着径と同程度のサイズで設ける。効果として、外部端子８を通じて伝わるワイヤボンディング時の衝撃を最上層メタル４中に設けた低誘電率パターン１２が割れることで応力を分散させ、第２の層間絶縁膜５に至るクラックの発生を抑制することができ、その結果として最上層メタル４と下層メタル３の間のリークを防止することが可能になる。   As shown in FIG. 1, an electrode 4 made of a conductive layer such as copper, an external terminal 8 made of a conductive layer such as aluminum formed on the electrode 4, and a different potential with an insulating layer 5 sandwiched between the electrodes 4. And a low dielectric constant film layer 12 is embedded in the electrode 4. In this case, the second interlayer insulating film 5 is a low dielectric constant film, and a low dielectric constant film pattern 12 of the same material as that of the second inter-wiring insulating film 6 is formed in a cylindrical shape in the uppermost metal layer 4. . The diameter of the circle of the low dielectric constant film pattern 12 is set to the same size as the ball crimping diameter of the bonding wire 10. As an effect, the impact during wire bonding transmitted through the external terminal 8 is broken by the low dielectric constant pattern 12 provided in the uppermost metal layer 4 to disperse the stress, and the generation of cracks reaching the second interlayer insulating film 5 is suppressed. As a result, leakage between the uppermost metal 4 and the lower metal 3 can be prevented.

なお、前記の第２の層間絶縁膜５は低誘電率膜に限らず、低誘電率膜の機械的強度以上を有する絶縁膜であればよい。低誘電率膜パターン１２はワイヤボンド時の応力を分散できれば円柱以外の形状でもよい。また、最上層メタル４の導電材料は銅、外部端子８の導電材料はアルミニウムとしたがこれ以外でもよい。   The second interlayer insulating film 5 is not limited to a low dielectric constant film, but may be an insulating film having a mechanical strength higher than that of the low dielectric constant film. The low dielectric constant film pattern 12 may have a shape other than a cylinder as long as the stress during wire bonding can be dispersed. In addition, although the conductive material of the uppermost metal 4 is copper and the conductive material of the external terminal 8 is aluminum, other materials may be used.

図２は本発明の実施形態における半導体装置の製造方法を示す工程図である。
図２（ａ）に示すように、第1の層間絶縁膜１の上に第1の配線間絶縁膜２を化学気相堆積法（以下、ＣＶＤと略す）により成膜する。図２（ｂ）に示すように、第1の配線間絶縁膜２にドライエッチ法により第１の配線溝１４を形成する。図２（ｃ）に示すように、第1の配線溝１４に電解めっきにより第1のメタル１５を埋め込む。図２（ｄ）に示すように、図２（ｃ）で埋め込んだ第1のメタル１５を機械的化学研磨（以下、ＣＭＰと略す）により第1の配線間絶縁膜２が露出するまで平坦化を進める。これにより第１のメタル１５から下層メタル３を形成する。図２（ｅ）に示すように、ＣＶＤにより第２の層間絶縁膜５を成膜する。図２（ｆ）に示すように、第２の層間絶縁膜５の上に第２の配線間絶縁膜６をＣＶＤにより成膜する。図２（ｇ）に示すように、低誘電率膜パターン１２を残して、第２の配線間絶縁膜６に第２の配線溝１６をドライエッチ法により形成する。図２（ｈ）に示すように、第２の配線溝１６へ電解めっきにより第２のメタル１７を埋め込む。図２（ｉ）に示すように、図２（ｈ）で埋め込んだ第２のメタル１７をＣＭＰにより第２の配線間絶縁膜６が露出するまで平坦化を進める。これにより第２のメタル１７から最上層メタル４を形成する。 FIG. 2 is a process diagram showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.
As shown in FIG. 2A, a first inter-wiring insulating film 2 is formed on the first interlayer insulating film 1 by chemical vapor deposition (hereinafter abbreviated as CVD). As shown in FIG. 2B, a first wiring groove 14 is formed in the first inter-wiring insulating film 2 by a dry etching method. As shown in FIG. 2C, a first metal 15 is embedded in the first wiring groove 14 by electrolytic plating. As shown in FIG. 2D, the first metal 15 buried in FIG. 2C is planarized by mechanical chemical polishing (hereinafter abbreviated as CMP) until the first inter-wiring insulating film 2 is exposed. To proceed. As a result, the lower metal 3 is formed from the first metal 15. As shown in FIG. 2E, a second interlayer insulating film 5 is formed by CVD. As shown in FIG. 2F, a second inter-wiring insulating film 6 is formed on the second interlayer insulating film 5 by CVD. As shown in FIG. 2G, the second wiring trench 16 is formed in the second inter-wiring insulating film 6 by the dry etching method, leaving the low dielectric constant film pattern 12. As shown in FIG. 2H, a second metal 17 is embedded in the second wiring groove 16 by electrolytic plating. As shown in FIG. 2I, the second metal 17 buried in FIG. 2H is planarized by CMP until the second inter-wiring insulating film 6 is exposed. As a result, the uppermost metal 4 is formed from the second metal 17.

次に図２（ｊ）に示すように、ウェーハ全面にＣＶＤを用いて第1の保護膜７を成膜する。保護膜材料はＳｉＮが採用される。図２（ｋ）に示すように、図２（ｊ）で成膜した第1の保護膜７をドライエッチ法により最上層メタル４の上のみ開口する。図２（ｌ）に示すように、ウェーハ全面にＣＶＤを用いて外部端子８の材料となるメタルを成膜する。外部端子８の材料にはＡｌ系が用いられる。図２（ｍ）に示すように、ドライエッチ法により図２（ｌ）で成膜した外部端子８のメタルを外部端子８の形状に形成する。図２（ｎ）に示すように、ウェーハ全面にＣＶＤを用いて第２の保護膜９を成膜する。保護膜材料はＳｉＮが採用される。図２（ｏ）に示すように、外部端子８上の第２の保護膜９をドライエッチ法により開口する。以上の工程を経て本発明の実施形態の半導体装置を製造する。   Next, as shown in FIG. 2J, a first protective film 7 is formed on the entire wafer surface using CVD. SiN is adopted as the protective film material. As shown in FIG. 2 (k), the first protective film 7 formed in FIG. 2 (j) is opened only on the uppermost metal 4 by dry etching. As shown in FIG. 2L, a metal as a material for the external terminals 8 is formed on the entire wafer surface by CVD. Al material is used for the material of the external terminal 8. As shown in FIG. 2M, the metal of the external terminal 8 formed in FIG. 2L is formed in the shape of the external terminal 8 by dry etching. As shown in FIG. 2 (n), a second protective film 9 is formed on the entire wafer surface using CVD. SiN is adopted as the protective film material. As shown in FIG. 2 (o), the second protective film 9 on the external terminal 8 is opened by a dry etching method. The semiconductor device of the embodiment of the present invention is manufactured through the above steps.

以上のように本実施形態によれば、ワイヤボンドの衝撃に対して最上層メタル中に設けた低誘電率膜パターンによって外部端子下部へ掛かる応力を分散するため、ワイヤボンド時に発生する最上層メタルから層間絶縁膜を介して下層メタルに至るクラックの発生を抑制することが可能である。また、半導体装置の製造期間については、低誘電率膜パターンを配線間絶縁膜と同一材料で形成するため、パッド構造特有のプロセスを追加する必要がなく従来と同様の拡散期間が維持できる。   As described above, according to the present embodiment, the stress applied to the lower part of the external terminal is dispersed by the low dielectric constant film pattern provided in the uppermost layer metal in response to the impact of the wirebond. It is possible to suppress the generation of cracks from the metal through the interlayer insulating film to the lower layer metal. In addition, regarding the manufacturing period of the semiconductor device, since the low dielectric constant film pattern is formed of the same material as the inter-wiring insulating film, it is not necessary to add a process peculiar to the pad structure, and a diffusion period similar to the conventional one can be maintained.

この発明の第２の実施の形態を図３に基づいて説明する。図３（ａ）は本発明の第２の実施形態の半導体装置のボンディングパッドを示す断面図、（ｂ）はそのＡ−Ａ'断面図である。   A second embodiment of the present invention will be described with reference to FIG. FIG. 3A is a cross-sectional view showing a bonding pad of a semiconductor device according to a second embodiment of the present invention, and FIG. 3B is an AA ′ cross-sectional view thereof.

図３に示すように、銅等の導電層からなる電極４と、電極４上に形成されたアルミニウム等の導電層からなる外部端子８と、電極４の下部に絶縁層５を挟んで異電位の配線層３とを備え、電極４に円柱状の低誘電率膜層１３が埋設されている。また、低誘電率膜層１３中に電極４と同一材料からなる円柱状の導電層４ａを設け、電極４と円柱状の導電層４ａとを、電極４と同一材料で円柱状の導電層４ａを中心として相互に等角度をなすように形成された配線４ｂで４方向を繋いでいる。   As shown in FIG. 3, an electrode 4 made of a conductive layer such as copper, an external terminal 8 made of a conductive layer such as aluminum formed on the electrode 4, and a different potential with an insulating layer 5 sandwiched between the electrodes 4 And a cylindrical low dielectric constant film layer 13 is embedded in the electrode 4. In addition, a cylindrical conductive layer 4 a made of the same material as the electrode 4 is provided in the low dielectric constant film layer 13, and the electrode 4 and the cylindrical conductive layer 4 a are made of the same material as the electrode 4 and the cylindrical conductive layer 4 a. The four directions are connected by a wiring 4b formed so as to be equiangular with each other.

この場合、図３において、低誘電率膜パターン１３は図１の低誘電率膜パターン１２の中に円柱状のメタル４ａを設け、中心線に対して４５°のメタル配線４ｂで四方繋いだ形態を有するものである。低誘電率膜パターン１３の円の外径はボンディングワイヤ１０のボール圧着径と同程度、内径は外径の４０〜６０％のサイズで設ける。効果として、超音波の振幅方向に対して垂直及びクラックの発生しやすいボンディングワイヤ１０の接合部エッジの下部の最上層メタル４中に設けた低誘電率パターン１３が割れることで応力を分散させ、第２の層間絶縁膜５に至るクラックの発生を抑制することができ、その結果として最上層メタル４と下層メタル３の間のリークを防止することが可能になる。また低誘電率膜パターン１３は４方向にスリット状の低誘電率膜が存在するため、チップの方向が９０°回転しても問題なく対応することが可能である。   In this case, in FIG. 3, the low dielectric constant film pattern 13 is a form in which a cylindrical metal 4a is provided in the low dielectric constant film pattern 12 of FIG. It is what has. The outer diameter of the circle of the low dielectric constant film pattern 13 is approximately the same as the ball crimping diameter of the bonding wire 10, and the inner diameter is 40 to 60% of the outer diameter. As an effect, the stress is dispersed by cracking the low dielectric constant pattern 13 provided in the uppermost layer metal 4 at the lower part of the bonding edge of the bonding wire 10 that is perpendicular to the ultrasonic amplitude direction and easily generates cracks, Generation of cracks reaching the second interlayer insulating film 5 can be suppressed, and as a result, leakage between the uppermost layer metal 4 and the lower layer metal 3 can be prevented. In addition, since the low dielectric constant film pattern 13 has slit-like low dielectric constant films in four directions, it is possible to cope with the problem even if the direction of the chip is rotated by 90 °.

なお、本実施形態の製造方法は、円柱状のメタル４ａ、メタル配線４ｂを設ける点を除いては第１の実施形態の図２と同様である。その他の構成効果は、第１の実施の形態と同様である。   Note that the manufacturing method of the present embodiment is the same as that of FIG. 2 of the first embodiment except that the columnar metal 4a and the metal wiring 4b are provided. Other structural effects are the same as those of the first embodiment.

本発明にかかる半導体装置は、ワイヤボンド時の応力により発生する上層の電極と下層の配線層の層間にある絶縁膜中に発生するクラックを抑制することが可能となり、上層の電極と下層の配線層間でのリーク発生防止を実現できるという効果を有し、小型化、高密度化及び高速化が要求されるコンピュータや通信機器を中心とした電子機器として有用である。   The semiconductor device according to the present invention can suppress cracks generated in the insulating film between the upper electrode layer and the lower wiring layer, which are generated by stress during wire bonding, and the upper electrode layer and the lower wiring layer can be suppressed. It has the effect of preventing leakage between layers, and is useful as an electronic device centering on computers and communication devices that require miniaturization, high density, and high speed.

（ａ）は本発明の第１の実施形態の半導体装置のボンディングパッドを示す断面図、（ｂ）はそのＡ−Ａ'断面図である。(A) is sectional drawing which shows the bonding pad of the semiconductor device of the 1st Embodiment of this invention, (b) is the AA 'sectional drawing. 本発明の実施形態における半導体装置の製造方法を示す工程図である。It is process drawing which shows the manufacturing method of the semiconductor device in embodiment of this invention. （ａ）は本発明の第２の実施形態の半導体装置のボンディングパッドを示す断面図、（ｂ）はそのＡ−Ａ'断面図である。(A) is sectional drawing which shows the bonding pad of the semiconductor device of the 2nd Embodiment of this invention, (b) is the AA 'sectional drawing. （ａ）は従来の半導体製造装置のボンディングパッドを示す断面図、（ｂ）そのＡ−Ａ'断面図である。(A) is sectional drawing which shows the bonding pad of the conventional semiconductor manufacturing apparatus, (b) is the AA 'sectional drawing.

符号の説明Explanation of symbols

１ 第1の層間絶縁膜
２ 第1の配線間絶縁膜
３ 下層メタル
４ 最上層メタル
５ 第２の層間絶縁膜
６ 第２の配線間絶縁膜
７ 第1の保護膜
８ 外部端子
９ 第２の保護膜
１０ ボンディングワイヤ
１１ クラック
１２ 低誘電率膜パターン
１３ 低誘電率膜パターン
１４ 第1の配線溝
１５ 第1のメタル
１６ 第２の配線溝
１７ 第２のメタル DESCRIPTION OF SYMBOLS 1 1st interlayer insulation film 2 1st interlayer insulation film 3 Lower layer metal 4 Uppermost layer metal 5 2nd interlayer insulation film 6 2nd interlayer insulation film 7 1st protective film 8 External terminal 9 2nd Protective film 10 Bonding wire 11 Crack 12 Low dielectric constant film pattern 13 Low dielectric constant film pattern 14 First wiring groove 15 First metal 16 Second wiring groove 17 Second metal

Claims (3)

導電層からなる電極と、前記電極上に形成された導電層からなる外部端子と、前記電極の下部に絶縁層を挟んで異電位の配線層とを備えた半導体装置であって、前記電極に低誘電率膜層が埋設されていることを特徴とする半導体装置。   A semiconductor device comprising: an electrode made of a conductive layer; an external terminal made of a conductive layer formed on the electrode; and a wiring layer having a different potential with an insulating layer sandwiched below the electrode. A semiconductor device having a low dielectric constant film layer embedded therein. 前記電極の導電材料は銅からなり、前記外部端子の導電材料はアルミニウムからなる請求項１記載の半導体装置。   The semiconductor device according to claim 1, wherein the conductive material of the electrode is made of copper, and the conductive material of the external terminal is made of aluminum. 前記電極に埋設された低誘電率膜層を円柱状とし、前記低誘電率膜層中に前記電極と同一材料からなる円柱状の導電層を設け、前記電極と前記円柱状の導電層とを、前記電極と同一材料で前記円柱状の導電層を中心として相互に等角度をなすように形成された配線で４方向を繋いでいる請求項１記載の半導体装置。   The low dielectric constant film layer embedded in the electrode has a cylindrical shape, a cylindrical conductive layer made of the same material as the electrode is provided in the low dielectric constant film layer, and the electrode and the cylindrical conductive layer are provided. 2. The semiconductor device according to claim 1, wherein the four directions are connected by wirings that are formed of the same material as the electrode and are formed at equal angles with respect to the cylindrical conductive layer.
JP2003309881A 2003-09-02 2003-09-02 Semiconductor device Pending JP2005079432A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006351588A (en) * 2005-06-13 2006-12-28 Nec Electronics Corp Semiconductor device and its manufacturing method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006351588A (en) * 2005-06-13 2006-12-28 Nec Electronics Corp Semiconductor device and its manufacturing method
JP4717523B2 (en) * 2005-06-13 2011-07-06 ルネサスエレクトロニクス株式会社 Semiconductor device and manufacturing method thereof

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