JP2005079431A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP2005079431A
JP2005079431A JP2003309880A JP2003309880A JP2005079431A JP 2005079431 A JP2005079431 A JP 2005079431A JP 2003309880 A JP2003309880 A JP 2003309880A JP 2003309880 A JP2003309880 A JP 2003309880A JP 2005079431 A JP2005079431 A JP 2005079431A
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Prior art keywords
electrode
semiconductor chip
wiring
opening
insulating film
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Japanese (ja)
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Kazuhiko Matsumura
和彦 松村
Takayuki Yoshida
隆幸 吉田
Katsuyoshi Matsumoto
克良 松本
Noriyuki Kaino
憲幸 戒能
Takeshi Kawabata
毅 川端
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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Priority to JP2003309880A priority Critical patent/JP2005079431A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To prevent the disconnection of the top layer wiring of a semiconductor chip under an electrode for external connection by the film stress of the metal film of the electrode for the external connection. <P>SOLUTION: A semiconductor device is provided with a first organic insulation film 6, a wiring pattern 7 and a second organic insulation film 14, and is provided with the wiring or electrode 13 of a size equal to or larger than the second opening, where the electrode 5 for the external connection is formed, of the first organic insulation film 6 on the position of the top layer of the semiconductor chip 1 facing the electrode 5 for the external connection of the wiring pattern 7. Thus, damages given to the wiring of the top layer of the semiconductor chip 1 by the generation of cracks on a protective film 4 by the film stress of the metal film forming the electrode 5 for the external connection are reduced. Thus, the process cost of the semiconductor chip 1 is reduced. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

この発明は、配線基板への実装効率を高め、高密度実装を可能にし、信頼性の高い基板実装を実現できるチップ状の半導体装置に関するものであり、特に半導体チップ上で外部端子用の電極パッドが再配線され、外部端子が２次元エリア配置された半導体装置に関するものである。   The present invention relates to a chip-like semiconductor device capable of improving mounting efficiency on a wiring board, enabling high-density mounting, and realizing highly reliable board mounting, and more particularly, electrode pads for external terminals on a semiconductor chip. Relates to a semiconductor device in which the wiring is rewired and the external terminals are arranged in a two-dimensional area.

近年、携帯機器の軽量小型化、高密度化にともない、リード端子を外部端子として有した半導体パッケージの高密度実装化が進む中、より高密度実装を図るため、チップ状の半導体装置を電子機器の配線基板等に実装する技術が開発されている。   In recent years, with the reduction in weight and size and the increase in density of portable devices, semiconductor packages having lead terminals as external terminals are being mounted with higher density. A technology for mounting on a wiring board or the like has been developed.

以下、従来の配線基板への基板実装における半導体装置と、その半導体装置の実装方法について図面を参照しながら説明する。   Hereinafter, a semiconductor device in a conventional substrate mounting on a wiring board and a method for mounting the semiconductor device will be described with reference to the drawings.

図５は従来の半導体装置を示す断面図である。   FIG. 5 is a cross-sectional view showing a conventional semiconductor device.

図５に示す従来の半導体装置は、ベアチップ実装に用いられるチップ状の半導体装置であり、その上面内に半導体集積回路が形成された半導体チップ１上に半導体チップの電極２が形成され、かつ電極２が形成された同一配線層に半導体チップ１の半導体集積回路と電気的に接続された内部配線３が形成されている。また、この半導体チップ１の表面は電極２の部分を開口した絶縁性の保護膜４で覆われている。そして、この半導体チップ２の保護膜４表面には半導体チップ１の電極２と外部接続用電極５の部分を開口した感光性の有機樹脂である第１の有機絶縁膜６が形成されている。この第１の有機絶縁膜６上には半導体チップ１の電極２と外部接続用電極５とを電気的に接続する配線パターン７が形成され、外部接続用電極５上にははんだバンプ８とＵＢＭ９(アンダー・バリア・メタル)が形成されている。さらに、外部接続用電極５の周辺部と第１の有機絶縁膜６と配線パターン７上には第２の有機絶縁膜１４が形成されている。   The conventional semiconductor device shown in FIG. 5 is a chip-like semiconductor device used for bare chip mounting. A semiconductor chip electrode 2 is formed on a semiconductor chip 1 having a semiconductor integrated circuit formed on the upper surface thereof. The internal wiring 3 electrically connected to the semiconductor integrated circuit of the semiconductor chip 1 is formed in the same wiring layer in which 2 is formed. The surface of the semiconductor chip 1 is covered with an insulating protective film 4 having an opening in the electrode 2 portion. On the surface of the protective film 4 of the semiconductor chip 2, a first organic insulating film 6, which is a photosensitive organic resin having openings in the electrodes 2 and the external connection electrodes 5 of the semiconductor chip 1, is formed. A wiring pattern 7 for electrically connecting the electrode 2 of the semiconductor chip 1 and the external connection electrode 5 is formed on the first organic insulating film 6. The solder bump 8 and the UBM 9 are formed on the external connection electrode 5. (Under barrier metal) is formed. Further, a second organic insulating film 14 is formed on the periphery of the external connection electrode 5, the first organic insulating film 6 and the wiring pattern 7.

次に従来の半導体装置の実装方法について図６を参照しながら説明する。   Next, a conventional method for mounting a semiconductor device will be described with reference to FIG.

図５に示したような半導体装置をプリント配線基板上に実装する場合、まず図６（ａ）に示すように、電子機器に組み込むプリント配線基板１０の接続用配線電極１１と半導体チップ１に形成したはんだバンプ８とを位置合わせする。   When a semiconductor device as shown in FIG. 5 is mounted on a printed wiring board, first, as shown in FIG. 6A, it is formed on the connecting wiring electrode 11 and the semiconductor chip 1 of the printed wiring board 10 incorporated in the electronic device. The solder bumps 8 are aligned.

そして図６（ｂ）に示すように、プリント配線基板１０の接続用配線電極１１と半導体チップ１のはんだバンプ８とを接続する。この際、はんだボール８を溶融させた状態でプリント配線基板１０の接続用配線電極１１とを接合する。   Then, as shown in FIG. 6B, the connection wiring electrodes 11 of the printed wiring board 10 and the solder bumps 8 of the semiconductor chip 1 are connected. At this time, the connection wiring electrode 11 of the printed wiring board 10 is joined in a state where the solder ball 8 is melted.

そして図６（ｃ）に示すように、プリント配線基板１０に半導体チップ１をはんだボール８が接続された状態で、半導体チップ１とプリント配線基板１０との間隙に絶縁性樹脂等のアンダーフィル材１２を充填封止し、アンダーフィル材１２を硬化させて基板実装を完了する。   Then, as shown in FIG. 6C, an underfill material such as an insulating resin is provided in the gap between the semiconductor chip 1 and the printed wiring board 10 in a state where the solder balls 8 are connected to the printed wiring board 10. 12 is filled and sealed, and the underfill material 12 is cured to complete the substrate mounting.

以上のように従来においては、配線基板の配線電極とベアチップ実装に用いるチップ状の半導体装置とを突起電極を介して接続し、両者の間隙にアンダーフィル材を形成して実装するものであり、アンダーフィル材は両者の接続後または、接続前に予め供給して形成するものであった。近年、ＬＳＩの小型・高密度化に伴い外部接続用端子の多ピン化が進んでいる。このためＬＳＩパッケージには、パッケージの裏面に半田ボールをエリア配置したＢＧＡ（Ｂａｌｌ Ｇｒｉｄ Ａｒｒａｙ）タイプが多用されるようになっている。   As described above, in the past, the wiring electrode of the wiring board and the chip-like semiconductor device used for bare chip mounting are connected via the protruding electrode, and the underfill material is formed in the gap between the two and mounted. The underfill material was formed by supplying in advance after the connection between the two or before the connection. In recent years, with the miniaturization and high density of LSI, the number of pins for external connection has been increased. Therefore, BGA (Ball Grid Array) type in which solder balls are arranged on the back surface of the package is often used for LSI packages.

また、半導体装置に適応した例として、特許文献１，２に示されるように、半導体チップの周辺部に形成された電極より再配線をして、半導体チップ全面にはんだバンプ等の突起電極を用いてプリント基板等と接続するための電極形成構造および電極形成方法が提案されている。
特許第３３５６９２１号公報 特開昭６４−１２５７号公報 Further, as an example adapted to a semiconductor device, as shown in Patent Documents 1 and 2, rewiring is performed from an electrode formed on the periphery of a semiconductor chip, and a protruding electrode such as a solder bump is used on the entire surface of the semiconductor chip. An electrode forming structure and an electrode forming method for connecting to a printed board or the like have been proposed.
Japanese Patent No. 3356921 JP-A 64-1257

しかし、上述した構造の半導体装置においては下記に示すような課題があった。   However, the semiconductor device having the above-described structure has the following problems.

第１の課題は、半導体装置の回路素子が形成された面上に再配線パターンを形成する構造の半導体装置において、プリント回路基板に接続するためのはんだバンプ等の突起電極を形成するための再配線パターンの外部接続用電極を半導体チップの表面の保護膜に直接形成する際に、外部接続用電極の直下に半導体チップの配線パターンルールの再配線が存在すると、図７に示すように半導体チップ１の保護膜４上に形成された再配線の膜応力により半導体チップ１の保護膜４にクラックＡが入り、半導体チップ１の最上層の配線３が断線してしまう課題が出てきた。   A first problem is that in a semiconductor device having a structure in which a rewiring pattern is formed on a surface on which circuit elements of the semiconductor device are formed, re-generation for forming protruding electrodes such as solder bumps for connection to a printed circuit board is performed. When the external connection electrode of the wiring pattern is formed directly on the protective film on the surface of the semiconductor chip, if there is a rewiring of the wiring pattern rule of the semiconductor chip directly under the external connection electrode, the semiconductor chip as shown in FIG. The problem is that the crack A enters the protective film 4 of the semiconductor chip 1 due to the film stress of the rewiring formed on the protective film 4, and the uppermost wiring 3 of the semiconductor chip 1 is disconnected.

第２の課題は、半導体チップの最上層に半導体チップの電極をエリア状に半導体チップ表面全面に配置した半導体装置において、半導体チップの電極の直下の配線層に配線が存在すると、電極上に外部接続用電極を形成する際に、外部接続用電極を形成する金属膜の膜応力により、半導体チップの電極の直下の配線層にダメージを与えてしまう課題があった。   A second problem is that, in a semiconductor device in which the semiconductor chip electrodes are arranged in an area on the entire surface of the semiconductor chip on the uppermost layer of the semiconductor chip, if wiring exists in the wiring layer immediately below the electrodes of the semiconductor chip, When the connection electrode is formed, there is a problem that the wiring layer immediately below the electrode of the semiconductor chip is damaged by the film stress of the metal film forming the external connection electrode.

第３の課題は、第２の課題を改善するために、現状半導体チップの配線層の形成時に半導体チップの電極を形成する配線層より下の配線層を上部配線層の応力によるダメージを無くすために平坦化プロセスを導入していたが、平坦化プロセスを導入することで、半導体チップのコストが上昇してしまう課題があった。   The third problem is to eliminate the damage caused by the stress of the upper wiring layer in the wiring layer below the wiring layer forming the electrode of the semiconductor chip when forming the wiring layer of the current semiconductor chip in order to improve the second problem. However, there has been a problem that the cost of the semiconductor chip increases due to the introduction of the planarization process.

したがって、この発明の目的は、上記問題点に鑑み、半導体チップの表面に形成された再配線パターンの外部接続用電極下の半導体チップ内の最上層の配線において、外部接続用電極の金属膜の膜応力により、最上層配線が断線してしまうことを防止する半導体装置を提供することである。   Therefore, in view of the above problems, an object of the present invention is to form the metal film of the external connection electrode in the uppermost layer wiring in the semiconductor chip under the external connection electrode of the rewiring pattern formed on the surface of the semiconductor chip. It is an object of the present invention to provide a semiconductor device that prevents the uppermost layer wiring from being disconnected due to film stress.

上記課題を解決するためにこの発明の請求項１記載の半導体装置は、半導体チップの電極が形成された最上層の面上に、前記半導体チップの電極の位置に第１の開口部および前記半導体チップと電気的に絶縁された第２の開口部をそれぞれ有するように形成した感光性を有する第１の有機絶縁膜と、前記第１の有機絶縁膜、第１の開口部および第２の開口部上に前記半導体チップの電極と電気的に接続されるように形成した配線パターンと、前記第１の有機絶縁膜および前記配線パターン上に形成した第２の有機絶縁膜とを備え、前記第１の開口部と前記第２の開口部とが前記配線パターンで電気的に接続されるとともに前記第２の開口部に形成された前記配線パターンが外部接続用電極となり、前記第２の有機絶縁膜は前記外部接続用電極の位置を開口した半導体装置であって、前記外部接続用電極に相対する前記半導体チップの最上層の位置に、前記第１の有機絶縁膜の第２の開口部と同等以上のサイズの配線あるいは電極を有する。   In order to solve the above-described problems, according to a first aspect of the present invention, there is provided a semiconductor device according to a first aspect of the present invention, wherein the first opening and the semiconductor are formed on the uppermost surface of the semiconductor chip where the electrodes are formed. A photosensitive first organic insulating film formed so as to have a second opening electrically insulated from the chip, the first organic insulating film, the first opening, and the second opening A wiring pattern formed on the portion so as to be electrically connected to the electrode of the semiconductor chip, a first organic insulating film and a second organic insulating film formed on the wiring pattern, The first opening and the second opening are electrically connected by the wiring pattern, and the wiring pattern formed in the second opening serves as an external connection electrode, whereby the second organic insulation The membrane is the external connection electrode A semiconductor device having a position opened, wherein a wiring or an electrode having a size equal to or larger than that of the second opening of the first organic insulating film is provided at the uppermost layer position of the semiconductor chip opposite to the external connection electrode. Have

請求項２記載の半導体装置は、請求項１記載の半導体装置において、前記第１の有機絶縁膜の第２の開口部と同等以上のサイズの配線あるいは電極が前記半導体チップの内部回路と電気的に独立している。   The semiconductor device according to claim 2 is the semiconductor device according to claim 1, wherein a wiring or an electrode having a size equal to or larger than the second opening of the first organic insulating film is electrically connected to the internal circuit of the semiconductor chip. Independent.

請求項３記載の半導体装置は、半導体チップの電極が形成された第１の配線層の面上に、前記半導体チップの電極の位置に開口部を有するように形成した感光性を有する有機絶縁膜と、前記有機絶縁膜の開口部に前記半導体チップの電極と電気的に接続されるように形成した外部接続用電極とを備えた半導体装置であって、前記第１の配線層の下の第２の配線層の、前記第１の配線層に形成された前記半導体チップの電極と相対する位置に、前記有機絶縁膜の開口部と同等以上のサイズの配線あるいは電極を有する。   4. The semiconductor device according to claim 3, wherein the photosensitive organic insulating film is formed on the surface of the first wiring layer on which the electrode of the semiconductor chip is formed so as to have an opening at the position of the electrode of the semiconductor chip. And an external connection electrode formed so as to be electrically connected to the electrode of the semiconductor chip in the opening of the organic insulating film, the semiconductor device comprising: a first device under the first wiring layer; In the second wiring layer, a wiring or an electrode having a size equal to or larger than the opening of the organic insulating film is provided at a position facing the electrode of the semiconductor chip formed in the first wiring layer.

請求項４記載の半導体装置は、請求項３記載の半導体装置において、前記有機絶縁膜の開口部と同等以上のサイズの配線あるいは電極が前記半導体チップの内部回路と電気的に独立している。   A semiconductor device according to a fourth aspect is the semiconductor device according to the third aspect, wherein a wiring or an electrode having a size equal to or larger than the opening of the organic insulating film is electrically independent of the internal circuit of the semiconductor chip.

この発明の請求項１記載の半導体装置によれば、第１の課題のように半導体チップの保護膜表面に再配線パターンを形成した構成において、再配線パターンの外部接続用電極に相対する半導体チップの最上層の位置に、第１の有機絶縁膜の第２の開口部と同等以上のサイズの配線あるいは電極を有するので、外部接続用電極を形成する金属膜の膜応力により保護膜にクラックが生じて半導体チップの最上層の配線へ与えるダメージを低減することができる。そのため、半導体チップのプロセスコストを低減できる。   According to the semiconductor device of the first aspect of the present invention, in the configuration in which the rewiring pattern is formed on the surface of the protective film of the semiconductor chip as in the first problem, the semiconductor chip facing the external connection electrode of the rewiring pattern Since the wiring or electrode having a size equal to or larger than that of the second opening of the first organic insulating film is provided at the position of the uppermost layer, the protective film is cracked by the film stress of the metal film forming the external connection electrode. It is possible to reduce damage caused to the uppermost wiring of the semiconductor chip. Therefore, the process cost of the semiconductor chip can be reduced.

請求項２では、第１の有機絶縁膜の第２の開口部と同等以上のサイズの配線あるいは電極が半導体チップの内部回路と電気的に独立している構成において、請求項１の効果が得られる。   According to a second aspect of the present invention, the effect of the first aspect can be obtained in a configuration in which a wiring or an electrode having a size equal to or larger than that of the second opening of the first organic insulating film is electrically independent from the internal circuit of the semiconductor chip. It is done.

この発明の請求項３記載の半導体装置によれば、第２、第３の課題のように半導体チップの最上層（第１の配線層）に半導体チップの電極をエリア状に半導体チップ表面全面に配置した構成において、第１の配線層の下の第２の配線層の、第１の配線層に形成された半導体チップの電極と相対する位置に、有機絶縁膜の開口部と同等以上のサイズの配線あるいは電極を有するので、はんだ、バンプ等を形成する外部接続用電極を形成する金属膜の応力による電極直下の第２の配線層へのダメージを低減することができる。また、電極下の配線層に平坦化プロセスを導入しなくてもよいので、プロセスコストを低減することができる。   According to the semiconductor device of the third aspect of the present invention, as in the second and third problems, the electrodes of the semiconductor chip are arranged in an area on the entire surface of the semiconductor chip on the uppermost layer (first wiring layer) of the semiconductor chip. In the arrangement, the second wiring layer below the first wiring layer is at a size equal to or larger than the opening of the organic insulating film at a position facing the electrode of the semiconductor chip formed in the first wiring layer. Therefore, it is possible to reduce damage to the second wiring layer immediately below the electrode due to the stress of the metal film forming the external connection electrodes for forming solder, bumps and the like. In addition, since it is not necessary to introduce a planarization process into the wiring layer under the electrode, the process cost can be reduced.

請求項４では、有機絶縁膜の開口部と同等以上のサイズの配線あるいは電極が半導体チップの内部回路と電気的に独立している構成において、請求項３の効果が得られる。   According to the fourth aspect of the present invention, the effect of the third aspect can be obtained in a configuration in which wirings or electrodes having a size equal to or larger than the opening of the organic insulating film are electrically independent from the internal circuit of the semiconductor chip.

この発明の第１の実施の形態を図１および図２に基づいて説明する。図１は本発明の第１の実施形態の半導体装置の断面図である。   A first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention.

図１において、１は半導体チップ、２は電極、３は内部配線、４は保護膜、５は外部接続用電極、６は第１の有機絶縁膜、７は配線パターン、８ははんだボール、９はＵＢＭ(アンダー・バリア・メタル)、１３は外部接続用電極下電極、１４は第２の有機絶縁膜である。   In FIG. 1, 1 is a semiconductor chip, 2 is an electrode, 3 is an internal wiring, 4 is a protective film, 5 is an external connection electrode, 6 is a first organic insulating film, 7 is a wiring pattern, 8 is a solder ball, 9 Is UBM (under barrier metal), 13 is a lower electrode for external connection, and 14 is a second organic insulating film.

図１に示すように、半導体チップ１の電極２が形成された最上層の面上に、半導体チップ１の電極２の位置に第１の開口部および半導体チップ１と電気的に絶縁された第２の開口部をそれぞれ有するように形成した感光性を有する第１の有機絶縁膜６と、第１の有機絶縁膜６、第１の開口部および第２の開口部上に半導体チップ１の電極２と電気的に接続されるように形成した配線パターン７と、第１の有機絶縁膜６および配線パターン７上に形成した第２の有機絶縁膜１４とを備えている。また、第１の開口部と第２の開口部とが配線パターン７で電気的に接続されるとともに第２の開口部に形成された配線パターンが外部接続用電極５となり、第２の有機絶縁膜１４は外部接続用電極５の位置を開口部としている。また、外部接続用電極５に相対する半導体チップ１の最上層の位置に、第１の有機絶縁膜６の第２の開口部と同等以上のサイズの配線あるいは電極１３を有する。   As shown in FIG. 1, the first opening and the semiconductor chip 1 are electrically insulated from each other at the position of the electrode 2 of the semiconductor chip 1 on the surface of the uppermost layer where the electrode 2 of the semiconductor chip 1 is formed. A first organic insulating film 6 having photosensitivity formed so as to have two openings, and an electrode of the semiconductor chip 1 on the first organic insulating film 6, the first opening, and the second opening. 2 and a second organic insulating film 14 formed on the wiring pattern 7 and the first organic insulating film 6. Further, the first opening and the second opening are electrically connected by the wiring pattern 7 and the wiring pattern formed in the second opening becomes the external connection electrode 5, and the second organic insulation The film 14 uses the position of the external connection electrode 5 as an opening. Further, a wiring or electrode 13 having a size equal to or larger than that of the second opening of the first organic insulating film 6 is provided at the position of the uppermost layer of the semiconductor chip 1 facing the external connection electrode 5.

この場合、図１に示す半導体装置は、ベアチップ実装に用いられるチップ状の半導体装置であり、その上面内に半導体集積回路が形成された半導体チップ１上に半導体チップの電極２が形成され、かつ電極２が形成された同一配線層に半導体チップ１の半導体集積回路と電気的に接続された内部配線３が形成されている。また、この半導体チップ１の表面は電極２の部分を開口した絶縁性の保護膜４で覆われている。そして、この半導体チップ２の保護膜４表面には半導体チップ１の電極２と外部接続用電極５の部分を開口した感光性の有機樹脂である第１の有機絶縁膜６が形成されている。この第１の有機絶縁膜６上には半導体チップ１の電極２と外部接続用電極５とを電気的に接続する配線パターン７が形成され、外部接続用電極５上にははんだバンプ８とＵＢＭ９(アンダー・バリア・メタル)が形成されている。また、この外部接続用電極５の周辺部と第１の有機絶縁膜６と配線パターン７上に第２の有機絶縁膜１４が形成されている。この外部接続用電極５下には半導体チップ１の電極と同一の配線層上に形成された内部配線３として外部接続用電極下電極１３が設置された構造になっている。   In this case, the semiconductor device shown in FIG. 1 is a chip-like semiconductor device used for bare chip mounting, and an electrode 2 of the semiconductor chip is formed on the semiconductor chip 1 on which the semiconductor integrated circuit is formed, and An internal wiring 3 electrically connected to the semiconductor integrated circuit of the semiconductor chip 1 is formed in the same wiring layer on which the electrode 2 is formed. The surface of the semiconductor chip 1 is covered with an insulating protective film 4 having an opening in the electrode 2 portion. On the surface of the protective film 4 of the semiconductor chip 2, a first organic insulating film 6, which is a photosensitive organic resin having openings in the electrodes 2 and the external connection electrodes 5 of the semiconductor chip 1, is formed. A wiring pattern 7 for electrically connecting the electrode 2 of the semiconductor chip 1 and the external connection electrode 5 is formed on the first organic insulating film 6. The solder bump 8 and the UBM 9 are formed on the external connection electrode 5. (Under barrier metal) is formed. A second organic insulating film 14 is formed on the periphery of the external connection electrode 5, the first organic insulating film 6, and the wiring pattern 7. Under this external connection electrode 5, an external connection electrode lower electrode 13 is provided as an internal wiring 3 formed on the same wiring layer as the electrode of the semiconductor chip 1.

さらに、この外部接続用電極下電極１３は半導体チップ１の集積回路に電気的に接続されていても、電気的に独立していてもどちらでも良い。   Further, the external connection electrode lower electrode 13 may be electrically connected to the integrated circuit of the semiconductor chip 1 or may be electrically independent.

図２は本発明の第１の実施形態の外部接続用電極下電極のサイズの関係を示した説明図である。図２において、ａは第１の有機絶縁膜６の外部接続用電極５部の開口サイズ、ｂは外部接続用電極下電極１３のサイズを示している。   FIG. 2 is an explanatory diagram showing the size relationship of the external connection electrode lower electrode according to the first embodiment of the present invention. In FIG. 2, a indicates the opening size of the external connection electrode 5 portion of the first organic insulating film 6, and b indicates the size of the external connection electrode lower electrode 13.

図２（ａ）は、第１の有機絶縁膜６の外部接続用電極５部の開口サイズａと外部接続用電極下電極１３のサイズｂが同じである場合である。図２（ｂ）は、外部接続用電極下電極１３のサイズｂが第１の有機絶縁膜６の外部接続用電極５部の開口サイズａより大きい場合である。   FIG. 2A shows a case where the opening size a of the external connection electrode 5 portion of the first organic insulating film 6 and the size b of the external connection electrode lower electrode 13 are the same. FIG. 2B shows a case where the size b of the external connection electrode lower electrode 13 is larger than the opening size a of the external connection electrode 5 portion of the first organic insulating film 6.

以上のように本実施形態によれば、外部接続用電極５に相対する半導体チップ１の最上層の位置に、第１の有機絶縁膜６の第２の開口部と同等以上のサイズの配線あるいは電極を有するので、外部接続用電極５を形成する金属膜の膜応力により保護膜４にクラックが生じて半導体チップ１の最上層の配線へ与えるダメージを低減することができる。そのため、半導体チップ１のプロセスコストを低減できる。   As described above, according to the present embodiment, a wiring having a size equal to or larger than that of the second opening of the first organic insulating film 6 is provided at the uppermost layer position of the semiconductor chip 1 facing the external connection electrode 5. Since the electrode is provided, the protective film 4 is cracked by the film stress of the metal film forming the external connection electrode 5, and damage to the uppermost layer wiring of the semiconductor chip 1 can be reduced. Therefore, the process cost of the semiconductor chip 1 can be reduced.

この発明の第２の実施の形態を図３および図４に基づいて説明する。図３は本発明の第２の実施形態の半導体装置の断面図である。   A second embodiment of the present invention will be described with reference to FIGS. FIG. 3 is a cross-sectional view of the semiconductor device according to the second embodiment of the present invention.

図３において、１は半導体チップ、４は保護膜、５は外部接続用電極、６は第１の有機絶縁膜、８ははんだボール、１５は第１の配線層、１６は第１の電極、１７は第２の配線層、１８は第２の電極である。   In FIG. 3, 1 is a semiconductor chip, 4 is a protective film, 5 is an external connection electrode, 6 is a first organic insulating film, 8 is a solder ball, 15 is a first wiring layer, 16 is a first electrode, Reference numeral 17 denotes a second wiring layer, and 18 denotes a second electrode.

図３に示すように、半導体チップ１の電極２が形成された第１の配線層１５の面上に、半導体チップ１の電極２の位置に開口部を有するように形成した感光性を有する有機絶縁膜６と、有機絶縁膜６の開口部に半導体チップ１の電極１６と電気的に接続されるように形成した外部接続用電極５とを備えている。また、第１の配線層１５の下の第２の配線層１７の、第１の配線層１５に形成された半導体チップの電極１６と相対する位置に、有機絶縁膜６の開口部と同等以上のサイズの配線あるいは電極１８を有する。   As shown in FIG. 3, a photosensitive organic material formed so as to have an opening at the position of the electrode 2 of the semiconductor chip 1 on the surface of the first wiring layer 15 on which the electrode 2 of the semiconductor chip 1 is formed. An insulating film 6 and an external connection electrode 5 formed so as to be electrically connected to the electrode 16 of the semiconductor chip 1 in the opening of the organic insulating film 6 are provided. Further, the second wiring layer 17 under the first wiring layer 15 is equal to or more than the opening of the organic insulating film 6 at a position facing the electrode 16 of the semiconductor chip formed in the first wiring layer 15. The size of the wiring or the electrode 18 is provided.

この場合、図３に示す半導体装置は、ベアチップ実装に用いられるチップ状の半導体装置であり、その上面内に半導体集積回路が形成された半導体チップ１上に半導体チップ１の半導体集積回路と電気的に接続された第１の配線層１５により半導体チップ１の全面にエリア状に第１の電極１６が形成されている。また、この半導体チップ１の表面は第１の電極１６の部分を開口した絶縁性の保護膜４で覆われている。そして、この半導体チップ１の保護膜４表面には半導体チップ１の第１の電極１６の部分を開口した感光性の有機樹脂である第１の有機絶縁膜６が形成されている。この第１の有機絶縁膜６上には半導体チップ１の電極１６と接続される外部接続用電極５が形成され、外部接続用電極５上にははんだバンプ８が形成されている。しかも第１の配線層１５の下の第２の配線層１７の第１の電極１６と相対する位置に第２の電極１８が形成された構造になっている。   In this case, the semiconductor device shown in FIG. 3 is a chip-like semiconductor device used for bare chip mounting, and is electrically connected to the semiconductor integrated circuit of the semiconductor chip 1 on the semiconductor chip 1 on which the semiconductor integrated circuit is formed. A first electrode 16 is formed in the form of an area on the entire surface of the semiconductor chip 1 by the first wiring layer 15 connected to. The surface of the semiconductor chip 1 is covered with an insulating protective film 4 having an opening at the first electrode 16. On the surface of the protective film 4 of the semiconductor chip 1, a first organic insulating film 6 that is a photosensitive organic resin having an opening at the first electrode 16 of the semiconductor chip 1 is formed. An external connection electrode 5 connected to the electrode 16 of the semiconductor chip 1 is formed on the first organic insulating film 6, and a solder bump 8 is formed on the external connection electrode 5. In addition, the second electrode 18 is formed at a position facing the first electrode 16 of the second wiring layer 17 below the first wiring layer 15.

さらに、この第２の電極１８は半導体チップ１の集積回路に電気的に接続されていても、電気的に独立していてもどちらでも良い。   Further, the second electrode 18 may be electrically connected to the integrated circuit of the semiconductor chip 1 or may be electrically independent.

図４は本発明の第２の実施形態の第１の電極１６と第２の電極１８のサイズの関係を示した説明図である。図４において、ａは第１の電極１６のサイズ、ｂは第２の電極１８のサイズを示している。また、第１の電極１６のサイズａと第１の有機絶縁膜６の開口部のサイズは同等である。   FIG. 4 is an explanatory diagram showing the size relationship between the first electrode 16 and the second electrode 18 according to the second embodiment of the present invention. In FIG. 4, a indicates the size of the first electrode 16, and b indicates the size of the second electrode 18. Further, the size a of the first electrode 16 and the size of the opening of the first organic insulating film 6 are equivalent.

図４（ａ）は、第１の電極１６のサイズａと第２の電極１８のサイズｂが同じである場合である。図４（ｂ），（ｃ）は第１の電極１６のサイズａが第２の電極１８のサイズｂより小さい場合である。   FIG. 4A shows the case where the size a of the first electrode 16 and the size b of the second electrode 18 are the same. 4B and 4C show the case where the size a of the first electrode 16 is smaller than the size b of the second electrode 18.

図４（ｃ）は第１の電極１６の下に、複数の配線または電極が存在する場合を想定している。第１の電極１６の下にある電極あるいは配線が複数個あっても、第１の有機絶縁膜６の開口部の周囲と重なる位置にある電極あるいは配線のエッジ間が、第１の有機絶縁膜６の開口部のサイズより大きければ、図４の（ａ），（ｂ）と同じ効果が得られる。   FIG. 4C assumes a case where a plurality of wirings or electrodes exist under the first electrode 16. Even if there are a plurality of electrodes or wirings under the first electrode 16, the first organic insulating film is between the edges of the electrodes or wirings that overlap with the periphery of the opening of the first organic insulating film 6. If it is larger than the size of the opening 6, the same effect as in FIGS. 4A and 4B can be obtained.

本発明にかかる半導体装置は、外部接続用電極を形成する金属膜の膜応力による半導体チップの最上層の配線へのダメージを低減することができる等の効果を有し、特に半導体チップ上で外部端子用の電極パッドが再配線され、外部端子が２次元エリア配置された半導体装置として有用である。   The semiconductor device according to the present invention has such an effect that the damage to the wiring on the uppermost layer of the semiconductor chip due to the film stress of the metal film forming the external connection electrode can be reduced. This is useful as a semiconductor device in which electrode pads for terminals are rewired and external terminals are arranged in a two-dimensional area.

本発明の第１の実施形態の半導体装置の断面図である。1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention. 本発明の第１の実施形態の外部接続用電極下電極のサイズの関係を示した説明図である。It is explanatory drawing which showed the size relationship of the electrode for external connection electrodes of the 1st Embodiment of this invention. 本発明の第２の実施形態の半導体装置の断面図である。It is sectional drawing of the semiconductor device of the 2nd Embodiment of this invention. 本発明の第２の実施形態の第１の電極と第２の電極のサイズの関係を示した説明図である。It is explanatory drawing which showed the relationship between the size of the 1st electrode of the 2nd Embodiment of this invention, and a 2nd electrode. 従来例の半導体装置を示す断面図である。It is sectional drawing which shows the semiconductor device of a prior art example. 従来例の半導体装置の実装方法を示す断面図である。It is sectional drawing which shows the mounting method of the semiconductor device of a prior art example. 従来例の半導体装置の問題点を示す断面図である。It is sectional drawing which shows the problem of the semiconductor device of a prior art example.

符号の説明Explanation of symbols

１ 半導体チップ
２ 電極
３ 内部配線
４ 保護膜
５ 外部接続用電極
６ 第１の有機絶縁膜
７ 配線パターン
８ はんだボール
９ ＵＢＭ(アンダー・バリア・メタル)
１０ プリント配線基板
１１ 接続用配線電極
１２ アンダーフィル
１３ 外部接続用電極下電極
１４ 第２の有機絶縁膜
１５ 第１の配線層
１６ 第１の電極
１７ 第２の配線層
１８ 第２の電極 DESCRIPTION OF SYMBOLS 1 Semiconductor chip 2 Electrode 3 Internal wiring 4 Protective film 5 External connection electrode 6 1st organic insulating film 7 Wiring pattern 8 Solder ball 9 UBM (under barrier metal)
DESCRIPTION OF SYMBOLS 10 Printed wiring board 11 Connection wiring electrode 12 Underfill 13 External connection electrode lower electrode 14 Second organic insulating film 15 First wiring layer 16 First electrode 17 Second wiring layer 18 Second electrode

Claims (4)

半導体チップの電極が形成された最上層の面上に、前記半導体チップの電極の位置に第１の開口部および前記半導体チップと電気的に絶縁された第２の開口部をそれぞれ有するように形成した感光性を有する第１の有機絶縁膜と、前記第１の有機絶縁膜、第１の開口部および第２の開口部上に前記半導体チップの電極と電気的に接続されるように形成した配線パターンと、前記第１の有機絶縁膜および前記配線パターン上に形成した第２の有機絶縁膜とを備え、前記第１の開口部と前記第２の開口部とが前記配線パターンで電気的に接続されるとともに前記第２の開口部に形成された前記配線パターンが外部接続用電極となり、前記第２の有機絶縁膜は前記外部接続用電極の位置を開口した半導体装置であって、前記外部接続用電極に相対する前記半導体チップの最上層の位置に、前記第１の有機絶縁膜の第２の開口部と同等以上のサイズの配線あるいは電極を有することを特徴とする半導体装置。   Formed on the surface of the uppermost layer where the electrodes of the semiconductor chip are formed so as to have a first opening and a second opening electrically insulated from the semiconductor chip at the position of the electrode of the semiconductor chip, respectively. The first organic insulating film having photosensitivity and the first organic insulating film, the first opening, and the second opening are formed to be electrically connected to the electrode of the semiconductor chip. A wiring pattern; and a first organic insulating film and a second organic insulating film formed on the wiring pattern, wherein the first opening and the second opening are electrically connected by the wiring pattern. And the wiring pattern formed in the second opening serves as an external connection electrode, and the second organic insulating film is a semiconductor device having an opening at the position of the external connection electrode, Relative to the external connection electrode Wherein the top layer of the position of the semiconductor chip, a semiconductor device and having a second opening and the wiring or the electrode of equal or greater size of the first organic insulating film. 前記第１の有機絶縁膜の第２の開口部と同等以上のサイズの配線あるいは電極が前記半導体チップの内部回路と電気的に独立している請求項１記載の半導体装置。   2. The semiconductor device according to claim 1, wherein a wiring or an electrode having a size equal to or larger than that of the second opening of the first organic insulating film is electrically independent of an internal circuit of the semiconductor chip. 半導体チップの電極が形成された第１の配線層の面上に、前記半導体チップの電極の位置に開口部を有するように形成した感光性を有する有機絶縁膜と、前記有機絶縁膜の開口部に前記半導体チップの電極と電気的に接続されるように形成した外部接続用電極とを備えた半導体装置であって、前記第１の配線層の下の第２の配線層の、前記第１の配線層に形成された前記半導体チップの電極と相対する位置に、前記有機絶縁膜の開口部と同等以上のサイズの配線あるいは電極を有することを特徴とする半導体装置。   An organic insulating film having photosensitivity formed so as to have an opening at the position of the electrode of the semiconductor chip on the surface of the first wiring layer on which the electrode of the semiconductor chip is formed, and the opening of the organic insulating film And an external connection electrode formed so as to be electrically connected to the electrode of the semiconductor chip, wherein the first wiring layer under the first wiring layer has the first wiring layer. A semiconductor device comprising a wiring or an electrode having a size equal to or larger than the opening of the organic insulating film at a position facing the electrode of the semiconductor chip formed in the wiring layer. 前記有機絶縁膜の開口部と同等以上のサイズの配線あるいは電極が前記半導体チップの内部回路と電気的に独立している請求項３記載の半導体装置。   4. The semiconductor device according to claim 3, wherein a wiring or an electrode having a size equal to or larger than that of the opening of the organic insulating film is electrically independent from an internal circuit of the semiconductor chip.
JP2003309880A 2003-09-02 2003-09-02 Semiconductor device Pending JP2005079431A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011114304A (en) * 2009-11-30 2011-06-09 Shinko Electric Ind Co Ltd Semiconductor device built-in substrate and method of manufacturing the same
WO2018198990A1 (en) * 2017-04-24 2018-11-01 ローム株式会社 Electronic component and semiconductor device

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011114304A (en) * 2009-11-30 2011-06-09 Shinko Electric Ind Co Ltd Semiconductor device built-in substrate and method of manufacturing the same
WO2018198990A1 (en) * 2017-04-24 2018-11-01 ローム株式会社 Electronic component and semiconductor device
JPWO2018198990A1 (en) * 2017-04-24 2020-02-27 ローム株式会社 Electronic components and semiconductor devices
US11239189B2 (en) 2017-04-24 2022-02-01 Rohm Co., Ltd. Electronic component and semiconductor device
JP7160797B2 (en) 2017-04-24 2022-10-25 ローム株式会社 Electronic components and semiconductor equipment
JP2022179747A (en) * 2017-04-24 2022-12-02 ローム株式会社 Semiconductor device
JP7509849B2 (en) 2017-04-24 2024-07-02 ローム株式会社 Semiconductor Device
US12051662B2 (en) 2017-04-24 2024-07-30 Rohm Co., Ltd. Electronic component and semiconductor device

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