JP2005079221A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device wherein layout of a large number of I/O cells is enabled in small area even when I/O cells with measures against plug-and-play and I/O cells without the measures are intermingled and double well structure is adopted to each of the I/O cells. <P>SOLUTION: In the semiconductor device wherein the I/O cells (100c) without the measures against plug-and-play and the I/O cells (100a) with the measures against plug-and-play are intermingled, grouping of the I/O cells (100a) with the measures against plug-and-play is performed, and they are arranged. Deep n-type wells (T-Well) are subject to common configuration between the I/O cell (100a) to which grouping is performed. Deep n-type wells (T-Well) are formed being isolated from each other, regarding a part wherein the I/O cell (100a) with the measures against plug-and-play and the I/O cell (100c) without the measures are adjacent to each other. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an I / O technique for a semiconductor device, and more particularly to a technique that is useful for a semiconductor device mounted on a module that can be inserted and removed without turning off the power of the system.

  For example, at the time of maintenance and inspection of a mainframe (large computer), so-called hot-line insertion / removal may be performed in which individual modules constituting the mainframe are inserted / removed from the system without turning off the system power. In such a hot-swap operation, in a LSI (semiconductor device) mounted on the module, a high level signal may be input from the outside to the input / output terminal in a state where power supply is stopped. This is because the power supply pins and the signal pins are connected in an unpredictable order when the module is inserted or removed from the system.

  In an I / O circuit of an LSI having an I / O circuit that is mounted on a module and has no measures for hot-swap, as shown in the chip cross-sectional view of FIG. 9, the power supply voltage VDD is 0V. When a high level (for example, 5 V) voltage is applied to the input / output pad 20, the drain 121d of the P-channel type output MOS transistor Q1 (the source is omitted in FIG. 9) and the N-type well N-Well During this time, a forward voltage is generated, and a current flows from the drain 121d to the terminal of the power supply voltage VDD. The carriers at this time are diffused from the N-type well N-Well through the substrate P-SUB to the pre-buffer 22 of the input circuit and the CMOS circuit constituting the internal logic, and these are supplied when the power supply voltage VDD is supplied. Latch-up may occur in the CMOS circuit.

  Therefore, conventionally, as a countermeasure against hot-swapping, as shown in the chip cross-sectional view of FIG. 10, the P-channel type output MOS transistor Q1 has a floating well structure in which power is not supplied to the N-type well N-Well. As shown in the circuit diagram of FIG. 6, the control MOS transistors Q27 and Q28 and the well-feeding MOS transistor Q29 are provided, and the N-type well N of the P-channel type MOS transistors Q21 and Q25 is provided only when the power supply voltage VDD is supplied. A circuit in which power is supplied to the well and the terminal of the power supply voltage VDD is disconnected from the N-type well N-Well of the P-channel MOS transistors Q21 and Q25 when the power supply voltage VDD is not supplied to be the same as the floating well structure The configuration was being applied.

  In recent years, for the purpose of improving noise immunity of each element of a semiconductor integrated circuit, a well of an output MOS transistor or a protection diode has a deep N-type well formed by diffusing impurity ions to a deep position on the substrate, and the deep N-type well. A technique of using a double structure with a well formed in the upper layer of a well is used.

  Currently, in a semiconductor device that requires a large number of external connection terminals, the I / O circuit is provided in a limited area of the semiconductor chip such as the peripheral portion, and therefore, the interval between the individual I / O circuits can be made too large. The reality is that you can't. For example, when 1000 I / O circuits are mounted, the size of the I / O circuit needs to be about 40 to 50 μm.

  Further, when the well of the circuit element has a double structure, the area of the diffusion region of the deep N-type well needs to be larger than that of the upper N-type well, and the deep N-type well diffuses ions to a deep range. Therefore, it is necessary to form a distance of about 10 μm, for example, in order to separate two independent well regions from each other. In the case of a normal well having a single structure, an interval of, for example, about 2.0 μm may be provided in order to separate and separate two wells. In comparison, a distance of about 5 times is required. For this reason, the size of a transistor that can be laid out is smaller than that of a single well I / O circuit, making it difficult to achieve desired performance.

  From the above, when a double well structure is applied to an I / O circuit, it is conceivable to share a deep N-type well between adjacent I / O cells. When I / O cells with measures for hot-swap are mixed with I / O cells without measures for hot-swap, a deep N-type well is shared between these I / O cells If it does so, the problem that the effect of a hot-swap countermeasure will be lose | eliminated also in the I / O cell by which the hot-swap countermeasure is originally taken. This is because, for example, in the I / O cell with hot-swap countermeasures shown in FIG. 10, current does not flow during hot-swap from the P-type diffusion region 121d to which the input / output pad 20 is connected due to the floating well structure. This is because by sharing the deep N-type well, a current flows to the I / O cell without hot-swapping measures through this well.

  On the other hand, if the deep N-type wells are separated and independent for all the I / O cells, the interval between the I / O cells becomes too large, and it becomes impossible to lay out a large number of I / O cells. There is.

  The object of the present invention is to lay out almost the same number of I / O cells as compared to the case where deep N-type wells are formed in common for all I / O cells, and to provide an I / O with hot-swap countermeasures. Even when O cells and I / O cells without countermeasures are mixed, an object of the present invention is to provide a semiconductor device in which the I / O cells with countermeasures can exert their effects as they are.

Outlines of representative ones of the inventions disclosed in the present application will be described as follows.
That is, an I / O cell without hot-swap measures (that is, when the power supply voltage is not supplied and a high level signal is input to the external connection terminal, the power supply voltage is supplied from the external connection terminal via the P-type diffusion region. I / O cell having a current path through which current flows to the terminal) and I / O cell with hot-swap measures (that is, when the power supply voltage is not supplied and a high level signal is input to the external connection terminal) In a semiconductor device in which an I / O cell having no current path through which current flows from an external connection terminal to a power supply voltage terminal via the P-type diffusion region is mixed, The grouped I / O cells are grouped and arranged side by side, and a deep N-type well is shared between the grouped I / O cells. An I / O cell with a countermeasure against hot-swapping and an I / O cell without a countermeasure are adjacent to each other. Together It is obtained so as to separate the deep N-well to the portion.

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
That is, according to the present invention, in a semiconductor device in which I / O cells with and without hot-swap countermeasures are mixed, a terminal has a P-type diffusion region connected to an external connection terminal. In the circuit element, the N-type well is separated from the I / O circuit with countermeasure and the I / O circuit without countermeasure, so that the I / O circuit with countermeasure can exert its effect as it is. On the other hand, since the I / O cells with hot-swap countermeasures are grouped and N-type wells are combined, the number of regions separating the N-type wells can be reduced to one or two. Therefore, the number of I / O cells that can be laid out in the same area is hardly reduced.

Embodiments of the present invention will be described below with reference to the drawings of FIGS.
FIG. 1 is a layout diagram showing a semiconductor device according to an embodiment of the present invention.
The semiconductor device 10 of this embodiment is, for example, an LSI mounted on a module board that performs one function of a main frame, and exchanges signals with the outside at the periphery so as to surround internal circuits that realize various functions. Many (for example, 1000) I / O cells are formed. The I / O cell group 11 is formed in a row along each of the four sides of the semiconductor device 10.

  It is assumed that the semiconductor device 10 is mounted on a module board that can be hot-plugged with respect to the main frame. Therefore, the I / O cell group 11 of the semiconductor device 10 is provided with measures for hot-swap. I / O cell groups 11A and 11B are included.

  In general, when a module board can be hot-swapped, hot-swap is performed for I / O cells directly connected to external connection terminals of the module board among a plurality of LSI I / O cells mounted on the module board. However, it is not necessary to take measures for hot-swapping for I / O cells connected to other LSIs and other ICs in the module board. This is because, when the power supply to the module board is stopped during hot plugging, a high level voltage may be applied to the external connection terminal of the module board, but from other LSIs or ICs in the module board This is because a high level signal is not output because power supply is stopped. That is, a high level signal is applied to the I / O cells connected to other LSIs and other ICs in the module board after the power supply voltage is supplied.

  In the semiconductor integrated circuit 10 of this embodiment, the I / O cell groups 11A and 11B in which measures against the hot-swap are taken, for example, form two systems of I / O ports that are directly connected to the external connection terminals of the module board. ing. Of these, one I / O cell group 11A is composed of, for example, 64-bit I / O cells, and the other I / O cell group 11B is composed of, for example, 8-bit I / O cells. Has been laid out. The other I / O cell group 11C is a collection of I / O cells for which measures for hot-swap are not taken.

  FIG. 2 shows an enlarged layout view of the connection portion between the I / O cell group 11A with hot-swap countermeasures and the I / O cell group 11C without countermeasures. FIG. 3 shows a chip cross-sectional view of an I / O circuit without hot-swap countermeasures, and FIG. 4 shows a chip cross-sectional view of an I / O circuit with hot-swap countermeasures.

  Although the circuit diagram of the I / O circuit of this embodiment is omitted, a P-channel output MOS transistor Q1 and an N-channel output MOS transistor Q2 are connected in series between the power supply voltage VDD-VSS. An output circuit having a connection node N1 wired to an input / output pad 20 serving as an external connection terminal, and an inverter composed of a P-channel MOS transistor Q11 and an N-channel MOS transistor Q12 having both gate terminals wired to the external connection terminal It has a pre-buffer 22 as a type input circuit.

  As shown in FIGS. 3 and 4, the P-channel output MOS transistor Q1 and the N-channel output MOS transistor Q2 are applied when a voltage higher than the power supply voltage VDD-VSS is applied to the input / output pad 20. , And also serves as a protective diode that allows the drain terminals 121d and 123d to escape to the source terminals (power supply voltage terminals) 121s and 123s through the wells N-Well and P-Well.

  In FIG. 2, each cell 100a surrounded by a one-dot chain line is one I / O cell with a hot-swap countermeasure, and a cell 100c surrounded by a one-dot chain line is one without a hot-swap countermeasure. Each I / O cell is shown.

  As shown in FIG. 2 and FIG. 3, the I / O cell 100c without hot-swap countermeasures, in order from the outer peripheral side of the semiconductor chip, is an input / output pad 20 serving as an external connection terminal, a P-channel type output MOS transistor Q1, An N channel type output MOS transistor Q2 and a P channel type MOS transistor Q11 and an N channel type MOS transistor Q12 constituting the pre-buffer 22 are formed in a line.

  Separated deep N-type wells T-Well are formed in the output MOS transistors Q1 and Q2 and the prebuffer 22 constituting the I / O cell 100c. Then, an N-type well N-Well and a P-type well P-Well are formed inside the deep N-type well T-Well, and the source and drain of the transistor are formed inside these wells N-Well and P-Well. Diffusion regions 121d, 121s, 123d, 123s, 124d, 124s, 126d, and 126s are formed with gate electrodes G1 to G4 and wirings thereon via an insulating film (not shown).

  Further, in each of the wells N-Well and P-Well and the deep N-type well T-Well of the N-channel type output MOS transistor Q2, well-fed diffusion regions 111 to 115 are formed, and the power supply voltages VDD and VSS are respectively provided. The power supply wiring is connected. In FIG. 2, the well power supply diffusion regions 111 to 115 are omitted. These diffusion regions 111 to 115 are formed so as to surround the center along the peripheral edge of each well.

  On the other hand, as shown in FIGS. 2 and 4, the I / O cell 100a with a hot-swap countermeasure supplies power to the well N-Well of the output MOS transistor Q1 from the I / O cell 100c without the hot-swap countermeasure in FIG. Thus, the output MOS transistor Q1 has a floating well structure without the wiring to be used. According to the output circuit including such an output MOS transistor Q1, the operation characteristics slightly vary depending on the well voltage as compared with the case where the well power supply is performed, but a desired logical operation can be obtained as the operation of the circuit. I can do it.

  As shown in FIG. 2, it is necessary to provide a large number of I / O cells 100a and 100c formed as described above in a limited space such as a peripheral portion of a semiconductor chip. The deep N-type well T-Well is shared between cells without separation. However, the deep N-type well T-Well is separated and formed between the I / O cell 100a with the hot-swap countermeasure and the I / O cell 100c without the countermeasure.

  Therefore, a slightly large interval (for example, one I / O cell) is used to separate the deep N-type well T-Well between the I / O cell group 11A with hot-swap countermeasures and the I / O cell group 11C without countermeasures. The separation region is provided with an interval of O cells), but the I / O cell group 11A with a countermeasure against hot-swapping is grouped, and the portion where the separation region is provided is a grouped I / O cell group 11A. , 11B, the number of I / O cells that can be formed by this region is reduced, or the layout area loss is small.

  Further, in the semiconductor device 10 of this embodiment, a power input / output pad 20A for inputting power supply voltages VDD and VSS and a wiring (not shown) are provided in this isolation region, and this isolation region is used as a power supply voltage input cell 200. . By arranging the power source cells that do not depend on the diffusion region in this way, the separation region is effectively used, and the waste on the layout is completely eliminated.

  As described above, according to the semiconductor device 10 of this embodiment, for the I / O cell 100a directly connected to the external connection terminal of the module board, the P channel type output MOS transistor Q1 is made a floating well type. When the module board is hot-plugged, even when the power supply voltage VDD is 0 V and a high level signal is input to the input / output pad 20 of the I / O cell 100a, the output MOS transistor Q1 is connected to the terminal of the power supply voltage VDD. The carrier does not move, and therefore, it is avoided that the carrier diffuses to other CMOS circuits via the substrate P-SUB, thereby preventing the occurrence of latch-up during hot-swap. .

  In addition, for the I / O cell 100c of the semiconductor device 10 connected to another LSI, IC, or the like on the same module board, a normal I / O circuit that is not subjected to hot-swap measures is applied. Therefore, an I / O circuit with optimized signal input / output characteristics can be employed.

  Furthermore, both the I / O cell 100a with the countermeasure against hot-swapping and the I / O cell 100c without the countermeasure have a structure in which each component element has a deep N-type well, and the occurrence of latch-up due to noise is uniformly reduced. For example, noise resistance is improved.

  In addition, the I / O cells 100a with hot-swap countermeasures are grouped, and the same circuit elements in the adjacent I / O cells 100a are shared without deeply separating deep N-type wells. Compared with the configuration in which the N-type wells are independently separated, the interval between the I / O cells 100a can be reduced. Therefore, many I / O cells 100a can be formed in a limited space.

  In addition, the I / O cell 100a with the countermeasure against hot-swap and the I / O cell 100c without the countermeasure need to separate the deep N-type wells independently, so the I / O cell group 11A with the countermeasure against hot-swapping is necessary. , 11B and the I / O cell group 11C without countermeasures are provided, but the I / O cells 100a with hot-swap countermeasures are grouped. Furthermore, since the power supply voltage input cell that receives the supply of the power supply voltage is formed using this isolation region, layout waste is almost eliminated.

[Second Embodiment]
In the semiconductor device of the second embodiment, a control switch type I / O circuit is applied as an I / O circuit with hot-swap countermeasures.
FIG. 5 is a cross-sectional view of a chip showing the control switch type I / O cell, and FIG. 6 is a circuit diagram thereof.

  The control switch type I / O cell (I / O circuit) 100e includes output MOS transistors Q21 and Q22 that generate an output signal based on the signals IN_Pcontrol and IN_Ncontrol generated by the internal circuit, and the internal signal IN_Pcontrol at the time of hot plugging. Transmission transistors Q23 and Q24 to be cut off, an output PMOS control MOS transistor Q25 for controlling the state of the P-channel type output MOS transistor Q21 during hot-line insertion, and a source terminal of the control MOS transistor Q25 for hot-line insertion and removal A charge MOS transistor Q26 for supplying the potential of the input / output pad 20, a power supply MOS transistor Q29 for supplying the power supply voltage VDD to the wells and sources of the P-channel MOS transistors Q21, Q24 to Q27 during normal use, This power supply MOS transistor Q is used at the time of wire insertion / extraction. Control MOS transistor to control the state of 9 Q27, are those composed of Q28 and the like.

  FIG. 7 shows an explanatory diagram of the control switch type I / O circuit during normal operation. In the figure, a wiring to which the power supply voltage VDD is supplied is shown by a two-dot chain line, and a wiring having the same potential as the input / output pad 20 is shown by a dotted line.

  In normal use in which the power supply voltage VDD is supplied, as shown in the figure, the power supply MOS transistor Q29 is turned on by the control MOS transistors Q27 and Q28 provided in the I / O circuit 100e, and the P channel type The power supply voltage VDD is supplied to the well of the output MOS transistor Q21. As a result, the output MOS transistors Q21 and Q22 perform an output operation with normal characteristics.

  FIG. 8 shows an explanatory diagram when the control switch type I / O circuit is hot-plugged. In the figure, a dotted line indicates a wiring to which a high level voltage is applied from the input / output pad 20.

  On the other hand, at the time of hot-plugging when the supply of the power supply voltage VDD is cut off, if a high level (VDD) voltage is applied to the input / output pad 20 from the outside, the control MOS transistors Q27 and Q28 cause the power supply MOS transistor Q29. Is turned off, the current path connected from the well of the P-channel type output MOS transistor Q21 to the terminal of the power supply voltage VDD is cut off, so that no current flows from the input / output pad 20 to the terminal of the power supply voltage VDD. Latch-up does not occur even if hot-line insertion / extraction is performed.

  As shown in FIG. 5, the control switch type I / O circuit 100e of this embodiment further includes N-type wells N-Well of P-channel type MOS transistors Q21, Q24 to Q27, Q29 that are deeper than deep N. The structure is enclosed by a well T-Well. The double well structure improves noise resistance such as preventing latch-up caused by noise of an external signal.

  The control switch type I / O cell 100e adopting such a double well structure also has, for example, a byte (a is a natural number), like the floating well type I / O cell 100a of the first embodiment. ) And laid out in a line, and for the plurality of grouped I / O cells 100e, the deep N-type well T-Well is made common to other I / O cells that are not grouped. Is formed so as to separate the deep N-type well T-Well with a cell interval (reference FIGS. 1 and 2).

  As described above, even with the semiconductor device of this embodiment, the control switch type I / O cell 100e with a countermeasure against hot-swapping can exhibit its function, and the interval on the layout of each I / O cell is reduced. Thus, a large number of I / O cells can be formed in the same layout area.

The invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Nor.
For example, I / O cell groups that share a deep N-type well T-Well can be divided into signal specifications based on input / output signal specifications, as well as whether or not there are hot-swap measures as in the embodiment. However, it is also possible to separate the deep N-type well T-Wells as the same group and those having different signal specifications as different groups.

  In the above embodiment, as shown in FIG. 2, the deep N-type well T-Well is separated between different groups for the N-channel output MOS transistor Q2 and the MOS transistors Q11 and Q12 of the prebuffer 22 as well. However, the deep N-type well T-Well may be formed so as to be coupled between different groups.

  Further, in the embodiment, the best mode in which the power source cell for receiving the power source voltage from the outside is provided in the isolation region of FIG. 2 is shown, but the power source cell may be provided separately so that nothing is formed in the isolation region. .

  In the embodiment, the P-type is applied as the first conductivity type and the N-type is applied as the second conductivity type. However, when the power supply voltage and the signal level are reversed from those in the embodiment, the first conductivity type is applied. A similar configuration can be realized by applying N-type as the conductivity type and P-type as the second conductivity type.

  In the above description, the invention mainly made by the present inventor has been described for the LSI mounted on the module board of the mainframe, which is the field of use behind the invention, but the present invention is not limited thereto, for example, It can be widely used in various semiconductor devices such as ICs that are affected by hot-plugging in electronic devices having an IEEE (American Institute of Electrical and Electronics Engineers) 1394 interface.

1 is a layout diagram illustrating a semiconductor device according to an embodiment of the present invention. FIG. 2 is an enlarged view of a part of the I / O cell group in FIG. 1. FIG. 3 is a chip cross-sectional view showing an I / O cell not corresponding to a floating well in the I / O cell group of FIG. 2. FIG. 3 is a chip cross-sectional view showing an I / O cell having a floating well structure in the I / O cell group of FIG. 2. As an application example, a chip cross-sectional view of an I / O cell with a hot-swap control circuit is shown instead of an I / O cell having a floating well structure. It is a circuit diagram which shows an I / O circuit with a hot-wire insertion / extraction control circuit. FIG. 6 is a diagram for explaining the operation of the I / O circuit of FIG. 6 and showing a normal operation. FIG. 7 is a diagram for explaining the operation of the I / O circuit in FIG. It is chip | tip sectional drawing which shows an example of the conventional I / O circuit. It is chip | tip sectional drawing which shows an example of the I / O circuit of the conventional floating well structure.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Semiconductor device 11 I / O cell group 11A, 11B I / O cell group with hot-swap countermeasure 11C I / O cell group without hot-swap countermeasure 20 Input / output pad 20A Input / output pad for power input Q1 P channel Type output MOS transistor Q2 N-channel type output MOS transistor 22 Pre-buffer 100a I / O cell with hot-swap countermeasure 100c I / O cell without hot-swap countermeasure 100e Control switch type I / O cell
N-Well N-type well
P-Well P-type well
T-Well Deep N type well

Claims (5)

A second conductivity type well is formed in the first conductivity type semiconductor substrate, and the first conductivity type diffusion region serving as the drain of the output MOS transistor or the anode or cathode of the PN junction protection diode is formed in the second conductivity type well. A semiconductor device in which a plurality of input / output circuits are formed in which the diffusion region of the first conductivity type is connected to an external connection terminal for inputting / outputting an external signal,
The plurality of input / output circuits include
When no power supply voltage is supplied to the input / output circuit and a high potential voltage is applied to the external connection terminal, a current path from the external connection terminal to the power supply voltage terminal is formed through the diffusion region of the first conductivity type. An input / output circuit of the first form,
A second form in which no current path is formed from the external connection terminal to the power supply voltage terminal through the diffusion region of the first conductivity type when the power supply voltage is not supplied and a high potential voltage is applied to the external connection terminal I / O circuit and
A semiconductor device, wherein a plurality of input / output circuits of the second form are formed in a well of a common second conductivity type formed continuously. The second conductivity type well includes a first well in which impurities are diffused to a first depth of a semiconductor substrate, and an impurity diffused in the first well to a second depth shallower than the first depth. A second well,
2. The semiconductor device according to claim 1, wherein the first well is a common well of elements of the plurality of input / output circuits by being continuous.   3. The semiconductor device according to claim 1, wherein a plurality of the common second conductivity type wells are provided on one semiconductor substrate.   The input / output circuit of the second form is constituted by a floating well type element having the diffusion region of the first conductivity type as a terminal and no power supply wiring connected to the well of the second conductivity type. The semiconductor device according to claim 1, wherein:   The input / output circuit of the second form is turned on when the power supply voltage is supplied between the power supply voltage terminal and the well of the second conductivity type, and is turned off when the power supply voltage is not supplied. 4. The semiconductor device according to claim 1, further comprising a transistor.

Images