CN113140558A - Device structure for multi-port ESD protection - Google Patents

Device structure for multi-port ESD protection Download PDF

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Publication number
CN113140558A
CN113140558A CN202110467124.0A CN202110467124A CN113140558A CN 113140558 A CN113140558 A CN 113140558A CN 202110467124 A CN202110467124 A CN 202110467124A CN 113140558 A CN113140558 A CN 113140558A
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CN
China
Prior art keywords
region
well
pmos
esd protection
device structure
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Pending
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CN202110467124.0A
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Chinese (zh)
Inventor
邓樟鹏
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Priority to CN202110467124.0A priority Critical patent/CN113140558A/en
Publication of CN113140558A publication Critical patent/CN113140558A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
    • H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices

Abstract

The invention provides a device structure for multi-port ESD protection, which comprises a first PMOS and a second PMOS; the P trap is positioned between the first PMOS and the second PMOS; the first PMOS includes a first N-well; the first N trap is provided with a first N + region, a second N + region, a first P + region and a second P + region; the first N + region, the first P + region, the second N + region and the first N well are connected to a power voltage VDD 1; the second P + region is connected to the first IO terminal; the P well is provided with a third N + region, a third P + region and a fourth N + region; the third N + region, the third P + region and the fourth N + region are grounded together; the second PMOS includes a second N-well; a fifth N + region, a fourth P + region, a fifth P + region and a sixth N + region are arranged on the second N well; the fifth N + region, the fourth P + region, the sixth N + region and the second N well are commonly connected to a second power voltage VDD 2; the fifth P + region is connected to the second IO terminal. The invention can realize ESD protection among five ports, is convenient for circuit design, saves IO area and improves the whole ESD performance of the chip.

Description

Device structure for multi-port ESD protection
Technical Field
The invention relates to the technical field of semiconductors, in particular to a device structure for multi-port ESD protection.
Background
As shown in fig. 1, fig. 1 is a schematic diagram illustrating an ESD protection circuit in the prior art. In the ESD protection circuit, ESD protection devices are usually required to be respectively disposed between VDD and GND, between VDD and IO, and between IO and GND, so as to establish an ESD path between any two pins.
However, the conventional ESD protection circuit cannot realize ESD protection of a plurality of ports, and the circuit design and the IO area are large, so that the ESD performance cannot be integrally improved.
Disclosure of Invention
In view of the above drawbacks of the prior art, an object of the present invention is to provide a device structure for multi-port ESD protection, which is used to solve the problem that the ESD protection circuit in the prior art cannot realize ESD protection for more ports, and cannot improve the ESD performance as a whole due to larger circuit design and IO area.
To achieve the above and other related objects, the present invention provides a device structure for multi-port ESD protection, comprising at least: a first PMOS and a second PMOS; the P trap is positioned between the first PMOS and the second PMOS;
the first PMOS includes a first N-well; the first N trap is provided with a first N + region, a second N + region, a first P + region and a second P + region; the first N + region, the first P + region, the second N + region and the first N well are commonly connected to a power supply voltage VDD 1; the second P + region is connected to a first IO end;
a third N + region, a third P + region and a fourth N + region are arranged on the P well; the third N + region, the third P + region and the fourth N + region are grounded together;
the second PMOS includes a second N-well; a fifth N + region, a fourth P + region, a fifth P + region and a sixth N + region are arranged on the second N well; the fifth N + region, the fourth P + region, the sixth N + region and the second N well are commonly connected to a second power voltage VDD 2; the fifth P + region is connected to the second IO terminal.
Preferably, the first P + region and the second P + region on the first N well are located between the first N + region and the second N + region.
Preferably, the first P + region on the first N well is close to the first N + region; the second P + region on the first N well is close to the second N + region.
Preferably, the third P + region on the P-well is located between the third N + region and the fourth N + region.
Preferably, the third N + region on the P-well is adjacent to the second N + region on the first N-well.
Preferably, the fourth and fifth P + regions on the second N-well are located between the fifth and sixth N + regions.
Preferably, the fourth P + region on the second N well is close to the fifth N + region; the fifth P + region is adjacent to the sixth N + region.
Preferably, the fifth N + region on the second N-well is close to the fourth N + region on the P-well.
Preferably, the first and second N + regions are the sources of the first PMOS; the second P + region is a drain of the first PMOS.
As described above, the device structure for multi-port ESD protection of the present invention has the following beneficial effects: the invention is based on placing a P well between two traditional ESD PMOS, and placing two N + regions and a P + region in the P well. The drain terminals of the two ESD PMOS are respectively connected with two IO terminals, and the source terminal and the N-well terminal are respectively connected with the corresponding power supply voltage terminals. The structure only needs one structure, ESD protection among five ports can be realized, circuit design is facilitated, IO area is saved, and the whole ESD performance of a chip is improved.
Drawings
FIG. 1 is a schematic diagram of an ESD protection circuit according to the prior art;
FIG. 2 is a schematic diagram of a device structure for multi-port ESD protection according to the present invention;
fig. 3 shows a schematic diagram of a device structure for multi-port ESD protection in which multiple vias are formed.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 3. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
The invention provides a device structure for multi-port ESD protection, the structure at least comprises:
a first PMOS and a second PMOS; the P trap is positioned between the first PMOS and the second PMOS; the first PMOS includes a first N-well; the first N trap is provided with a first N + region, a second N + region, a first P + region and a second P + region; the first N + region, the first P + region, the second N + region and the first N well are commonly connected to a power supply voltage VDD 1; the second P + region is connected to a first IO end; a third N + region, a third P + region and a fourth N + region are arranged on the P well; the third N + region, the third P + region and the fourth N + region are grounded together; the second PMOS includes a second N-well; a fifth N + region, a fourth P + region, a fifth P + region and a sixth N + region are arranged on the second N well; the fifth N + region, the fourth P + region, the sixth N + region and the second N well are commonly connected to a second power voltage VDD 2; the fifth P + region is connected to the second IO terminal.
As shown in fig. 2, fig. 2 is a schematic diagram of a device structure for multi-port ESD protection according to the present invention, in which the first PMOS (01) includes the first N well (NW1), and the first N + region (N +1), the second N + region (N +2), and the first P + region (P +1), the second P + region (P +2) are disposed on the first N well (NW 1).
The first N + region (N +1), the first P + region (P +1), the second N + region (N +2), and the first N well (NW1) are commonly connected to a power supply voltage VDD1, and the second P + region (P +2) is connected to a first IO terminal (IO 1).
The second PMOS (02) comprises a second N-well (NW 2); a fifth N + region (N +5), a fourth P + region (P +4), a fifth P + region (P +5), and a sixth N + region (N +6) are disposed on the second N well (NW 2); the fifth N + region (N +5), the fourth P + region (P +4), the sixth N + region (N +6), and the second N-well (NW2) are commonly connected to a second power supply voltage VDD 2; the fifth P + region (P +5) is connected to the second IO terminal (IO 2).
A third N + region (N +3), a third P + region (P +3) and a fourth N + region (N +4) are arranged on the P Well (PW) 03; and the third N + region (N +3), the third P + region (P +3), and the fourth N + region (N +4) are commonly Grounded (GND).
Further, the first P + region (P +1) and the second P + region (P +2) on the first N well (NW1) of the present embodiment are located between the first N + region (N +1) and the second N + region (N + 2).
Further, the first P + region (P +1) on the first N well (NW1) of the present embodiment is close to the first N + region (N + 1); the second P + region (P +2) on the first N-well (NW1) is adjacent to the second N + region (N + 2).
Further, the third P + region (P +3) on the P-well (PW) of the present embodiment is located between the third N + region (N +3) and the fourth N + region (N + 4).
Further, the third N + region (N +3) on the P-well (PW) of the present embodiment is close to the second N + region (N +2) on the first N-well (NW 1).
Further, the fourth P + region (P +4) and the fifth P + region (P +5) on the second N well (NW2) of the present embodiment are located between the fifth N + region (N +5) and the sixth N + region (N + 6).
Further, the fourth P + region (P +4) on the second N well (NW2) of the present embodiment is close to the fifth N + region (N + 5); the fifth P + region (P +5) is adjacent to the sixth N + region (N + 6).
Further, the fifth N + region (N +5) on the second N well (NW2) of the present embodiment is close to the fourth N + region (N +4) on the P well.
Further, the first and second N + regions of this embodiment are the sources of the first PMOS; the second P + region is a drain of the first PMOS.
As shown in fig. 3, fig. 3 is a schematic diagram illustrating a structure of a device for multi-port ESD protection according to the present invention, in which a plurality of vias are formed.
A first passage: VDD1 to IO 1: PNP path formed by P +1/NW1/P + 2.
And a second passage: IO1 to GND: SCR paths formed by P +2/NW1/PW/N + 3.
A third passage: VDD1 to GND: SCR paths formed by P +1/NW1/PW/N + 3.
And a fourth passage: GND to VDD: a diode path formed by PW/NW 1.
A fifth passage: GND to IO 1: PW/NW1/P + 2.
A passage six: the ESD paths between VDD2, IO2, GND are similar. There is also a smooth ESD path through GND, VDD1 and VDD2 between the two different power domains.
In summary, the present invention is based on placing a P-well between two conventional ESD PMOS devices, where two N + regions and one P + region are placed. The drain terminals of the two ESD PMOS are respectively connected with two IO terminals, and the source terminal and the N-well terminal are respectively connected with the corresponding power supply voltage terminals. The structure only needs one structure, ESD protection among five ports can be realized, circuit design is facilitated, IO area is saved, and the whole ESD performance of a chip is improved. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (9)

1. A device structure for multi-port ESD protection, comprising at least:
a first PMOS and a second PMOS; the P trap is positioned between the first PMOS and the second PMOS;
the first PMOS includes a first N-well; the first N trap is provided with a first N + region, a second N + region, a first P + region and a second P + region; the first N + region, the first P + region, the second N + region and the first N well are commonly connected to a power supply voltage VDD 1; the second P + region is connected to a first IO end;
a third N + region, a third P + region and a fourth N + region are arranged on the P well; the third N + region, the third P + region and the fourth N + region are grounded together;
the second PMOS includes a second N-well; a fifth N + region, a fourth P + region, a fifth P + region and a sixth N + region are arranged on the second N well; the fifth N + region, the fourth P + region, the sixth N + region and the second N well are commonly connected to a second power voltage VDD 2; the fifth P + region is connected to the second IO terminal.
2. The device structure for multi-port ESD protection according to claim 1, characterized in that: the first and second P + regions on the first N well are located between the first and second N + regions.
3. The device structure for multi-port ESD protection according to claim 2, characterized in that: the first P + region on the first N well is close to the first N + region; the second P + region on the first N well is close to the second N + region.
4. The device structure for multi-port ESD protection according to claim 3, characterized in that: the third P + region on the P-well is located between the third N + region and the fourth N + region.
5. The device structure for multi-port ESD protection according to claim 4, characterized in that: the third N + region on the P-well is adjacent to the second N + region on the first N-well.
6. The device structure for multi-port ESD protection according to claim 5, characterized in that: the fourth and fifth P + regions on the second N well are located between the fifth N + region and the sixth N + region.
7. The device structure for multi-port ESD protection according to claim 6, characterized in that: the fourth P + region on the second N well is close to the fifth N + region; the fifth P + region is adjacent to the sixth N + region.
8. The device structure for multi-port ESD protection according to claim 7, characterized in that: the fifth N + region on the second N-well is adjacent to the fourth N + region on the P-well.
9. The device structure for multi-port ESD protection according to claim 1, characterized in that: the first N + region and the second N + region are source electrodes of the first PMOS; the second P + region is a drain of the first PMOS.
CN202110467124.0A 2021-04-28 2021-04-28 Device structure for multi-port ESD protection Pending CN113140558A (en)

Priority Applications (1)

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CN202110467124.0A CN113140558A (en) 2021-04-28 2021-04-28 Device structure for multi-port ESD protection

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Application Number Priority Date Filing Date Title
CN202110467124.0A CN113140558A (en) 2021-04-28 2021-04-28 Device structure for multi-port ESD protection

Publications (1)

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CN113140558A true CN113140558A (en) 2021-07-20

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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1132936A (en) * 1995-04-06 1996-10-09 财团法人工业技术研究院 Electrostatic discharge protection circuit
US5814845A (en) * 1995-01-10 1998-09-29 Carnegie Mellon University Four rail circuit architecture for ultra-low power and voltage CMOS circuit design
TW404040B (en) * 1998-06-08 2000-09-01 Taiwan Semiconductor Mfg The electrostatic discharge (ESD) protection design of the integrated circuit with multiple pairs of power lead
CN102810539A (en) * 2011-06-03 2012-12-05 美国亚德诺半导体公司 Metal oxide semiconductor output circuits and methods of forming the same
CN103985706A (en) * 2013-02-08 2014-08-13 创杰科技股份有限公司 Electrostatic discharge protection device and electronic device thereof
US9437591B1 (en) * 2015-09-09 2016-09-06 Vanguard International Semiconductor Corporation Cross-domain electrostatic discharge protection device
CN106876388A (en) * 2017-03-09 2017-06-20 东南大学 A kind of ghyristor circuit for prevention at radio-frequency port electrostatic discharge protective

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5814845A (en) * 1995-01-10 1998-09-29 Carnegie Mellon University Four rail circuit architecture for ultra-low power and voltage CMOS circuit design
CN1132936A (en) * 1995-04-06 1996-10-09 财团法人工业技术研究院 Electrostatic discharge protection circuit
TW404040B (en) * 1998-06-08 2000-09-01 Taiwan Semiconductor Mfg The electrostatic discharge (ESD) protection design of the integrated circuit with multiple pairs of power lead
CN102810539A (en) * 2011-06-03 2012-12-05 美国亚德诺半导体公司 Metal oxide semiconductor output circuits and methods of forming the same
CN103985706A (en) * 2013-02-08 2014-08-13 创杰科技股份有限公司 Electrostatic discharge protection device and electronic device thereof
US9437591B1 (en) * 2015-09-09 2016-09-06 Vanguard International Semiconductor Corporation Cross-domain electrostatic discharge protection device
CN106876388A (en) * 2017-03-09 2017-06-20 东南大学 A kind of ghyristor circuit for prevention at radio-frequency port electrostatic discharge protective

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