JP2005077507A - Gradation voltage generating circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a gradation voltage generating circuit, by which electric current consumption can be reduced and the size of an IC chip can be reduced at of circuit integration. <P>SOLUTION: A control circuit 5 sets variable resistors 12 and 22, in such a manner that the voltages corresponding to gradation voltages V<SB>out1</SB>and V<SB>out3</SB>are outputted from operational amplifiers 1 and 2, thereby putting specific sample-and-hold circuits SH 1 and SH 21 into an on state and putting another sample-and-hold circuits SH 2 and SH 22 into off state. After the lapse of a prescribed time, the control circuit sets variable resistors 12 and 22, in such a manner that voltages corresponding to gradation voltages V<SB>out2</SB>and V<SB>out4</SB>are outputted from the operational amplifiers 1 and 2, thereby putting the specific sample-and-hold circuits SH 1 and SH 21 into the on state and putting the another sample-and-hold circuits SH 2 and SH 22 into the off state. Such a configuration enables the two gradation voltages to be generated by using one operational amplifier. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a gradation voltage generating circuit that generates a driving voltage used for realizing gradation display in an image display element such as a liquid crystal display element.

  A display device such as a liquid crystal display device is required to perform multi-gradation display in order to realize color display. For example, in order to realize a color display of 260,000 colors, it is required to display 64 gradations for each of R, G, and B colors.

In an active matrix type liquid crystal display device using TFT, in order to realize multi-grayscale display (for example, 64-grayscale display) for each of R, G, and B colors, a grayscale voltage in a source driver that drives a source line A generation circuit is used (see, for example, Patent Document 1). As shown in FIG. 8, the conventional grayscale voltage generation circuit divides the voltage of the difference between the power supply voltage on the high potential side and the power supply voltage on the low potential side in order to realize 64 grayscale display. Resistors R _{1 to} R ₆₅ (R _{4 to} R ₆₂ are not shown) and 64 voltage follower-connected operational amplifiers 801 to 864 that introduce voltages obtained by voltage division by the resistors R _{1 to} R ₆₅ . (Operational amplifiers 803 to 862 are omitted) 64 types of gradation voltages (drive voltages used to realize gradation display) V _{1 to} V ₆₄ are generated.

JP 2003-157054 A (paragraph 0004, FIG. 1, FIG. 10)

  In the conventional gradation voltage generating circuit, operational amplifiers corresponding to the number of gradations are provided. Therefore, when the number of gradations is large, a large number of operational amplifiers are provided, and the current consumption of the drive circuit including the gradation voltage generation circuit increases. In addition, since a large number of operational amplifiers exist in the drive circuit, the IC chip size increases when the drive circuit is integrated into an IC.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a grayscale voltage generation circuit that can reduce current consumption and reduce the chip size of an IC when an IC is formed.

  A gradation voltage generating circuit according to the present invention includes an operational amplifier that outputs an output voltage obtained by amplifying an input voltage with a predetermined amplification degree, a gain changing circuit that changes the amplification degree of the operational amplifier, and an output voltage of the operational amplifier. A plurality of sample and hold circuits that input and output as gradation voltages, and a condition that only one sample and hold circuit at a time is in an ON state for inputting the output voltage of the operational amplifier, Set the output voltage of the operational amplifier to the ON state, and set the gain to the gain change circuit so that the operational amplifier outputs the output voltage corresponding to the gradation voltage to be output by the sample-and-hold circuit set to the ON state. And a control circuit for setting.

  For example, the control circuit is configured to repeat a process of turning on each of the plurality of sample and hold circuits only for a fixed time in a fixed cycle. In such a configuration, by shortening the period, the degree of decrease due to the discharge of the capacitor output voltage of the sample and hold circuit can be reduced, and the driving circuit including the gradation voltage generating circuit can be reduced. In the case of an IC, the system clock for driving control can be used as it is or just divided in the IC.

  The control circuit is configured to repeat the process of turning on each of the plurality of sample and hold circuits at a fixed period, and to change the length of the on state of each of the sample and hold circuits. Also good. In the case of such a configuration, the degree of decrease in the output voltage can be reduced by adjusting the sample-hold circuit to be on for a long time.

  A detection circuit that outputs a detection signal when detecting that the output voltage of a specific (one or more) sample hold circuit among the plurality of sample hold circuits has reached a lower limit voltage allowed as a gradation voltage is provided and controlled. The circuit may be configured to set a specific sample and hold circuit to an on state when a detection signal is output from the detection circuit when the specific sample and hold circuit is not set to an on state. In such a configuration, the frequency with which the sample hold circuit is switched between the on state and the off state can be reduced, and current consumption in the control circuit can be reduced.

  According to the present invention, since a plurality of types of gradation voltages can be created by one operational amplifier, the consumption current of the gradation voltage generation circuit can be reduced, and the gradation voltage generation circuit or the drive circuit including the gradation voltage generation circuit can be reduced. The IC chip size can be reduced when the IC is made into an IC.

(Embodiment 1) An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a configuration diagram showing a configuration example of a gradation voltage generating circuit according to the present invention. FIG. 1 also shows a conventional example for comparison. FIG. 1 shows a portion that generates four kinds of gradation voltages among other kinds (for example, 64 kinds) of gradation voltages. In the configuration of the present invention shown in FIG. 1, the resistors R ₁₂ and R ₃₄ are other resistors (not shown) connected in series between the high-potential-side power supply voltage V _H and the low-potential-side power supply voltage V _L. In addition, the difference voltage between the high-potential-side power supply voltage _VH and the low-potential-side power supply voltage _VL is divided. The high potential side of the voltage of the resistor _{R 12 V in12,} the high potential side of the voltage of the resistor _{R 34} (voltage on the low potential side of the resistor _{R 12)} and _{V in34.}

A voltage _Vin12 is introduced into a non-inverting input terminal of an operational amplifier (hereinafter referred to as an operational amplifier) 1. An output voltage is introduced to the inverting input terminal via the resistor 11. The inverting input terminal is connected to a variable resistor (an example of a gain changing circuit) 12 whose other is grounded. Therefore, the operational amplifier 1 has an amplification factor (gain) determined by the ratio between the resistance value of the resistor 11 and the resistance value of the variable resistor 12. The gain of the operational amplifier 1 is changed by changing the resistance value of the variable resistor 12.

The output of the operational amplifier 1 is connected to sample and hold circuits SH1 and SH2 each composed of an analog switch and a capacitor. The outputs of the sample hold circuits SH1 and SH2 are taken out as two gradation voltages V _out1 and V _out2 .

The operational amplifier 2 introduces the gradation voltage V _in34 and outputs a voltage with a gain determined by the ratio between the resistance value of the resistor 21 and the resistance value of the variable resistor 22. The output of the operational amplifier 2 is connected to sample and hold circuits SH21 and SH22 each comprising an analog switch and a capacitor. The outputs of the sample hold circuits SH21 and _SH22 are taken out as two gradation voltages V _out3 and V _out4 .

The sample hold circuits SH1, SH2, SH21, and SH22 charge the capacitor based on the input voltage when the inputs are connected. One end of the capacitor is grounded, and the voltage (output voltage) at the other end is taken out as gradation voltages V _out1 , V _out2 , V _out3 , V _out4 . In the state where the inputs of the sample hold circuits SH1, SH2, SH21, and SH22 are disconnected, the output voltage of the capacitor gradually decreases due to the discharge, but is allowed as the gradation voltages V _out1 , V _out2 , V _out3 , and V _out4. Before the voltage falls below the lower limit voltage, the control circuit 5 again connects the inputs of the sample hold circuits SH1, SH2, SH21, and SH22.

  Hereinafter, a state where the inputs of the sample hold circuits SH1, SH2, SH21, SH22 are connected is referred to as an on state, and a state where the inputs of the sample hold circuits SH1, SH2, SH21, SH22 are disconnected is referred to as an off state. As will be described below, the control circuit 5 does not turn on the sample hold circuits SH1 and SH2 at the same time, and does not turn on the sample hold circuits SH21 and SH22 at the same time. That is, a plurality of sample and hold circuits to which the output of one operational amplifier is input are not simultaneously turned on.

The control circuit 5 sets the variable resistors 12 and 22 so that voltages corresponding to V _out1 and V _out3 are output from the operational amplifiers 1 and 2 to turn on the sample and hold circuits SH1 and SH21, and the sample and hold circuit. SH2 and SH22 are turned off. When a predetermined time has elapsed, the variable resistors 12 and 22 are set so that voltages corresponding to V _out2 and V _out4 are output from the operational amplifiers 1 and 2, and the sample hold circuits SH 1 and SH 21 are turned off and the sample hold is performed. The circuits SH2 and SH22 are turned on.

With such a configuration, two gradation voltages can be created using one operational amplifier. FIG. 1 also shows a conventional example for comparison. In the conventional example, four operational amplifiers 51 to 54 are _provided to generate four kinds of gradation voltages V _out1 , V _out2 , V _out3 , and V _out4. On the other hand, according to the present invention, four types of gradation voltages V _out1 , V _out2 , V _out3 , and V _out4 can be generated by two of the half. FIG. 1 illustrates a portion for generating four types of gradation voltages V _out1 , V _out2 , V _out3 , and V _out4 , but a portion for generating other types of gradation voltages is also included in the control circuit. 5 is configured by a circuit in which an operational amplifier for switching the output of two voltages with a gain controlled by 5 and two sample-and-hold circuits are combined. Therefore, for example, when 64 types of gradation voltages are created, it is sufficient that 32 operational amplifiers exist.

Next, a control example of the control circuit 5 and a signal waveform example of the gradation voltage generation circuit will be described with reference to FIG. The configuration shown in FIG. 2A is the configuration of the portion shown in the upper side of FIG. 1, that is, the portion where the output of the operational amplifier 1 is used. As shown in FIG. 2B, the control circuit 5 turns on the sample hold circuit SH2 at the timing P. At this time, the control circuit 5 sets the variable resistor 12 so that a voltage corresponding to V _out2 is output from the operational amplifier 1. Then, when the first predetermined time elapses and the timing Q is reached, the sample hold circuit SH2 is turned off. The first predetermined time is a time longer than the time until the output voltage of the capacitor of the sample hold circuit SH2 reaches V _out2 from the value at the timing P (the capacitor is fully charged).

Further, when the second predetermined time has elapsed and the timing R is reached, the control circuit 5 turns on the sample hold circuit SH1. At this time, the control circuit 5 sets the variable resistor 12 so that a voltage corresponding to V _out1 is output from the operational amplifier 1. Note that the timing Q may be set when the variable resistor 12 is set so that a voltage corresponding to V _out1 is output from the operational amplifier 1.

At timing S, the control circuit 5 turns off the sample hold circuit SH1, turns on the sample hold circuit SH2, and turns on the variable resistor 12 so that a voltage corresponding to V _out2 is output from the operational amplifier 1. Set. Therefore, the setting state of the variable resistor 12 and the state of the sample hold circuits SH1 and SH2 are returned to the state at the timing P.

The time from the timing R to the timing S is longer than the time until the output voltage of the capacitor of the sample hold circuit SH1 reaches V _out1 from the value at the time of the timing R (the capacitor is fully charged).

  The control circuit 5 sets the time from the timing P to the timing S as one cycle so that the period in which the sample hold circuit SH1 is turned on and the period in which the sample hold circuit SH2 is turned on in one cycle do not overlap. Set sequentially. As a period during which the sample hold circuits SH1 and SH2 are turned off, the control circuit 5 allows the output voltage of the capacitors in the sample hold circuits SH1 and SH2 to be allowed when the sample hold circuits SH1 and SH2 are in the off state. Set a time that does not fall below the lower limit voltage.

FIG. 3A is a configuration diagram showing a more specific circuit configuration example of the gradation generation circuit shown in FIG. In the circuit configuration example shown in FIG. 3A, the control circuit 5 shown in FIG. 2 is realized by a control signal circuit 5a and inverting circuits 5b and 5c. The control signal circuit 5a outputs signals CT ₁ and CT ₂ for turning on the sample hold circuits SH1 and SH2. Inverting circuit 5b, 5c are signal _CT 1, CT ₂ logic inverts the signal _CT 1 ¯, and outputs the CT ₂ ¯. The variable resistor 12 shown in FIG. 2 has two resistors 12b and 12c, one end (for example, a source terminal) is grounded, and the other end (for example, a drain terminal) is connected to a connection point between the resistors 12b and 12c, and an input terminal ( For example, the signal CT ₁ to the gate terminal) is realized by the connected transistors 12a to the control signal circuit 5a as input.

Then, the sum of the resistance value and the value obtained by multiplying the gain determined by the ratio to the input voltage _{V in12} of the resistance value of the resistor 12b becomes the voltage _{V out1,} the resistance value and the resistance 12b of the resistor 11, the resistance value of 12c of the resistor 11 The resistance values of the resistors 11, 12 b, and 12 c are selected so that a value _determined by multiplying the input voltage V _in12 by a gain determined by the ratio to the voltage V _out2 becomes the voltage V _out2 . In this embodiment, as an analog switch used in the sample hold circuits SH1 and SH2, when a high level is input to one input terminal and a low level is input to the other input terminal, the analog switch is turned on. When the polarity of the input signal at the input terminal is opposite to that in the on state, one that is in the off state is used.

As shown by a signal waveform example of FIG. 3 (b), the control signal circuit 5a, the timing P, the signal CT ₁ to low level, the signal CT ₂ to a high level. Therefore, the transistor 12a is turned off, and the output voltage of the operational amplifier 1 becomes _Vout2 . Further, when the signal CT ₁ becomes low level and the signal CT ₁に な る becomes high level, the sample hold circuit SH1 is turned off. Then, when the signal CT ₂ becomes high level and the signal CT ₂ロ ー becomes low level, the sample hold circuit SH2 is turned on. Therefore, the capacitor in the sample and hold circuit SH2 starts charging, and the capacitor in the sample and hold circuit SH1 starts discharging and gradually decreases the output voltage. However, the control signal circuit 5a controls the output voltage of the capacitor of the sample hold circuit SH1 so that it does not fall below the lower limit voltage allowed as _Vout1 . That is, the control signal circuit 5a, while the output voltage of the capacitor of the sample-and-hold circuits SH1 does not fall below the lower limit voltage to be acceptable V _out1, the signal CT ₁ again to the high level (see the timing R).

When it is time Q, the control signal circuit 5a, the signal CT ₂ to a low level. Sample-and-hold circuit SH2 by signal CT ₂ becomes signal CT 2 _¯ becomes low level to the high level is turned off. Therefore, the capacitor in the sample hold circuit SH2 starts discharging and gradually decreases the output voltage. However, the control signal circuit 5a controls the output voltage of the capacitor of the sample hold circuit SH2 so that it does not fall below the lower limit voltage allowed as V _out2 . That is, the control signal circuit 5a, while the output voltage of the capacitor of the sample-and-hold circuit SH2 does not fall below the lower limit voltage to be acceptable V _out2, the signal CT ₂ again to the high level (see the timing S).

When it is time R, the control signal circuit 5a, the signal CT ₁ to the high level. Therefore, the transistor 12a is turned on, and the output voltage of the operational amplifier 1 becomes _Vout1 . Further, when the signal CT ₁ becomes high level and the signal CT ₁に な る becomes low level, the sample hold circuit SH1 is turned on, and the capacitor in the sample hold circuit SH1 starts charging. At the timing S, the control signal circuit 5a performs the same control as the control at the timing P.

Here, the time of one cycle _Tc from the timing P to the timing S and the on-state time of the sample hold circuits SH1 and SH2 are fixed times, for example. That is, the control circuit 5 repeatedly executes the control at the timings P to S shown in FIG. 3B every time one cycle _Tc elapses from the timing P. When the on-state times of the sample hold circuits SH1 and SH2 are made constant, if one cycle _Tc is shortened, that is, if the frequency is increased, the degree of decrease due to the discharge of the capacitor output voltages of the sample hold circuits SH1 and SH2 The output voltage of the sample and hold circuits SH1 and SH2 can be reliably prevented from falling below the lower limit voltage allowed as the gradation voltage. Further, when the drive circuit including the gradation voltage generation circuit is made into an IC, the system clock for drive control in the IC can be used as it is or simply by dividing. It should be noted that the length of one cycle _Tc can be shortened to the sum of the on-state times of the sample hold circuits SH1 and SH2.

(Embodiment 2) In Embodiment 1, in the gradation voltage generating circuit, the time of one cycle _Tc and the on-state time of the sample hold circuits SH1 and SH2 are fixed times, but the sample hold circuit SH1. , SH2 may be configured to be able to change the ON state time. FIG. 4A is a configuration diagram illustrating a configuration example of a gradation voltage generation circuit in which the on-state time of the sample hold circuits SH1 and SH2 can be changed, and FIG. 4B is a waveform illustrating a signal waveform example. FIG. However, FIG. 4B shows two types of signal waveform examples for only the sample and hold circuit SH1.

As shown in FIG. 4A, a PWM signal circuit 6 is connected to the control signal circuit 5a. The PWM signal circuit 6 supplies a signal indicating the on-state time of the sample hold circuit SH1 and a signal indicating the on-state time of the sample hold circuit SH2 to the control signal circuit 5a. Control signal circuit 5a, when it is time R, although to a signal CT ₁ to a high level, the state, the time corresponding to the signal indicating the time of the ON state of the sample-and-hold circuits SH1 received from the PWM signal circuit 6 Just continue. When the time corresponding to a signal indicating the on state of the sample-hold circuit SH1 time has elapsed, the signal CT ₁ to a low level.

  The PWM signal circuit 6 indicates that, for example, an on-state time of the sample hold circuit SH1 is set from an external circuit (for example, MPU) that outputs display data or the like to a display device including a gradation voltage generation circuit. A time setting signal is provided. The time setting signal includes information indicating the time to be set. In response to the time setting signal, the PWM signal circuit 6 creates a signal indicating the time when the sample hold circuit SH1 is on. For example, the external circuit creates a time setting signal based on the switch operation by the operator and outputs the time setting signal to the PWM signal circuit 6.

Therefore, in the present embodiment, the time of one cycle _Tc is constant in the gradation voltage generation circuit, but the on-state time of the sample hold circuit SH1 can be changed. For example, when a display device including a gradation voltage generation circuit is actually used or the like, when the output voltage of the capacitor in the off-state is drastically reduced, as shown in FIG. 4B (B). As described above, the degree of decrease in the output voltage of the capacitor can be reduced by adjusting the sample-and-hold circuit SH1 so as to extend the on-state time.

Here, has been described by focusing on the sample-hold circuit SH1, the control signal circuit 5a, when the signal CT ₂ to a high level, the sample-and-hold that has received the status from the PWM signal circuit 6 The circuit SH2 continues for a time corresponding to the signal indicating the ON state time. When the time corresponding to a signal indicating the on state of the sample-and-hold circuit SH2 time has elapsed, the signal CT ₂ to a low level. Further, as in the case of the first embodiment, the control signal circuit 5a is configured so that the signal CT ₁ does not overlap when the sample hold circuit SH1 is on and when the sample hold circuit SH2 is on. controlling the timing of the timing signal CT ₂ to the high level to the high level. Therefore, the on-state time of the sample-and-hold circuits SH1 and SH2 can be adjusted under the condition that the on-states of both sample-and-hold circuits do not overlap.

(Embodiment 3) In Embodiment 2, the time of one cycle _Tc is a fixed time in the gradation voltage generating circuit, and the on-state time of the sample hold circuits SH1 and SH2 can be changed. The sample hold circuits SH1 and SH2 may be configured to change the length of one cycle while keeping the on-state time constant. FIG. 5A is a configuration diagram showing a configuration example of a gradation voltage generating circuit configured so that the length of one cycle is changed, and FIG. 5B is a waveform diagram showing a signal waveform example. is there.

In the present embodiment, a comparator (comparator) 7 is provided in which the output voltage of the operational amplifier 1 is a reference voltage and the output voltage of the sample hold circuit SH1 is a comparison voltage. As a comparator 7, the voltage difference between the lower limit voltage and the gradation voltages V _out1 allowed for the gray scale voltage V _out1 (hereinafter, referred to as the allowable drop value.) Fraction using a hysteresis function comparator having a hysteresis characteristic of. The output of the comparator 7 is input to the control circuit 5. When the output of the comparator 7 becomes a significant level (on level) when the sample hold circuit SH1 is in the off state, the control circuit 5 converts the output voltage of the sample hold circuit SH1, that is, the output voltage of the capacitor, to the gradation voltage V _out1. Therefore, it can be determined that the allowable drop value has been reduced. Note that the comparator 7 is a detection circuit that outputs a detection signal when it detects that the output voltage of a specific sample-and-hold circuit (sample-and-hold circuit SH1 in this embodiment) has reached a lower limit voltage that is allowed as a gradation voltage. It is an example.

Therefore, when the output of the comparator 7 is turned on, the sample hold circuit SH1 is turned on, and the resistance value of the variable resistor 12 is changed so that the output voltage of the operational amplifier 1 becomes _Vout1 . Therefore, the capacitor in the sample hold circuit SH1 starts charging. This time is defined as timing R. When the output voltage of the sample and hold circuit SH1 reaches V _out1 after the sample and hold circuit SH1 is turned on, the output of the comparator 7 is turned off.

When a predetermined time elapses from the timing R and reaches the timing S, the control circuit 5 changes the resistance value of the variable resistor 12 so that the output voltage of the operational amplifier 1 becomes V _out2 . Further, the sample hold circuit SH1 is turned off and the sample hold circuit SH2 is turned on. Therefore, the capacitor in the sample hold circuit SH1 starts discharging, and the capacitor in the sample hold circuit SH2 starts charging. When the output voltage of the sample and hold circuit SH1 decreases by an allowable drop value with respect to _Vout1 , the output of the comparator 7 is turned on, and the sample and hold circuit SH1 is turned on again by the control of the control circuit 5. become.

  This embodiment is effective, for example, when applied to a display device such as a liquid crystal display device in which the output voltage of the sample and hold circuit decreases relatively slowly. When the output voltage of the sample and hold circuit decreases relatively slowly, the cycle (the period from timing R to timing U in FIG. 5B) can be lengthened. Therefore, the frequency with which the control circuit 5 switches the variable resistor 12 and the frequency with which the sample hold circuit is switched between the on state and the off state can be reduced. Since the frequency of switching is reduced, current consumption in the control circuit 5 can be reduced.

In this embodiment, the sample hold circuit SH2 is not controlled based on the output voltage. However, the sample hold circuit SH2 has a sufficient period during which the sample hold circuit SH1 is in the off state. If longer, the output voltage of the sample-and-hold circuit SH2 can be prevented from falling below the lower limit voltage allowed as the gradation voltage _Vout2 . Alternatively, by switching the output voltage of the sample hold circuit SH1 and the output voltage of the sample hold circuit SH2 and inputting them to the comparator 7, the timing for switching the sample hold circuit SH2 from the off state to the on state is also determined. can do.

  In the first, second, and third embodiments, there is a period in which both of the sample and hold circuits SH1 and SH2 are in the off state. However, when one of the sample and hold circuits is in the off state, the control circuit 5 always Control may be performed so that the hold circuit is turned on.

(Embodiment 4) In the first, second and third embodiments, the case where two kinds of gradation voltages V _out1 and V _out2 are created by one operational amplifier 1 is shown. The regulated voltages V _out1 , V _out2 , and V _out3 may be created. FIG. 6A is a configuration diagram showing a configuration example of a gradation voltage generation circuit having three sample hold circuits SH1, SH2, and SH3, and FIG. 6B is a waveform diagram showing an example of a signal waveform.

The resistor R ₁₂₃ divides the voltage of the difference between the high-potential side power supply voltage and the low-potential side power supply voltage together with other resistors (not shown). The high potential side of the voltage of the resistor _{R 123} and _{V in123.} The operational amplifier 1 is introduced with a voltage _Vin123 . As shown in FIG. 6B, the control circuit 5 turns on the sample hold circuit SH2 at the timing P. At this time, the control circuit 5 sets the variable resistor 12 so that a voltage corresponding to V _out2 is output from the operational amplifier 1. When the first predetermined time elapses, the sample hold circuit SH2 is turned off and the sample hold circuit SH3 is turned on. At this time, the control circuit 5 sets the variable resistor 12 so that a voltage corresponding to V _out3 is output from the operational amplifier 1. The first predetermined time is a time longer than the time until the output voltage of the capacitor of the sample hold circuit SH2 reaches V _out2 from the value at the timing P (the capacitor is fully charged).

Further, when the second predetermined time elapses, the control circuit 5 turns off the sample hold circuit SH3 and turns on the sample hold circuit SH1. At this time, the control circuit 5 sets the variable resistor 12 so that a voltage corresponding to V _out1 is output from the operational amplifier 1. The second predetermined time is a time longer than the time until the output voltage of the capacitor of the sample hold circuit SH3 reaches V _out3 (the capacitor is fully charged).

When the third predetermined time elapses, the control circuit 5 changes the sample hold circuit SH1 to be in an off state, the sample hold circuit SH2 to be in an on state, and a voltage corresponding to V _out2 is output from the operational amplifier 1. The resistor 12 is set. That is, the control state returns to the timing P. Note that the third predetermined time is longer than the time until the output voltage of the capacitor of the sample hold circuit SH1 reaches V _out1 (the capacitor is fully charged). Thereafter, the control circuit 5 repeatedly executes the above control on the variable resistor 12 and the sample hold circuits SH1, SH2, SH3.

  Further, when the sample and hold circuits SH1, SH2 and SH3 are in the OFF state, the sample and hold circuit so that the output voltage of the capacitor in the sample and hold circuits SH1, SH2 and SH3 does not fall below the allowable lower limit voltage. A period in which SH1, SH2, and SH3 are turned off is set.

In the present embodiment, three types of gradation voltages V _out1 , V _out2 , and V 3 are controlled by the operational amplifier 1 that controls the gain by the control circuit 5 and switches and outputs three voltages, and the three sample and hold circuits SH1, SH2, and SH3. _out3 can be created. Therefore, the number of operational amplifiers can be further reduced with respect to the required number of types of gradation voltages.

  Similarly to the case of the first embodiment, the time of one cycle from the timing P to the timing S and the on-state time of the sample hold circuits SH1, SH2, and SH3 may be fixed times. As in the case of the second embodiment, the time during which the sample hold circuits SH1, SH2, and SH3 are on may be changed within one cycle. Further, as in the case of the third embodiment, the timing for turning on the sample hold circuit SH1 next may be determined based on the value of the output voltage in the off state of the sample hold circuit SH1.

  FIG. 7A uses three sample-and-hold circuits SH1, SH2, and SH3, and determines the next timing to turn on the sample-and-hold circuit SH1 based on the value of the output voltage in the off-state of the sample-and-hold circuit SH1. It is a block diagram which shows the structural example of a gradation voltage generation circuit. FIG. 7B is a waveform diagram showing a signal waveform example of the gradation voltage generating circuit. The comparator 7 shown in FIG. 7A is a comparator with a hysteresis function having hysteresis characteristics corresponding to the allowable drop value, as in the case of the third embodiment.

As in the case of the third embodiment, when a predetermined time elapses after the sample hold circuit SH1 is turned on, the control circuit 5 turns the sample hold circuit SH1 off. Therefore, the capacitor in the sample hold circuit SH1 starts discharging. When the output voltage of the sample hold circuit SH1 decreases by an allowable drop value with respect to _Vout1 , the output of the comparator 7 is turned on, so that the control circuit 5 turns the sample hold circuit SH1 on again. To do. Control circuit 5, a sample-hold circuit SH1 is in the period is in the OFF state, while the sample-and-hold circuit SH2, SH3 sequentially on state, the variable resistor 12 so that the output voltage of the operational amplifier 1 becomes _{V out2, V out3} Change the resistance value.

As described above, even when the three sample hold circuits SH1, SH2, and SH3 are used, it is possible to realize control for determining one cycle by feeding back the output voltage of the sample hold circuit SH1. In this embodiment, the sample hold circuits SH2 and SH3 are not controlled based on the output voltage. However, the sample hold circuits SH2 and SH3 are in the on state during the period in which the sample hold circuit SH1 is in the off state. Taking a period of time long enough, it is possible to output voltage of the sample-and-hold circuit SH2,3 is so as not to fall below the lower limit voltage allowed as the gradation voltages _{V out2, V out3.}

  In each of the above embodiments, two or three types of gradation voltages are created using one operational amplifier, but other types of gradation voltages may be created using one operational amplifier.

  The present invention can be applied to a grayscale voltage generation circuit that is built in a drive circuit that supplies a drive signal to a display device such as a liquid crystal display device and generates a grayscale voltage used for grayscale display.

The block diagram which shows the structural example of the gradation voltage generation circuit by this invention. The block diagram which shows the structural example of the gradation voltage generation circuit which produces two types of gradation voltages with one operational amplifier. FIG. 2 is a configuration diagram and a signal waveform diagram showing a more specific circuit configuration of the grayscale generation circuit of the first embodiment. FIG. 3 is a configuration diagram and a signal waveform diagram illustrating a configuration of a grayscale generation circuit according to a second embodiment. FIG. 4 is a configuration diagram and a signal waveform diagram illustrating a configuration of a gradation generation circuit according to a third embodiment. FIG. 6 is a configuration diagram and a signal waveform diagram illustrating a configuration of a gradation generation circuit according to a fourth embodiment. FIG. 6 is a configuration diagram and a signal waveform diagram showing a specific example of Embodiment 4. The block diagram which shows the structure of the conventional gradation voltage generation circuit.

Explanation of symbols

1, 2 operational amplifier (op amp)
5 Control Circuit 5a Control Signal Circuit 5b, 5c Inverting Circuit 6 PWM Signal Circuit 7 Comparator
11, 21 Resistance 12 Variable resistance 12a Transistor 12b, 12c Resistance SH1, SH2, SH3 Sample hold circuit

Claims (4)

In a gradation voltage generating circuit for generating a plurality of kinds of gradation voltages used for realizing gradation display in an image display element,
An operational amplifier that outputs, as an output voltage, a voltage obtained by amplifying the input voltage at a predetermined amplification degree;
A gain changing circuit for changing the amplification degree of the operational amplifier;
A plurality of sample-and-hold circuits that input the output voltage of the operational amplifier and output it as gradation voltages;
Each of the plurality of sample and hold circuits is set to an on state for inputting the output voltage of the operational amplifier under the condition that only one sample and hold circuit is turned on to input the output voltage of the operational amplifier at a time. A control circuit that causes the gain changing circuit to set an amplification degree so that the operational amplifier outputs an output voltage corresponding to a gradation voltage to be output by the sample-and-hold circuit that is set to an on state. A gradation voltage generation circuit. The gradation voltage generation circuit according to claim 1, wherein the control circuit repeats a process of turning on each of the plurality of sample and hold circuits only for a fixed time at a fixed period. 2. The control circuit according to claim 1, wherein the control circuit repeats the process of turning on each of the plurality of sample and hold circuits at a fixed period, and can change the length of time of the on state of each of the sample and hold circuits. Regulated voltage generation circuit. A detection circuit that outputs a detection signal when detecting that the output voltage of a specific sample-hold circuit among the plurality of sample-hold circuits has reached a lower limit voltage allowed as a gradation voltage,
The control circuit sets the specific sample and hold circuit to an on state when a detection signal is output from the detection circuit when the specific sample and hold circuit is not set to an on state. Regulated voltage generation circuit.

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