JP2005072800A5 - - Google Patents
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- JP2005072800A5 JP2005072800A5 JP2003297805A JP2003297805A JP2005072800A5 JP 2005072800 A5 JP2005072800 A5 JP 2005072800A5 JP 2003297805 A JP2003297805 A JP 2003297805A JP 2003297805 A JP2003297805 A JP 2003297805A JP 2005072800 A5 JP2005072800 A5 JP 2005072800A5
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- pixel data
- reference image
- register
- block matching
- difference
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Claims (4)
入力された参照画像の画素データを保持するレジスタと、このレジスタに保持された参照画像の画素データと入力された現画像の画素データとの差分絶対値和演算を行う第１の演算部を有するプロセッシング・エレメントをＮ（１＜Ｎ，Ｎは自然数）個備えるとともに、これらＮ個のプロセッシング・エレメントのレジスタを接続して前記参照画像の画素データを順次シフトするシフトレジスタを構成する第１の差分絶対値和演算手段と、
入力された参照画像の画素データを保持するレジスタと、このレジスタに保持された参照画像の画素データと入力された現画像の画素データとの差分絶対値和演算を行う第２の演算部を有するプロセッシング・エレメントをＮ−１個備えるとともに、これらＮ−１個のプロセッシング・エレメントのレジスタを接続して前記参照画像の画素データを順次シフトするシフトレジスタを構成する第２の差分絶対値和演算手段と、
前記第１の差分絶対値和演算手段内のＮ個のプロセッシング・エレメントが構成するシフトレジスタの初段および第２の差分絶対値和演算手段内のＮ−１個のプロセッシング・エレメントが構成するシフトレジスタの初段に参照画像の画素データを入力するメモリインタフェース部と、
を備え、
前記メモリインタフェース部は、
参照画像の水平方向１ライン分のブロックマッチング処理が開始されるたびに、前記第２の差分絶対値和演算手段への出力を前記第１の差分絶対和演算手段への出力より１サイクル遅延させることを特徴とするブロックマッチング演算装置。 In a block matching arithmetic processing apparatus that is applied to a video compression / decompression system and performs block matching between a current image and a reference image to calculate a sum of absolute differences,
A register that holds the pixel data of the input reference image; and a first calculation unit that performs a sum of absolute differences between the pixel data of the reference image held in the register and the pixel data of the input current image A first difference constituting N (1 <N, N is a natural number) processing elements and a shift register for sequentially shifting the pixel data of the reference image by connecting the registers of these N processing elements. Absolute value sum calculation means;
A register that holds the pixel data of the input reference image; and a second calculation unit that performs a sum of absolute differences between the pixel data of the reference image held in the register and the pixel data of the input current image Second difference absolute value sum calculating means comprising N-1 processing elements and constituting a shift register for sequentially shifting pixel data of the reference image by connecting the registers of these N-1 processing elements. When,
The first stage of the shift register formed by N processing elements in the first difference absolute value sum operation means and the shift register formed by N-1 processing elements in the second difference absolute value sum operation means A memory interface unit for inputting pixel data of a reference image to the first stage of
With
The memory interface unit
Each time the block matching process for one horizontal line of the reference image is started, the output to the second difference absolute value sum calculating means is delayed by one cycle from the output to the first difference absolute sum calculating means. A block matching arithmetic device characterized by that.
をさらに備え、
前記メモリインタフェース部は、
前記メモリから読み出した参照画像の画素データを保持する複数のレジスタと、
前記レジスタに保持されている参照画像の画素データを前記第１および第２の差分絶対値和演算手段に出力するセレクタと、
を備えることを特徴とする請求項１に記載のブロックマッチング演算装置。 A memory for storing pixel data of the reference image;
Further comprising
The memory interface unit
A plurality of registers for holding pixel data of reference images read from the memory;
A selector that outputs pixel data of a reference image held in the register to the first and second absolute difference sum calculating means;
The block matching arithmetic device according to claim 1, further comprising:
をさらに備え、
前記メモリインタフェース部は、
前記メモリから読み出した参照画像の画素データを４つ以上保持するレジスタと、
前記レジスタに保持されている参照画像の画素データを前記第１および第２の差分絶対値和演算手段に出力するセレクタと、
を備えることを特徴とする請求項１に記載のブロックマッチング演算装置。 A memory for storing pixel data of the reference image;
Further comprising
The memory interface unit
A register that holds four or more pixel data of a reference image read from the memory;
A selector that outputs pixel data of a reference image held in the register to the first and second absolute difference sum calculating means;
The block matching arithmetic device according to claim 1, further comprising:
をさらに備え、
前記メモリインタフェース部は、
前記第１および第２の差分絶対値和演算手段に出力する参照画像の画素データを前記複数のメモリから同時に読み出すことを特徴とする請求項１に記載のブロックマッチング演算装置。 A plurality of memories for storing pixel data of the reference image;
Further comprising
The memory interface unit
2. The block matching calculation apparatus according to claim 1, wherein pixel data of a reference image output to the first and second difference absolute value sum calculation means is simultaneously read from the plurality of memories.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2003297805A JP4170173B2 (en) | 2003-08-21 | 2003-08-21 | Block matching arithmetic unit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2003297805A JP4170173B2 (en) | 2003-08-21 | 2003-08-21 | Block matching arithmetic unit |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2005072800A JP2005072800A (en) | 2005-03-17 |
| JP2005072800A5 true JP2005072800A5 (en) | 2006-09-28 |
| JP4170173B2 JP4170173B2 (en) | 2008-10-22 |
Family
ID=34403528
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2003297805A Expired - Fee Related JP4170173B2 (en) | 2003-08-21 | 2003-08-21 | Block matching arithmetic unit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP4170173B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8290044B2 (en) | 2006-05-10 | 2012-10-16 | Qualcomm Incorporation | Instruction for producing two independent sums of absolute differences |
| CN103079074B (en) * | 2013-01-17 | 2016-08-03 | 深圳市中瀛鑫科技股份有限公司 | Block matching method, method for estimating and module, device |
-
2003
- 2003-08-21 JP JP2003297805A patent/JP4170173B2/en not_active Expired - Fee Related
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