JP2005070339A - Electro-optical device, method of driving the electro-optical device, and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To correct lateral crosstalks using a relatively simple circuit configuration. <P>SOLUTION: A correction quantity calculating circuit 7 includes a weighting circuit 71, which converts gradation data D into (i) (i≥2) weighted codes according to a conversion rule, wherein the correspondence relation between gradation values prescribed by the gradation data D and values allocated to the (i) weighted codes fewer than the displayed gradations, and (i) counting circuits 73 which calculate correction quantities K1 to K5 to count the (i) weighted codes by pixel lines, corresponding to scanning lines. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an electro-optical device, a driving method of the electro-optical device, and an electronic apparatus, and more particularly to measures against lateral crosstalk by correcting a voltage pulse width.

  Conventionally, regarding a liquid crystal panel using pulse width modulation, which is one of pixel driving methods, a technique for reducing display unevenness (lateral crosstalk) generated in the extending direction (row direction) of a scanning line has been proposed. Yes. For example, in Patent Document 1, the number of gradation values included in gradation data for one pixel row is counted separately for each gradation value, and each pixel in this pixel row is counted based on these counting results. A technique for correcting the pulse width of the supplied voltage is disclosed. The effective voltage applied to the liquid crystal element varies due to capacitive coupling between the data line and the scanning line. Therefore, if the pulse width of the voltage is corrected in anticipation of fluctuations in the effective voltage depending on the display pattern for one pixel row, the fluctuations can be offset, and as a result, lateral crosstalk can be reduced. it can.

JP-A-8-160392

  In the above-described prior art, since the number of gradation values needs to be counted for each gradation value, it is necessary to provide circuit blocks including decoders, weighting circuits, logic circuits, and counters for the number of display gradations. For example, when 64 gradation display is performed using 6-bit gradation data, 64 circuit blocks are required. When 256 gradation display is performed using 8 bit gradation data, 256 circuits are required. A block is required. As a result, as the number of gradations is increased, the correction calculation processing becomes complicated and the circuit scale increases, resulting in inconveniences such as low cost and low power consumption.

  In the prior art, the number of gradation values for one pixel row is counted for each gradation value, and the correction amount as an output is specified by referring to the correction amount table using the count result of each gradation value as an input. doing. In this case, as the number of gradations increases, the description content of the correction amount table becomes enormous, and the parameter setting work considering the characteristics of the liquid crystal becomes complicated. As a result, inconveniences such as reduced compatibility with various models and increased design costs arise.

  Accordingly, an object of the present invention is to perform lateral crosstalk correction with a relatively simple circuit configuration.

  Another object of the present invention is to improve design flexibility by ensuring compatibility with multiple models regarding calculation of correction amounts.

  In order to solve such a problem, the first to third inventions have a plurality of pixels provided corresponding to the intersections of a plurality of scanning lines and a plurality of data lines, and supply voltage pulses to the pixels. An electro-optical device that sets the gradation of a pixel by setting the width to be variable is provided.

  An electro-optical device according to a first aspect of the invention includes a correction amount calculation circuit that calculates a correction amount based on gradation data that defines the gradation of a pixel, and a voltage pulse width supplied to the pixel based on the correction amount. A correction amount adding circuit for correction. This correction amount calculation circuit follows a conversion rule that defines the correspondence between the gradation value defined by the gradation data and the value assigned to i (i ≧ 2) weighting codes that are smaller than the number of display gradations. , A weighting circuit for converting gradation data into i weighting codes, and i counting circuits for calculating a correction amount by counting the values of i weighting codes for each pixel row corresponding to the scanning line. Including.

  Here, in the first invention, the conversion rule is assigned to one of i weighting codes after weighting gradation values, and to a case of assigning to two or more of i weighting codes. It is preferable to contain.

  In the first invention, the correction amount calculation circuit may further include a product coefficient setting circuit that outputs i operation results by performing a product-sum operation according to the values of i weighting codes. . In this case, it is preferable that the i counting circuits calculate i correction amounts by counting each of the i calculation results.

  In the first invention, the weighting circuit may output a carry signal generated by adding the weighting code for one pixel to each of the i weighting codes to the product coefficient setting circuit. In this case, the product coefficient setting circuit preferably performs a product-sum operation with i carry signals as inputs.

  In the first invention, the correction amount adding circuit calculates the number of correction amounts corresponding to the number of display gradations by interpolating i correction amounts, and sets the voltage pulse width based on the calculated correction amount. It may be corrected.

  In the first invention, it is preferable that the correction amount adding circuit interpolates the correction amounts by interpolating adjacent correction amounts among i correction amounts.

  The electro-optical device according to the second aspect of the invention includes a logic circuit that performs a product-sum operation, and performs a product-sum operation based on gradation data that defines the gradation of the pixel for each pixel row corresponding to the scanning line. By performing the correction, a correction amount calculation circuit that calculates a correction amount and a correction amount addition circuit that corrects the voltage pulse width supplied to the pixel based on the correction amount are provided.

  Furthermore, the electro-optical device according to the third aspect of the invention is provided with i (i ≧ 2) smaller than the number of display gradations based on gradation data defining the gradation of the pixel for each pixel row corresponding to the scanning line. ) And a correction amount calculation circuit for calculating the correction amount, and by interpolating i correction amounts, a number of correction amounts corresponding to the number of display gradations are calculated. And a correction amount adding circuit for correcting the voltage pulse width to be supplied. The correction amount adding circuit preferably interpolates correction amounts by interpolating adjacent correction amounts among i correction amounts.

  According to a fourth aspect of the invention, there is provided an electronic apparatus in which the electro-optical device according to any one of the first to third aspects described above is mounted.

  On the other hand, as the fifth to seventh inventions, a plurality of pixels provided corresponding to respective intersections of the plurality of scanning lines and the plurality of data lines are provided, and the voltage pulse width supplied to the pixels is variably set. Thus, a driving method of an electro-optical device that sets the gradation of a pixel is provided.

  A driving method according to a fifth aspect of the invention includes a first step of calculating a correction amount based on gradation data defining the gradation of the pixel, and correcting a voltage pulse width supplied to the pixel based on the correction amount. And a second step. The first step is according to a conversion rule that defines a correspondence relationship between a gradation value defined by gradation data and a value assigned to i weighting codes (i ≧ 2) smaller than the number of display gradations. A third step of converting gradation data into i weighting codes, and a fourth step of calculating a correction amount by counting the values of i weighting codes for each pixel row corresponding to the scanning line. Including.

  In the fifth invention, the conversion rule includes a case where the gradation value is weighted and assigned to one of i weighting codes and a case of assigning to two or more of i weighting codes. Is preferred.

  In the fifth invention, the first step may further include a fifth step of outputting i operation results by performing a product-sum operation based on the values of i weighting codes. . In this case, the fourth step is preferably a step of calculating i correction amounts by counting each of i calculation results.

  In the fifth invention, the third step further includes a sixth step of outputting a carry signal generated by adding the weighting code for one pixel row for each of the i weighting codes. Also good. In this case, the fifth step is preferably a step of performing a product-sum operation with i carry signals as inputs.

  In the fifth invention, the second step is based on the seventh step of calculating the number of correction amounts according to the number of display gradations by interpolating i correction amounts, and the calculated correction amounts. And an eighth step of correcting the voltage pulse width. Here, the eighth step may be a step of interpolating correction amounts by interpolation of correction amounts adjacent to each other among i correction amounts.

  A driving method according to a sixth aspect of the present invention is a first step of calculating a correction amount by performing a product-sum operation based on gradation data defining a gradation of a pixel for each pixel row corresponding to a scanning line. And a second step of correcting the voltage pulse width supplied to the pixel based on the correction amount.

  The drive method according to the seventh aspect of the present invention provides i (i ≧ 2) corrections that are smaller than the number of display gradations, based on gradation data that defines the gradation of the pixel for each pixel row corresponding to the scanning line. A voltage pulse to be supplied to the pixel based on the calculated correction amount by calculating the number of correction amounts corresponding to the number of display gradations by first step of calculating the amount and interpolation of i correction amounts. A second step of correcting the width.

  Here, in the seventh invention, it is preferable that the second step is a step of interpolating correction amounts by interpolation of correction amounts adjacent to each other among i correction amounts.

  According to the present invention, lateral crosstalk can be corrected with a relatively simple circuit configuration. In addition, regarding the calculation of the correction amount, it is possible to improve design flexibility by ensuring compatibility with various models.

  FIG. 1 is a block diagram of the electro-optical device according to the present embodiment. The display unit 1 is an active matrix panel that drives a liquid crystal element by a switching element. In the display unit 1, pixels 2 for m dots × n lines are arranged in a matrix (in a two-dimensional plane). The display unit 1 also includes n scanning lines Y1 to Yn each extending in the row direction (X direction) and m data lines X1 to Xm each extending in the column direction (Y direction). And are provided. The scanning lines Y1 to Yn and the data lines X1 to Xm intersect each other, and the pixels 2 are arranged corresponding to these intersections.

  FIG. 2 is an equivalent circuit diagram of the pixel 2. One pixel 2 has a TFD 20 and a liquid crystal capacitor 21 connected in series. The TFD 20 is a kind of two-terminal switching element and has a nonlinear current-voltage characteristic. That is, almost no current flows when the voltage (absolute value | V |) is near zero, but when the voltage exceeds the threshold voltage | Vth |, the current rapidly flows as the voltage increases. One end of the TFD 20 is connected to the scanning electrode 22 corresponding to the scanning line Y (Y indicates any one of Y1 to Yn). The liquid crystal capacitor 21 is provided between the signal electrode 23 corresponding to the data line X (X indicates any one of X1 to Xm) and the other end of the TFD 20, and between the pair of electrodes and these electrodes. And a liquid crystal layer sandwiched therebetween. When the scanning signal and the data signal are supplied to the pixel 2 at the voltage level, the liquid crystal capacitor 21 is charged / discharged on the assumption that the TFD 20 is turned on. Then, the transmittance (or reflectance) of the liquid crystal layer is set by the potential difference generated between the electrodes of the liquid crystal capacitor 21, and gradation display corresponding to this is performed. In the figure, the TFD 20 is provided on the scanning electrode 22 side, and the liquid crystal capacitor 21 is provided on the signal electrode 23 side. Further, instead of the TFD, for example, another two-terminal switching element such as an MIM element may be used.

  The timing signal generation circuit 5 generates various internal signals based on external signals such as a vertical synchronization signal Vs, a horizontal synchronization signal Hs, and a dot clock signal DCLK input from a host device (not shown). Examples of the generated internal signals include a polarity instruction signal POL, scanning line drive system signals DY and CLY, data line drive system signals LP, CLX and DX, and correction system signals RES and BCLK. The polarity instruction signal POL is a signal for instructing the voltage polarity when the liquid crystal is AC driven, and is output to both the scanning line driving circuit 3 and the data line driving circuit 4. Of the signals of the scanning line driving system, the start pulse DY is a signal that defines one vertical scanning period (1F), and rises in a pulse shape at the start of 1F. The clock signal CLY is a signal that defines a selection period of one scanning line Y, that is, one horizontal scanning period (1H), and has a period of 1H. Among the signals of the data line driving system, the latch pulse LP is a pulse signal output at the beginning of 1H, and rises in a pulse shape at the time of level transition of the clock signal CLY, that is, at the rise and fall. The latch pulse LP is output not only to the data line driving circuit 4 but also to the correction amount calculation circuit 7. The clock signal CLX is a dot clock signal for data writing to the pixel 2. The start signal DX defines the timing for starting to take in data for one pixel row. Further, among the correction system signals, the base clock BCLK defines the minimum step size of the gradation defining signal GCP, and the resolution of pulse width correction described later improves as the step size is set narrower. The reset signal RES defines 1H, and rises in a pulse shape at the beginning of 1H. The base clock BCLK and the reset signal RES are output to the correction amount adding circuit 8.

  The voltage generation circuit 6 generates six fixed voltages ± Vsig, ± Vhld, and ± Vsel. The positive / negative signal voltage ± Vsig is supplied to the data line driving circuit 4, and the positive / negative selection voltage ± Vsel and the positive / negative holding voltage ± Vhld (| Vhld | <| Vsel |) are supplied to the scanning line driving circuit 3. . The voltage polarity is determined with reference to the reference voltage Vss, and the higher voltage side is the positive electrode and the lower voltage side is the negative electrode.

  The scanning line driving circuit 3 is mainly composed of a shift register, an output circuit and the like, and outputs scanning signals to the scanning lines Y1 to Yn to select the scanning lines Y1 to Yn in order for every 1H. Go. By such line-sequential scanning, in 1F, pixel rows to which data is to be written are sequentially selected in a predetermined scanning direction (generally from the top to the bottom). Here, the voltage level of the scanning signal includes a positive / negative selection voltage ± Vsel and a positive / negative holding voltage ± Vhld, and these polarities are determined based on the polarity instruction signal POL. When the polarity instruction signal POL is at the L level (when positive polarity is instructed), the positive selection voltage + Vsel is set, and when it is at the H level (when negative polarity is indicated), the negative selection voltage -Vsel is set. When a selection voltage having one polarity (for example, + Vsel) is applied to the scanning line Y to be selected, a holding voltage (for example, + Vhld) having the same polarity as the previous selection voltage is applied immediately after the selection. Is done. The voltage polarity applied to the scanning lines Y1 to Yn is inverted every frame. Further, in order to reduce flicker or the like, reverse polarity voltages are applied to the odd-numbered scanning lines Y and the even-numbered scanning lines Y in the same frame.

  The data line driving circuit 4 writes data to the pixel row selected by the scanning line driving circuit 3. Specifically, simultaneous output of data for a pixel row to which data is to be written in 1H of this time and point-sequential latching of data relating to a pixel row to which data is to be written in 1H are performed in parallel.

  FIG. 3 is a block diagram of the data line driving circuit 4. The data line driving circuit 4 includes a shift register 41, a first latch circuit 42, a second latch circuit 43, and a pulse generation circuit 44. The shift register 41 transfers the one-shot pulse of the start signal DX output at the beginning of 1H according to the clock signal CLX, and sequentially sets the levels of the latch signals S1, S2, S3,. To do. The first latch circuit 42 sequentially latches the gradation data D serially supplied from the host device when the latch signals S1, S2, S3,. The second latch circuit 43 latches the gradation data D for m dots (one pixel row) stored in the first latch circuit 42 at the rising edge (next 1H) of the latch pulse LP, and these are latched. The signals are output simultaneously to the subsequent pulse generation circuit 44.

  The pulse generation circuit 44 generates a data signal having a voltage pulse width corresponding to the gradation data D that defines the gradation of the pixel 2 by pulse width modulation, and outputs the data signal to the corresponding data line X. There are positive and negative signal voltages ± Vsig as the voltage level of the data signal. Which is the “on voltage Von” (voltage for driving the liquid crystal) depends on the polarity of the selection voltage ± Vsel, and the selection voltage The reverse polarity is the on-voltage Von. That is, when the positive selection voltage + Vsel is applied, the negative signal voltage −Vsig becomes the on voltage Von, and the positive signal voltage + Vsig becomes the “off voltage Voff” (voltage that does not drive the liquid crystal). On the other hand, when the negative selection voltage -Vsel is applied, the positive signal voltage + Vsig becomes the on voltage Von, and the negative signal voltage -Vsig becomes the off voltage Voff. In the present embodiment, a single ON voltage Von is used, but a binary ON voltage or higher can be set.

  FIG. 4 is an explanatory diagram of pulse width modulation in the pulse generation circuit 44. In this embodiment, as an example, “right-justified driving”, that is, a normally white mode using a pulse width modulation method that sets an on voltage Von (an off voltage Voff in the first half) in the second half of a predetermined period (1H). A case where the liquid crystal to be driven is displayed in 64 gradations will be described. However, the present invention also applies to “left-justified driving”, that is, a pulse width modulation method in which an on-voltage Von is set in the first half of a predetermined period (an off-voltage Voff in the second half) or a liquid crystal driven in a normally black mode. Of course, the present invention can be applied, and the number of display gradations is not limited to this.

  The gradation defining signal GCP rises in the form of a pulse 62 times in 1H defined by the latch pulse LP except for the first and last of 1H. The number of rises is set according to the number of display gradations, and each rise timing defines the pulse width of the on voltage Von related to the halftone. Although details will be described later, since the horizontal crosstalk occurs depending on the display pattern for one pixel row, the rising timing of the gradation defining signal GCP is based on the gradation data D for one pixel row. Correction is performed for each pixel row.

  Each time the gradation defining signal GCP rises, the pulse generation circuit 44 counts down the number of times by the down counter provided therein. Specifically, the count value of the down counter is reset to the initial value 63 by the rising edge of the latch pulse LP that defines the beginning of 1H, and thereafter, every time the gradation defining signal GCP rises, the count value becomes 1 from the current count value. Will be decremented. The count value is compared with the gradation data D (latch value) for one pixel latched in the second latch circuit 43 as needed. When the count value is larger than the latch value, + Vsig is applied to the data line X, and when the count value is less than or equal to the latch value, −Vsig is applied to the data line X (when POL = L). Accordingly, when the latch value is k (k = 0 to 63), the data signal is from + Vsig (off voltage Voff) to −Vsig at a timing tk at which the count value indicating the number of rising times of the gradation defining signal GCP coincides with k. It falls to (ON voltage Von). The falling timing tk is uniquely specified by the gradation data D latched by the second latch circuit 43, and is variably set within a range of 1H.

  The display gradation of the pixel 2 depends on the time density (that is, the on-duty ratio) of the on-voltage Von occupying 1H. First, when the off voltage Voff is applied over the entire period of 1H (on duty ratio = 0), the liquid crystal voltage Vlcd is equal to the voltage Vw (= | Vsel−Vsig | − | Vth |) 2 is turned on, and charges are accumulated in the liquid crystal capacitor 21. However, when Vlcd = Vw, the threshold voltage driven by the liquid crystal layer is not exceeded, so that white display is performed. On the other hand, when the on-voltage Von is applied as part of 1H (on-duty ratio ≠ 0), more charge is accumulated in the liquid crystal capacitor 21 than during white display, and the liquid crystal voltage Vlcd exceeds the threshold voltage of the liquid crystal layer. . As a result, the liquid crystal layer is driven to display halftone (gray). As the on-duty ratio increases, the display approaches black.

  Next, processing contents in the correction amount calculation circuit 7 will be described. The correction amount calculation circuit 7 calculates correction amounts K1 to K5 for each pixel row on the basis of the gradation data D for one pixel row corresponding to one scanning line Y, and calculates these correction amount addition circuits in the subsequent stage. 8 is output. The reason why the correction amounts K1 to K5 are calculated for each pixel row is that the horizontal crosstalk occurs depending on the display pattern of the same pixel row, and the display patterns in the other display areas have little influence. .

  FIG. 5 is a block diagram of the correction amount calculation circuit 7. The correction amount calculation circuit 7 has five circuit blocks 7a to 7e provided by the number of correction amounts K1 to K5. These circuit blocks 7 a to 7 e have the same configuration, and each includes a weighting circuit 71, a product coefficient setting circuit 72, a counting circuit 73, and a correction amount register 74. For each of the circuit blocks 7a to 7e, the gradation data D is serially input to the weighting circuit 71, and the latch pulse LP is input to the weighting circuit 71, the counting circuit 73, and the correction amount register 74.

  The feature of the correction amount calculation circuit 7 is that, first, the correction amounts K1 to K5 are calculated by i (i ≧ 2) circuit blocks 7a to 7e which are smaller than the number of display gradations. In the present embodiment, the number of display gradations is 64, whereas the number of circuit blocks 7a to 7e is 5, so this condition is satisfied. Second, the gradation data D is converted into a weighting code according to a preset conversion rule. Basically, since the number of weighting codes corresponds to the number of circuit blocks 7a to 7e, five weighting codes are required in this embodiment. Third, from the viewpoint of reducing the circuit scale and ensuring design flexibility, the correction amounts K1 to K5 are calculated by a logical operation using a weighting code as an input, specifically, a product-sum operation. . In the following description, each system of the circuit blocks 7a to 7e may be specified as i = 1, 2, 3, 4, 5 in the order from top to bottom.

  FIG. 6 is a block configuration diagram of the weighting circuit 71. The weighting circuit 71 includes a code conversion circuit 71a, an adder circuit 71b, and a 3-bit latch circuit 71c that operates with an external system clock and whose latch contents are cleared by a latch pulse LP that defines 1H. . The code conversion circuit 71a converts the gradation data D into the weighting codes W1 to W5 according to a conversion rule that defines the correspondence between the gradation values defined by the gradation data D and the values assigned to the weighting codes W1 to W5. Convert. This conversion rule may be realized by a configuration of a logic circuit, or may be realized by a LUT (Look Up Table) process using a conversion table in which the conversion rule is described. The five code conversion circuits 71a in the circuit blocks 7a to 7e output five weighting codes W1 to W5 in parallel.

  FIG. 7 is a diagram illustrating an example of a conversion rule in the code conversion circuit 71a. This conversion rule shows the correspondence between the gradation data D and the weighting code Wi. As a premise, the number of weighting codes Wi (= 5) is set to be smaller than the number of display gradations (= 64). Please note that. Since the circuit blocks 7a to 7e and the weighting codes W1 to W5 are associated one-to-one, if the number of weighting codes Wi is reduced, the number of circuit blocks can be reduced and the circuit scale can be reduced. On the other hand, however, the lateral crosstalk correction accuracy is lowered. Therefore, it is important to appropriately set the number of weighting codes Wi in consideration of the balance between the two.

  Each of the gradation values 0 to 63 defined by the 6-bit gradation data D is weighted 0 to 7 and converted to a 3-bit weighting code Wi. W1 is a code on the lowest gradation side, and is a code on the high gradation side in the order of W2, W3,. Therefore, the lower the gradation value that is input, the more the output is weighted to the lower gradation side, and the higher the gradation value that is the input, the higher gradation side, the output is weighted to the high gradation side. It will be. Here, for conversion to the weighting code Wi, one gradation value is weighted and assigned to one weighting code Wi (for example, W1 = 7 in the case of gradation value 12), and one gradation There are cases where the values are weighted and assigned to two or more adjacent weighting codes Wi, Wi + 1,... (For example, W1 = 6, W2 = 1 for a gradation value of 13). The reason for providing the latter case is to improve the correction accuracy by ensuring the continuity of the weighting codes W1 to W5 accompanying the transition of the gradation value.

  The adder circuit 71b at the subsequent stage of the code conversion circuit 71a adds the weighting code Wi output from the code conversion circuit 71a to the 3-bit latch value α output from the latch circuit 71c, and latches the added value (α + Wi). It outputs to the circuit 71c. However, when the added value (α + Wi) is larger than 7 (111 in binary notation), 1 is output as the carry signal Cai (carry signal), and the value obtained by subtracting 8 from (α + Wi) is latched. It is output to the circuit 71c. The latch circuit 71c latches the value from the adder circuit 71b as a new latch value (α ← α + Wi). For example, regarding the circuit block 7a with i = 1, when the current latch value of the latch circuit 71c is 4 and the input gradation value is 15 (W1 = 5), 1 is output as the carry signal Ca1. The latch value of the latch circuit 71c is updated from 4 to 1.

  As described above, the weighting circuit 71 sequentially converts the gradation data D for one pixel row into the weighting code Wi and then adds the weighting code Wi over time. 1 is output as Cai. When the number of pixels included in one pixel row is m, the above-described code conversion process and addition process are repeated m times in 1H. In this way, five weighting codes W1 to W5 are output from the five weighting circuits 71 in the circuit blocks 7a to 7e.

The product coefficient setting circuit 72 in the subsequent stage of the weighting circuit 71 is composed of a logic circuit, and receives the five carry signals Ca1 to Ca5 as inputs and performs the arithmetic processing shown in the following equation to obtain five arithmetic results k1 to k5. Is output. Here, specific values of the product coefficients a11 to a55 are set in advance in consideration of the overall characteristics of the display unit 1 obtained through experiments and simulations.

  The values of the 25 coefficients al1 to a55 are preferably set and changed arbitrarily by an external device externally attached to the electro-optical device. Thereby, it is possible to optimize according to the characteristics of the display unit 1 only by changing the coefficients a11 to a55 without changing the circuit configuration itself of the product coefficient setting circuit 72. As a result, it becomes possible to deal with multiple models, so that design flexibility can be improved.

  FIG. 8 is a diagram for explaining the correspondence between carry signals Ca1 to Ca5 and calculation results k1 to k5 in the processing for one pixel included in a certain pixel row. As processing results for one pixel, there are ten combinations of carry signals Ca1 to Ca5 output from the five weighting circuits 71, and these can be classified into any of three patterns. That is, first, a pattern in which the carry signals Ca1 to Ca5 are all “0” (case 10), and second, a pattern in which only one carry signal Cai is “1” (cases 1, 3, 5). , 7, 9), and third, a pattern in which two adjacent carry signals Cai, Cai + 1 are both “1” (cases 2, 4, 6, 8). Therefore, in the processing for one pixel, the combinations of the outputs k1 to k5 of the product-sum operation using the carry signals Ca1 to Ca5 as inputs are also aggregated as a result.

  FIG. 9 is a block configuration diagram of the counting circuit 73 located at the subsequent stage of the product coefficient setting circuit 72. The counting circuit 73 includes a 12-bit adder circuit 73a and a 12-bit latch circuit 73b that operates with an external system clock and whose latch contents are cleared by a latch pulse LP that defines 1H. The adder circuit 73a adds the operation result ki output from the product coefficient setting circuit 72 to the 12-bit latch value Ki latched by the latch circuit 73b as needed, and outputs the count result (Ki + ki) to the latch circuit 73b. . The latch circuit 73b newly latches the value from the adder circuit 73a (Ki ← Ki + ki). As a result, the five counting results K1 to K5 are output while being updated as needed from the latch circuits 73b of the five circuit blocks 7a to 7e. As described above, the product-sum operation processing is performed by the product coefficient setting circuit 72 and the counting circuit 73.

  The correction amount register 74 at the subsequent stage of the counting circuit 73 is configured by a simple latch circuit, and operates with a latch pulse LP to capture and latch the counting result Ki output from the latch circuit 73b at the previous stage. The value latched in the correction amount register 74 is a final counting result after the counting for one pixel row is completed, and this value corresponds to the correction amount Ki. As a result, the correction amounts K1 to K5 are latched in the five correction amount registers 74 in the circuit blocks 7a to 7e.

  Note that the number of bits of the correction amount register 74 is not necessarily the same as the number of bits of the latch circuit 73b, and may be smaller than that in consideration of the correction accuracy. In this case, the upper bits of the latch circuit 73b are latched in the correction amount register 74. However, in this embodiment, the upper five bits of the final count result are latched in the correction amount register 74 as the correction amount Ki. Is done.

  As can be seen from the above description, the correction amount calculation circuit 7 fetches the correction amounts K1 to K5 relating to the pixel row selected at 1H this time into the correction amount register 74 provided therein, and then is selected at the next 1H. The calculation processing of the correction amounts K1 to K5 related to the pixel row is started. The output of the correction amount Ki latched in the correction amount register 74 is performed based on the count value CT1 from the selection counter 81 that constitutes a part of the correction amount addition circuit 8 described below.

  Next, processing contents in the correction amount adding circuit 8 will be described. The correction amount adding circuit 8 generates a gradation defining signal GCP based on the correction amounts K1 to K5 fetched into the correction amount register 74 and the base clock BCLK, and this is generated by a part of the data line driving circuit 4. This is output to a certain pulse generation circuit 44. In the present embodiment, the correction of the voltage pulse width supplied to the pixel 2 is realized by adjusting the gradation defining signal GCP that defines the pulse width by the correction amounts K1 to K5.

  FIG. 10 is a block diagram of the correction amount adding circuit 8. The correction amount adding circuit 8 includes a selection counter 81, a basic pulse width setting circuit 82, a pulse width correction circuit 83, a base clock counter 84, and a coincidence detection circuit 85. The selection counter 81 counts up the number of rises of the gradation defining signal GCP and outputs the current number of rises as the count value CT1. The count value CT1 is reset every 1H based on the instruction of the reset signal RES. The basic pulse width setting circuit 82 receives the count value CT1 of the selection counter 81 as an input, and selects one corresponding to the current count value CT1 from a set of basic pulse widths T (voltage pulse width) prepared in advance. Select one. The rising timing of one pulse in the gradation defining signal GCP is set by the interval (pulse width) from the immediately preceding pulse to the one pulse, and the basic pulse width T is the basis of this interval. The basic pulse width setting circuit 82 outputs one selected basic pulse width T (actually, the number of base clocks BCLK corresponding thereto).

  The pulse width correction circuit 83 individually sets a correction amount for each basic pulse width T (for each gradation value), corrects the basic pulse width T based on the correction amount, and sets a correction pulse width Tamd (actually , The number of base clocks BCLK corresponding to this) is output. The correction pulse width Tamd defines the actual pulse interval in the gradation defining signal GCP. The base clock counter 84 counts up the number of rises of the base clock BCLK, and outputs the current number of rises as a count value CT2. The count value CT2 is reset every 1H based on the instruction of the reset signal RES, and is reset every time the gradation defining signal GCP rises. The coincidence detection circuit 85 compares the correction pulse width Tamd and the count value CT2 as needed, and generates a one-shot pulse at a timing when the coincidence occurs. The gradation defining signal GCP is constituted by a time-series arrangement of the one-shot pulses generated in this way. Note that when the inversion occurs due to the correction, the interval between the corresponding gradation values is forcibly set to a predetermined interval (for example, the minimum interval) without performing correction.

  Here, the correction amount added to the basic pulse width T needs to be equal to the number of basic pulse widths T selected by the count value CT1, in other words, the number corresponding to the number of display gradations (corresponding to the halftone number). Become. However, in practice, there are only five correction amounts Ki latched in the correction amount register 74, and they exist only sparsely. Therefore, as shown in FIG. 11, the pulse width correction circuit 83 sets the correction amount for the necessary number by interpolating between the specific values 4a to 4e of the correction amount. The correction amount is positive, meaning that the pulse width of the ON voltage Von is increased. Therefore, in the case of right justification driving, a calculation for subtracting the correction amount from the basic pulse width T is performed.

  In the figure, the single correction amount 4e is used as it is for the gradation values 1 to 14. Similarly, the correction amount 4d for the gradation values 22 to 26, the correction amount 4c for the gradation values 34 to 38, the correction amount 4b for the gradation values 46 to 50, and the correction amount 4a for the gradation values 58 to 62. Are used respectively. On the other hand, for the gradation values 15 to 21, a total value of a prorated value obtained by apportioning the correction amount 4d by an appropriate apportioning rate and an apportioning value obtained by apportioning the correction amount 4e by an appropriate apportioning rate is used. This distribution ratio is changed according to the gradation value. For gradation values 15 and 16, the distribution ratio of the correction amount 4e is 3/4 and the distribution ratio of the correction amount 4d is 1/4. Further, both of the gradation values 17 to 19 are 2/4, and the gradation values 20 and 21 are 1/4 for the former and 3/4 for the latter. That is, the lower the gradation, the larger the proportion of the correction amount 4e and the smaller the proportion of the correction amount 4d. Conversely, the higher the gradation, the larger the proportion of the correction amount 4d and the proportion of the correction amount 4e. Set the rate small. Similarly, for the gradation values 27 to 33, the total value obtained by dividing the correction amounts 4c and 4d, and for the gradation values 39 to 45, the total value and the gradation value obtained by dividing the correction amounts 4b and 4c. For 51 to 57, the total values of the values obtained by apportioning the correction amounts 4a and 4b are used. In this way, the necessary correction amounts are set by interpolation of the correction amounts K1 to K5 by interpolation using two correction amounts Ki and Ki + 1 adjacent to each other. The interpolation of the correction amounts K1 to K5 may be performed using three or more correction amounts adjacent to each other.

  The apportioned value can be generated with a relatively simple circuit configuration by shifting the bits of the correction amount latched in the correction amount register 74. For example, when the correction amount latched is 4a (5 bits), if this is shifted to the lower side by 1 bit and the upper 4 bits are extracted, and 0 (1 bit) is added to the upper side, the apportioned value 2a (5 bits) can be generated. Further, if the upper 3 bits are extracted by shifting 4a to the lower side of 2 bits and 00 (2 bits) is added to the upper side, the prorated value a (5 bits) can be generated. Further, the prorated value 3a can be generated by adding two prorated values a and 2a obtained by the above method.

Next, a specific operation of the correction amount adding circuit 8 will be described by taking the following case as an example and referring to the timing chart shown in FIG. For convenience of explanation, it should be noted that the relationship between the gradation value and the correction amount in this case is different from that shown in FIG.
(Case)
CT1 0 1 2 3 4 5 ...
Correction amount 4a 4a 3a + b 2a + 2b a + 3b 4b...

  First, at the beginning of 1H indicated by the reset signal RES, both the count value CT1 of the selection counter 81 and the count value CT2 of the base clock counter 84 are reset to zero. When the count value CT1 is 0, the first basic pulse width T1 is selected. Since the correction amount at CT1 = 0 is 4a, (T1-4a) is the correction pulse width Tamd. This correction pulse width (T1-4a) defines the interval from the beginning of 1H to the next pulse (gradation value 62) in the gradation defining signal GCP. The count value CT2 is incremented by 1 every time the base clock BCLK rises. Then, when the count value CT2 reaches the correction pulse width (T1-4a), the first pulse rises as the gradation defining signal GCP. Since the first pulse is generated ahead of the basic pulse width T1 by the correction amount 4a, the actual display gradation of the pixel 2 on which the gradation value 62 is to be displayed is also corrected by this correction amount. As the first pulse rises, the count value CT1 is counted up from 0 to 1, and the count value CT2 is reset to 0.

  When the count value CT1 is 1, the second basic pulse width T2 is selected. Further, since the correction amount at CT1 = 1 is 4a, the basic pulse width T2 becomes the correction pulse width Tamd as it is. This correction pulse width T2 defines the interval from the first pulse to the next pulse (gradation value 61) in the gradation defining signal GCP. The reason for setting the calculation amount to 0 is that the calculation amount 4a at CT1 = 0 is inherited as it is because the next pulse correction pulse width Tamd is set based on the first pulse in the gradation defining signal GCP. It is. Then, when the count value CT2 reaches the correction pulse width T2, the second pulse rises as the gradation defining signal GCP. Since the second pulse is generated ahead of time (T1 + T2) by the correction amount 4a, the actual display gradation of the pixel 2 on which the gradation value 61 is to be displayed is also corrected by this correction amount. As the second pulse rises, the count value CT1 is counted up from 1 to 2, and the count value CT2 is reset to 0 again.

  When the count value CT1 is 2, the third basic pulse width T3 is selected. Since the correction amount at CT1 = 2 is (3a + b), (T3− (b−a)) is the correction pulse width Tamd in consideration of the already corrected 4a. Then, when the count value CT2 reaches the correction pulse width (T3− (b−a)), the third pulse rises as the gradation defining signal GCP. Since the third pulse is generated ahead of time (T1 + T2 + T3) by the correction amount (3a + b), the actual display gradation of the pixel 2 that should display the gradation value 60 is also corrected by this correction amount. . With the rising edge of the third pulse, the count value CT1 is counted up from 2 to 3, and the count value CT2 is reset to 0 again.

  The same applies to the following, and when CT1 = 3 (gradation value 59), correction is made by (2a + 2b) by applying the calculation amount (ba) to the basic pulse width T4, and CT1 = 4 (gradation value 58). ), A calculation amount (ba) is applied to the basic pulse width T5 to correct for (a + 3b). When CT = 6 (gradation value 57), the calculation amount (ba) is applied to the basic pulse width T6. As a result, correction for 4b is performed. Thereby, each gradation value is corrected while interpolating between 4a and 4b.

  The correction process as described above is repeated until CT1 = 61 (gradation value 1) is reached, and correction for all halftones is performed.

  Thus, in the present embodiment, the gradation data D is converted into i (i ≧ 2) weighting codes Wi smaller than the number of display gradations, and i circuit blocks 7a to 7e are used. A correction amount Ki corresponding to each weighting code Wi is calculated. Therefore, the circuit scale can be reduced as compared with the prior art that requires the number of circuit blocks corresponding to the number of display gradations, and lateral crosstalk can be corrected with a relatively simple configuration.

  Further, in the present embodiment, the correction amount Ki is calculated by performing the product-sum operation based on the gradation data D by the product coefficient setting circuit 72 configured by a logic circuit that performs the product-sum operation. Therefore, a conversion table becomes unnecessary, the circuit scale can be reduced, and design flexibility can be improved. In the present embodiment, the product-sum operation of the weighting code Wi obtained by converting the gradation data D is performed. From this point of view, the present invention provides gradation data without conversion of the weighting code Wi. The present invention can also be applied to a product-sum operation using D itself as an input.

  Further, in the present embodiment, the number of correction amounts corresponding to the number of display gradations is calculated by interpolation of i correction amounts Wi, and the voltage pulse width is corrected based on the calculated correction amount. Therefore, it is possible to ensure the accuracy of the correction degree while suppressing an increase in the scale of the circuit that calculates the correction amount Ki.

  Note that the electro-optical device according to the present embodiment can be mounted on various electronic devices including, for example, a television, a projector, a mobile phone, a mobile terminal, a mobile computer, a personal computer, and the like. When the above-described electro-optical device is mounted on these electronic devices, the commercial value of the electronic devices can be further increased, and the product appeal of electronic devices in the market can be improved.

Block diagram of the electro-optical device according to the present embodiment Pixel equivalent circuit diagram Block diagram of data line drive circuit Explanatory drawing of pulse width modulation in pulse generation circuit Block diagram of correction amount calculation circuit Block diagram of weighting circuit The figure which shows an example of the conversion rule in a code conversion circuit Explanatory drawing of the correspondence between the carry signal and the calculation result in the processing of one pixel Block diagram of counting circuit Block diagram of correction amount addition circuit Diagram showing correspondence between gradation value, correction amount and calculation amount Timing chart of correction amount addition circuit

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Display part 2 Pixel 3 Scan line drive circuit 4 Data line drive circuit 5 Timing signal generation circuit 6 Voltage generation circuit 7 Correction amount calculation circuit 8 Correction amount addition circuit 41 Shift register 42 First latch circuit 43 Second latch circuit 44 Pulse generation circuit 71 Weighting circuit 72 Product coefficient setting circuit 73 Counting circuit 74 Correction amount register 81 Selection counter 82 Basic pulse width setting circuit 83 Pulse width correction circuit 84 Base clock counter 85 Match detection circuit

Claims (19)

It has a plurality of pixels provided corresponding to each intersection of a plurality of scanning lines and a plurality of data lines, and the gradation of the pixels is set by variably setting the voltage pulse width supplied to the pixels In the electro-optical device
A correction amount calculation circuit for calculating a correction amount based on gradation data defining the gradation of the pixel;
A correction amount addition circuit for correcting the voltage pulse width supplied to the pixel based on the correction amount;
The correction amount calculation circuit includes:
The gradation data is converted according to a conversion rule that defines a correspondence relationship between gradation values defined by the gradation data and values assigned to i (i ≧ 2) weighting codes that are smaller than the number of display gradations. A weighting circuit for converting into the i weighting codes;
An electro-optical device comprising: i counting circuits that calculate the correction amount by counting the value of the i weighting codes for each pixel row corresponding to the scanning line.   The conversion rule includes a case in which the gradation value is weighted and assigned to one of the i weighting codes and a case in which the gradation value is assigned to two or more of the i weighting codes. The electro-optical device according to claim 1. The correction amount calculation circuit further includes a product coefficient setting circuit that outputs i operation results by performing a product-sum operation according to the values of the i weighting codes.
3. The electro-optical device according to claim 1, wherein the i counting circuits calculate i correction amounts by counting each of the i calculation results. The weighting circuit outputs a carry signal generated by adding the weighting code for one pixel to each of the i weighting codes to the product coefficient setting circuit,
The electro-optical device according to claim 3, wherein the product coefficient setting circuit performs a product-sum operation with i carry signals as inputs.   The correction amount adding circuit calculates the number of correction amounts corresponding to the number of display gradations by interpolating the i correction amounts, and corrects the voltage pulse width based on the calculated correction amount. The electro-optical device according to claim 3, wherein the electro-optical device is provided.   6. The electro-optical device according to claim 5, wherein the correction amount adding circuit interpolates the correction amount by interpolation of the correction amounts adjacent to each other among the i correction amounts. It has a plurality of pixels provided corresponding to each intersection of a plurality of scanning lines and a plurality of data lines, and the gradation of the pixels is set by variably setting the voltage pulse width supplied to the pixels In the electro-optical device
A correction amount that includes a logic circuit that performs a product-sum operation, and calculates a correction amount by performing a product-sum operation based on gradation data that defines the gradation of the pixel for each pixel row corresponding to the scanning line A calculation circuit;
An electro-optical device comprising: a correction amount adding circuit that corrects the voltage pulse width supplied to the pixel based on the correction amount. It has a plurality of pixels provided corresponding to each intersection of a plurality of scanning lines and a plurality of data lines, and the gradation of the pixels is set by variably setting the voltage pulse width supplied to the pixels In the electro-optical device
A correction amount calculation circuit that calculates i correction amounts (i ≧ 2) smaller than the number of display gradations, for each pixel row corresponding to the scanning line, based on gradation data defining the gradation of the pixel. When,
A correction amount for calculating the number of correction amounts corresponding to the number of display gradations by interpolation of the i correction amounts, and correcting the voltage pulse width supplied to the pixel based on the calculated correction amount An electro-optical device having an additional circuit.   9. The electro-optical device according to claim 8, wherein the correction amount adding circuit performs interpolation of the correction amount by interpolation of the correction amounts adjacent to each other among the i correction amounts.   An electronic apparatus comprising the electro-optical device according to claim 1 mounted thereon. It has a plurality of pixels provided corresponding to each intersection of a plurality of scanning lines and a plurality of data lines, and the gradation of the pixels is set by variably setting the voltage pulse width supplied to the pixels In the driving method of the electro-optical device,
A first step of calculating a correction amount based on gradation data defining a gradation of the pixel;
A second step of correcting the voltage pulse width supplied to the pixel based on the correction amount;
The first step includes
The gradation data is converted according to a conversion rule that defines a correspondence relationship between gradation values defined by the gradation data and values assigned to i (i ≧ 2) weighting codes that are smaller than the number of display gradations. A third step of converting into the i weighting codes;
And a fourth step of calculating the correction amount by counting the value of the i weighting codes for each pixel row corresponding to the scanning line.   The conversion rule includes a case in which the gradation value is weighted and assigned to one of the i weighting codes and a case in which the gradation value is assigned to two or more of the i weighting codes. The driving method of the electro-optical device according to claim 11. The first step further includes a fifth step of outputting i operation results by performing a product-sum operation based on the values of the i weighting codes,
13. The electro-optical device according to claim 11, wherein the fourth step is a step of calculating i correction amounts by counting each of the i calculation results. Driving method. The third step further includes a sixth step of outputting a carry signal generated by adding the weighting codes for one pixel row for each of the i weighting codes,
14. The method of driving an electro-optical device according to claim 13, wherein the fifth step is a step of performing a product-sum operation using i number of carry signals as inputs. The second step includes
A seventh step of calculating a number of correction amounts corresponding to the number of display gradations by interpolation of the i correction amounts;
The method of driving an electro-optical device according to claim 13, further comprising an eighth step of correcting the voltage pulse width based on the calculated correction amount.   16. The electricity according to claim 15, wherein the eighth step is a step of interpolating the correction amount by interpolation of the correction amounts adjacent to each other among the i correction amounts. Driving method of optical device. It has a plurality of pixels provided corresponding to each intersection of a plurality of scanning lines and a plurality of data lines, and the gradation of the pixels is set by variably setting the voltage pulse width supplied to the pixels In the driving method of the electro-optical device,
A first step of calculating a correction amount for each pixel row corresponding to the scanning line by performing a product-sum operation based on gradation data defining a gradation of the pixel;
And a second step of correcting the voltage pulse width supplied to the pixel based on the correction amount. It has a plurality of pixels provided corresponding to each intersection of a plurality of scanning lines and a plurality of data lines, and the gradation of the pixels is set by variably setting the voltage pulse width supplied to the pixels In the driving method of the electro-optical device,
First step of calculating i correction amounts (i ≧ 2) smaller than the number of display gradations for each pixel row corresponding to the scanning line, based on gradation data defining gradations of the pixels. When,
A number of correction amounts corresponding to the number of display gradations is calculated by interpolation of the i correction amounts, and the voltage pulse width supplied to the pixel is corrected based on the calculated correction amount. And a method for driving the electro-optical device.   The electric power according to claim 18, wherein the second step is a step of interpolating the correction amount by interpolation of the correction amounts adjacent to each other among the i correction amounts. Driving method of optical device.

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