JP2005065188A - Control signal output circuit for output signals, and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To allow a control signal output circuit for output signals to output an appropriate control signal even when a receiving side circuit includes different terminating resistors. <P>SOLUTION: The control signal output circuit for output signals includes a control signal generating circuit that generates a control signal for controlling an output signal of an output circuit on the basis of a reference voltage. Furthermore, the control signal generating circuit includes a differential amplifier that inputs the reference voltage and a feedback voltage thereto, and a feedback voltage switching circuit which switches the feedback voltage. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an output signal control signal output circuit and a semiconductor device, and more particularly to an output signal control signal output circuit and a semiconductor device for an output circuit.

  Conventionally, a small amplitude differential signal by an RSDS (Reduced Swing Differential Signaling) output circuit or the like has been used in various electronic devices. Since the RSDS output circuit uses a small amplitude differential signal, it contributes to low power consumption and low EMI (Electro Magnetic Interference) of various electronic devices. For example, a substrate on the liquid crystal display device side receives a low-amplitude differential signal such as LVDS (Low Voltage Differential Signals) from the main body of a notebook personal computer (hereinafter referred to as a PC), and the inside of the substrate on the liquid crystal display device side In, signal transmission by RSDS signals is performed.

  Two bias voltage signals for controlling the center voltage and the amplitude are input as reference voltages from the bias voltage generating circuit to the RSDS output circuit that outputs the RSDS signal. The RSDS output circuit is based on two input bias signals, and the difference between the small amplitudes of the input “0” and “1” digital signals with a predetermined voltage width based on a predetermined center voltage. It converts into a motion signal and outputs it (for example, refer patent document 1).

  The operation check of the bias voltage generation circuit is performed by examining whether or not a predetermined current is flowing in a circuit that outputs an amplitude control signal for controlling the amplitude of the RSDS signal. Specifically, a test internal resistor for measuring a current value is provided in a circuit that outputs an amplitude control signal for controlling the amplitude of the differential signal, and both ends of the internal resistor are connected to two input terminals to the tester. By connecting and detecting the voltage value generated at both ends of the internal resistance, it is inspected whether a predetermined current is flowing in the circuit that outputs the amplitude control signal.

In addition, the bias voltage generation circuit is configured so that the RSDS output circuit outputs a differential signal having a predetermined amplitude according to the termination resistance of the receiving side circuit that receives the small amplitude differential signal output from the RSDS output circuit. An internal resistor is provided so that an external resistor corresponding to the terminating resistor of the receiving circuit can be connected to the internal resistor. The internal resistance also served as the test internal resistance of the predetermined current described above.
JP 2002-314397 (paragraph number 0026, FIG. 2)

  However, the receiving side circuit that receives the small-amplitude differential signal output from the RSDS output circuit may have a resistance value different from the assumed termination resistance. In that case, since the internal resistance of the bias voltage generation circuit is provided in accordance with the initially assumed termination resistance, the bias voltage output from the bias voltage generation circuit is the appropriate voltage signal corresponding to the receiving side circuit. It will not be. As a result, the RSDS output circuit that has received such an inappropriate voltage signal output from the bias voltage generation circuit does not output a differential signal that can be properly received by the receiving circuit.

  Therefore, the present invention provides an output signal control signal output circuit that allows an output signal control signal output circuit to output an appropriate control signal even when the receiving side circuit has different termination resistors. With the goal.

  The output signal control signal output circuit of the present invention is an output signal control signal output circuit having a control signal generation circuit for generating a control signal for controlling the output signal of the output circuit based on a reference voltage, The control signal generation circuit includes a differential amplifier that inputs the reference voltage and a feedback voltage, and a feedback voltage switching circuit that switches the feedback voltage.

  The semiconductor device of the present invention preferably has the above-described output signal control signal output circuit.

  According to such a configuration, the output signal control signal output circuit can output an appropriate control signal even when the receiving circuit has different termination resistors. can do.

  Further, in the control signal output circuit for output signals of the present invention, the feedback voltage switching circuit includes a resistor connected to the output of the differential amplifier and a voltage generated at either end of the resistor. It is desirable to have selection means for selecting to supply as.

  According to such a configuration, the feedback voltage can be supplied with a simple configuration.

  In the output signal control signal output circuit of the present invention, it is preferable that the output circuit outputs a differential signal as the output signal.

  According to such a configuration, an appropriate control signal can be output when the output signal is a differential signal.

  In the output signal control signal output circuit of the present invention, it is preferable that the control signal is an amplitude control signal for controlling the amplitude of the differential signal.

  According to such a configuration, an appropriate amplitude control signal can be output when the output signal is a differential signal.

  In the output signal control signal output circuit according to the present invention, it is preferable that the resistor is connected to a connection terminal for connecting an external resistor.

  According to such a configuration, it is possible to connect an external resistor corresponding to the termination resistance of the receiving circuit that receives the output signal of the output circuit, and output an appropriate control signal according to various receiving circuits. it can.

  In the output signal control signal output circuit of the present invention, it is preferable that the resistor is also a test resistor.

  According to such a configuration, the resistor can be used as a test resistor.

Embodiments of the present invention will be described below with reference to the drawings.
First, based on FIG. 1, the structure of the semiconductor device which outputs the differential signal concerning this Embodiment is demonstrated. FIG. 1 is a block diagram showing the configuration of the differential signal output interface circuit according to this embodiment.
The interface circuit 1 shown in FIG. 1 inputs an LVDS (Low Voltage Differential Signals) small-amplitude differential signal as a first differential signal, and an RSDS (Reduced Swing Differential Signaling) as a second differential signal. It is an interface circuit that converts to a small amplitude differential signal and outputs it. The interface circuit 1 is formed on one semiconductor chip. The interface circuit 1 receives a plurality of LVDS signals and outputs a plurality of RSDS signals. The interface circuit 1 has a unit interface circuit including an input circuit 2, a timing control circuit 3, and an output circuit 4 that are LVDS reception circuits, in a number corresponding to the number of input signals and output signals. Each output circuit 4 includes an RSDS output circuit which is a differential signal output circuit. Further, the interface circuit 1 is provided with a bias voltage generation circuit 5 which is a reference voltage supply circuit. The bias voltage generation circuit 5 supplies a plurality of bias voltage signals to each output circuit 4 as predetermined various reference voltages. Supply.

  For example, the interface circuit 1 is provided in the panel substrate of the LCD device of the notebook PC, and receives the LVDS signal output from the PC main body, and transmits the signal by the RSDS signal in the panel substrate. This circuit is formed on a semiconductor substrate. That is, the interface circuit 1 is a semiconductor device used by being mounted on a substrate in an electronic device such as a notebook PC.

  Each input circuit 2 that is an LVDS receiving circuit receives the small amplitude differential signals IN + and IN−, and outputs digital signals “0” and “1” to the timing control circuit 3. The timing control circuit 3 adjusts the timing of the received digital signal and outputs the digital signal DD to the output circuit 4. The output circuit 4 including the RSDS output circuit receives the digital signal DD from the timing control circuit 3 and outputs small amplitude differential signals OUT + and OUT−.

  Each input circuit 2 receives, for example, a full swing small amplitude differential signal IN +, IN− that swings in a voltage range of 0V to 3.3V, while each output circuit 4 has, for example, 1.1V Outputs small-amplitude differential signals OUT + and OUT- that swing in the voltage range of 1.5V. The bias voltage generation circuit 5 outputs a center voltage so that the output circuit 4 outputs small amplitude differential signals OUT + and OUT− having a predetermined center voltage, for example, a predetermined amplitude and plus / minus 0.2V with respect to 1.3V. The reference voltage level signal CV indicating the current level and the amplitude control signal PB are generated and supplied to each output circuit 4.

The reference voltage level signal CV is a predetermined voltage value generated in the bias voltage generation circuit 5. The amplitude control signal PB is a voltage value for controlling the amplitude of the differential signal generated from the bias voltage generation circuit 5 and output from the RSDS output circuit. Therefore, it can be said that the bias voltage generation circuit 5 is an amplitude control signal generation circuit.
FIG. 2 is a circuit diagram showing a configuration example of the output circuit 4. As shown in FIG. 2, the output circuit 4 includes an RSDS output circuit 6 and a center voltage level control signal generation circuit 7. The center voltage level control signal generation circuit 7 includes P-channel transistors 21 and 22 connected in series, resistors 23 and 24 connected in series, and N-channel transistors 25, 26, and 27 connected in series. Includes connected series circuits. A resistor 28 is connected to a connection point between the N-channel transistors 26 and 27. The center voltage level control signal generating circuit 7 includes a differential amplifier 29. One input terminal of the differential amplifier 29 is connected to a connection point B between the resistors 23 and 24, and the other input terminal is connected to a reference voltage level signal. CV is entered.

  The RSDS output circuit 6 includes a P-channel transistor 31, a transistor parallel circuit including four transistors 32, 33, 34, and 35, a series circuit in which an N-channel transistor 36 and an N-channel transistor 37 are connected in series. . In the transistor parallel circuit, a series circuit of a P-channel transistor 32 and an N-channel 33 transistor connected in series, and a series circuit of a P-channel transistor 34 and an N-channel transistor 35 connected in series are connected in parallel. . A resistor 38 is connected to a connection point between the N-channel transistors 36 and 37. One end of two inversion circuits 39 connected in series is connected to the gates of the P-channel transistor 32 and the N-channel transistor 33. One end of three inversion circuits 40 connected in series is connected to the gates of a P-channel transistor 34 and an N-channel transistor 35. The other end of the inverting circuits 39 and 40 is supplied with the digital signal DD from the timing control circuit 3.

A connection point C1 between the source of the P-channel transistor 32 and the drain of the N-channel transistor 33 and a connection point C2 between the source of the P-channel transistor 34 and the drain of the N-channel transistor 35 are forward and inversion differentials, respectively. Signals are OUT + and OUT-.
Here, the circuit including the P-channel transistors 21 and 22, resistors 23 and 24, N-channel transistors 25, 26, and 27 and the resistor 28 in the center voltage level control signal generation circuit 7 is the P-channel transistor in the RSDS output circuit 6. 31 is a replica circuit of an output circuit including a P channel transistor 32, an N channel transistor 33, a P channel transistor 34, an N channel transistor 35, an N channel transistor 36, an N channel transistor 37, and a resistor 38, in other words, a replica circuit.
That is, when the digital signal DD from the timing control circuit 3 is input to the inverting circuits 39 and 40, in the RSDS output circuit 6, the P channel transistor 32 and the N channel transistor 35 are turned on, and the N channel transistor 33 and the P channel transistor 34 are turned on. Is turned off, or the P-channel transistor 32 and the N-channel transistor 35 are turned off and the N-channel transistor 33 and the P-channel transistor 34 are turned on. As a result, the current flows through the P-channel transistor 32 and N-channel transistor 35 and the terminating resistor, or the differential signal output circuit is formed by flowing through the P-channel transistor 34 and N-channel transistor 33 and the terminating resistor. .
The center voltage level control signal generation circuit 7 includes a circuit equivalent to the differential signal output circuit formed in this way, that is, a circuit that is a duplicate of the RSDS output circuit 6. By providing such a duplicating circuit in the center voltage level control signal generating circuit 7, the output characteristics of the differential signal in the RSDS output circuit 6 can be matched with each other reliably.

Next, the operation will be described.
The bias voltage generation circuit 5 outputs a reference voltage level signal CV of 1.3 V, for example, and an amplitude control signal PB.
The differential amplifier 29 of the center voltage level control signal generation circuit 7 controls the output signal, that is, the center voltage level control so that the voltage at the connection point B matches the reference voltage level signal CV input to one of the input terminals. The signal NB is output. This is because the center voltage level control signal NB is supplied to the gate of the N-channel transistor 27 and the current flowing between the source and drain of the N-channel transistor 27 changes, so that the voltage at the connection point B becomes the reference voltage level signal CV. This is because it comes to match.

  This central voltage level control signal NB is supplied to the gate of the N-channel transistor 37 of the RSDS output circuit 6, and the current flowing through the RSDS output circuit 6 at the timing of the timing signal EN input to the gate of the N-channel transistor 36 is also connected. The voltage generated at both ends of the end point resistor between the points C1 and C2 is the voltage generated at both ends of the series circuit of the resistors 23 and 24 of the replica circuit of the output circuit 4 included in the center voltage level control signal generating circuit 7. Controlled to be the same.

  At this time, the RSDS output circuit 6 and the center voltage level control signal generation circuit 7 are formed at positions close to each other on the semiconductor substrate of the semiconductor chip. In other words, on the semiconductor substrate of the semiconductor chip, the formation region of the RSDS output circuit 6 and the formation region of the center voltage level control signal generation circuit 7 are close so that the operation characteristics of the transistors included in the respective circuits are equivalent. Formed in the distance. Therefore, since the center voltage level of the differential signal output from the RSDS output circuit 6 can be set to a desired level, it can be reliably received by the circuit on the receiving side that receives the differential signal.

Next, the bias voltage generation circuit 5 will be described. FIG. 3 is a diagram illustrating a circuit configuration example of the bias voltage generation circuit 5.
Reference numeral 101 denotes a bias circuit, which is a reference voltage circuit based on the thermal voltage, and the generated voltage is used as the operating voltage of each differential amplifier in the bias voltage generating circuit 5 and the operating voltage BB of each RSDS output circuit 6. Supply.

Reference numeral 102 denotes a bandgap circuit which is a reference voltage generation circuit, which uses the silicon bandgap to output a reference voltage while eliminating temperature characteristics and power supply voltage dependence as much as possible.
An output NB1 of the band gap circuit 102 which is a reference voltage generation circuit is input to one input terminal of the differential amplifier 103. The other input terminal of the differential amplifier 103 is input to the selector 104.

  The selector 104 has a plurality of connections in order to supply a voltage at one connection point among a plurality of connection points of the series resistance circuit 105 in which a plurality of resistors are connected in series to one input terminal of the differential amplifier 103. This is a circuit for selecting one connection point among the points. The selector 104 has one input and the number of outputs corresponding to a plurality of connection points, and performs resistance division of the resistor series circuit 105. Reference numeral 106 denotes a P-channel transistor which is normally turned on, a predetermined voltage is applied to the source side, and the drain side is connected to one end of the series resistance circuit 105. Note that the other end of the series resistance circuit 105 is connected to the ground.

Therefore, the differential amplifier 103 outputs an output so that the voltages at the two input terminals are equal by a feedback loop formed by including a resistor between the connection point selected by the selector 104 and the P-channel transistor 106. Control.
The reference voltage generated and output by the band gap circuit 102 varies slightly depending on the manufacturing process or the like, and may not output a desired voltage value. The selector 104 is a circuit for finely adjusting the output voltage value when the desired voltage value is not output due to the fluctuation. Therefore, the reference voltage from the band gap circuit 102 is set to a predetermined value so that the output circuit 4 outputs an appropriate differential signal even when the band gap circuit 102 does not output a desired voltage depending on the manufacturing process. By adjusting the range, the bias voltage generation circuit 5 can output an appropriate bias voltage.

  The differential amplifier 103, the selector 104, and the series resistance circuit 105 constitute a reference voltage adjustment circuit that adjusts the reference voltage within a predetermined range, and the reference voltage adjustment circuit is connected to each of the resistors of the series resistance circuit 105. The reference voltage generated by the band gap circuit 102 is finely adjusted by using the divided voltage at the point as the feedback voltage of the differential amplifier 103.

  Reference numeral 107 denotes a selector, which outputs one connection point among a plurality of connection points in order to output a voltage at a connection point selected from a plurality of connection points of a series resistance circuit 105 in which a plurality of resistors are connected in series. This is a circuit for selecting. The series resistance circuit 105 is a multiple reference voltage generation circuit that generates a plurality of reference voltages, and can easily generate a plurality of reference voltages by using a resistance circuit in which a plurality of resistors are connected in series. The selector 107 outputs the divided voltage generated by the resistance division of the resistor series circuit 105 at the selected connection point to one input terminal of the differential amplifier 108. The selector 107 is a voltage selection circuit that selects and outputs one reference voltage from a plurality of reference voltages.

The selector 107 is a circuit for selecting and changing the center voltage by changing the center voltage of the differential signal, for example, in a range of 1.1V to 1.5V in steps of 0.1V. Depending on the circuit that receives the RSDS signal, the center voltage may be different. In such a case, the reference voltage level signal CV output from the RSDS output circuit 4 is changed according to the receiving side circuit. It is to do. In FIG. 3, the voltage CV1 at the connection point C11 of the series resistor circuit 105 is 1.5V, the voltage CV2 at the connection point C12 is 1.4V, the voltage CV3 at the connection point C13 is 1.3V, and the voltage CV4 at the connection point C17 is 1.4. The voltage CV5 at the connection point C18 corresponds to 1.5V. Therefore, the center voltage can be changed in steps of 0.1V, such as 1.2V or 1.4V.
The output of the differential amplifier 108 is supplied as the reference voltage level signal CV to the differential amplifier 29 of the above-described center voltage level control signal generation circuit 7.

Here, the selector 104, the series resistance circuit 105, and the selector 107 will be described in more detail. FIG. 4 is a circuit diagram for explaining the selector 104, the series resistance circuit 105, and the selector 107 in more detail.
One input terminal of the differential amplifier 103 is connected to the input of the selector 104, that is, one end of each of a plurality (here, five) switches SW11 to SW15. Which of SW11 to SW15 is selected is selected by a setting pin or the like. In the series resistance circuit 105, a plurality of resistors, here, eight resistors are connected in series, and the other ends of SW11 to SW15 are connected to a connection point between predetermined resistors.

  Further, a connection point between predetermined resistors of the series resistor circuit 105 is connected to one end of each of a plurality of (here, five) switches SW21 to SW25 of the selector 107. Which of SW21 to SW25 is selected is selected by a setting pin or the like. The other ends of the switches SW21 to SW25 of the selector 107 are connected to one of the input ends of the differential amplifier 108 as an output of the selector 107.

  In the series resistance circuit 105, among the eight resistors, SW21 is connected to a connection point C11 of the P-channel transistor 106 and the resistor R1, SW22 is connected to a connection point C12 of the resistors R1 and R2, and a connection point of the resistors R2 and R3. SW23 is connected to C13, and one end of the switch SW11 is connected to a connection point C13 of the resistors R2 and R3. One end of the switch SW12 is connected to a connection point C14 between the resistors R3 and R4. One end of the switch SW13 is connected to the connection point C15 of the resistors R4 and R5, and one end of the switch SW14 is connected to the connection point C16 of the resistors R5 and R6. One end of the switch SW15 is connected to the connection point C17 of the resistors R6 and R7, and the connection point C17 of the resistors R6 and R7 is connected to the SW24. SW25 is connected to the connection point C18 of the resistors R7 and R8.

  Here, the resistance values of the resistors R1, R2, R7 and R8 are the same, and the resistance values of the resistors R3, R4, R5 and R6 are the same, but the former resistors (R1, R2, R7 and R8) And the resistance values of the latter resistors (R3, R4, R5 and R6) are different. The latter resistors (R3, R4, R5 and R6) are resistors for adjusting the range in which the voltage value output from the bandgap circuit 102 varies depending on the manufacturing process, whereas the former resistors (R1, The resistance values of R2, R7, and R8) are resistors for changing the center voltage according to the receiver circuit standard, so the resistance values of the former resistors (R1, R2, R7, and R8) are those of the latter. Greater than (R3, R4, R5 and R6).

  For example, when the center voltage of the RSDS signal can be selected in the range of 1.1V to 1.5V in increments of 0.1V, the connection point C11 is 1.5V, the connection point C12 is 1.4V, and the connection point C13 is 1.3V. The resistance values of the resistors are selected so that the connection point C17 is 1.2V and the connection point C18 is 1.1V. Similarly, the resistance value of each resistor is selected so that the voltage value output from the band gap circuit 102 can be adjusted in increments of 25 mV, for example.

  In this way, the reference voltage generated by the bandgap circuit 102 is adjusted by using the divided voltage at each connection point between the plurality of resistors of the series resistor circuit 105 as the feedback voltage of the differential amplifier 103. Therefore, it is possible to easily generate a plurality of reference voltages and to adjust the reference voltage generated by the band gap circuit 102 using the same resistance circuit.

Next, returning to FIG. 3, a control signal generation circuit that generates an amplitude control signal PB that is an output signal control signal will be described.
The control signal generation circuit includes a differential amplifier 109, P-channel transistors 110 and 113, resistors 111 and 114, and a switch SW31. One connection point of the series resistance circuit 105, here the connection point C13, is connected to one input terminal of the differential amplifier 109. The output of the differential amplifier 109 is connected to the gate of the P channel transistor 110. The drain of the P channel transistor 110 is connected to a connection terminal REXT for connecting an external resistor as a setting resistor via the P channel transistor 113 and resistors 111 and 114. The external resistor is connected to the connection terminal REXT according to the standard of the RSDS signal receiving circuit. The circuit including the P-channel transistors 110 and 113, the resistors 111 and 114, and the external resistor is the transistors 21 and 22, resistors 23 and 24, N-channel transistors 25, 26, and 27 in the central voltage level control signal generation circuit 7. A replica circuit of the circuit including the resistor 28, in other words, a replica circuit.

  The other input terminal of the differential amplifier 109 for inputting the feedback voltage is connected to one of the switches SW31. The switch SW31 is selection means for switching and selecting the other input terminal of the differential amplifier 109 so as to be connected to either one of both ends of the resistor 114. In other words, the switch SW31 and the resistor 114 are a feedback voltage switching circuit that switches the feedback voltage of the differential amplifier 109. According to the configuration using the switch SW31 and the resistor 114, the feedback voltage can be supplied with a simple configuration. The differential amplifier 109 outputs an amplitude control signal PB that is a control signal for controlling the output signal of the RSDS output circuit 6 based on the reference voltage supplied from the series resistance circuit 105 and the feedback voltage.

The gate of the P-channel transistor 110 is connected to one input terminal of the differential amplifier 112, and the other input terminal of the differential amplifier 112 is connected to the output of the differential amplifier 112.
When the external resistor is connected to the terminal REXT, the amplitude control signal PB of the differential signal output from the RSDS circuit 6 is determined based on the current flowing through the resistor 111.

  The switch SW31 is a circuit for switching when a reception side circuit having a resistance value different from a predetermined resistance value is connected to the termination resistance of the reception side circuit output from the RSDS output circuit 6.

  For example, when the terminating resistance of the receiving circuit output from the RSDS output circuit 6 has a certain resistance value, a certain external resistor is connected to the terminal REXT according to the resistance value of the terminating resistance. In this case, the switch SW31 selects the connection point C22 side between the terminal REXT and the resistor 114. When the switch SW31 selects the connection point C22 side and the potential of the connection point C22 is applied to one input terminal of the differential amplifier 109, a predetermined constant current value, for example, a current of 100 μA is a resistance. As a result, the amplitude control signal PB becomes a predetermined output.

  Further, when the terminating resistance of the receiving side circuit that receives the differential signal of the RSDS output circuit 6 has a resistance value smaller than that in the above case, for example, the switch SW31 selects the connection point C21 side of the resistors 111 and 114. . When the switch SW31 selects the connection point C21 side, the potential of the connection point C21 is applied to one input terminal of the differential amplifier 109. As a result, the resistor 111 has a predetermined constant current value, For example, a current of 100 μA flows. Therefore, the amplitude control signal PB becomes a predetermined output.

  Therefore, when the receiving side circuit that receives the differential signal of the RSDS output circuit 6 has a termination resistance different from the termination resistance originally assumed, an appropriate difference is also obtained with respect to the reception side circuit having the different termination resistance. The bias voltage generation circuit 5 supplies a bias voltage that outputs a dynamic signal to the RSDS output circuit 6. In other words, the bias voltage generation circuit 5 can supply an appropriate bias voltage as an output signal control signal to the output circuit 4 by switching the switch SW31 according to the receiving side circuit that receives the differential signal. .

  Further, when the switch SW31 selects the connection point C21 side, the bias voltage generation circuit 5 is checked by connecting the terminal of the current tester to the terminal REXT, specifically, the amplitude of the differential signal. It is possible to check whether or not a predetermined current for control is flowing. Since the resistor 114 can also be used as a test resistor, it is necessary to provide a separate test resistor when inspecting a product after manufacturing a semiconductor device on which an output signal control signal output circuit is formed. Absent.

  In the above-described example, the external resistor has been described in the case where the specification of the receiving side circuit is two. However, the specification of the receiving side circuit may be three or more. The internal resistance may be switched.

  As described above, according to the bias voltage generation circuit that is the output signal control signal output circuit of the present embodiment, the bias voltage generation circuit is configured to have an appropriate bias even when the reception side circuit has different termination resistors. A voltage can be output.

  The present invention is not limited to the above-described embodiments, and various changes and modifications can be made without departing from the scope of the present invention.

The block block diagram of the interface circuit concerning embodiment of this invention. The circuit diagram of the output circuit concerning an embodiment of the invention. 1 is a circuit diagram of a bias voltage generation circuit according to an embodiment of the present invention. FIG. 4 is a circuit diagram for explaining the selector and the like of FIG. 3 in more detail.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Interface circuit for differential signal output 2 Input circuit 3 Timing control circuit 4 Output circuit 5 Bias voltage generation circuit 6 RSDS output circuit 7 Center voltage level control signal generation circuit 101 Reference voltage circuit 102 Band gap Circuit, 104, 107 selector

Claims (7)

An output signal control signal output circuit having a control signal generation circuit for generating a control signal for controlling an output signal of the output circuit based on a reference voltage,
The control signal generation circuit includes:
A differential amplifier for inputting the reference voltage and the feedback voltage;
A control signal output circuit for an output signal, comprising: a feedback voltage switching circuit for switching the feedback voltage.   The feedback voltage switching circuit includes a resistor connected to the output of the differential amplifier, and selection means for selecting a voltage generated at either end of the resistor to supply as the feedback voltage. The output signal control signal output circuit according to claim 1.   The output signal control signal output circuit according to claim 1, wherein the output circuit outputs a differential signal as the output signal.   4. The output signal control signal output circuit according to claim 1, wherein the control signal is an amplitude control signal for controlling an amplitude of the differential signal.   5. The output signal control signal output circuit according to claim 2, wherein the resistor is connected to a connection terminal for connecting an external resistor.   6. The output signal control signal output circuit according to claim 5, wherein the resistor is also a test resistor.   7. A semiconductor device comprising the output signal control signal output circuit according to claim 1.

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