JP2005065065A - Decoding device, decoding method, and program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the circuit scale of a decoding device, concerning the decoding device, a decoding method, and a program for decoding codes encoded by low density parity check codes. <P>SOLUTION: A control unit 316 selects any one of a check node calculator 313 for performing operation of check node for decoding an LDPC code and a variable node calculator 312 for performing operation of variable node for decoding the LDPC code, and supplies a selecting signal D323 indicating the selection to a switch 311 and a selector 314. A branch memory 310 stores the message D314 of the result of the variable node operation, and the message D315 of the result of the check node operation. The switch 311 supplies the message D311 stored in the branch memory 310 to the check node calculator 313 or the variable node calculator 312 on the basis of the selecting signal D323. This device is applicable to a decoding device for decoding an LDPC code. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a decoding device, a decoding method, and a program, and more particularly to a decoding device, a decoding method, and a program for decoding a code that has been encoded by a low-density parity check code.

  In recent years, for example, the field of communication such as mobile communication and deep space communication and the field of broadcasting such as terrestrial or satellite digital broadcasting have been remarkably advanced. Research on coding theory is also actively conducted.

  As the theoretical limit of code performance, the Shannon limit given by the so-called Shannon (C. E. Shannon) channel coding theorem is known. Research on code theory is being conducted with the goal of developing codes that exhibit performance close to the Shannon limit. In recent years, as a coding method showing performance close to the Shannon limit, for example, so-called turbo codes such as parallel concatenated convolutional codes (PCCC (Parallel Concatenated Convolutional Codes)) and tandem concatenated convolutional codes (SCCC) A technique called Turbo coding has been developed. While these turbo codes are being developed, low density parity check codes (hereinafter referred to as LDPC codes), which is an encoding method that has been known for a long time, are attracting attention.

  The LDPC code was first proposed in "RG Gallager," Low Density Parity Check Codes ", Cambridge, Massachusetts: MIT Press, 1963 by RG Gallager, and then" DJC MacKay, "Good error correcting codes based on very sparse matrices ", Submitted to IEEE Trans. Inf. Theory, IT-45, pp. 399-431, 1999" and "MG Luby, M. Mitzenmacher, MA Shokrollahi and DA Spielman," Analysis of low density codes and improved designs using irregular graphs ", in Proceedings of ACM Symposium on Theory of Computing, pp. 249-258, 1998".

  Recent studies have shown that LDPC codes can achieve performance close to the Shannon limit as the code length is increased, similar to turbo codes and the like. In addition, since the LDPC code has the property that the minimum distance is proportional to the code length, its characteristic is that the block error probability characteristic is good, and furthermore, the so-called error floor phenomenon observed in the decoding characteristic such as turbo code is observed. An advantage is that it hardly occurs.

  Hereinafter, such an LDPC code will be specifically described. Note that the LDPC code is a linear code and does not necessarily need to be binary, but will be described here as being binary.

  The LDPC code is characterized by the fact that the parity check matrix that defines the LDPC code is sparse. Here, the sparse matrix is configured so that the number of "1" of the matrix components is very small. If the sparse check matrix is represented by H, as such a check matrix, for example, As shown in FIG. 1, the hamming weight (number of “1” s) (weight) of each column is “3” and the hamming weight of each row is “6”.

  Thus, an LDPC code defined by a parity check matrix H in which the Hamming weight of each row and each column is constant is referred to as a regular LDPC code. On the other hand, an LDPC code defined by a parity check matrix H in which the Hamming weight of each row and each column is not constant is referred to as an irregular LDPC code.

Such an LDPC code encoding is realized by generating a generator matrix G based on the check matrix H and generating a codeword by multiplying the binary information message by the generator matrix G. . Specifically, the encoding device which performs encoding by LDPC codes, first, between the transposed matrix H ^T of the parity check matrix H, calculates a generator matrix G which formula GH ^T = 0 is established. Here, when the generator matrix G is a k × n matrix, the encoding device multiplies the generator matrix G by an information message (vector u) consisting of k bits, and a codeword c consisting of n bits. (= UG) is generated. The codeword generated by this encoding device is transmitted after being mapped such that the sign bit having a value of “0” is “+1”, the sign bit having a value of “1” is “−1”, and the like. The signal is received on the receiving side via a predetermined communication path.

  On the other hand, decoding of an LDPC code is an algorithm proposed by Gallager called probabilistic decoding (Probabilistic Decoding), which is a variable node (also called a message node) and a check node (check node). ) And a message passing algorithm based on belief propagation on a so-called Tanner graph. Here, hereinafter, the variable node and the check node are also simply referred to as nodes as appropriate.

  However, in probabilistic decoding, since the message passed between each node is a real value, in order to solve it analytically, it is necessary to track the probability distribution itself of messages that take consecutive values. It will require analysis with difficulty. Therefore, Gallager has proposed algorithm A or algorithm B as a decoding algorithm for LDPC codes.

The decoding of the LDPC code is generally performed according to a procedure as shown in FIG. Here, the received value is U ₀ (u _0i ), the message output from the check node is u _j, and the message output from the variable node is v _i . Further, here, the message is a real value expressing the value of “0” as a so-called log likelihood ratio.

First, in decoding of the LDPC code, as shown in FIG. 2, in step S11, the received value U ₀ (u _0i ) is received, the message u _j is initialized to “0”, and the counter of the iterative process is performed. The variable k taking an integer is initialized to “0”, and the process proceeds to step S12. In step S12, based on the received value U ₀ (u _0i), message v _i is obtained by performing the calculation shown in Equation (1), further, on the basis of this message v _i, shown in Equation (2) A message u _j is obtained by performing an operation.

・・・（１）

... (1)

・・・（２）

... (2)

Here, d _v and d _c in Equation (1) and Equation (2) can be arbitrarily selected to indicate the number of “1” s in the vertical direction (column) and horizontal direction (row) of the parity check matrix H, respectively. For example, in the case of a (3, 6) code, d _v = 3 and d _c = 6.

Note that in the calculation of the expression (1) or (2), the message input from the edge to which the message is to be output is not used as a parameter for the sum or product operation. The range of operation is 1 to d _v -1 or 1 to d _c -1. In addition, the calculation shown in equation (2) actually creates a table of function R (v ₁ , v ₂ ) shown in equation (3) defined by one output for two inputs v ₁ and v ₂ in advance. This is done by using it continuously (recursively) as shown in equation (4).

・・・（３）

... (3)

・・・（４）

... (4)

  In step S12, the variable k is further incremented by “1”, and the process proceeds to step S13. In step S13, it is determined whether or not the variable k is equal to or greater than a predetermined iterative decoding count N. If it is determined in step S13 that the variable k is not equal to or greater than N, the process returns to step S12, and the same processing is repeated thereafter.

  If it is determined in step S13 that the variable k is greater than or equal to N, the process proceeds to step S14, and the message v as the decoding result that is finally output is obtained by performing the calculation shown in equation (5). The LDPC code decoding process ends.

・・・（５）

... (5)

  Here, unlike the operation of equation (1), the operation of equation (5) is performed using input messages from all branches connected to the variable node.

For example, in the case of a (3, 6) code, such an LDPC code is decoded as shown in FIG. In FIG. 3, the calculation shown in Expression (1) is performed at the node indicated by “=” (variable node), and the calculation shown in Expression (2) is performed at the node indicated by “+” (check node). Done. In particular, in algorithm A, the message is binarized, and the exclusive OR operation of d _c −1 input messages is performed at the node indicated by “+”, and the received value is obtained at the node indicated by “=”. For R, if d _v −1 input messages all have different bit values, the sign is inverted and output.

  On the other hand, in recent years, research on an implementation method for decoding an LDPC code is also being conducted. Before describing the mounting method, first, decoding of an LDPC code will be schematically described.

  FIG. 4 is an example of a parity check matrix of a (3, 6) LDPC code (coding rate 1/2, code length 12). The parity check matrix of the LDPC code can be written using a Tanner graph as shown in FIG. In FIG. 5, “+” represents a check node, and “=” represents a variable node. Check nodes and variable nodes correspond to the rows and columns of the parity check matrix, respectively. The connection between the check node and the variable node is an edge and corresponds to “1” of the parity check matrix. That is, when the component in the j-th row and i-th column of the parity check matrix is 1, the i-th variable node ("=" node) from the top and the j-th check node ("from the top) in FIG. + "Node") are connected by a branch. The branch indicates that the sign bit corresponding to the variable node has a constraint condition corresponding to the check node. Note that FIG. 5 is a Tanner graph of the parity check matrix of FIG.

  The Sum Product Algorithm, which is an LDPC code decoding method, repeatedly performs a variable node operation and a check node operation.

In the variable node, the calculation of Expression (1) is performed as shown in FIG. That is, in FIG. 6, the message v _i corresponding to the branch to be calculated is calculated using the messages u ₁ and u ₂ from the remaining branches connected to the variable node and the reception information u _0i . Messages corresponding to other branches are similarly calculated.

  Before explaining the operation of the check node, the expression (2) is changed to the expression a × b = exp {ln (| a |) + ln (| b |)} × sign (a) × sign (b). And rewrite as equation (6). However, sign (x) is 1 when x ≧ 0, and −1 when x <0.

・・・（６）

... (6)

Furthermore, when x ≧ 0 and φ (x) = ln (tanh (x / 2)) is defined, φ ⁻¹ (x) = 2 tanh ⁻¹ (e ^−x ), so equation (6) is It can be written as equation (7).

・・・（７）

... (7)

In the check node, the calculation of Expression (7) is performed as shown in FIG. That is, in FIG. 7, the message u _j corresponding to the branch to be calculated is calculated using the messages v ₁ , v ₂ , v ₃ , v ₄ , v ₅ from the remaining branches connected to the check node. The Messages corresponding to other branches are similarly calculated.

The function φ (x) can also be expressed as φ (x) = ln ((e ^x +1) / (e ^x −1)). When x> 0, φ (x) = φ ⁻¹ ( x). When the functions φ (x) and φ ⁻¹ (x) are mounted on hardware, they may be mounted using a LUT (Look Up Table), but both are the same LUT.

  When the thumb product algorithm is implemented in hardware, it is necessary to repeatedly perform the variable node operation represented by Expression (1) and the check node operation represented by Expression (7) with an appropriate circuit scale and operating frequency. .

  As an example of implementation of a decoding device, first, an implementation method in the case where decoding is performed by simply performing operations of each node one by one (full serial decoding) will be described.

  Here, for example, a code (coding rate 2/3, code length 90) represented by a parity check matrix of 30 (rows) × 90 (columns) in FIG. 8 is decoded. The number of 1s in the parity check matrix in FIG. 8 is 269. Therefore, in the Tanner graph, the number of branches is 269. Here, in the parity check matrix of FIG. 8, 0 is represented by “.”.

  FIG. 9 illustrates a configuration example of a decoding device that performs one-time decoding of an LDPC code.

  In the decoding device of FIG. 9, a message corresponding to one branch is calculated for each clock that operates.

  9 includes two branch memories 100 and 102, one check node calculator 101, one variable node calculator 103, one reception memory 104, and one control unit 105.

  In the decoding device of FIG. 9, message data is read one by one from the branch memory 100 or 102, and message data corresponding to a desired branch is calculated using the message data. The message data obtained by the calculation is stored in the branch memory 102 or 100 in the subsequent stage one by one. When iterative decoding is performed, iterative decoding is realized by connecting a plurality of decoding devices of FIG. 9 that perform this one-time decoding in a column or by repeatedly using the decoding device of FIG. Here, for example, it is assumed that a plurality of decoding devices in FIG. 9 are connected.

  The branch memory 100 stores the message D100 supplied from the variable node calculator 103 of the preceding decoding device (not shown) in the order in which the subsequent check node calculator 101 reads the message D100. In the check node calculation phase, the branch memory 100 supplies the message D100 to the check node calculator 101 as the message D101 in the stored order.

  Based on the control signal D106 supplied from the control unit 105, the check node calculator 101 uses the message D101 supplied from the branch memory 100 to perform an operation according to Expression (7), and obtains the message obtained by the operation. D102 is supplied to the branch memory 102 in the subsequent stage.

  The branch memory 102 stores the message D102 supplied from the previous check node calculator 101 in the order in which the subsequent variable node calculator 103 reads the message D102. In the variable node calculation phase, the branch memory 102 supplies the message D102 to the variable node calculator 103 as the message D103 in the stored order.

  Further, the control signal D107 is supplied from the control unit 105 to the variable node calculator 103, and the reception data D104 is supplied from the reception memory 104. Based on the control signal D107, the variable node calculator 103 uses the message D103 supplied from the branch memory 100 and the received data D104 supplied from the reception memory 100 to perform an operation according to the equation (1), and The message D105 obtained as a result is supplied to the branch memory 100 of the decoding device in the subsequent stage (not shown).

  The reception memory 104 stores LDPC-encoded reception data (LDPC code). The control unit 105 supplies a control signal D106 for controlling the variable node calculation and a control signal D107 for controlling the check node calculation to the check node calculator 101 and the variable node calculator 103, respectively. When all branch messages are stored in the branch memory 100, the control unit 105 supplies the control signal D106 to the check node calculator 101, and when all branch messages are stored in the branch memory 102, A control signal D107 is supplied to the variable node calculator 103.

  FIG. 10 shows a configuration example of the check node calculator 101 of FIG. 9 that performs check node operations one by one.

  In FIG. 10, the check node calculator 101 is represented on the assumption that each message is quantized to a total of 6 bits including code bits. Further, in FIG. 10, a check node calculation of the LDPC code represented by the parity check matrix of FIG. 8 is performed. Further, a clock ck is supplied to the check node computing unit 101 in FIG. 10, and this clock ck is supplied to a necessary block. Each block performs processing in synchronization with the clock ck.

  The check node calculator 101 in FIG. 10 is supplied from the control unit 105, for example, based on the 1-bit control signal D106, and using the message D101 read one by one from the branch memory 100, Equation (7) Therefore, calculation is performed.

That is, the check node calculator 101 reads one 6-bit message D101 (message v _i ) from the variable node corresponding to each column of the parity check matrix one by one, and the absolute value D122 (| v _i ) as its lower bits. |) Is supplied to the LUT 121, and the sign bit D121 which is the most significant bit is supplied to the EXOR circuit 129 and the FIFO (First In First Out) memory 133, respectively. The check node calculator 101 is supplied with a control signal D106 from the control unit 105, and the control signal D106 is supplied to the selector 124 and the selector 131.

The LUT 121 reads the 5-bit operation result D123 (φ (| v _i |)) obtained by performing the operation of φ (| v _i |) in the equation (7) with respect to the absolute value D122 (| v _i |). The adder 122 and the FIFO memory 127 are supplied.

The adder 122 adds the operation result D123 (φ (| v _i |)) and the 9-bit value D124 stored in the register 123, thereby accumulating the operation result D123, and 9 bits obtained as a result. Is stored again in the register 123. Note that the register 123 is reset when the calculation results for the absolute value D122 (| v _i |) of the message D101 from all branches over one row of the check matrix are accumulated.

  When the message D101 over one row of the check matrix is read one by one and the accumulated value obtained by integrating the operation result D123 for one row is stored in the register 123, the control signal D106 supplied from the control unit 105 is: It changes from 0 to 1. For example, when the row weight is “9”, the control signal D106 is “0” from the first to the eighth clock, and “1” at the ninth clock.

When the control signal D106 is "1", selector 124 selects the value stored in the register 123, i.e., phi obtained from the messages D101 from all of the branches across one line of the parity check matrix (message v _i) ( | v _i |) 9-bit value that is accumulated D124 (Sigma] [phi of i = 1 through _{i = d c (| v i} |) select), as a value D125, and stores and outputs to the register 125. The register 125 supplies the stored value D125 to the selector 124 and the adder 126 as a 9-bit value D126. When the control signal D106 is “0”, the selector 124 selects the value D126 supplied from the register 125, outputs it to the register 125, and stores it again. That is, until φ (| v _i |) obtained from the message D101 (message v _i ) from all branches over one row of the check matrix is accumulated, the register 125 accumulates φ (| v _i |) is supplied to the selector 124 and the adder 126.

On the other hand, FIFO memories 127, (from i = 1 i = Σφ to _{d c (| v i |)} ) a new value D126 from the register 125 until it is output, the result calculation LUT121 has output D123 (phi (| v _i |)) is delayed and supplied to the subtractor 126 as a 5-bit value D127. The subtractor 126 subtracts the value D127 supplied from the FIFO memory 127 from the value D126 supplied from the register 125, and supplies the subtraction result to the LUT 128 as a 5-bit subtraction value D128. In other words, the subtractor 126 determines the message D101 () from the branch to be obtained from the integrated value of φ (| v _i |) obtained from the message D101 (message v _i ) from all the branches over one row of the check matrix. Φ (| v _i |) obtained from the message v _i ) is subtracted, and the subtraction value (Σφ (| v _i |) from i = 1 to i = d _c −1) is used as the subtraction value D128. To supply.

The LUT 128 calculates φ ⁻¹ (Σφ (| v _i |)) in Expression (7) with respect to the subtraction value D128 (Σφ (| v _i |) from i = 1 to i = d _c −1). A 5-bit calculation result D129 (φ ⁻¹ (Σφ (| v _i |))) is output.

  In parallel with the above processing, the EXOR circuit 129 multiplies the sign bits by calculating an exclusive OR of the 1-bit value D131 stored in the register 130 and the sign bit D121. The bit multiplication result D130 is stored again in the register 130. When the sign bit D121 of the message D101 from all branches over one row of the check matrix is multiplied, the register 130 is reset.

If (Paisign from i = 1 to d _c (v _i)) multiplication result D130 to the sign bit D121 is multiplied by the message D101 from all of the branches across one line of the parity check matrix stored in the register 130, the control The control signal D106 supplied from the unit 105 changes from “0” to “1”.

When the control signal D106 is “1”, the selector 131 is the value stored in the register 130, that is, the value D131 (multiplied by the sign bit D121 of the message D101 from all the branches over one row of the check matrix). select i = from 1 to _{i = d c Πsign (v i} )), and stores and outputs a 1-bit value D132 to the register 132. The register 132 supplies the stored value D132 to the selector 131 and the EXOR circuit 134 as a 1-bit value D133. When the control signal D106 is “0”, the selector 131 selects the value D133 supplied from the register 132, outputs it to the register 132, and stores it again. In other words, the register 132 supplies the previously stored value to the selector 131 and the EXOR circuit 134 until the sign bit D121 of the message D101 (message v _i ) from all branches over one row of the check matrix is multiplied. .

On the other hand, FIFO memories 133, between (from i = 1 i = Πsign to d _c (v _i)) a new value D133 from the register 132 until is supplied to the EXOR circuit 134 delays the sign bit D121, The 1-bit value D134 is supplied to the EXOR circuit 134. The EXOR circuit 134 calculates the exclusive OR of the value D133 supplied from the register 132 and the value D134 supplied from the FIFO memory 133, thereby dividing the value D133 by the value D134 and dividing by 1 bit. The result is output as the division value D135. That is, the EXOR circuit 134 uses the sign bit D121 of the message D101 from the branch to be obtained as the multiplication value of the sign bit D121 (sign (| v _i |)) of the message D101 from all branches over one row of the check matrix. Divide by (sign (| v _i |)), and the division value (Πsign (| v _i |) from i = 1 to i = d _c −1) is output as the division value D135.

In the check node calculator 101, the 5-bit operation result D129 output from the LUT 128 is set to the lower 5 bits, and the total 6 bits including the 1-bit division value D135 output from the EXOR circuit 134 as the most significant bit is a message. D102 (message u _j ) is output.

As described above, the check node calculator 101 performs the calculation of Expression (7) to obtain the message u _j .

Note that since the maximum row weight of the parity check matrix in FIG. 8 is 9, that is, the maximum number of messages supplied to the check node is 9, the check node calculator 101 has nine messages (φ FIFO memory 127 and FIFO memory 133 for delaying (| v _i |)). When calculating a message for a row with a row weight less than 9, the amount of delay in the FIFO memory 127 and the FIFO memory 133 is reduced to the value of the row weight.

  FIG. 11 shows a configuration example of the variable node calculator 103 of FIG. 9 that performs variable node operations one by one.

  In FIG. 11, the variable node calculator 103 is represented on the assumption that each message is quantized to a total of 6 bits including code bits. Further, in FIG. 11, a variable node calculation of the LDPC code represented by the parity check matrix of FIG. 8 is performed. Further, the variable node computer 103 of FIG. 11 is supplied with a clock ck, and the clock ck is supplied to a necessary block. Each block performs processing in synchronization with the clock ck.

  The variable node calculator 103 shown in FIG. 11 is supplied from the control unit 105, for example, based on a 1-bit control signal D107, and is read from the branch memory 102 one by one and the reception memory 104. Using received data D104, calculation is performed according to equation (1).

That is, the variable node calculator 103 reads 6-bit messages D103 (message u _j ) from the check node corresponding to each row of the check matrix one by one, and the message D103 is read into the adder 151 and the FIFO memory 155. Supplied. Further, the variable node calculator 103 reads 6-bit reception data D104 one by one from the reception memory 104 and supplies it to the adder 156. Further, the control signal D107 is supplied from the control unit 105 to the variable node calculator 103, and the control signal D107 is supplied to the selector 153.

The adder 151 adds the message D103 (message u _j ) and the 9-bit value D151 stored in the register 152 to accumulate the message D103, and the resulting 9-bit accumulated value is stored in the register. Store again in 152. Note that when the messages D103 from all branches over one column of the check matrix are accumulated, the register 152 is reset.

  When the message D103 over one column of the check matrix is read one by one and the value obtained by integrating the message D103 for one column is stored in the register 152, the control signal D107 supplied from the control unit 105 is “0”. To "1". For example, when the column weight is “5”, the control signal D107 is “0” from the first to the fourth clock, and “1” at the fifth clock.

When the control signal D107 is “1”, the selector 153 has 9 bits obtained by integrating the values stored in the register 152, that is, the messages D103 (message u _j ) from all branches over one column of the check matrix. select the value D151 (? uj _j from j = 1 to d _V), and stores and outputs to the register 154. The register 154 supplies the stored value D151 to the selector 153 and the adder / subtracter 156 as a 9-bit value D152. When the control signal D107 is “0”, the selector 153 selects the value D152 supplied from the register 154, outputs it to the register 154, and stores it again. That is, until the message D103 (message u _j ) from all branches over one column of the check matrix is accumulated, the register 154 supplies the previously accumulated value to the selector 153 and the adder / subtractor 156.

On the other hand, FIFO memories 155, between (from j = 1? Uj _j to d _V) a new value D152 from the register 154 until the output delays the message D103 from check nodes, as a 6-bit value D153 This is supplied to the adder / subtracter 156. The adder / subtracter 156 subtracts the value D153 supplied from the FIFO memory 155 from the value D152 supplied from the register 154. That is, the adder / subtracter 156 subtracts the message u _j from the branch to be obtained from the integrated value of the message D103 (message u _j ) from all branches over one column of the check matrix, and the subtraction value (j = Find Σu _j ) from 1 to d _v −1. Further, the adder / subtracter 156 adds the reception data D104 supplied from the reception memory 104 to the subtraction value (Σu _j from j = 1 to d _v −1), and a 6-bit obtained as a result. The value is output as message D105 (message v _i ).

As described above, the variable node calculator 103 performs the calculation of Expression (1) to obtain the message v _i .

Since the maximum column weight of the parity check matrix in FIG. 8 is 5, that is, the maximum number of messages supplied to the variable node is 5, the variable node calculator 103 uses five messages (u a FIFO memory 155 for delaying _j ). When calculating a message for a column with a column weight less than 5, the amount of delay in the FIFO memory 155 is reduced to the value of the column weight.

  In the decoding apparatus in FIG. 9, a control signal is given from the control unit 105 according to the weight of the check matrix. Then, according to the decoding apparatus of FIG. 9, only the control signal is changed as long as the capacity of the FIFO memories 127, 133, and 155 of the branch memories 100 and 102 and the check node calculator 101 and the variable node calculator 103 is sufficient. Thus, LDPC codes of various check matrices can be decoded.

  Although not shown in the figure, in the decoding apparatus of FIG. 9, in the final stage of decoding, the calculation of Expression (5) is performed instead of the variable node calculation of Expression (1). Output as decryption result.

  When the LDPC code is decoded by repeatedly using the decoding device of FIG. 9, the check node calculation and the variable node calculation are alternately performed. That is, in the decoding apparatus of FIG. 9, the variable node calculation is performed by the variable node calculator 103 using the check node calculation result by the check node calculator 101, and the variable node calculation result by the variable node calculator 103 is used. Thus, the check node calculator 101 performs a check node calculation.

  Therefore, 269 × 2 = 538 clocks are required for one decoding using the parity check matrix of FIG. 8 having 269 branches. For example, in order to perform 50 times of iterative decoding, it is necessary that 90 codes (received data), which is the code length, be one frame, and that 538 × 50 = 26900 clock operation be performed during the reception of that one frame. Therefore, a high-speed operation of about 300 (≈26900 / 90) times the reception frequency is required. If the reception frequency is several tens of MHz, operation at a speed of GHz or higher is required.

  In addition, for example, when decoding the LDPC code by connecting 50 decoding apparatuses as shown in FIG. 9, the check node calculation of the second frame is performed while the variable node calculation of the first frame is performed. A plurality of variable node computations and check node computations can be performed simultaneously, such as performing variable node computations in the third frame. In this case, since 269 branches may be calculated while 90 codes are received, the decoding apparatus only needs to operate at a frequency about 3 (≈269 / 90) times the reception frequency. Is fully feasible. However, in this case, the circuit scale is simply 50 times that of the decoding apparatus of FIG.

  Next, a description will be given of a method for implementing a decoding apparatus when decoding is performed by performing operations on all nodes simultaneously (full parallel decoding).

  This mounting method is described in Non-Patent Document 1, for example.

  FIG. 12 illustrates a configuration of an example of a decoding device that decodes a code (coding rate 2/3, code length 90) represented by the parity check matrix in FIG.

  In the decoding device of FIG. 12, all message data corresponding to 269 branches are simultaneously read from the branch memory 202 or 206, and new message data corresponding to 269 branches are calculated using the message data. . Further, all new message data obtained as a result of the calculation are simultaneously stored in the subsequent branch memory 206 or 202. Then, iterative decoding is realized by repeatedly using the decoding device of FIG.

In FIG. 12, the decoding device includes one reception memory 205, two branch switching devices 200 and 203, two branch memories 202 and 206, thirty check node calculators 201 _{1 to} 201 ₃₀ , and 90 variable variables. The node calculators 204 _{1 to} 204 _{90 are included} . Hereinafter, each part will be described in detail.

Branch memory 206 stores all messages D206 ₁ to D206 ₉₀ from the preceding variable node calculator 204 ₁ to 204 ₉₀ At the same time, the next time (the timing of the next clock), a message D206 ₁ to D206 ₉₀ The messages D207 _{1 to} D207 ₉₀ are read out and supplied as messages D200 (D200 _{1 to} D200 ₉₀ ) to the branch switching apparatus 200 in the next stage. Branch swapping device 200, the order of the supplied message D200 ₁ to D200 ₉₀ from the branch memory 206, rearrangement according check matrix of FIG. 8 (replacement), the check node calculator 201 ₁ to 201 _30, the message D201 Supply as _{1 to} D201 ₃₀ .

The check node calculators 201 _{1 to} 201 ₃₀ perform computations according to the equation (7) using the messages D201 _{1 to} D201 ₃₀ supplied from the branch switching apparatus 200, and messages D202 _{1 to} D202 ₃₀ obtained as a result of the computations. Is supplied to the branch memory 202.

Branch memory 202, the message D202 ₁ to D202 ₃₀ supplied from the preceding check node calculator 201 ₁ to 201 ₃₀ store all simultaneously, the next time, all of its messages D202 ₁ to D202 _30, the message As D203 _{1 to} D203 ₃₀ , they are supplied to the branch replacement device 203 at the next stage.

Branch swapping device 203 rearranges the order of the supplied message D203 ₁ to D203 ₃₀ from the branch memory 202 in accordance with the parity check matrix of FIG. 8, the variable node calculator 204 ₁ to 204 _90, the message D 204 ₁ to D 204 ₉₀ Supply as.

The variable node calculators 204 _{1 to} 204 ₉₀ use the messages D204 _{1 to} D204 ₉₀ supplied from the branch switching device 203 and the received data D205 _{1 to} D205 ₉₀ supplied from the reception memory 205 to formula (1). Accordingly, an operation is performed, and messages D206 _{1 to} D206 ₉₀ obtained as a result of the operation are supplied to the branch memory 206 at the next stage.

FIG. 13 shows a configuration example of the check node calculator 201 _m (m = 1, 2,..., 30) of FIG.

The check node calculator 201 _m in FIG. 13 performs the check node calculation of Expression (7) in the same manner as the check node calculator 101 in FIG. 10, and the check node calculation is simultaneously performed for all branches. .

That is, the check node calculator 201 _m in FIG. 13 simultaneously reads all the messages D221 _{1 to} D221 ₉ (v _i ) from the variable nodes corresponding to the columns of the parity check matrix in FIG. are, respectively, the lower 5 bits in which the absolute value D222 ₁ to D222 ₉ (| v _i |) is supplied to LUT221 ₁ to 221 _9. Further, 1-bit sign bits D223 _{1 to} D223 ₉ which are the most significant bits of the messages D221 _{1 to} D221 ₉ (v _i ) are supplied to the EXOR circuits 226 _{1 to} 226 ₉ and supplied to the EXOR circuit 225, respectively. The

LUT221 ₁ to 221 _9, the absolute value D222 ₁ to D222 ₉ (| v _i |) with respect to, phi in the formula _{(7) (| v i |} ) 5 -bit operation result of the operation of D224 ₁ to D224 ₉ (φ (| v _i |)) is read out and supplied to the subtracters 223 _{1 to} 223 ₉ respectively. The LUTs 221 _{1 to} 221 ₉ supply the operation results D224 _{1 to} D224 ₉ (φ (| v _i |)) to the adder 222.

The adder 222 calculates the sum of the values of the calculation results D224 _{1 to} D224 ₉ (φ (| v _i |)) (sum of the calculation results for one row), and calculates the 9-bit calculation result D225 (from i = 1). 9 Σφ (| v _i |)) is supplied to the subtracters 223 _{1 to} 223 ₉ . The subtracters 223 _{1 to} 223 ₉ subtract the calculation results D224 _{1 to} D224 ₉ (φ (| v _i |)) from the calculation result D225, respectively, and subtract the 5-bit subtraction values D227 _{1 to} D227 ₉ to the LUTs 224 _{1 to} 224 ₉ That is, the subtracters 223 _{1 to} 223 ₉ obtain φ (|) obtained from the message v _i from the branch to be obtained from the integrated value of φ (| v _i |) obtained from the message v _i from all the branches. v _i |) is subtracted, and the subtraction values D227 _{1 to} D227 ₉ (Σφ (| v _i |) from i = 1 to 8) are supplied to LUTs 224 _{1 to} 224 ₉ , respectively. The LUTs 224 _{1 to} 224 ₉ perform 5-bit calculation results D228 _{1 to} D228 ₉ obtained by performing the calculation of φ ⁻¹ (Σφ (| v _i |)) in Expression (7) for the subtraction values D227 _{1 to} D227 ₉ . Is read and output.

On the other hand, EXOR circuit 225, by calculating all the exclusive OR of the sign bit D223 ₁ to D223 _9, multiplies the sign bits D223 ₁ to D223 _9, 1 bit multiplier D226 (for one row The multiplication value of the sign bit (i sign (v _i ) from 1 to 9) is supplied to the EXOR circuits 226 _{1 to} 226 ₉ , respectively. EXOR circuit 226 ₁ through 226 _9, by calculating an exclusive OR of the multiplication value D226 and the sign bit D223 ₁ to D223 ₉ respectively, 1-bit multiplication value D226, divided by the sign bit D223 ₁ to D223 ₉ respectively The division values D229 _{1 to} D229 ₉ (Πsign (v _i ) from i = 1 to 8) are obtained and output.

In the check node calculator 201 _m , the 5-bit calculation results D228 _{1 to} D228 ₉ output from the LUTs 224 _{1 to} 224 ₉ are set to the lower 5 bits, and the division value D229 output from the EXOR circuits 226 _{1 to} 226 ₉ is used. ₁ to D229 ₉ total 6 bits of the most significant bit, respectively, are outputted as a message D230 ₁ to D230 ₉ obtained as a result of the check node operation.

As described above, in the check node calculator 201 _m , the calculation of Expression (7) is performed and the message u _j is obtained.

In FIG. 13, the check node calculator 201 _m is represented on the assumption that each message is quantized to a total of 6 bits including the sign bit. The circuit in FIG. 13 corresponds to one check node. Since the check matrix of FIG. 8 to be processed here has 30 check nodes, which is the number of rows, the decoding device of FIG. 12 uses the check node calculator 201 _m as shown in FIG. 30 are included.

Here, the check node calculator 201 _m in FIG. 13 can simultaneously calculate nine messages. The weights of the check matrix in FIG. 8 to be processed here are 8 for the first row and 9 for the second to 30th rows, that is, the number of messages supplied to the check node. but one of 8 cases, for 9 cases 29, the check node calculator 201 ₁ has a circuit configuration that can calculate the same eight messages and the circuit of Figure 13 at the same time, the remaining The check node calculators 201 _{2 to 20 30} have the same configuration as the circuit of FIG.

FIG. 14 shows a configuration example of the variable node calculator 204 _p (p = 1, 2,..., 90) of FIG.

In the variable node calculator 204 _p in FIG. 14, the variable node calculation of Expression (1) is performed in the same manner as the variable node calculator 103 in FIG. 11, but the variable node calculation is simultaneously performed for all branches. .

That is, in the variable node calculator 204 _{p of} FIG. 14, all of the 6-bit messages D251 _{1 to} D251 ₅ (message u _j ) supplied from the branch replacement device 203 from the check nodes corresponding to each row of the check matrix are simultaneously transmitted. It is read and supplied to the adders 252 _{1 to} 252 ₅ and supplied to the adder 251. Further, the variable node calculator 204 _p, the reception data D271 supplied from the receiving memory 205, the received data D271 are supplied to the subtracter 252 ₁ to 252 _5.

The adder 251 accumulates all the messages D251 _{1 to} D251 ₅ (message u _j ), and adds a 9-bit accumulated value D252 (total value of messages for one column (Σu _j from j = 1 to 5)). The data is supplied to the adders / subtracters 252 _{1 to} 252 ₅ . The adders / subtracters 252 _{1 to} 252 ₅ subtract the messages D251 _{1 to} D251 ₅ (message u _j ) from the added value D252. That is, the adder / subtracters 252 _{1 to} 252 ₅ subtract the messages D251 _{1 to} D251 ₅ (message u _j ) from the branches to be obtained from the integrated values D252 of the messages u _j from all the branches, respectively. (Σu _j from j = 1 to 4) is obtained.

Further, the adder / subtracters 252 _{1 to} 252 ₅ add the reception data D271 (u _0i ) to the subtraction value (Σu _j from j = 1 to 4), and add 6-bit addition values D253 _{1 to} D253 ₅ , Output as a result of variable node operation.

As described above, the variable node calculator 204 _p performs the calculation of Expression (1) to obtain the message v _i .

In FIG. 14, the variable node calculator 204 _p is represented on the assumption that each message is quantized to a total of 6 bits including the sign bits. The circuit in FIG. 14 corresponds to one variable node. Since the parity check matrix in FIG. 8 to be processed here has 90 variable nodes, which is the number of columns, the decoding device in FIG. 12 has 90 circuits as shown in FIG. ing.

Here, the variable node calculator 204 _p in FIG. 14 can simultaneously calculate five messages. 8 has 15 columns, 45 columns, 29 columns, and 1 column, respectively, so that the variable node calculator 204 has the columns of weights 5, 3, 2, and 1, respectively. the 15 of ₁ to 204 _90, and a circuit having the same configuration of Figure 14, the remaining 45, 29, one is the same 3,2,1 single message and the circuit of Figure 14 Each circuit configuration can be calculated simultaneously.

  Although not shown, in the decoding apparatus of FIG. 12 as well, in the final stage of decoding, the calculation of Expression (5) is performed instead of the variable node calculation of Expression (1). The calculation result is output as the final decoding result.

  According to the decoding apparatus of FIG. 12, all the messages corresponding to 269 branches can be calculated simultaneously in one clock.

  When the decoding apparatus of FIG. 12 is repeatedly used for decoding, check node calculation and variable node calculation can be alternately performed, and one decoding can be performed in two clocks. Therefore, for example, in order to perform decoding 50 times, it is only necessary to operate 2 × 50 = 100 clocks during reception of reception data having a code length of 90 codes as one frame, and the reception frequency is almost the same. The same operating frequency is sufficient. In general, an LDPC code has a code length as large as several thousand to several tens of thousands. Therefore, if the decoding apparatus shown in FIG. 12 is used, the number of times of decoding can be extremely increased, and an improvement in error correction performance can be expected. it can.

  However, since the decoding apparatus of FIG. 12 performs message operations corresponding to all branches of the Tanner graph in parallel, the circuit scale increases in proportion to the code length. In addition, when the decoding apparatus of FIG. 12 is configured as an apparatus that decodes an LDPC code having a certain check length and having a certain coding rate, in the decoding apparatus, other code lengths, It becomes difficult to decode an LDPC code having a coding rate and another check matrix. That is, like the decoding device of FIG. 9, the decoding device of FIG. 12 is difficult to cope with decoding various codes only by changing the control signal, and has high code dependency.

Also, a method of approximating and implementing the sum product algorithm has been proposed, but this method causes performance degradation.
C. Howland and A. Blanksby, "Parallel Decoding Architectures for Low Density Parity Check Codes", Symposium on Circuits and Systems, 2001

  In the decoding device of FIG. 9, two memories, a branch memory 100 for storing the calculation result of the variable node and a branch memory 102 for storing the calculation result of the check node, are provided, and the branch memory 100 and the branch memory 102 are provided. Since messages corresponding to the total number of branches are stored, there is a problem that a large-capacity memory is required and the circuit scale of the decoding device increases.

  In addition, since the decoding device of FIG. 9 includes two calculators, the check node calculator 101 and the variable node calculator 103, the circuit scale of the decoding device increases.

  As described above, the decoding device of FIG. 9 has a problem that the circuit scale becomes large, resulting in an increase in cost and an increase in power consumption of the device.

  The present invention has been made in view of such a situation, and makes it possible to reduce the circuit scale of a decoding device.

  The first decoding apparatus of the present invention requires check node calculation means for performing a check node operation for decoding an LDPC code using a necessary message, and a variable node operation for decoding an LDPC code. Variable node calculation means using a message, storage means for storing a check node calculation or a message obtained as a result of variable node calculation, and a message stored in the storage means for check node calculation means or variable And a supply means for selecting and supplying one of the node calculation means.

  The storage means may be a dual port RAM (Random Access Memory) or a single port RAM (Random Access Memory).

  A first decoding method of the present invention includes a check node calculation step in which a check node calculation for decoding an LDPC code by a check node calculation unit is performed using a necessary message, and decoding of an LDPC code by a variable node calculation unit. Variable node calculation step for performing a variable node calculation for the required message, a storage step for storing a check node or a message obtained as a result of the variable node calculation in the storage unit, and storing in the storage unit And a supplying step of supplying the received message to one of the check node calculation means and the variable node calculation means.

  The first program of the present invention includes a check node calculation step in which a check node calculation for decoding an LDPC code by a check node calculation unit is performed using a necessary message, and decoding of an LDPC code by a variable node calculation unit. Variable node calculation step for performing a variable node calculation for the required message, a storage step for storing a check node or a message obtained as a result of the variable node calculation in the storage unit, and storing in the storage unit A supply step of supplying the received message to one of the check node calculation means and the variable node calculation means.

The second decoding apparatus of the present invention includes: a selection unit that selects one of a check node calculation for decoding an LDPC code or a variable node calculation; and a check node selected by the selection unit, or A node calculation means for performing a variable node operation using a necessary message; a storage means for storing a check node operation by the node calculation means or a message obtained as a result of the variable node operation;
And a supply means for supplying the message stored in the storage means to the node calculation means.

  The storage means may be a dual port RAM (Random Access Memory) or a single port RAM (Random Access Memory).

  The second decoding method of the present invention includes a selection step for selecting one of a check node operation for decoding an LDPC code or a variable node operation, and an operation for a check node selected by the processing of the selection step. Or a node calculation step for causing the node calculation means to perform a variable node calculation using a necessary message, and a message obtained as a result of the check node calculation or variable node calculation by the node calculation means is stored in the storage means. And a supplying step of supplying the message stored by the processing of the storing step to the node calculating means.

  A second program of the present invention includes a selection step for selecting one of a check node operation for decoding an LDPC code or a variable node operation, and a check node operation selected by the processing of the selection step, Alternatively, a node calculation step for causing the node calculation means to perform a variable node calculation using a necessary message and a message obtained as a result of the check node calculation or the variable node calculation by the node calculation means are stored in the storage means. A storage step and a supply step of supplying the message stored by the processing of the storage step to the node calculation means are provided.

  The third decoding apparatus according to the present invention requires check node calculation means for performing a check node operation for decoding an LDPC code using a necessary message, and a variable node operation for decoding an LDPC code. Variable node calculation means using a message, first storage means for storing a message obtained as a result of check node calculation, and second storage means for storing a message obtained as a result of variable node calculation, The first storage means and the second storage means are shared by one storage means.

  Further, the check node calculation means and the variable node calculation means can be shared by one node calculation means.

  In the first aspect of the present invention, the check node calculation for decoding the LDPC code is performed by using the necessary message by the check node calculation means, and the variable node calculation for decoding the LDPC code is performed by the variable node. This is done by using a necessary message by the calculation means. Then, a message obtained as a result of the check node calculation or the variable node calculation is stored, and the stored message is supplied by selecting one of the check node calculation means and the variable node calculation means.

  In the second aspect of the present invention, one of a check node operation or a variable node operation for decoding an LDPC code is selected, and the selected check node operation or variable node operation is performed as a node calculation. By means, the necessary message is used. Then, a message obtained as a result of the check node calculation or the variable node calculation is stored, and the stored message is supplied to the node calculation means.

  In the third aspect of the present invention, a check node operation for decoding an LDPC code is performed using a necessary message, and a variable node operation for decoding an LDPC code is performed using a necessary message. Is called. Then, a message obtained as a result of the check node calculation is stored in the first storage means, and a message obtained as a result of the variable node calculation is stored in the second storage means. The first storage means and the second storage means are shared by one storage means.

  According to the present invention, the circuit scale of the LDPC code decoding apparatus can be reduced, so that the cost can be reduced and the power consumption of the apparatus can be reduced.

  Embodiments of the present invention will be described below. Correspondences between constituent elements described in the claims and specific examples in the embodiments of the present invention are exemplified as follows. This description is to confirm that specific examples supporting the invention described in the claims are described in the embodiments of the invention. Therefore, even if there are specific examples that are described in the embodiment of the invention but are not described here as corresponding to the configuration requirements, the specific examples are not included in the configuration. It does not mean that it does not correspond to a requirement. On the contrary, even if a specific example is described here as corresponding to a configuration requirement, this means that the specific example does not correspond to a configuration requirement other than the configuration requirement. not.

  Further, this description does not mean that all the inventions corresponding to the specific examples described in the embodiments of the invention are described in the claims. In other words, this description is an invention corresponding to the specific example described in the embodiment of the invention, and the existence of an invention not described in the claims of this application, that is, in the future, a divisional application will be made. Nor does it deny the existence of an invention added by amendment.

  The decoding device according to claim 1, wherein the decoding device decodes an LDPC (Low Density Parity Check) code, and performs a check node operation for decoding the LDPC code using a necessary message. A calculation means (for example, the variable node calculator 312 in FIG. 15) and a variable node calculation means (for example, a check node calculation in FIG. 15) for performing a variable node calculation for decoding the LDPC code using a necessary message. 313), storage means (for example, branch memory 310 in FIG. 15) for storing a message obtained as a result of the check node operation or the variable node operation, and the message stored in the storage means Supply means for selecting and supplying one of the check node calculation means and the variable node calculation means (example: For example, a switch 311) in FIG. 15 is provided.

The decoding method according to claim 3 is a decoding method of a decoding device for decoding an LDPC (Low Density Parity Check) code, and the LDPC code by a check node calculation means (for example, the check node calculator 313 in FIG. 15). The check node calculation step (for example, step S29 in FIG. 16) in which the calculation of the check node for decoding is performed using a necessary message, and the variable node calculation means (for example, the variable node calculator 312 in FIG. 15). A variable node calculation step (for example, step S23 in FIG. 16) in which a variable node calculation for decoding an LDPC code is performed using a necessary message, and the result of the check node calculation or the variable node calculation are obtained. Storing the stored message in the storage means, and storing the message in the storage means The message, characterized in that it comprises a said check node calculation means or supplying step of supplying to one of the variable node calculation means (e.g., step S22 or step S28 in FIG. 16).

  The decoding device according to claim 5 is a decoding device that decodes an LDPC (Low Density Parity Check) code, and performs one of a check node operation and a variable node operation for decoding the LDPC code. A selection means (for example, the control unit 356 in FIG. 17) to select, and a node calculation means (for example, to perform the calculation of the check node selected by the selection means or the calculation of the variable node using a necessary message) The node calculator 354) of FIG. 17 and a storage means (for example, branch memory 351 or 352 of FIG. 17) for storing a message obtained as a result of the computation of the check node by the node computation means or the computation of the variable node. And supply means for supplying the message stored in the storage means to the node calculation means (for example, in FIG. And a switch 350).

  The decoding method according to claim 7 is a decoding method of a decoding device that decodes an LDPC (Low Density Parity Check) code, and includes a check node calculation or a variable node calculation for decoding the LDPC code. A selection step (for example, step S41 or step S47 in FIG. 19), and the calculation of the check node selected by the processing of the selection step or the calculation of the variable node is performed by a node calculation means (for example, A node calculation step (for example, step S43 or step S49 in FIG. 19) that causes the node calculator 354) in FIG. 17 to perform using a necessary message, the calculation of the check node by the node calculation means, or the variable node A message obtained as a result of the operation of the storage means (for example, the branch memory 3 in FIG. 51 or 352) and a supply step (for example, FIG. 19) for supplying the message stored by the processing of the storage step to the node calculation means. Step S42 or step S48).

The decoding device according to claim 9, check node calculation means (for example, check node calculator 312 in FIG. 15) that performs a check node operation for decoding the LDPC code using a necessary message; Variable node calculation means (for example, variable node calculator 312 in FIG. 15) that performs a variable node calculation for decoding an LDPC code using a necessary message, and a message obtained as a result of the check node calculation are stored. First storage means (for example, the branch memory 310 in FIG. 15) and second storage means (for example, the branch memory 310 in FIG. 15) for storing a message obtained as a result of the variable node calculation; The first storage unit and the second storage unit are shared by one storage unit.

  The decoding device according to claim 10 is the decoding device according to claim 9, and further includes the check node calculation means (for example, the node calculator of FIG. 17) and the variable node calculation means (for example, FIG. 17). Node calculator) is shared by one node calculation means.

  A specific example of each step of the program according to claim 4 is also a specific example in the embodiment of the invention of each step of the decoding method according to claim 3, and a specific example of each step of the program according to claim 8. Is the same as the specific example in the embodiment of the invention of each step of the decoding method according to claim 7.

  Hereinafter, specific embodiments to which the present invention is applied will be described in detail with reference to the drawings.

  FIG. 15 is a block diagram showing a configuration example of an embodiment of a decoding device to which the present invention is applied.

  FIG. 15 illustrates an example of a decoding device 300 that performs one decoding of an LDPC code. The iterative decoding can be performed by connecting a plurality of decoding devices 300 in a column or using the decoding devices 300 repeatedly.

  The decoding device 300 includes a branch memory 310, a switch 311, a variable node calculator 312, a check node calculator 313, a selector 314, a reception memory 315, and a control unit 316.

In the decoding device 300, a message (message v _i ) corresponding to a branch obtained as a result of the variable node calculation by the variable node calculator 312 or a message corresponding to a branch obtained as a result of the check node calculation by the check node calculator 313. (Message u _j ) is stored in one branch memory 310.

  In the branch memory 310, a message (data) D314 corresponding to a branch obtained as a result of the variable node calculation by the variable node calculator 312 or a message corresponding to a branch obtained as a result of the check node calculation by the check node calculator 313 ( One of the data (D315) is supplied from the selector 314 as the message D310. The branch memory 310 stores (stores) the message D310 supplied from the selector 314, and supplies the already stored message D311 to the switch 311. When the branch memory 310 stores the message D315 corresponding to the branch obtained as a result of the last check node calculation by the check node calculator 313, the message D315 is subjected to the calculation of the above-described equation (5). Supply to a block (not shown)

  That is, the branch memory 310 reads one message D310 supplied from the selector 314 and stored in the order that the variable node calculator 312 or the check node calculator 313 operates, and sends it to the switch 311 as a message D311. At the same time, the message D310 output from the selector 314 is received and written to the address where the already read message (message D311) of the branch memory 310 is stored. That is, the branch memory 310 simultaneously reads the message (data) D311 supplied to the switch 311 and writes the message (data) D310 supplied from the selector 314.

  The branch memory 310 stores a message corresponding to a branch calculated by the variable node calculation of the variable node calculator 312 or the check node calculation of the check node calculator 313. Therefore, the branch memory 310 stores the message. The amount of data to be processed, that is, the storage capacity required for the branch memory 310 is a product of the number of quantization bits of the message and the total number of branches. The same applies to the branch memory 100 and the branch memory 102 shown in FIG.

  Further, the branch memory 310 can be configured by, for example, a dual port RAM capable of reading and writing simultaneously.

  The switch 311 is supplied with a message D311 from the branch memory 310 and a selection signal D323 indicating selection of one of the variable node calculator 312 or the check node calculator 313 from the control unit 316. The switch 311 supplies the message D311 to one of the variable node calculator 312 or the check node calculator 313 based on the selection signal D323. That is, the switch 311 supplies the message D311 to the variable node calculator 312 as the message D312 or to the check node calculator 313 as the message D313.

The variable node calculator 312 is supplied from the switch 311 with a message D312 necessary for variable node calculation. The variable node calculator 312 is supplied with the control signal D321 from the control unit 316 and is also supplied with the reception data D316 of the LDPC code from the reception memory 315. Based on the control signal D321, the variable node calculator 312 uses the message D312 supplied from the switch 311 and the reception data D316 supplied from the reception memory 315, similarly to the variable node calculator 103 of FIG. A variable node operation for decoding the LDPC code is performed according to the equation (1), and a message D314 (message v _i ) corresponding to the branch obtained as a result of the operation is supplied to the selector 314. The detailed configuration of the variable node calculator 312 is the same as that of the variable node calculator 103 shown in FIG.

The check node calculator 313 is supplied from the switch 311 with a message D313 necessary for the check node calculation, and also supplied with a control signal D322 from the control unit 316. Based on the control signal D322 supplied from the control unit 316, the check node calculator 313 uses the message D313 supplied from the switch 311 as in the above-described check node calculator 101 in FIG. Accordingly, the check node for decoding the LDPC code is calculated, and the message D315 (message u _j ) obtained by the calculation is supplied to the selector 314. The detailed configuration of the check node calculator 313 is the same as that of the check node calculator 101 shown in FIG.

  The selector 314 is supplied with a selection signal D323 indicating selection of one of the variable node calculator 312 or the check node calculator 313 from the control unit 316. The selector 314 is supplied with the message D314 from the variable node calculator 312 and the message D315 from the check node calculator 313. The selector 314 selects either the message D314 or the message D315 based on the selection signal D323, and supplies the selected message D314 to the branch memory 310 as the message D310.

  The reception memory 315 stores (stores) LDPC-encoded reception data (LDPC code) D316. The reception memory 315 reads the stored reception data D316 and supplies it to the variable node calculator 312 and a block (not shown) that performs the calculation of Expression (5).

  The reception data is supplied from the reception unit (not shown) to the reception memory 315 and stored. The amount of data stored in the reception memory 315, that is, the storage capacity required for the reception memory 315 is a product of the code length of the LDPC code and the number of quantization bits of the reception data.

  The control unit 316 controls the variable node calculator 312 by supplying the control signal D321 to the variable node calculator 312 and supplies the control signal D322 to the check node calculator 313, thereby causing the check node calculator 313 to Control. In addition, the control unit 316 controls the switch 311 and the selector 314 by supplying a selection signal D323 indicating selection of one of the variable node calculator 312 and the check node calculator 313 to the switch 311 and the selector 314. .

  FIG. 16 is a flowchart for explaining the decoding process of the decoding device 300 of FIG. This process is started, for example, when reception data to be decoded is stored in the reception memory 315.

  In step S21, the control unit 316 selects the variable node calculator 312 from among the variable node calculator 312 and the check node calculator 313, generates a selection signal D323 indicating the selection, and sends the selection signal D323 to the switch 311 and the selector 314. Supply.

After the process of step S21, the process proceeds to step S22, and the switch 311 selects one of the variable node calculator 312 and the check node calculator 313 based on the control signal D323 supplied in step S21, and selects the selected node. One computer is supplied with the message D310 (message u _j ) stored in step S31, which will be described later, read out one by one from the branch memory 310 as the message D311. That is, here, since the control signal D323 supplied in step S21 represents selection of the variable node calculator 312, the switch 311 selects the variable node calculator 312 and selects the selected variable node calculator 312. In addition, a message D311 necessary for variable node calculation is supplied as a message D312.

  Note that when the check node operation is not yet performed on the reception data D316 supplied from the reception memory 315 and the message D311 is not stored in the branch memory 310, the variable node calculator 312 Sets the message used for node operation to the initial value.

  After the processing of step S22, the process proceeds to step S23, and the variable node calculator 312 performs variable node calculation. That is, the variable node calculator 312 is supplied with the reception data D316 from the reception memory 315 and the control signal D321 from the control unit 316. Based on the control signal D321, the variable node calculator 312 uses the received data D316 and the message D312 supplied from the switch 311 in step S22 to calculate the variable node according to the above-described equation (1).

  That is, the control signal D321 supplied from the control unit 316 to the variable node calculator 312 corresponds to the control signal D107 described with reference to FIG. 11, and the variable node calculator 312 switches according to the control signal D321. A necessary message D311 (D312) is read out from the branch memory 310 via 311 and a variable node calculation is performed using the reception data D316 supplied from the reception memory 315.

After the process of step S23, the process proceeds to step S24, and the variable node calculator 312 outputs the message D314 (message v _i ) obtained as a result of the variable node calculation to the selector 314, and the process proceeds to step S25.

  In step S25, the selector 314 selects one of the variable node calculator 312 and the check node calculator 313 based on the selection signal D323 supplied in step S21, and outputs a message output from the selected one. The message D310 is stored in the branch memory 310. Here, since the selection signal D323 indicates selection of the variable node calculator 312, the selector 314 outputs the message D314 obtained as a result of the variable node calculation output in step S24 to the branch memory 310 as the message D310. Store. In other words, the selector 314 supplies the branch memory 310 with the message output from the calculator currently performing the computation among the variable node calculator 312 and the check node calculator 313 and stores it.

  After the processing of step S25, the process proceeds to step S26, and the control unit 316 determines whether or not the message of the total number of branches has been calculated by the variable node calculator 312 and determines that the message of the total number of branches has not been calculated. If so, the process returns to step S22 and the above-described processing is repeated.

  On the other hand, in step S26, when the control unit 316 determines that the message of the total number of branches has been calculated by the variable node calculator 312, the process proceeds to step S27, and the control unit 316 selects the check node calculator 313, The control signal D323 indicating selection of the variable node calculator 312 generated in step S21 is changed to a control signal D323 indicating selection of the check node calculator 313.

After the process of step S27, the process proceeds to step S28, and the switch 311 selects one of the variable node calculator 312 and the check node calculator 313 based on the control signal D323 changed in step S27, and selects the selected node. On the other hand, the message D310 (message v _i ) stored in step S25, which is read one by one as the message D311 from the branch memory 310, is supplied. Here, since the control signal D323 changed in step S27 represents the selection of the check node calculator 312, the switch 311 selects the check node calculator 313, and the selected check node calculator 313 A message D311 necessary for the check node calculation is supplied as a message D313.

  After the process of step S28, the process proceeds to step S29, and the check node calculator 313 performs a check node calculation. That is, the control signal D322 is supplied from the control unit 316 to the check node calculator 313. Based on the control signal D322, the check node calculator 313 performs a check node calculation according to the above-described equation (7) using the message D313.

  That is, the control signal D322 supplied from the control unit 316 to the check node calculator 313 corresponds to the control signal D106 described with reference to FIG. 10, and the check node calculator 313 switches according to the control signal D322. The check node is calculated while reading out the necessary message D313 from the branch memory 310 via 311.

After the processing of step S29, the process proceeds to step S30, where the check node calculator 313 outputs a message D315 (message u _j ) obtained as a result of the check node calculation to the selector 314, and proceeds to step S31.

  In step S31, the selector 314 selects one of the variable node calculator 312 and the check node calculator 313 based on the selection signal D323 changed in step S27, and outputs a message output from the selected one. The message D310 is supplied to the branch memory 310 and stored. Here, since the selection signal D323 indicates the selection of the check node calculator 313, the selector 314 outputs the message D315 obtained as a result of the check node calculation output in step S30 to the branch memory 310 as the message D310. Store. In other words, the selector 314 supplies the branch memory 310 with the message output from the calculator currently performing the computation among the variable node calculator 312 and the check node calculator 313 and stores it.

  After the processing of step S31, the process proceeds to step S32, and the control unit 316 determines whether or not the message of all branches is calculated by the check node calculator 313, and determines that the message of all branches is not calculated. If so, the process returns to step S28 and the above-described processing is repeated.

  On the other hand, when the check node calculator 312 determines that the message of the total number of branches has been calculated in step S32, the control unit 316 ends the process.

Note that the decoding device 300 repeats the decoding process of FIG. 16 as many times as the number of decoding, and when the message D315 (message u _j ) obtained as a result of the last check node operation is stored in the branch memory 310, the branch memory 310 supplies the message D315 to a block (not shown) that performs the calculation of the above-described equation (5). The block (not shown) is further supplied with reception data D316 from the reception memory 315. The block (not shown) uses the message D315 and the reception data D316 to perform the calculation of Expression (5), and the calculation result is obtained. Output as the final decoding result.

As described above, the branch memory 310 stores a message output from the calculator currently performing the computation among the variable node calculator 312 and the check node calculator 313. That is, the variable node operation is performed using the message u _j that is the result of the check node operation, and the check node operation is performed using the message v _i that is the result of the variable node operation. Variable node calculation and check node calculation are performed alternately. Therefore, by storing the message output from the calculator currently performing the calculation among the variable node calculator 312 and the check node calculator 313, the branch memory storing the result of the variable node calculation and the check are stored. The branch memory for storing the result of the node operation can be shared into one memory, and the branch memory 100 for storing the message obtained as a result of the variable node operation and the message obtained as a result of the check node operation are stored. The circuit scale of the decoding device 300 can be reduced as compared with the decoding device of FIG. 9 having the branch memory 102 separately.

  The branch memory 310 may be composed of a plurality of single port RAMs instead of the dual port RAMs. In this case, it is necessary to perform control so that reading and writing to one single-port RAM do not overlap at the same time. When a plurality of single-port RAMs are used, the circuit scale of the decoding device 300 can be reduced as compared with the case where a dual-port RAM is used.

  FIG. 17 is a block diagram showing a configuration example of another embodiment of a decoding device to which the present invention is applied.

  Note that FIG. 17 illustrates an example of a decoding device 340 that performs one decoding of an LDPC code. The iterative decoding can be performed by connecting a plurality of decoding devices 340 in cascade or by repeatedly using the decoding device 340.

  The decoding device 340 includes a switch 350, a branch memory 351, a branch memory 352, a selector 353, a node calculator 354, a reception memory 355, and a control unit 356.

In the decoding device 340, the node calculator 354 alternately performs a variable node calculation and a check node calculation, and a message (message v _i ) obtained as a result of the variable node calculation and a message (message u _j ) obtained as a result of the check node calculation are displayed. , And stored in the branch memory 351 or the branch memory 352. That is, the variable node calculator and the check node calculator are shared, and one variable calculator 354 performs both the variable node calculation and the check node calculation.

  The switch 350 is supplied with a message D350 from the node calculator 354, and represents selection of either the branch memory 351 or the branch memory 352 as a memory for storing (writing) the message D350 from the control unit 356. A selection signal D363 is supplied. Based on the selection signal D363, the switch 350 supplies the message D350 supplied from the node calculator 354 to the branch memory 351 as the message D351 or to the branch memory 352 as the message D352.

  For example, a message D350 corresponding to a branch obtained as a result of the variable node calculation by the node calculator 312 is supplied from the switch 350 to the branch memory 351 as a message D351. The branch memory 351 stores the message D351 in the order in which the check node calculation is performed. Then, the branch memory 351 supplies the message D351 to the selector 353 as the message D353 in the stored order.

  For example, a message D350 corresponding to a branch obtained as a result of the check node calculation by the node calculator 354 is supplied from the switch 350 to the branch memory 352 as a message D352. The branch memory 352 stores the message D352 in the order in which the variable node calculation is performed. Then, the branch memory 352 supplies the message D352 to the selector 353 as the message D354 in the stored order. When the branch memory 352 stores a message D350 obtained as a result of the last check node calculation by the node calculator 354, the message D350 is a block (not shown) that performs the calculation of the above-described equation (5). To supply.

  The branch memory 351 stores a message corresponding to the branch obtained as a result of the variable node calculation of the node calculator 354, and the branch memory 352 obtains the result of the check node calculation of the node calculator 354. Since the messages corresponding to the branches are stored, the amount of data stored in the branch memory 351 and the branch memory 352, that is, the storage capacity required for the branch memory 351 and the branch memory 352 is determined as follows. This is a product of the number of quantization bits and the number of all branches.

  The selector 353 is supplied with the message D353 from the branch memory 351 and the message D354 from the branch memory 352. The selector 353 is supplied with a selection signal D364 indicating selection of one of the branch memory 351 and the branch memory 352 as a memory for reading a message to be supplied from the control unit 356 to the node calculator 354. The selector 353 selects one of the branch memory 351 and the branch memory 352 based on the selection signal D364, and a message (message D353 or message D354) stored from the selected branch memory is used as the message D355. To the node calculator 354.

  The node calculator 354 is supplied with the message D355 from the selector 353 and the reception data D356 from the reception memory 355. Further, the node calculator 354 receives from the control unit 356 a selection signal D361 representing one of a variable node calculation and a check node calculation as a calculation performed by the node calculator 354, and a control for controlling the node calculation. Signal D362 is provided. Based on the selection signal D361, the node calculator 354 performs the operation selected by the control unit 356 among the variable node calculation and the check node calculation. That is, the node calculator 354 uses the message D355 supplied from the selector 353 and the reception data D356 supplied from the reception memory 355 based on the control signal D362 to decode the LDPC code according to the equation (1). Or the check node for decoding the LDPC code is performed according to Expression (7) using the message D355 supplied from the selector 353.

Then, the node calculator 354 supplies a message (message v _i or message u _j ) corresponding to a branch obtained as a result of the variable node calculation or the check node calculation to the switch 350 as a message D350.

  The reception memory 355 stores (stores) LDPC-encoded reception data (LDPC code) D356. The reception memory 355 reads the stored reception data D356 and supplies it to the node calculator 354 and a block (not shown) that performs the calculation of Expression (5).

  The reception data is supplied to and stored in the reception memory 355 from a reception unit (not shown). The amount of data stored in the reception memory 355, that is, the storage capacity required for the reception memory 355 is a product of the code length of the LDPC code and the number of quantization bits of the reception data.

  The control unit 356 selects one of the variable node calculation and the check node calculation as the calculation performed by the node calculator 354 and supplies the selection signal D361 indicating the selection and the control signal D362 to the node calculator 354. Thus, the node calculator 354 is controlled. In addition, the control unit 356 selects one of the branch memory 351 and the branch memory 352 as a memory for reading, and selects the other as a memory for writing. Then, the control unit 356 supplies a selection signal D363 indicating selection of one of the branch memory 351 and the branch memory 352 to the switch 350 as a memory for storing (writing) the message D350. The selector 353 is controlled by supplying a selection signal D364 representing the other selection to the selector 353 as a memory for reading the message D355 supplied to the node calculator 354.

  FIG. 18 is a block diagram illustrating a configuration example of the node calculator 354 of FIG.

  The node calculator 354 in FIG. 18 performs a check node operation or a variable node operation.

  In FIG. 18, the node calculator 354 is represented on the assumption that each message is quantized to a total of 6 bits including the sign bits. Further, a clock ck is supplied to the node calculator 354 of FIG. 18, and this clock ck is supplied to a necessary block. Each block performs processing in synchronization with the clock ck.

  The node calculator 354 of FIG. 18 reads from the branch memory 351 or the branch memory 352 one by one based on, for example, the 1-bit control signal D362 and the 1-bit selection signal D361 supplied from the control unit 356. Then, using the message D355 required for the check node calculation supplied via the selector 353, the check node calculation is performed according to the equation (7), or the message D355 required for the variable node calculation and the reception memory 355 are used. A variable node calculation is performed according to the equation (1) using the supplied reception data D356.

  That is, in the node calculator 354, a 6-bit message from the variable node corresponding to each column of the check matrix or a 6-bit message from the check node corresponding to each row of the check matrix is read one by one as the message D355. Then, the absolute value D402 which is the lower 5 bits is supplied to the LUT 401, and the sign bit D401 which is the most significant bit is supplied to the EXOR circuit 411 and the FIFO memory 415, respectively. In the node calculator 354, a 6-bit message D355 read one by one is supplied to the selector 402.

  Further, the control signal D362 is supplied from the control unit 356 to the node calculator 354, and the control signal D362 is supplied to the selector 405 and the selector 413. The node calculator 354 is supplied from the control unit 356 with a selection signal D361 representing one of the check node calculation and variable node calculation as the calculation performed by the node calculator 354, and the selection signal D361. Is supplied to the selector 402 and the selector 419. Further, the reception data D356 is supplied from the reception memory 355 to the node calculator 354, and the reception data D356 is supplied to the adder 417.

First, the processing of the node calculator 354 when a 6-bit message (message u _j ) from the check node corresponding to each row of the check matrix is read one by one as the message D355 will be described. At this time, the control unit 356 selects the variable node operation of the check node operation or the variable node operation as the operation to be performed by the node calculator 354 and checks the branch memory 351 or the branch memory 352. The selector 353 is supplied with a control signal D364 that selects the branch memory 352 storing a message corresponding to the branch from the node as a memory for reading the message. Further, since the control unit 356 has selected the variable node calculation as the calculation performed by the node calculator 354, the value of the control signal D362 for controlling the node calculation is displayed in one column by the node calculator 354. Each time a message is read, it is changed from “0” to “1”. Furthermore, the control unit 356 supplies a control signal D361 indicating selection of variable node calculation to the node calculator 354.

  Thus, when the variable node operation is selected by the control unit 356 as the operation to be performed by the node calculator 354, the node calculator 354 is supplied from the control unit 356, for example, a 1-bit control signal. Based on D362, using the message D355 read one by one from the branch memory 351 or the branch memory 352, the calculation is performed according to Expression (1).

  When the node calculator 354 performs variable node calculation, the selector 402 selects the value D355 from the message D355 and the value D404 based on the control signal D361 supplied from the control unit 356, and the selector 419 A value D421 is selected from the values D421 and D419. Therefore, in the following description, only calculation of values selected by the selector 402 and the selector 419 will be described.

The node calculator 354 reads one 6-bit message D355 (message u _j ) from the check node corresponding to each row of the parity check matrix, and the 6-bit message D355 is passed through the selector 402 as a value D405. The data is supplied to the adder 403 and the FIFO memory 408.

The adder 403 adds the value D405 (u _j ) and the 9-bit value D406 stored in the register 404 to add up the value D405, and the resulting 9-bit integrated value is stored in the register 404. Store again. Note that when the messages D355 from all branches over one column of the check matrix are accumulated, the register 404 is reset.

  When the message D355 over one column of the check matrix is read one by one and the accumulated value obtained by accumulating the value D405 for one column is stored in the register 404, the control signal D362 supplied from the control unit 356 is 0. Changes from 1 to 1. For example, when the row weight is “5”, the control signal D362 is “0” from the first to the fourth clock, and “1” at the fifth clock.

When the control signal D362 is “1”, the selector 405 adds the value stored in the register 404, that is, 9 bits obtained by integrating the message D355 (message u _j ) from all branches over one column of the check matrix. select the value D406 (? uj _j from j = 1 to j = d _v), as a value D407, and stores and outputs to the register 406. The register 406 supplies the stored value D407 to the selector 405 and the adder 407 as a 9-bit value D408.

When the control signal D362 is “0”, the selector 405 selects the value D408 supplied from the register 406, outputs it to the register 406, and stores it again. That is, the register 406 supplies u _j accumulated last time to the selector 405 and the adder 407 until the message D355 (message u _j ) from all the branches over one column of the check matrix is accumulated.

On the other hand, FIFO memories 408, between (from j = 1? Uj _j to j = d _v) a new value D408 from the register 406 until the output of the 6-bit selector 402 outputs a value D405 (u _j) Is supplied to the subtractor 407 as a 6-bit value D409. The subtractor 407 subtracts the value D409 supplied from the FIFO memory 408 from the value D408 supplied from the register 406, and supplies the subtraction result to the clip circuit 409 and the adder 417 as a 9-bit subtraction value D410. To do. That is, the subtractor 407, from the integrated value of message D355 (message u _j) from all of the branches across one row of the check matrix, by subtracting the messages from a desired branch D355 (message u _j), the subtraction The value (Σu _j from j = 1 to j = d _v −1) is supplied to the adder 417 as the subtraction value D410.

In the adder 417, a 9-bit subtraction value D410 is supplied from the subtractor 407, and a 60-bit reception value D356 is supplied from the reception memory 355. The adder 417 adds the reception data D356 (reception value u _0i ) supplied from the reception memory 355 to the subtraction value D410 (Σu _j from j = 1 to j = d _v −1), and the result The obtained 90-bit value D420 is supplied to the clip circuit 418.

The clip circuit 418 clips the 9-bit value D420 and outputs the lower 6-bit value D421 (message v _i ) as the message D350 via the selector 419.

As described above, when the variable node operation is selected as the operation performed by the node calculator 354 by the control unit 356, the node calculator 354 performs the operation of Expression (1) and obtains the message v _i. .

Next, the processing of the node calculator 354 when a 6-bit message (message v _i ) from the variable node corresponding to each column of the check matrix is read one by one as the message D355 will be described. At this time, the control unit 356 selects the check node operation of the check node operation or the variable node operation as the operation to be performed by the node calculator 354, and selects the variable memory from the branch memory 351 or the branch memory 352. The selector 353 is supplied with a control signal D364 for selecting the branch memory 351 storing a message corresponding to the branch from the node as a memory for reading the message. Further, since the control unit 356 has selected the check node calculation as the calculation performed by the node calculator 354, the value of the control signal D362 for controlling the node calculation is set to one line by the node calculator 354. Each time a message is read, it is changed from “0” to “1”. Further, the control unit 356 supplies a control signal D361 indicating selection of the check node calculation to the node calculator 354.

  As described above, when the check node calculation is selected by the control unit 356 as the calculation performed by the node calculator 354, the node calculator 354 supplies the control signal 356, for example, a 1-bit control signal. Based on D362, using the message D355 read one by one from the branch memory 351 or the branch memory 352, the calculation is performed according to Expression (7).

  When the node calculator 354 performs the check node calculation, the selector 402 selects the value D404 from the message D355 and the value D404 based on the control signal D361 supplied from the control unit 356, and the selector 419 The value D419 is selected from the value D421 and the value D419. Therefore, in the following description, only calculation of values selected by the selector 402 and the selector 419 will be described.

The node calculator 354 reads one 6-bit message D355 (message v _i ) from the variable node corresponding to each column of the parity check matrix one by one, and the absolute value D402 (| v _i |) which is the lower 5 bits thereof. Is supplied to the LUT 401 and the sign bit D401 (sign (v _i )) which is the most significant bit is supplied to the EXOR circuit 411 and the FIFO memory 415, respectively.

The LUT 401 reads the 5-bit calculation result D403 (φ (| v _i |)) obtained by performing the calculation of φ (| v _i |) in the expression (7) with respect to the absolute value D402 (| v _i |). ,Output. Then, in the read calculation result D403, 1-bit value “0” is added to the most significant bit to perform bit expansion, and the 6-bit value D404 ( φ (| v _i |)) is supplied to the adder 403 and the FIFO memory 408 through the selector 402 as a 6-bit value D405.

The adder 403 adds the value D405 (φ (| v _i |)) and the 9-bit value D406 stored in the register 404, thereby adding up the value D405, and the resulting 9-bit integration. The value is stored again in the register 404. Note that when the value D405 for the absolute value D402 (| v _i |) of the message D355 from all branches over one row of the check matrix is accumulated, the register 404 is reset.

  When the message D355 over one row of the check matrix is read one by one and the accumulated value obtained by accumulating the value D405 for one row is stored in the register 404, the control signal D362 supplied from the control unit 356 is 0. Changes from 1 to 1. For example, when the row weight is “9”, the control signal D362 is “0” from the first to the eighth clock, and “1” at the ninth clock.

When the control signal D362 is "1", the selector 405, the value stored in the register 404, i.e., phi obtained from the messages D355 from all of the branches across one line of the parity check matrix (message v _i) ( | v _i |) 9-bit value that is accumulated is D406 (Sigma] [phi of i = 1 through _{i = d c (| v i} |) select), as a value D407, and stores and outputs to the register 406. The register 406 supplies the stored value D407 to the selector 405 and the adder 407 as a 9-bit value D408.

When the control signal D362 is “0”, the selector 405 selects the value D408 supplied from the register 406, outputs it to the register 406, and stores it again. That is, until φ (| v _i |) obtained from the message D355 (message v _i ) from all the branches over one row of the check matrix is accumulated, the register 406 stores φ (| v _i |) is supplied to the selector 405 and the adder 407.

On the other hand, FIFO memories 408, (Sigma] [phi of i = 1 through _{i = d c (| v i} |)) a new value D408 from the register 406 until it is output, the value selector 402 has output D405 (phi (| v _i |)) is delayed and supplied to the subtractor 407 as a 6-bit value D409. The subtractor 407 subtracts the value D409 supplied from the FIFO memory 408 from the value D408 supplied from the register 406, and supplies the subtraction result to the clip circuit 409 and the adder 417 as a 9-bit subtraction value D410. To do. In other words, the subtractor 407 calculates the message D355 () from the branch to be obtained from the integrated value of φ (| v _i |) obtained from the message D355 (message v _i ) from all the branches over one row of the check matrix. Φ (| v _i |) obtained from the message v _i ) is subtracted, and the subtraction value (Σφ (| v _i |) from i = 1 to i = d _c −1) is used as the subtraction value D410. This is supplied to the clip circuit 409.

The clip circuit 409 clips the 9-bit subtraction value D410 supplied from the adder 407, and the lower 5-bit value D411 (Σφ (| v _i |) from i = 1 to i = d _c −1). Is supplied to the LUT 410.

The LUT 410 calculates φ ⁻¹ (Σφ (| v _i |)) in Expression (7) for the value D411 (Σφ (| v _i |) from i = 1 to i = d _c −1). The performed 5-bit operation result D412 (φ ⁻¹ (Σφ (| v _i |))) is output.

  In parallel with the above processing, the EXOR circuit 411 performs the multiplication of the sign bits by calculating the exclusive OR of the 1-bit value D414 stored in the register 412 and the sign bit D401. The bit multiplication result D413 is stored again in the register 412. Note that when the sign bit D401 of the message D355 from all branches over one row of the check matrix is multiplied, the register 412 is reset.

The multiplication result D413 (Πsign (v _i ) from i = 1 to d _c ) obtained by multiplying the sign bit D401 (sign (v _i )) of the message D355 from all the branches over one row of the check matrix is the register 412. Stored in the control signal 362, the control signal D362 supplied from the control unit 356 changes from “0” to “1”.

When the control signal D362 is “1”, the selector 413 selects the value stored in the register 412, that is, the value D414 (multiplied by the sign bit D401 of the message D355 from all branches of one row of the check matrix). select Πsign from i = 1 to _{i = d c (v i)} ), and stores and outputs a 1-bit value D415 to the register 414. The register 414 supplies the stored value D415 as a 1-bit value D416 to the selector 413 and the EXOR circuit 416.

When the control signal D362 is “0”, the selector 413 selects the value D416 supplied from the register 414, outputs it to the register 414, and stores it again. That is, the register 414 supplies the previously stored value to the selector 413 and the EXOR circuit 416 until the sign bit D401 of the message D355 (message v _i ) from all branches over one row of the check matrix is multiplied. .

On the other hand, FIFO memories 415, between (from i = 1 i = Πsign to d _c (v _i)) a new value D416 from the register 414 until is supplied to the EXOR circuit 416 delays the sign bit D401, The 1-bit value D417 is supplied to the EXOR circuit 416. The EXOR circuit 416 calculates the exclusive OR of the value D416 supplied from the register 414 and the value D417 supplied from the FIFO memory 415, thereby dividing the value D416 by the value D417 and dividing by 1 bit. The result is output as the division value D418. That is, the EXOR circuit 416 obtains the multiplication value of the sign bit D401 (sign (| v _i |)) of the message D355 from all branches over one row of the check matrix, and the sign bit D401 of the message D355 from the branch to be obtained. Divide by (sign (| v _i |)) and output the divided value (Πsign (| v _i |) from i = 1 to i = d _c −1) as a divided value D418.

A 5-bit operation result D412 output from the LUT 410 is set to the lower 5 bits, and a total 6-bit value D419 (message u _j ) using the 1-bit division value D418 output from the EXOR circuit 416 as the most significant bit is obtained. It is output as a message D350 via the selector 419.

As described above, when the check node operation is selected as the operation performed by the node calculator 354 by the control unit 356, the node calculator 354 performs the operation of Expression (7) and obtains the message u _j. .

  As described above, the node calculator 354 shares the common blocks necessary for the variable node calculation and the check node calculation, and thereby has a block necessary for the variable node calculation and the check node calculation separately. Thus, the circuit scale of the node calculator 354 can be reduced.

  Here, in the node calculator 354 in FIG. 18, the adder 122 and the adder 151 in the check node calculator in FIG. 10 and the variable node calculator 103 in FIG. 11 are added, and the register 123 and the register 152 are added in the adder 403. In the register 4040, the selector 124 and the selector 153, the selector 405, the register 125 and the register 154, the register 406, and the addition part of the adder 126 and the adder / subtractor 156 are the adder 407, the FIFO memory 127, and the FIFO memory. 155 are shared by the FIFO memory 408, respectively.

  In the node calculator 354, when the check node calculation is performed, the delay amount in the FIFO memory 408 and the FIFO memory 415 is reduced to the value of the weight of the row based on the row weight of each row of the check matrix. When a variable node operation is performed, based on the column weight of each column of the check matrix, the delay amount in the FIFO memory 408 is reduced to the value of the column weight.

FIG. 19 is a flowchart for explaining the decoding process of the decoding device 340 of FIG. This process is started, for example, when reception data to be decoded is stored in the reception memory 355. In FIG. 19, for example, a message (message v _i ) obtained as a result of the variable node calculation is stored in the branch memory 351, and a message (message u _j ) obtained as the result of the check node calculation is stored in the branch memory 352, respectively. Shall be. However, the message v _i may be stored in the branch memory 352, and the message u _j may be stored in the branch memory 351.

In step S41, the control unit 356 selects a variable node operation from among the variable node operation and the check node operation as an operation to be performed by the node calculator 354, and sends a selection signal D361 indicating the selection to the node calculator 354. Supply. In step S51, which will be described later, the control unit 356 selects the branch memory 352 storing the message D350 (message u _j ) obtained as a result of the check node calculation as a memory for reading a message to be supplied to the node calculator 354. Then, the selection signal D364 representing the selection is supplied to the selector 353, and the branch memory 351 stores (writes) the message D350 (message v _i ) obtained as a result of the variable node calculation in step S45 described later. A selection signal D363 indicating the selection is supplied to the switch 350 as a memory.

After the processing in step S41, the process proceeds to step S42, and the selector 353 sends a message supplied from the branch memory 351 or the branch memory 352 to the node calculator 354 based on the selection signal D364 supplied in step S41. , Supplied as message D355. That is, here, since the selection signal D364 supplied in step S41 represents the selection of the branch memory 352 in which the message corresponding to the branch from the check node is stored, the selector 353 receives from the branch memory 352. The message D354 (message u _j ) read one by one is supplied to the node calculator 354 as a message D355.

Note that if the check node operation has not yet been performed on the reception data D356 supplied from the reception memory 355 and the message D352 is not stored in the branch memory 352, the node calculator 354 determines that the message u Set _j to the initial value.

  After step S42, the process proceeds to step S43, and the node calculator 354 performs variable node calculation. That is, the node calculator 354 is supplied with the reception data D356 from the reception memory 355 and the control signal D362 from the control unit 356. Based on the control signal D362, the node calculator 354 uses the received data D356 and the message D355 supplied from the selector 353 in step S42 to perform a variable node calculation according to the above equation (1).

  That is, the node calculator 354 reads the necessary message D354 (D355) from the branch memory 352 via the selector 353 according to the control signal D362, and uses the reception data D356 supplied from the reception memory 355. , Variable node calculation is performed.

After the process of step S43, the process proceeds to step S44, and the node calculator 354 outputs the message D350 (message v _i ) obtained as a result of the variable node calculation to the switch 350, and proceeds to step S45.

  In step S45, the switch 350 uses the node calculator 354 based on a selection signal D363 representing one of the branch memory 351 and the branch memory 352 as the memory for storing the message D350 supplied in step S41. Is stored in the branch memory 351 or the branch memory 352. Here, since the selection signal D363 represents the selection of the branch memory 351 as the memory for storing the message D350, the switch 350 displays the message D350 obtained as a result of the variable node calculation output in step S44 as the message. This is stored in the branch memory 351 as D351. That is, the switch 350 writes the message D350 in the memory other than the branch memory selected as the memory for reading the message to be supplied to the node calculator 354 out of the branch memory 351 and the branch memory 352.

  After the processing of step S45, the process proceeds to step S46, and the control unit 356 determines whether or not the message of all branches is calculated by the node calculator 354, and determines that the message of all branches is not calculated. If so, the process returns to step S42 and the above-described processing is repeated.

On the other hand, when the control unit 356 determines in step S46 that the message of the total number of branches has been calculated by the node calculator 354, the control unit 356 proceeds to step S47, and the control unit 356 now performs the calculation performed by the node calculator 354. Then, the check node calculation is selected, and the control signal D361 indicating the selection of the variable node calculation generated in step S41 is changed to the control signal D361 indicating the selection of the check node calculation. In step S45, the control unit 356 selects the branch memory 351 in which the message (message v _i ) obtained as a result of the variable node calculation is stored as a memory for reading the message to be supplied to the node calculator 354. A selection signal D364 representing selection is supplied to the selector 353, and the branch memory 352 is selected as a memory for storing (writing) the message D350 (message u _j ) obtained as a result of the check node calculation in step S51 described later. Then, the selection signal D363 indicating the selection is supplied to the switch 350.

After the processing in step S47, the process proceeds to step S48, and the selector 353 sends a message supplied from the branch memory 351 or the branch memory 352 to the node calculator 354 based on the selection signal D364 supplied in step S47. , Supplied as message D355. That is, here, since the selection signal D364 supplied in step S47 represents the selection of the branch memory 351 in which the message corresponding to the branch from the variable node is stored, the selector 353 receives from the branch memory 351. The message D353 (message v _i ) read one by one is supplied to the node calculator 354 as a message D355.

  After the process of step S48, the process proceeds to step S49, and the node calculator 354 performs a check node calculation. That is, the node calculator 354 is supplied with the control signal D362. Based on the control signal D362, the node calculator 354 uses the message D355 supplied from the selector 353 in step S48 to calculate the check node according to the above-described equation (7).

  That is, when the check node operation is selected by the control unit 356 as the operation to be performed by the node calculator 354, the control signal D362 supplied to the node calculator 354 by the control unit 356 has been described with reference to FIG. The node calculator 354 corresponds to the control signal D106. The node calculator 354 performs a check node calculation while reading the necessary message D353 (D355) from the branch memory 351 via the selector 353 according to the control signal D362.

After the process of step S49, the process proceeds to step S50, and the node calculator 354 outputs the message D350 (message u _j ) obtained as a result of the check node calculation to the switch 350, and proceeds to step S51.

  In step S51, the switch 350 uses the node calculator 354 based on the selection signal D363 representing the selection of one of the branch memory 351 and the branch memory 352 as the memory for storing the message D350 supplied in step S47. Is stored in the branch memory 351 or the branch memory 352. Here, since the selection signal D363 represents the selection of the branch memory 352 as the memory for storing the message D350, the switch 350 displays the message D350 obtained as a result of the check node operation output in step S50 as the message. It is stored in the branch memory 352 as D352. That is, the switch 350 writes the message D350 in the memory other than the branch memory selected as the memory for reading the message to be supplied to the node calculator 354 out of the branch memory 351 and the branch memory 352.

  After the processing of step S51, the process proceeds to step S52, and the control unit 356 determines whether or not the message of all branches is calculated by the node calculator 354, and determines that the message of all branches is not calculated. If so, the process returns to step S48 and the above-described processing is repeated.

  On the other hand, in step S52, when the control unit 356 determines that the message of all branches has been calculated by the node calculator 354, the process ends.

Note that the decoding device 340 repeats the decoding process of FIG. 19 as many times as the number of decoding, and when the message D350 (message u _j ) obtained as a result of the last check node operation is stored in the branch memory 352, the branch memory 352 supplies the message D350 to a block (not shown) that performs the calculation of the above-described equation (5). The block (not shown) is further supplied with reception data D356 from the reception memory 355. The block (not shown) performs the calculation of Expression (5) using the message D350 and the reception data D356, and the calculation result is obtained. Output as the final decoding result.

As described above, the node calculator 354 performs both the variable node calculation and the check node calculation. That is, the variable node operation is performed using the message u _j that is the result of the check node operation, and the check node operation is performed using the message v _i that is the result of the variable node operation. Variable node calculation and check node calculation are performed alternately. The node calculator 354 shares the common blocks necessary for the variable node calculation and the check node calculation, and alternately performs the variable node calculation and the check node calculation, thereby sharing the variable node calculator and the check node calculator. The circuit scale of the decoding device 340 can be reduced compared to the decoding device of FIG. 9 that can be configured as a single node calculator and separately includes the variable node calculator 101 and the check node calculator 103 that perform variable node operations. be able to.

  FIG. 20 is a block diagram illustrating a configuration example of still another embodiment of a decoding device to which the present invention has been applied.

  FIG. 20 shows an example of a decoding device 430 that performs one decoding of an LDPC code. The iterative decoding can be performed by connecting a plurality of decoding devices 430 in a column or using the decoding devices 430 repeatedly.

  In the decoding device 430, the branch memory 351 and the branch memory 352 in FIG. 17 are shared by one branch memory 440, and a message obtained as a result of the variable node calculation or the check node calculation of the node calculator 354 is one. Stored in the branch memory 440.

  The decoding device 430 includes a node calculator 354, a reception memory 355, a branch memory 440, and a control unit 441. That is, the decoding device 430 shares the branch memory 351 and the branch memory 352 of the decoding device 340 of FIG. 17 into the branch memory 440, and deletes the switch 350 and the selector 353.

  Note that the same reference numerals as those in FIG. 17, that is, the node calculator 354 and the reception memory 355 of the decoding device 430 in FIG. 20 are the same as those in FIG. 17, and the description will be repeated. Omitted.

  The branch memory 440 is supplied from the node calculator 354 with a message D440 corresponding to a branch obtained as a result of the check node calculation or variable node calculation by the node calculator 354. The branch memory 440 stores the node calculator 354. Is stored (stored), and the already stored message D441 is supplied to the node calculator 354.

  That is, the branch memory 440 is supplied from the node calculator 354, and reads out the messages D440 stored one by one in the order in which the node calculator 354 performs variable node calculation or check node calculation. At the same time as it is supplied to the calculator 354, the message D440 output from the node calculator 354 is received and written to the address where the already read message (message D441) of the branch memory 440 is stored. That is, the branch memory 440 simultaneously reads the message D441 supplied to the node calculator 354 and writes the message D440 supplied from the node calculator 354.

  The branch memory 440 stores a message corresponding to the branch calculated by the variable node calculation or the check node calculation of the node calculator 354. Therefore, the amount of data stored in the branch memory 440, that is, The storage capacity required for the branch memory 440 is a product of the number of message quantization bits and the total number of branches.

  Further, the branch memory 440 can be configured by, for example, a dual port RAM capable of reading and writing simultaneously.

  As in the case of the node calculator 356 described with reference to FIG. 17, the control unit 441 now selects the selection signal D361 for selecting one of the variable node calculation and the check node calculation as the calculation performed by the node calculator 354, and the control signal D362. Is supplied to the node calculator 354 to control the node calculator 354.

  FIG. 21 is a flowchart for explaining the decoding process of the decoding device 430 of FIG. This process is started, for example, when reception data to be decoded is stored in the reception memory 355.

  In step S61, the control unit 441 selects a variable node operation from among the variable node operation and the check node operation as the operation performed by the node calculator 354, and sends a selection signal D361 indicating the selection to the node calculator 354. Supply.

After the processing of step S61, the process proceeds to step S62, and the node calculator 354 performs variable node calculation. That is, the node data 356 is supplied from the reception memory 355 to the node calculator 354, and the message D440 (message u _j ) stored in step S67 described later is supplied as the message D441 from the branch memory 440. Is done. The node calculator 354 is supplied with a control signal D362 from the control unit 441. Then, similarly to step S43 of FIG. 19 described above, the node calculator 354 calculates the variable node according to the above equation (1) using the reception data D356 and the message D355 based on the control signal D362. Do.

  Note that if the check node operation has not yet been performed on the reception data D356 supplied from the reception memory 355 and the message D440 is not stored in the branch memory 440, the node calculator 354 determines whether the variable node Sets the message used for calculation to the initial value.

After the process of step S62, the process proceeds to step S63, and the node calculator 354 stores the message (message v _i ) D440 obtained as a result of the variable node calculation in the branch memory 440, and proceeds to step S64.

  In step S64, the control unit 441 determines whether or not the message of the total number of branches has been calculated by the node calculator 354. When determining that the message of the total number of branches has not been calculated, the control unit 441 returns to step S62, and Repeat the process.

  On the other hand, in step S64, when the control unit 441 determines that the message of the total number of branches has been calculated by the node calculator 442, the control unit 441 proceeds to step S65, and the control unit 441 now performs an operation to be performed by the node calculator 354. Then, the check node calculation is selected, and the control signal D361 indicating the selection of the variable node calculation generated in step S61 is changed to the control signal D361 indicating the selection of the check node.

After the process of step S65, the process proceeds to step S66, and the node calculator 354 performs a check node calculation. That is, the node calculator 354 is supplied with the message D440 (message v _i ) stored in step S63 from the branch memory 440 as the message D441, and is also supplied with the control signal D362 from the control unit 441. The node calculator 354 uses the message D441 supplied from the branch memory 440 based on the control signal D362 as in step S49 of FIG. 19 described above to calculate the check node according to the above equation (7). I do.

After the process of step S66, the process proceeds to step S67, and the node calculator 354 stores the message (message u _j ) D440 obtained as a result of the check node calculation in the branch memory 440, and proceeds to step S68.

  In step S68, the control unit 441 determines whether or not the message of the total number of branches has been calculated by the node calculator 354. When determining that the message of the total number of branches has not been calculated, the control unit 441 returns to step S66, and Repeat the process.

  On the other hand, in step S68, when the control unit 441 determines that the message of all branches has been calculated by the node calculator 354, the process ends.

The decoding device 430 repeatedly performs the decoding process of FIG. 21 as many times as the number of decoding times, and when the message D440 (message u _j ) obtained as a result of the last check node operation is stored in the branch memory 440, the branch memory 440 supplies the message D440 to a block (not shown) that performs the calculation of the above-described equation (5). The block (not shown) is further supplied with reception data D356 from the reception memory 355. The block (not shown) performs the calculation of Expression (5) using the message D440 and the reception data D356, and the calculation result is obtained. Output as the final decoding result.

  As described above, since the decoding device 430 shares the calculator and further shares the branch memory, the decoding device 300 shown in FIG. 15 sharing the branch memory and the decoding of FIG. 17 sharing the calculator. The circuit scale can be further reduced as compared with the device 340.

  The branch memory 440 may be composed of a plurality of single port RAMs instead of the dual port RAMs. In this case, it is necessary to perform control so that reading and writing to one single-port RAM do not overlap at the same time. When a plurality of single-port RAMs are used, the circuit scale of the decoding device 430 can be reduced as compared with the case where a dual-port RAM is used.

  By the way, in FIGS. 15 to 21, an example of a decoding device that decodes messages one by one has been shown. However, sharing of a computer and sharing of memory are decoding by simultaneously decoding P (plural) messages. It can also be applied to devices. Hereinafter, a decoding apparatus that simultaneously decodes P messages one by one will be described.

  FIG. 22 shows an example of a 30 × 90 parity check matrix that is spaced in 5 × 5 matrix units. Note that the parity check matrix of FIG. 22 is the same as the parity check matrix shown in FIG.

  In FIG. 22, the check matrix is a 5 × 5 unit matrix, a matrix in which one or more of the unit matrix components 1 is 0 (hereinafter referred to as a quasi-unit matrix as appropriate), a unit matrix, A sum of two or more of a unit matrix, a cyclic matrix (hereinafter referred to as a shift matrix), a unit matrix, a quasi-unit matrix, or a shift matrix (hereinafter referred to as a sum matrix as appropriate). ) It is represented by a combination of 5 × 5 0 matrices. Note that the LDPC code represented by the parity check matrix in FIG. 22 has a coding rate of 2/3 and a code length of 90.

  It can be said that the parity check matrix in FIG. 22 includes a 5 × 5 unit matrix, a quasi-unit matrix, a shift matrix, a sum matrix, and a zero matrix. Therefore, these 5 × 5 matrices constituting the check matrix are hereinafter appropriately referred to as constituent matrices.

  FIG. 23 illustrates a configuration example of a decoding device that decodes the LDPC code represented by the parity check matrix of FIG.

23 includes a switch 510 and 515, a branch data storage memory 511 including _six FIFOs 511 _{1 to} 511 ₆ , a selector 512, a check node calculator 513 including _five check node calculators 513 _{1 to} 513 ₅ , From two cyclic shift circuits 514 and 520, a branch data storage memory 516 comprising ₁₈ FIFOs 516 _{1 to} 516 ₁₈ , a selector 517, a reception data memory 518 for storing reception information, a variable node calculation unit 519, and a control unit 521 Composed.

  Before describing each part of the decoding device 500 in detail, first, a method for storing data in the branch data storage memories 511 and 516 will be described.

The branch data storage memory 511 is composed of six FIFOs 511 _{1 to} 511 ₆ that are the number obtained by dividing the number of rows of the check matrix by the number of rows of the constituent matrix. The FIFO 511 _y (y = 1, 2,..., 6) can simultaneously read or write messages corresponding to five branches that are the number of rows and the number of columns of the configuration matrix, and its length. The size (number of stages) is 9, which is the maximum number of 1s (Humming weights) in the row direction of the check matrix.

In the FIFO 511 ₁ , data corresponding to positions 1 from the first row to the fifth row of the parity check matrix of FIG. 22 is stored in a form packed horizontally (ignoring 0). The That is, if the j-th row and the i-th column are represented as (j, i), the first element (first stage) of the FIFO 511 ₁ includes (1, 1) to (5, 5) of the parity check matrix. The data corresponding to the position of 1 in the 5 × 5 unit matrix is stored. The second element contains the shift matrix (1,21) to (5,25) shift matrix (shift matrix obtained by cyclically shifting three 5 × 5 unit matrices to the right by 3) in the second element. Corresponding data is stored. Similarly, the third to eighth elements store data in association with the check matrix. The ninth element includes a shift matrix (1,86) to (5,90) of the parity check matrix (1 in the first row of the 5 × 5 unit matrix is replaced with 0 and left by one). The data corresponding to the position 1 of the shift matrix (cyclically shifted to 1) is stored. Here, in the shift matrix (1,86) to (5,90) of the check matrix, since there is no _{1 in} the first row, the number of elements is 8 only in the first row of FIFO5111, and the remaining rows are the number of elements. Becomes 9.

The FIFO 511 ₂ stores data corresponding to 1 position from the sixth row to the tenth row of the parity check matrix in FIG. In other words, the first element of the FIFO 511 _{2 includes} a first matrix obtained by cyclically shifting one (5 × 5 unit matrix) to the right by a sum matrix (6,1) to (10,5) of the check matrix. The data corresponding to the 1 position of the first shift matrix constituting the matrix and the sum matrix that is the sum of the second shift matrix cyclically shifted by two to the right is stored. The second element stores data corresponding to position 1 of the second shift matrix constituting the sum matrix of (6,1) to (10,5) of the check matrix.

That is, for a configuration matrix with a weight of 2 or more, the configuration matrix is a P × P unit matrix with a weight of 1, a quasi-unit matrix with one or more of its components being 0, or a unit When the matrix or the quasi-unit matrix is expressed in the form of a plurality of shift matrices obtained by cyclic shift, the data corresponding to the position of the unit matrix, the quasi-unit matrix, or the shift matrix having a weight of 1 ( Messages corresponding to branches belonging to a unit matrix, a quasi-unit matrix, or a shift matrix are stored in the same address (the same FIFO among the FIFOs 511 _{1 to} 511 ₆ ).

Hereinafter, the third to ninth elements are also stored in association with the check matrix. The FIFO 511 ₂ has 9 elements for all rows.

Similarly, the FIFOs 511 _{3 to} 511 ₆ store data in association with the check matrix, and the length of each of the FIFOs 511 _{3 to} 511 ₆ is 9.

The branch data storage memory 516 includes 18 FIFOs 516 _{1 to} 516 ₁₈ obtained by dividing the number of columns of the check matrix by 90, which is the number of columns of the configuration matrix. The FIFO 516 _x (x = 1, 2,..., 18) can simultaneously read or write messages corresponding to five branches that are the number of rows and the number of columns of the configuration matrix.

The FIFO516 _1, data corresponding to the first position to the fifth row from the first row of the parity check matrix, (in the form ignoring 0) into a form packed in the longitudinal direction in each column both in FIG. 22 stores Is done. That is, the first element (first stage) of the FIFO 516 ₁ stores data corresponding to the position of 1 in the 5 × 5 unit matrix from (1,1) to (5,5) of the check matrix. . The second element includes the sum matrix (6,1) to (10,5) of the check matrix (a first shift matrix obtained by cyclically shifting one 5 × 5 unit matrix to the right, and the right The data corresponding to the position of 1 of the first shift matrix constituting the sum matrix with the second shift matrix shifted by two cyclic shifts) is stored. The third element stores data corresponding to position 1 of the second shift matrix constituting the sum matrix (6,1) to (10,5) of the check matrix.

That is, for a configuration matrix with a weight of 2 or more, the configuration matrix is a P × P unit matrix with a weight of 1, a quasi-unit matrix with one or more of its components being 0, or a unit When the matrix or the quasi-unit matrix is expressed in the form of a plurality of shift matrices obtained by cyclic shift, the data corresponding to the position of the unit matrix, the quasi-unit matrix, or the shift matrix having a weight of 1 ( Messages corresponding to branches belonging to the unit matrix, the quasi-unit matrix, or the shift matrix are stored in the same address (the same FIFO among the FIFOs 516 _{1 to} 516 ₁₈ ).

Hereinafter, data is also stored for the fourth and fifth elements in association with the check matrix. The number of elements (the number of stages) of the FIFO 516 ₁ is 5, which is the maximum number of 1s (Hamming weights) in the row direction in the first column to the fifth column of the parity check matrix.

Similarly, the FIFOs 516 ₂ and 516 ₃ store data in association with the check matrix, and their length (number of stages) is 5. Similarly, the FIFOs 516 _{4 to} 516 ₁₂ store data in association with the check matrix, and each has a length of 3. Similarly, the FIFOs 516 _{13 to} 516 ₁₈ store data in association with the check matrix, and each has a length of 2. However, the first element of the FIFO 516 ₁₈ corresponds to (1,86) to (5,90) of the check matrix, and the fifth column ((1,90) to (5,90) of the check matrix) Since there is no 1, no data is stored.

  Hereinafter, the operation of each unit of the decoding device 500 of FIG. 23 will be described in detail.

The switch 510 is supplied with five messages (data) D519 from the cyclic shift circuit 520, and is also supplied with a control signal D520 representing information (Matrix data) of which row of the parity check matrix belongs from the control unit 521. The In accordance with the control signal D520, a FIFO for storing five messages (data) D519 is selected from the FIFOs 511 _{1 to} 511 ₆ , and the five message data D519 are collectively supplied to the selected FIFO in order.

The branch data storage memory 511 includes six FIFOs 511 _{1 to} 511 ₆ . The FIFO511 ₁ to 511 ₆ the edge data storage memory 511, the switch 510, the five messages D519 supplied sequentially together, FIFO511 ₁ to 511 _6, will be stored in sequence together five messages D519 . Also, the edge data storage memory 511, when reading data, sequentially reads five messages from FIFO511 ₁ (data) D511 _1, supplied to the next stage of the selector 512. Edge data storage memory 511, after the end of the message D511 ₁ read from FIFO511 _1, from FIFO511 ₂ to 511 _6, in turn, read the message D511 ₁ to D511 ₆ respectively, to the selector 512.

The selector 512 is supplied from the control unit 521 with a selection signal D521 indicating selection of a FIFO (FIFO from which data is currently read) from which the message data is read out of the FIFOs 511 _{1 to} 511 ₆ , and stores branch data. Five messages (data) D511 _{1 to} D511 ₆ are supplied from the memory 511. The selector 512 selects a FIFO from which data is currently read out of the FIFOs 511 _{1 to} 511 ₆ according to the selection signal D521, and sets five message data supplied from the selected FIFO as a message D512. This is supplied to the check node calculation unit 513.

The check node calculation unit 513 includes five check node calculators 513 _{1 to} 513 ₅ . The check node calculation unit 513 is supplied with five messages D512 via the selector 512, and the message D512 is supplied to each of the check node calculators 513 _{1 to} 513 ₅ . The check node calculator 513 is supplied with a control signal D522 from the controller 521, and the control signal D522 is supplied to the check node calculators 513 _{1 to} 513 ₅ . Each of the check node calculators 513 _{1 to} 513 ₅ performs an operation according to Expression (7) using the message D512, and obtains a result message D513 of the operation. The check node calculation unit 513 supplies five messages D513 obtained as a result of the calculation by the check node calculators 513 _{1 to} 513 ₅ to the cyclic shift circuit 514.

Here, the control signal D522 supplied from the control unit 521 to the check node calculation unit 513 corresponds to the control signal D106 in FIG. 10, and each of the check node calculation units 513 _{1 to} 513 ₅ is shown in FIG. The check node calculator 101 is configured in the same manner.

  The cyclic shift circuit 514 is supplied with the five messages D513 calculated by the check node calculation unit 513, and from the control unit 521, determines how many unit matrices whose branches corresponding to the message D513 are based on the check matrix. A control signal D523 representing information (Matrix data) as to whether the data has been cyclically shifted is supplied. The cyclic shift circuit 514 performs a cyclic shift that rearranges the five messages D513 based on the control signal D523, and supplies the result to the switch 515 as a message D514.

The switch 515 is supplied with a control signal D524 indicating information on which column of the check matrix the five messages (data) D514 supplied from the cyclic shift circuit 514 belong to, and from the cyclic shift circuit 514, Message D514 is provided. The switch 515 selects a FIFO storing the message D514 from the FIFOs 516 _{1 to} 516 ₁₈ according to the control signal D524, and supplies the five messages D514 to the selected FIFO in order.

The branch data storage memory 516 includes 18 FIFOs 516 _{1 to} 516 ₁₈ . The FIFO516 ₁ to 516 ₁₈ the edge data storage memory 516, five messages D514 from the switch 515 is supplied to the collectively turn, FIFO516 ₁ to 516 _18, will store in sequence summarizes the five messages D514 . Also, the edge data storage memory 516, when reading data, sequentially reads five messages D515 ₁ from FIFO516 _1, supplied to the next stage of the selector 517. The branch data storage memory 516 reads the messages D515 _{2 to} D515 ₁₈ in order from the FIFOs 516 _{2 to} 516 ₁₈ and supplies them to the selector 517 after the reading of data from the FIFO 516 ₁ is completed.

The selector 517 is supplied from the control unit 521 with a selection signal D525 indicating selection of the FIFO (FIFO from which data is currently read) from which the message data is read out of the FIFOs 516 _{1 to} 516 ₁₈ , and the branch data storage memory. Message data D515 _{1 to} D515 ₁₈ are supplied from 516. The selector 517 selects the FIFO from which the current data is read out of the FIFOs 516 _{1 to} 516 ₁₈ according to the selection signal D525, and sets five message data supplied from the selected FIFO as a message D516. This is supplied to the variable node calculation unit 519.

  On the other hand, the reception data memory 518 calculates a reception LLR (log likelihood ratio) from the reception signal received through the communication path, and collects the calculated reception LLRs as reception data D517 as a variable node calculation unit. 519.

The variable node calculation unit 519 includes five variable node calculators 519 _{1 to} 519 ₅ . Five messages D516 are supplied to the variable node calculator 519 via the selector 517, and one message D516 is supplied to each of the variable node calculators 519 _{1 to} 519 ₅ . The variable node calculation unit 519 is supplied with five reception data D517 from the reception data memory 518, and the reception data D517 is supplied to each of the variable node calculators 519 _{1 to} 519 ₅ . Further, the control signal D526 is supplied from the control unit 521 to the variable node calculation unit 519, and the control signal D526 is supplied to the variable node calculators 519 _{1 to} 519 ₅ .

The variable node calculators 519 _{1 to} 519 ₅ use the message D516 and the received data D517 to perform calculations according to the equation (1), and obtain a message D518 as a result of the calculation. The variable node calculation unit 519 supplies the five messages D518 obtained as a result of the variable node calculators 519 _{1 to} 519 ₅ to the cyclic shift circuit 520.

Here, the control signal D526 supplied from the control unit 521 to the variable node calculation unit 519 corresponds to the control signal D107 in FIG. 11, and each of the variable node calculators 519 _{1 to} 519 ₅ has the variable signal in FIG. The configuration is the same as that of the node calculator 103.

  The cyclic shift circuit 520 is supplied with five messages D518 from the variable node calculation unit 519, and the control unit 521 cyclically shifts the unit matrix from which the branch corresponding to the message D518 is based on the check matrix. A control signal D527 indicating information on whether or not it has been supplied is supplied. The cyclic shift circuit 520 performs a cyclic shift for rearranging the messages D527 based on the control signal D527, and supplies the result to the switch 510 as a message D519.

  The control unit 521 includes a control signal D520, a selection signal D521, control signals D522 to D524, a selection signal D525, control signals D526 and D527, a switch 510, a selector 512, a check node calculation unit 513, a cyclic shift circuit 514, These are supplied to the switch 515, the selector 517, the variable node calculation unit 519, and the cyclic shift circuit 520, respectively, to control each.

  The LDPC code can be decoded once by completing the above operation. After decoding the LDPC code a predetermined number of times, decoding apparatus 500 in FIG. 23 obtains and outputs a final decoding result according to equation (5), although not shown.

  In addition, regarding the portion where the branch data (message corresponding to the branch) is missing, no message is stored when the memory is stored (when the data is stored in the branch data storage memories 511 and 516), and the node No calculation is performed even during the calculation (when the check node is calculated by the check node calculation unit 513 and when the variable node is calculated by the variable node calculation unit 519).

  FIG. 24 shows a configuration example of an embodiment of a decoding device that decodes the LDPC code represented by the parity check matrix H of FIG. 22 to which the present invention is applied.

  In the decoding device 530 of FIG. 24, the cyclic shift circuits 514 and 520 of FIG. 23 are shared to form one cyclic shift circuit 551.

The decoding device 530 includes three switches 540, 541 and 546, a branch data storage memory 542 composed of ₁₈ FIFOs 542 _{1 to} 542 ₁₈ , a selector 543, a reception data memory 544 for storing reception information, and five variable node calculations. A check node calculation unit 545 including units 545 _{1 to} 545 _5, a branch data storage memory 547 including _six FIFOs 547 _{1 to} 547 ₆ , a selector 548, and five check node calculators 549 _{1 to} 549 _6. , A selector 550, a cyclic shift circuit 551, and a control unit 552.

  The switch 540 is supplied with five message data D550 from the cyclic shift circuit 551, and among the variable node calculation unit 545 or the check node calculation unit 549 from the control unit 552 as a calculation unit to be operated now. A selection signal D551 representing one selection is supplied. Based on the selection signal D551, the switch 540 selects one of the switch 541 and the switch 546 as a switch for supplying the message data D550, and supplies the message data D550 to the selected switch.

The switch 541 is supplied with message data D550 from the switch 540, and is also supplied with a control signal D552 indicating information (Matrix data) of which column of the parity check matrix belongs from the control unit 552. The switch 541 selects the FIFO storing the five messages D550 from the FIFOs 542 _{1 to} 542 ₁₈ of the branch data storage memory 542 according to the control signal D552, and puts together the five messages D550 into the selected FIFO in order. Supply.

The branch data storage memory 542 includes 18 FIFOs 542 _{1 to} 542 ₁₈ as with the branch data storage memory 516 of FIG. The FIFO 542 ₁ to 542 ₁₈ the edge data storage memory 542, five messages D550 from the switch 541 is supplied to the collectively turn, FIFO 542 ₁ to 542 _18, will store in sequence summarizes the five messages D550 . Also, the edge data storage memory 542, when reading data, sequentially reads five messages D542 ₁ from FIFO 542 _1, to the selector 543. The branch data storage memory 542 reads the messages D542 _{2 to} D542 ₁₈ in order from the FIFOs 542 _{2 to} 542 ₁₈ and supplies them to the selector 543 after reading of the data from the FIFO 542 ₁ is completed.

The selector 543 is supplied from the control unit 552 with a selection signal D553 indicating selection of a FIFO (FIFO from which data is currently read) from which the message data is read out of the FIFOs 542 _{1 to} 542 ₁₈ and the branch data storage memory. Messages (data) D542 _{1 to} D542 ₁₈ are supplied from 542. In the same manner as the selector 517 in FIG. 23, the selector 543 selects a FIFO from which data is currently read from among the FIFOs 542 _{1 to} 542 _{18 in} accordance with the selection signal D553 supplied from the control unit 521, and selects the selected FIFO. The five pieces of message data supplied from the FIFO are supplied to the variable node calculation unit 545 as message (data) D543.

  On the other hand, the reception data memory 544 calculates a reception LLR (log-likelihood ratio) from the reception signal received through the communication path, and combines the calculated reception LLRs into reception data D544 as a variable node calculation unit. 545.

The variable node calculation unit 545 includes five variable node calculators 545 _{1 to} 545 ₅ , similar to the variable node calculation unit 519 of FIG. Five messages D543 are supplied to the variable node calculator 545 via the selector 543, and one message D543 is supplied to each of the variable node calculators 545 _{1 to} 545 ₅ . The variable node calculation unit 545 is supplied with five reception data D544 from the reception data memory 544, and the reception data D544 is supplied to each of the variable node calculators 545 _{1 to} 545 ₅ . Further, the control signal D554 is supplied from the control unit 552 to the variable node calculation unit 545, and the control signal D554 is supplied to the variable node calculators 545 _{1 to} 545 ₅ .

The variable node calculators 545 _{1 to} 545 ₅ each perform an operation according to the equation (1) using the message D543 and the received data D544, and obtain a message D545 as a result of the operation. That is, the variable node calculation unit 545 calculates five variable nodes for decoding the LDPC code, and simultaneously obtains five messages D545 as a result of the calculation. Then, the variable node calculation unit 545 supplies the five messages D545 obtained as a result of the variable node calculators 545 _{1 to} 545 ₅ to the selector 550.

Here, the control signal D554 supplied from the control unit 552 to the variable node calculation unit 545 corresponds to the control signal D107 of FIG. 11, and each of the variable node calculators 545 _{1 to} 545 ₅ is shown in FIG. The configuration is the same as that of the node calculator 103.

The switch 546 is supplied with five messages (data) D550 from the switch 540 and a control signal D555 indicating information indicating which row of the check matrix the message (data) D550 belongs to from the control unit 552. Is done. The switch 546 selects a FIFO for storing the message D550 from the FIFOs 547 _{1 to} 547 ₁₈ of the branch data storage memory 547 according to the control signal D555 supplied from the control unit 552, and five messages D550 are stored in the selected FIFO. Are supplied in order.

The branch data storage memory 547 includes six FIFOs 547 _{1 to} 547 ₁₈ as in the branch data storage memory 511 of FIG. The FIFO547 ₁ to 547 ₆ the edge data storage memory 547, the switch 546, the five messages D550 supplied sequentially together, FIFO547 ₁ to 547 _6, will be stored in sequence together five messages D550 . Also, the edge data storage memory 547, when reading data, sequentially reads five messages from FIFO547 ₁ (data) D546 _1, supplied to the next stage of the selector 548. Edge data storage memory 547, after the end of the message D546 ₁ read from FIFO547 _1, from FIFO547 ₂ to 547 _6, in turn, reads the message D546 ₂ to D546 _6, to the selector 548.

The selector 548 is supplied from the control unit 552 with a selection signal D556 indicating selection of a FIFO (FIFO from which data is currently read) from among the FIFOs 547 _{1 to} 547 ₆ to read message data, and stores branch data. Five messages (data) D546 _{1 to} D546 ₆ are supplied from the memory 547. The selector 548 selects the FIFO from which the current data is read out of the FIFOs 547 _{1 to} 547 ₆ according to the selection signal D546, and sets five message data supplied from the selected FIFO as a message D547. This is supplied to the check node calculation unit 549.

The check node calculation unit 549 includes five check node calculators 549 _{1 to} 549 ₅ as with the check node calculation unit 513 in FIG. Five messages D547 are supplied to the check node calculator 549 via the selector 548, and one message D547 is supplied to each of the check node calculators 549 _{1 to} 549 ₅ . Further, the control signal D557 is supplied from the control unit 552 to the check node calculation unit 549, and the control signal D557 is supplied to the check node calculators 549 _{1 to} 549 ₅ . Each of the check node calculators 549 _{1 to} 549 ₅ performs an operation according to the equation (7) using the message D547, and simultaneously determines five messages D548 as a result of the operation. That is, the check node calculation unit 513 performs five check node operations for decoding the LDPC code, and obtains five messages D548 as a result of the operation. Then, the check node calculation unit 513 supplies the five messages D548 to the selector 550.

Here, the control signal D557 supplied from the control unit 552 to the check node calculation unit 549 corresponds to the control signal D106 of FIG. 10, and each of the check node calculation units 549 _{1 to} 549 ₅ is shown in FIG. The check node calculator 101 is configured in the same manner.

  The selector 550 is supplied with the message D545 from the variable node calculation unit 545 and the message D548 from the check node calculation unit 549. Further, the selector 550 is supplied with a selection signal D558 representing one of the variable node calculation unit 545 and the check node calculation unit 549 as a calculation unit to be operated. The selector 550, based on the selection signal D558, receives the message D545 corresponding to the five branches obtained as a result of the variable node calculation by the variable node calculation unit 545, and the five obtained as a result of the check node calculation by the check node calculation unit 549. One of the messages D548 corresponding to the branch is selected, and the selected message is supplied to the cyclic shift circuit 551 as the message D549.

  The cyclic shift circuit 551 is supplied with the message D549 from the selector 550, and from the control unit 552, how many branches corresponding to the message D549 are obtained by cyclically shifting the original unit matrix in the check matrix. The control signal D559 representing the information (Matrix data) is supplied. The cyclic shift circuit 551 cyclically shifts (rearranges) the five messages D549 based on the control signal D559, and supplies the result to the switch 540 as a message D550.

  Note that the control unit 552 controls the selection signal D551 by supplying the selection signal D551 to the switch 540, the control signal D552 to the switch 541, and the selection signal D553 to the selector 543, respectively. In addition, the control unit 552 controls the control signal D554 by supplying the control signal D554 to the variable node calculation unit 545 and the control signal D555 to the switch 546, respectively. Further, the control unit 552 supplies the selection signal D556 to the selector 548, the control signal D557 to the check node calculation unit 549, the selection signal D558 to the selector 550, and the control signal D559 to the cyclic shift circuit 551, respectively. To control.

  The LDPC code can be decoded once by completing the above operation. After decoding the LDPC code a predetermined number of times, the decoding device 530 in FIG. 24 obtains and outputs a final decoding result according to Equation (5), although not shown.

  In addition, regarding the portion where the branch data (message corresponding to the branch) is missing, no message is stored when the memory is stored (when the data is stored in the branch data storage memories 542 and 547), and the node No computation is performed during computation (variable node computation in the variable node computation unit 545 and check node computation in the check node computation unit 549).

  FIG. 25 is a flowchart for explaining the decoding process of the decoding device 530 of FIG. This process is started, for example, when reception data to be decoded is stored in the reception data memory 544.

  In step S81, the control unit 552 selects the variable node calculation unit 545 as the calculation unit to be operated among the variable node calculation unit 545 and the check node calculation unit 549, and selects a selection signal D551 indicating the selection. The selection signal D558 is supplied to the switch 540 and the selector 550, respectively.

  After the process of step S81, the process proceeds to step S82, and the variable node calculation unit 545 performs a variable node calculation.

Specifically, five messages D543 (message u _j ) are supplied to the variable node calculation unit 545 via the selector 543. That is, the branch data storage memory 542 sequentially reads five messages D542 ₁ from the FIFO 542 ₁ stored in step S93, which will be described later, and then sequentially sends the messages D542 _{2 to} D542 ₁₈ from the FIFOs 542 _{2 to} 542 _{18 as} well. Read and supply to the selector 543.

The selector 543 is supplied with a selection signal D553 indicating selection of a FIFO (FIFO from which data is currently being read) from among the FIFOs 542 _{1 to} 542 ₁₈ from the control unit 552, and branch data. Message data D542 _{1 to} D542 ₁₈ are supplied from the storage memory 542. The selector 543 selects the FIFO from which the current data is read out of the FIFOs 542 _{1 to} 542 ₁₈ according to the selection signal D553, and sets five message data supplied from the selected FIFO as a message D543. This is supplied to the variable node calculation unit 545.

Note that when the check node operation has not yet been performed on the reception data D544 supplied from the reception memory 544 and the message D550 is not stored in the branch data storage memory 542, the variable node calculation unit 545 Set message u _j to the initial value.

The variable node calculation unit 545 is supplied with five reception data D544 (reception value u _0i ) from the reception data memory 544, and the reception data D544 is ₁ for each of the variable node calculators 545 _{1 to} 545 _5. Supplied one by one. Further, the control signal D554 is supplied from the control unit 552 to the variable node calculation unit 545, and the control signal D554 is supplied to the variable node calculators 545 _{1 to} 545 ₅ .

The variable node calculators 545 _{1 to} 545 ₅ use the message D543 and the received data D544 to perform calculations according to the expression (1) based on the control signal D554, and obtain five messages D545 as a result of the calculation. Ask at the same time.

That is, the control signal D554 supplied from the control unit 552 to the variable node calculation unit 545 corresponds to the control signal D107 described with reference to FIG. 11, and the variable node calculators 545 _{1 to} 545 ₅ are controlled by the control signal D544. Accordingly, the necessary messages D543 (D542) are read one by one from the branch data storage memory 542 via the selector 543, and variable node calculation is performed using the reception data D544 supplied from the reception data memory 544. And five messages D545 are obtained simultaneously as a result of the calculation.

After the process of step S82, the process proceeds to step S83, and the variable node calculation unit 545 outputs five messages D545 (message v _i ) obtained as a result of the variable node calculation of the variable node calculators 545 _{1 to} 545 ₅ to the selector 550. Then, the process proceeds to step S84.

  In step S84, the selector 550 selects one of the variable node calculation unit 545 and the check node calculation unit 549 based on the selection signal D558 supplied in step S81, and sends a message output from one of the messages to the message D549. Is supplied (output) to the cyclic shift circuit 551. Here, since the selection signal D558 represents the selection of the variable node calculation unit 545, the selector 550 cyclically shifts the five messages D545 obtained as a result of the variable node calculation output in step S83 as the message D549. This is supplied to the circuit 551. In other words, the selector 550 supplies the cyclic shift circuit 551 with a message output from the calculator currently performing the calculation among the variable node calculation unit 545 and the check node calculation unit 549.

  After the process of step S84, the process proceeds to step S85, and the cyclic shift circuit 551 cyclically shifts (reorders) the five messages D549 supplied from the selector 550.

  Specifically, the cyclic shift circuit 551 is supplied with the message D549 from the selector 550, and the control unit 552 cyclically shifts the unit matrix from which the branch corresponding to the message D549 is based on the check matrix. The control signal D559 representing the information (Matrix data) as to whether or not it has been supplied is supplied. The cyclic shift circuit 551 cyclically shifts five messages D549 based on the control signal D559, and supplies the result to the switch 540 as a message D550.

  After the process of step S85, the process proceeds to step S86, and the switch 540 selects one of the branch data storage memory 542 and the branch data storage memory 547 based on the control signal D551 supplied in step S81, and selects the selected one. In step S85, the five messages D550 supplied from the cyclic shift circuit 550 are supplied to one branch data storage memory via the switch. That is, here, since the control signal D551 supplied in step S81 represents the selection of the variable node calculation unit 545, the switch 540 selects the branch data storage memory 547 for storing the message from the variable node, A message D550 is supplied to the selected branch data storage memory 547 via the switch 546.

Specifically, five messages (data) D550 are supplied from the switch 540 to the switch 546, and a control signal D555 indicating information on which row of the check matrix the message (data) D550 belongs to. Supplied. The switch 546 selects the FIFO storing the message D550 from the FIFOs 547 _{1 to} 547 ₆ of the branch data storage memory 547 according to the control signal D555, and supplies the five message data D550 to the selected FIFO in order. I will do it.

The FIFOs 547 _{1 to} 547 ₁₈ of the branch data storage memory 547 collectively store the five message data D550 supplied from the switch 546 in order.

  After the processing of step S86, the process proceeds to step S87, and the control unit 552 determines whether the message of all branches is calculated by the variable node calculation unit 545, and determines that the message of all branches is not calculated. If so, the process returns to step S82 and the above-described processing is repeated.

  On the other hand, when the variable node calculation unit 545 determines in step S87 that the message of all branches has been calculated, the process proceeds to step S88, and the control unit 552 now checks the check node calculation unit as the calculation unit on which the calculation is performed. 549 is selected, and the selection signals D551 and D558 representing selection of the variable node calculation unit 545 generated in step S81 are changed to selection signals D551 and D558 representing selection of the check node calculation unit 549.

  After the processing of step S88, the process proceeds to step S89, and the check node calculation unit 549 performs check node calculation.

Specifically, five messages D547 are supplied to the check node calculation unit 549 via the selector 548. That is, the branch data storage memory 547 sequentially reads five messages D546 ₁ (message v _i ) from the FIFO 547 ₁ stored in step S86, and then sequentially reads the message data D546 ₂ from the FIFOs 547 _{2 to} 547 _6. To D546 ₆ are read out and supplied to the selector 548.

The selector 548 is supplied from the control unit 552 with a selection signal D556 indicating selection of a FIFO (FIFO from which data is currently read) from among the FIFOs 547 _{1 to} 547 ₆ to read message data, and a branch data storage memory. Message data D546 _{1 to} D546 ₆ are supplied from 547. The selector 548 selects the FIFO from which the current data is read out of the FIFOs 547 _{1 to} 547 ₆ according to the selection signal D556, and sets five message data supplied from the selected FIFO as a message D547. This is supplied to the check node calculation unit 549.

In addition, the control signal D557 is supplied from the control unit 552 to the check node calculation unit 549. Based on the control signal D557, the check node calculators 549 _{1 to} 549 ₅ of the check node calculation unit 549 perform the check node calculation according to the above-described equation (7) using the message D547, and the result is the calculation result. Five messages D548 (message u _j ) are obtained simultaneously.

That is, the control signal D557 supplied from the control unit 552 to the check node calculation unit 549 corresponds to the control signal D106 described with reference to FIG. 10, and the check node calculators 549 _{1 to} 549 ₅ receive the control signal D557. Accordingly, the check node operation is performed while reading the necessary messages D547 (D546) from the branch data storage memory 547 one by one via the selector 548, and five messages D548 are obtained simultaneously as a result of the operation.

  After the process of step S89, the process proceeds to step S90, and the check node calculation unit 549 outputs five messages D548 obtained as a result of the check node calculation to the selector 550, and the process proceeds to step S91.

  In step S91, the selector 555 selects one of the variable node calculation unit 545 and the check node calculation unit 549 based on the selection signal D558 changed in step S88, and a message output from one of them is set as a message D549. To the cyclic shift circuit 551. Here, since the selection signal D558 represents the selection of the check node calculation unit 549, the selector 550 uses the message D548 obtained as a result of the check node calculation output in step S90 as the message D549 and the cyclic shift circuit 551. To store. That is, the selector 550 supplies the cyclic shift circuit 551 with a message output from the calculation unit currently performing the calculation among the variable node calculation unit 545 and the check node calculation unit 549.

  After the process of step S91, the process proceeds to step S92, and the cyclic shift circuit 551 cyclically shifts the five messages D549 supplied from the selector 550.

  Specifically, the cyclic shift circuit 551 is supplied with the message D549 from the selector 550, and the control unit 552 cyclically shifts the unit matrix from which the branch corresponding to the message D549 is based on the check matrix. The control signal D559 representing the information (Matrix data) as to whether or not it has been supplied is supplied. The cyclic shift circuit 551 cyclically shifts five messages D549 based on the control signal D559, and supplies the result to the switch 540 as a message D550.

  After the processing of step S92, the process proceeds to step S93, and the switch 540 selects one of the branch data storage memory 542 and the branch data storage memory 547 based on the control signal D551 changed in step S88, and selects the selected one. Five messages D550 supplied from the cyclic shift circuit 550 in step S91 are supplied to one branch data storage memory via a switch. That is, here, since the control signal D551 supplied in step S88 represents the selection of the check node calculation unit 549, the switch 540 selects the branch data storage memory 542 for storing the message from the check node, A message D540 is supplied to the selected branch data storage memory 542 via the switch 541.

Specifically, five messages (data) D550 are supplied from the switch 540 to the switch 542, and a control signal D552 indicating information on which column of the check matrix the message (data) D550 belongs to. Supplied. The switch 541 selects the FIFO storing the message D550 from the FIFOs 542 _{1 to} 542 ₁₈ of the branch data storage memory 542 according to the control signal D552, and supplies the five message data D550 to the selected FIFO in order. To go.

The FIFOs 542 _{1 to} 542 ₁₈ of the branch data storage memory 542 collectively store the five message data D550 supplied from the switch 541 in order.

  After the processing of step S93, the process proceeds to step S94, and the control unit 552 determines whether the message of the total number of branches has been calculated by the check node calculation unit 549, and determines that the message of the total number of branches has not been calculated. If so, the process returns to step S89 and the above-described processing is repeated.

  On the other hand, in step S94, when the check node calculation unit 549 determines that the message of all branches has been calculated, the control unit 552 ends the process.

Note that the decoding device 530 repeats the decoding process of FIG. 25 as many times as the number of decoding times, and when the message D550 (message u _j ) obtained as a result of the last check node operation is stored in the branch data storage memory 542, the branch data The storage memory 542 supplies the message D550 to a block (not shown) that performs the calculation of Expression (5) described above. The reception data D544 is further supplied from the reception memory 544 to the block (not shown), and the block (not shown) performs the calculation of Expression (5) using the message D550 and the reception data D544, and the calculation result is finalized. Output as a typical decryption result.

As described above, the cyclic shift circuit 551 is supplied with a message output from the calculation unit that is currently performing the computation among the variable node calculation unit 545 and the check node calculation unit 549. That is, the variable node operation is performed using the message u _j that is the result of the check node operation, and the check node operation is performed using the message v _i that is the result of the variable node operation. Variable node calculation and check node calculation are performed alternately. Accordingly, the cyclic node shifts the message output from the calculation unit currently performing the calculation among the variable node calculation unit 545 and the check node calculation unit 549, so that the message that is the result of the variable node calculation is cyclic. The cyclic shift circuit that shifts and the cyclic shift circuit that cyclically shifts the message that is the result of the check node operation can be shared to form one cyclic shift circuit, and the message that is the result of the variable node operation can be The circuit scale of the decoding device 530 is smaller than that of the decoding device 500 of FIG. 23 that has a cyclic shift circuit 520 that performs click shift and a cyclic shift circuit 513 that cyclically shifts the message that is the result of the check node operation. You It is possible.

  FIG. 26 illustrates a configuration example of another embodiment of a decoding device that decodes the LDPC code represented by the parity check matrix H of FIG. 22 to which the present invention has been applied.

  In the decoding device 570 of FIG. 26, the variable node calculation unit 545 and the check node calculator 549 of FIG. 24 are further shared to form one node calculation unit 581.

  The decoding device 570 includes a switch 540, a switch 541, a branch data storage memory 542, a selector 543, a reception data memory 544, a switch 546, a branch data storage memory 547, a selector 548, a cyclic shift circuit 551, a selector 580, and a node calculation unit. 581 and a control unit 582. That is, the decoding device 570 of FIG. 26 further provides the variable node calculation unit 545 and the check node calculation unit 549 of the decoding device 530 of FIG. 24 as the node calculation unit 581, the selector 550 as the selector 580, and the control unit 552. Is replaced with the control unit 582.

  24, that is, the switch 540, the switch 541, the branch data storage memory 542, the selector 543, the reception data memory 544, the switch 546, and the branch data storage memory of the decoding device 570 in FIG. 547, the selector 548, and the cyclic shift circuit 551 are the same as those of the decoding device 530 of FIG.

The selector 580 is supplied with five messages D543 (message u _j ), which are the results of the check node operation stored in the branch data storage memory 542, via the selector 543, and via the selector 548, the branch Five messages D547 (message v _i ) that are the results of the variable node calculation stored in the data storage memory 547 are supplied. The selector 580 is supplied with a selection signal D582 indicating one of the variable node calculation and the check node calculation as the calculation performed by the node calculation unit 581. The selector 580 selects one of the message D543 and the message D547 based on the selection signal D582 from the control unit 582, and supplies the selected message to the node calculation unit 581 as the message D580.

The node calculation unit 581 includes five node calculators 581 _{1 to} 5815 ₅ . The node calculator 581 is supplied with the five messages D580 through the selector 580, the message D580 is supplied one by one to each of the node calculator 581 ₁ to 581 _5. Further, the node calculator 581, five received data D544 from the reception data memory 544 is supplied, the reception data D544 is supplied one by one to each of the node calculator 581 ₁ to 581 _5. Further, the control signal D583 is supplied from the control unit 582 to the node calculation unit 581, and a selection signal D584 representing one selection as an operation to be performed by the node calculation unit 581 among the variable node calculation or the check node calculation. and the logic circuit selecting signal D584 and the control signal D583 is supplied to the node calculator 581 ₁ to 581 _5.

The node calculators 581 _{1 to} 5815 ₅ select one of the variable node calculation and the check node calculation based on the control unit 582 selection signal D584, and perform the selected calculation. That is, the node calculators 581 _{1 to} 5815 ₅ use the message D580 supplied from the selector 580 and the reception data D544 supplied from the reception memory 544 based on the control signal D583, and according to the equation (1). Each performs variable node calculation for decoding the LDPC code, or uses the message D580 supplied from the selector 580 to perform check node calculation for decoding the LDPC code, respectively, according to Equation (7). Do. That is, the node calculation unit 581 performs five variable node calculations or five check node calculations for decoding the LDPC code.

Then, the node calculators 581 _{1 to} 581 ₅ supply five messages corresponding to the branches obtained as a result of the variable node calculation or the check node calculation to the cyclic shift circuit 551 as the message D581.

Here, the control signal D583 and the selection signal D584 supplied from the control unit 582 to the node calculation unit 581 correspond to the control signal D362 and the selection signal D361 supplied from the control unit 356 to the node calculator 354 in FIG. , and the each node calculator 581 ₁ to 581 _5, and similarly to the node calculator 354 of FIG. 18.

  The control unit 582 cyclically selects the selection signal D551 switch 540, the control signal D552 to the switch 541, the selection signal D553 to the selector 543, the control signal D555 to the switch 546, the selection signal D556 to the selector 548, and the control signal D559. By supplying the selection signal D582 to the selector 580 and the control signal D583 and the selection signal D584 to the node calculation unit 581 respectively to the shift circuit 551, the control is performed.

  FIG. 27 is a flowchart for explaining the decoding process of the decoding device 570 of FIG. This process is started, for example, when reception data to be decoded is stored in the reception data memory 544.

  In step S101, the control unit 582 selects a variable node operation as an operation to be performed by the node calculation unit 581 among the variable node operation and the check node operation, and selects selection signals D551, D582, and D584 indicating the selection. The data are supplied to the switch 540, the selector 580, and the node calculator 581, respectively.

After the processing in step S101, the process proceeds to step S102, and the selector 580 supplies the message D580 to the node calculation unit 581 based on the selection signal D582 supplied from the control unit 582 in step S101. Here, since the selection signal D582 supplied from the control unit 582 indicates selection of variable node calculation, the selector 580 obtains a message obtained as a result of the check node calculation used for variable node calculation in step S113 described later. The message D543 supplied via the selector 543 is supplied from the branch data storage memory 542 storing (message u _j ) to the node calculation unit 581 as the message D580.

That is, the branch data storage memory 542 sequentially reads five messages D542 ₁ from the FIFO 542 ₁ stored in step S113 described later, and then sequentially sends the messages D542 _{2 to} D542 ₁₈ from the FIFOs 542 _{2 to} 542 _{18 as} well. Read and supply to selector 543.

The selector 543 is supplied from the control unit 552 with a selection signal D553 indicating selection of a FIFO (FIFO from which data is currently read) from which the message data is read out of the FIFOs 542 _{1 to} 542 ₁₈ and the branch data storage memory. Message data D542 _{1 to} D542 ₁₈ are supplied from 542. The selector 543 selects the FIFO from which the current data is read out of the FIFOs 542 _{1 to} 542 _{18 in} accordance with the selection signal D553, and selects five message data D542 supplied from the selected FIFO as message data D543. To the selector 580. Then, the selector 580 selects the message D543 (message u _j ) supplied from the selector 543 based on the selection signal D582 supplied from the control unit 582, and the node calculation unit 581 uses the message D543 as the message D580. To supply.

Note that when the check node operation has not been performed on the reception data D544 supplied from the reception memory 544 and the message D550 is not stored in the branch data storage memory 542, the branch data storage memory 542 The message D580 is not supplied to the node calculation unit 582 via the selector 543 and the selector 580, and the node calculation unit 582 sets the message u _j to an initial value.

  After step S102, the process proceeds to step S103, where the node calculation unit 581 performs variable node calculation and supplies the calculation result to the cyclic shift circuit 551.

Specifically, the node calculator 581 is supplied with the five messages D580 from the selector 580 in step S102 and the five received data D544 from the received data memory 544, and the message D580 and the received data D544 are received. , One is supplied to each of the node calculators 581 _{1 to} 5815 ₅ of the node calculator 581. Further, the node calculator 581 is supplied with the control signal D583 and the selection signal D584 from the control unit 582, the selection signal D584 and the control signal D583 is supplied to the node calculator 581 ₁ to 581 _5.

The node calculators 581 _{1 to} 5815 ₅ select an operation to be performed based on the selection signal D584. That is, here, the selection signal D584 supplied from the control unit 582, since it represents the selection of the variable node operation, the node calculator 581 ₁ to 581 ₅ performs variable node operation selected by the control unit 582 . In other words, the node calculator 581 ₁ to 581 _5, using messages D580 and the reception data D544, based on the control signal D583, according to equation (1), respectively performs a calculation, obtained as a result of the operation message D581 Is supplied to the cyclic shift circuit 551.

Here, the control signal D583 and the selection signal D584 supplied from the control unit 582 to the node calculation unit 581 respectively correspond to the control signal D362 and the selection signal D361 described with reference to FIG. 18, and the node calculator 581 _1. to 581 _5, based on the selection signal D584, select the operation performed now, follow the control signal D582, via the selector 543 and 580, the message D543 (D542) required from the edge data storage memory 542, respectively 1 While reading each one, variable node calculation is performed using the reception data D544 supplied from the reception data memory 544, and a message D581 obtained as a result of the calculation is supplied to the cyclic shift circuit 551.

  After the processing in step S104, the process proceeds to step S105, where the cyclic shift circuit 551 cyclically shifts five messages D581 corresponding to the five branches obtained as a result of the variable node calculation supplied from the node calculation unit 581. To do.

  Specifically, the cyclic shift circuit 551 is supplied with the message D581 from the node calculation unit 581, and from the control unit 582, the unit corresponding to the branch corresponding to the message D581 is generated from the cyclic matrix. A control signal D559 representing information (Matrix data) as to whether it has been click-shifted is supplied. The cyclic shift circuit 551 cyclically shifts five messages D581 based on the control signal D559, and supplies the result to the switch 540 as a message D550.

  After the process of step S105, the process proceeds to step S106, and the switch 540 selects one of the branch data storage memory 542 and the branch data storage memory 547 based on the control signal D551 supplied in step S101, and selects the selected one. Five messages D550 supplied from the cyclic shift circuit 550 in step S105 are supplied to one branch data storage memory via a switch. That is, here, since the control signal D551 supplied in step S101 represents selection of variable node calculation, the switch 540 selects the branch data storage memory 547 for storing the message from the variable node and selects the selection. The message D550 is supplied to the branch data storage memory 547 via the switch 546.

Specifically, five messages (data) D550 are supplied from the switch 540 to the switch 546, and a control signal D555 indicating information on which row of the check matrix the message (data) D550 belongs to. Supplied. The switch 546 selects the FIFO storing the message D550 from the FIFOs 547 _{1 to} 547 ₆ of the branch data storage memory 547 according to the control signal D555, and supplies the five message data D550 to the selected FIFO in order. I will do it.

Then, the FIFOs 547 _{1 to} 547 ₁₈ of the branch data storage memory 547 collectively store the five message data D550 (message v _i ) supplied from the switch 546 in order.

  After the processing of step S106, the process proceeds to step S107, and the control unit 582 determines whether or not the message of the total number of branches has been calculated by the node calculation unit 581 and determines that the message of the total number of branches has not been calculated. If so, the process returns to step S102 and the above-described processing is repeated.

  On the other hand, in step S107, when the control unit 582 determines that the message of all branches has been calculated by the node calculation unit 581, the control unit 582 proceeds to step S108, and the control unit 582 now performs the calculation performed by the node calculation unit 581. Then, the check node calculation is selected, and the selection signals D551, D582, and D584 that indicate the selection of the variable node calculation generated in step S101 are changed to the selection signals D551, D582, and D584 that indicate the selection of the check node calculation.

After the processing in step S108, the process proceeds to step S109, and the selector 580 supplies the message D580 to the node calculation unit 581 based on the selection signal D582 supplied from the control unit 582 in step S101. Here, since the selection signal D582 changed in step S108 represents the selection of the check node operation, the selector 580 obtains a message (message v) obtained as a result of the variable node operation used for the check node operation in step S106. _The message D547 supplied via the selector 548 is supplied from the branch data storage memory 547 storing _i ) to the node calculation unit 581 as the message D580.

That is, the branch data storage memory 547 sequentially reads the five messages D546 ₁ from the FIFO 547 ₁ stored in step S106, and then sequentially reads the message data D546 _{2 to} D546 ₆ from the FIFOs 547 _{2 to} 547 _{6 as} well. , Supplied to the selector 548.

The selector 548 is supplied from the control unit 582 with a selection signal D556 indicating the selection of the FIFO (FIFO from which data is currently read) from among the FIFOs 547 _{1 to} 547 ₆ to read message data, and the branch data storage memory. Message data D546 _{1 to} D546 ₆ are supplied from 547. The selector 548 selects the FIFO from which the current data is read out of the FIFOs 547 _{1 to} 547 _{6 in} accordance with the selection signal D556, and sets five message data D546 supplied from the selected FIFO as a message D547. , Supplied to the selector 580. Then, the selector 580 selects the message D547 (message v _i ) supplied from the selector 548 based on the selection signal D582 supplied from the control unit 582, and the node calculation unit 581 uses the message D547 as the message D580. To supply.

  After the process of step S109, the process proceeds to step S110, where the node calculation unit 581 performs a check node calculation and supplies the calculation result to the cyclic shift circuit 551.

Specifically, five messages D580 are supplied from the selector 580 to the node calculator 581 in step S109, and one message D580 is supplied to each of the node calculators 581 _{1 to} 5815 ₅ of the node calculator 581. Is done. Further, the node calculator 581 is supplied with the control signal D583 and the selection signal D584 from the control unit 582, the selection signal D584 and the control signal D583 is supplied to the node calculator 581 ₁ to 581 _5.

The node calculators 581 _{1 to} 5815 ₅ select an operation to be performed based on the selection signal D584. That is, here, the selection signal D584 supplied from the control unit 582, since it represents the check node operation, the node calculator 581 ₁ to 581 _5, a check node calculation, which is selected by the control unit 582 . That is, node calculator 581 ₁ to 581 _5, using the message D580, based on the control signal D583, according to equation (7), respectively performs the operation, the cyclic shift circuit messages D581 obtained as a result of the calculation 551 is supplied.

Here, the control signal D583 and the selection signal D584 supplied from the control unit 582 to the node calculation unit 581 respectively correspond to the control signal D362 and the selection signal D361 described with reference to FIG. 18, and the node calculator 581 _1. to 581 _5, based on the selection signal D584, select the operation performed now, follow the control signal D582, via the selector 543 and 580, the message D543 (D542) required from the edge data storage memory 542, respectively 1 A check node operation is performed while reading each data, and a message D581 obtained as a result of the operation is supplied to the cyclic shift circuit 551.

  After the processing of step S111, the process proceeds to step S112, where the cyclic shift circuit 551 cyclically shifts five messages D581 corresponding to the five branches obtained as a result of the check node calculation supplied from the node calculation unit 581. To do.

  Specifically, the cyclic shift circuit 551 is supplied with the message D581 from the node calculation unit 581, and from the control unit 582, the unit corresponding to the branch corresponding to the message D581 is generated from the cyclic matrix. A control signal D559 representing information (Matrix data) as to whether it has been click-shifted is supplied. The cyclic shift circuit 551 cyclically shifts five messages D581 based on the control signal D559, and supplies the result to the switch 540 as a message D550.

  After the process of step S112, the process proceeds to step S113, and the switch 540 selects one of the branch data storage memory 542 and the branch data storage memory 547 based on the control signal D551 changed in step S108, and selects the selected one. In step S112, five messages D550 supplied from the cyclic shift circuit 551 are supplied to one branch data storage memory via a switch. That is, here, since the control signal D551 changed in step S108 represents the selection of the check node calculation, the switch 540 selects the branch data storage memory 542 for storing the message from the check node and selects the selection. The message D550 is supplied to the branch data storage memory 542 via the switch 541.

Specifically, five messages (data) D550 are supplied from the switch 540 to the switch 542, and a control signal D552 indicating information on which column of the check matrix the message (data) D550 belongs to. Supplied. The switch 546 selects the FIFO storing the message D550 from the FIFOs 542 _{1 to} 542 ₁₈ of the branch data storage memory 542 according to the control signal D552, and supplies the five message data D550 to the selected FIFO in order. I will do it.

The FIFOs 542 _{1 to} 542 ₁₈ of the branch data storage memory 542 collectively store the five message data D550 supplied from the switch 541 in order.

  After the processing of step S113, the process proceeds to step S114, and the control unit 582 determines whether or not the message of the total number of branches has been calculated by the node calculation unit 581 and determines that the message of the total number of branches has not been calculated. In the case, the process returns to step S109 and the above-described processing is repeated.

  On the other hand, when the check node calculator 581 determines in step S114 that the message of all branches has been calculated, the control unit 582 ends the process.

  The decoding device 570 repeats the decoding process of FIG. 27 as many times as the number of decoding times, and when the message D550 obtained as a result of the last check node operation is stored in the branch data storage memory 542, the branch data storage memory 542 The message D550 is supplied to a block (not shown) that performs the calculation of the above formula (5). The block (not shown) is further supplied with reception data D544 from the reception data memory 544. The block (not shown) performs the calculation of Expression (5) using the message D550 and the reception data D544, and the calculation result is as follows. Is output as the final decoding result.

As described above, the node calculation unit 581 performs both the variable node calculation and the check node calculation. That is, the variable node operation is performed using the message u _j that is the result of the check node operation, and the check node operation is performed using the message v _i that is the result of the variable node operation. Variable node calculation and check node calculation are performed alternately. Therefore, the node calculator 581 ₁ to 581 ₅ of the node calculator 581, by performing a common blocks required for a variable node calculation and a check node calculation respectively share, alternately variable node calculation and a check node calculation, variable The node calculator and the check node calculator can be shared to form one node calculator, and each of the nodes shown in FIG. 24 has a variable node calculation unit 545 and a check node calculation unit 549 that perform variable node calculation separately. Compared to the device 530, the circuit scale of the decoding device 570 can be further reduced.

  In the above description, the FIFO is used for storing the branch data (the branch data storage memories 542 and 547 are configured by the FIFO), but a RAM may be used instead of the FIFO. In this case, the RAM needs a bit width from which P pieces of branch information (messages corresponding to the branches) can be read simultaneously and the number of words of the total number of branches / P. Further, in writing to the RAM, the number of the data to be written is read when the data to be written is read next from the information in the check matrix, and the data is written at that position. When reading from the RAM, data is read sequentially from the beginning of the address. If RAM is used instead of FIFO, selectors 541 and 546 are not required.

  FIG. 28 shows a decoding apparatus in which RAM is used instead of FIFO for branch data storage and the branch data storage memory 542 and branch data storage memory 547 are further shared.

  FIG. 28 illustrates a configuration example of still another embodiment of a decoding device that decodes an LDPC code represented by the parity check matrix H of FIG. 22 to which the present invention has been applied.

  In the decoding device 600 of FIG. 28, the branch data storage memory 542 and the branch data storage memory 547 of FIG. 26 are further shared to form one branch storage memory 610.

  The decoding device 600 includes a reception data memory 544, a cyclic shift circuit 551, a node calculation unit 581, a branch memory 610, and a control unit 611. That is, the decoding device 600 of FIG. 28 shares the branch data storage memory 542 and the branch data storage memory 547 of the decoding device 570 of FIG. 26 into the branch memory 610, deletes the switch 540 and the selector 580, and 582 is replaced with a control unit 611.

  26, that is, the received data memory 544, the cyclic shift circuit 551, and the node calculation unit 581 of the decoding device 600 of FIG. 28 are the same as those of the decoding device 570 of FIG. Since the description is the same, the description will be omitted.

  In the branch memory 610, five messages D611 corresponding to five branches obtained as a result of the check node calculation by the node calculation unit 581 or the variable node calculation are cyclically shifted from the cyclic shift circuit 551. Five messages D550 are supplied, and the branch memory 610 stores (stores) the five messages D550 supplied from the cyclic shift circuit 551 at the same address, and stores the five messages D550 already stored in five Five messages D610 are simultaneously read and supplied to the node calculator 581.

  That is, the branch memory 610 is supplied from the cyclic shift circuit 551, and reads the five messages D550 stored at the same address in the order used by the node calculation unit 581 for the variable node calculation or the check node calculation. At the same time, the five messages D550 output from the cyclic shift circuit 551 are received at the same time as the five messages are supplied to the node calculation unit 581, and the already read message (message D610) in the branch memory 610 is stored. Write five addresses simultaneously. That is, the branch memory 610 simultaneously reads five messages D610 supplied to the node calculation unit 581 and simultaneously writes five messages D550 supplied from the node calculation unit 581.

  The branch memory 610 stores a result obtained by cyclically shifting the message corresponding to the branch calculated by the variable node calculation or the check node calculation of the node calculation unit 581, and is stored in the branch memory 610. The amount of data to be processed, that is, the storage capacity required for the branch memory 610 is a product of the number of quantization bits of the message and the total number of branches.

  Further, the branch memory 610 can be configured by, for example, a dual port RAM capable of reading and writing simultaneously.

  The control unit 611 controls the control signal D559 or the control signal D583 and the selection signal D584 by supplying them to the cyclic shift circuit 551 or the node calculation unit 581, respectively.

  FIG. 29 is a flowchart for explaining the decoding process of the decoding device 600 of FIG. This process is started, for example, when reception data to be decoded is stored in the reception data memory 544.

  In step S <b> 121, the control unit 611 selects a variable node operation as an operation to be performed by the node calculation unit 581 out of the variable node operation and the check node operation, and receives a selection signal D584 indicating the selection as the node calculation unit 581. To supply.

  After the process of step S121, the process proceeds to step S122, and the node calculation unit 581 performs the current calculation of the variable node calculation and the check node calculation based on the selection signal D584 supplied from the control unit 611 in step S121. A variable node calculation is selected and a variable node calculation is performed.

Specifically, the node calculation unit 581 is supplied with five messages D610 (message u _j ) from the check node stored (stored) in step S129 described later from the branch memory 610 and received data. from use the memory 544 has five received data D544 are supplied, the message D610 as reception data D544 are supplied one by one to each of the node calculator 581 ₁ to 581 ₅ of the node calculator 581. Further, the control signal D583 and the selection signal D584 are supplied from the control unit 611 to the node calculation unit 581.

Note that if the check node operation has not yet been performed on the reception data D544 supplied from the reception memory 544 and the message D550 (D610) is not stored in the branch memory 610, the branch memory 610 , The message D610 is not supplied to the node calculation unit 581, and the node calculation unit 581 sets the message u _j to an initial value.

The node calculators 581 _{1 to} 5815 ₅ select an operation to be performed based on the selection signal D584. That is, here, the selection signal D584 supplied from the control unit 611, since it represents the selection of the variable node operation, the node calculator 581 ₁ to 581 _5, performs variable node operation. In other words, the node calculator 581 ₁ to 581 _5, using messages D610 and the reception data D544, based on the control signal D583, according to equation (1), respectively performs the operation, the message is the result of the calculation D611 Get.

Here, the control signal D583 and the selection signal D584 supplied from the control unit 582 to the node calculation unit 581 respectively correspond to the control signal D362 and the selection signal D361 described with reference to FIG. 18, and the node calculator 581 _1. to 581 _5, based on the selection signal D584, select the operation performed now, follow the control signal D583, the message D610 required from the branch for storing memory 610, reads out one each, from the reception data memory 544 The necessary reception data D544 is read one by one, variable node calculation is performed, and a message D611 as a result of the calculation is obtained.

  After the processing of step S122, the process proceeds to step S123, and the node calculation unit 581 supplies five messages D611 corresponding to the five branches obtained as a result of the variable node calculation to the cyclic shift circuit 551, and step S124. Proceed to

  In step S124, the cyclic shift circuit 551 cyclically shifts the five messages D611 supplied from the node calculation unit 581, and uses the result as five messages D550, which has already been read from the branch memory 610. Store (store) at address (D610). The five messages D550 are stored at the same address.

  After the processing of step S124, the process proceeds to step S125, and the node calculation unit 581 determines whether or not the message for all branches has been calculated. If it is determined that the message for all branches has not been calculated, the process proceeds to step S122. Return and repeat the process described above.

  On the other hand, in step S125, when the control unit 611 determines that the message of the total number of branches has been calculated by the node calculation unit 581, the control unit 611 proceeds to step S126, and the control unit 611 determines that the check node An operation is selected, and the selection signal D584 indicating selection of the variable node calculation generated in step S121 is changed to a selection signal D584 indicating selection of the check node calculation.

  After the process of step S126, the process proceeds to step S127, and the node calculation unit 581 performs a check node calculation as an operation to be performed among the variable node calculation and the check node calculation based on the selection signal D584 changed in step S126. Select and perform check node operation.

Specifically, the node calculation unit 581 is supplied with five messages D610 from the variable node stored (stored) in step S124 from the branch memory 610, and the message D610 is calculated by the node calculation unit 581. One is supplied to each of the devices 581 _{1 to} 5815 ₅ .

The node calculators 581 _{1 to} 5815 ₅ select an operation to be performed based on the selection signal D584 changed in step S126. That is, here, the selection signal D584, since it represents the check node operation, the node calculator 581 ₁ to 581 _5, a check node operation. That is, the node calculators 581 _{1 to} 5815 ₅ each perform an operation according to the equation (7) based on the control signal D583 using the message D610, and obtain a message D611 that is a result of the operation.

Here, the control signal D583 and the selection signal D584 supplied from the control unit 582 to the node calculation unit 581 respectively correspond to the control signal D362 and the selection signal D361 described with reference to FIG. 18, and the node calculator 581 _1. to 581 _5, based on the selection signal D584, select the operation performed now, follow the control signal D583, the message D610 required from the branch for storing memory 610, while reading one each, performs a check node operation, A message D611 that is a result of the calculation is obtained.

  After the process of step S127, the process proceeds to step S128, and the node calculation unit 581 supplies the message D611 corresponding to the branch obtained as a result of the check node operation to the cyclic shift circuit 551, and the process proceeds to step S129.

  In step S129, the cyclic shift circuit 551 cyclically shifts the five messages D611 supplied from the node calculation unit 581, and uses the result as the message D550 for the address of the message that has already been read from the branch memory 610. To store. The five messages D550 are stored (stored) at the same address.

  After the process of step S129, the process proceeds to step S130, and the control unit 611 determines whether or not the message of the total number of branches has been calculated by the node calculation unit 581 and determines that the message of the total number of branches has not been calculated. In the case, the process returns to step S127, and the above-described processing is repeated.

  On the other hand, in step S130, when the control unit 611 determines that the message of all branches has been calculated by the node calculator 581, the process ends.

Note that the decoding device 600 repeats the decoding process of FIG. 29 as many times as the number of decoding times, and when the message D550 (message u _j ) obtained as a result of the last check node calculation is supplied to the branch memory 610, the branch memory 610 Supplies the message D550 to a block (not shown) that performs the calculation of the above-described equation (5). The block (not shown) is further supplied with reception data D544 from the reception data memory 544. The block (not shown) performs the calculation of Expression (5) using the message D550 and the reception data D544, and the calculation result is as follows. Is output as the final decoding result.

As described above, the branch memory 610 stores a message obtained as a result of the currently executed operation among messages obtained as a result of the variable node operation or the check node operation. That is, the variable node calculation is performed using the message u _j that is the result of the check node calculation, and the check node calculation is performed using the message v _i that is the result of the variable node calculation. Variable node calculation and check node calculation are performed alternately. Therefore, in the decoding device 600, by storing the message obtained as a result of the current operation, the branch data storage memory 542 for storing the message obtained as a result of the variable node operation and the message obtained as a result of the check node operation are stored. The branch data storage memory 547 to be stored can be shared to form one branch memory 610. The memory 542 for storing a variable node message and the memory 547 for storing a check node message are separately provided. Compared to the decoding device 570, the circuit scale of the decoding device 600 can be further reduced.

  FIG. 30 illustrates a configuration example of another embodiment of a decoding device that decodes the LDPC code represented by the parity check matrix H of FIG. 22 to which the present invention has been applied.

In the decoding device 600 of FIG. 30, each block (arithmetic element) constituting each of the node calculators 581 _{1 to} 5815 ₅ of the node calculator 581 of FIG. 28 is further shared, and the calculator of the calculator 641 641 _{1 to} calculator 641 ₅ .

Here, calculations performed by the calculators 641 _{1 to} 641 ₅ of the calculator 641 will be described.

  The calculation unit 641 performs a variable node operation or a check node operation, outputs a message obtained as a result of the operation and stores it in the branch memory, and outputs an intermediate result of the variable node operation or the check node operation. Stored in the memory 640.

Specifically, the calculation unit 641 performs a first calculation according to the above-described formula (1) and the following formula (8), and a second calculation according to the following formula (9). The decoding intermediate result v _i ′ that is the result of the calculation and the decoding intermediate result u _j that is the second calculation result are stored in the memory 640.

・・・（８）

... (8)

・・・（９）

... (9)

That is, the absolute value | v _i '| of the decoding intermediate result v _i ' represented by the equation (8) is equal to the absolute value | φ (| v _i |) | Further, φ (x) is defined by x ≧ 0 and φ (x) = ln ((e ^x +1) / (e ^x −1)) = ln (1 + 2 / (e ^x −1)). , Φ (x) ≧ 0, and | φ (| v _i |) | is equal to φ (| v _i |). Therefore, the absolute value | v _i '| of the decoding result v _i ' is equal to φ (| v _i |). Further, since φ (x) ≧ 0, the sign bit sign (v _i ′) of the decoding intermediate result v _i ′ represented by the equation (8) is equal to the sign bit sign (v _i ) on the right side. As a result, φ (| v _i |) in equation (7) described above can be replaced with | v _i '|, and sign (v _i ) in equation (7) can be replaced with sign (v _i '). The message u _j represented by the above-described equation (7) can be represented by the above-described equation (9) using the decoding intermediate result v _i ′.

  Accordingly, the calculation unit 641 alternately performs the first calculation according to the expressions (1) and (8) and the second calculation according to the expression (9), and is not illustrated after the last second calculation. This block performs the calculation of the above equation (5), so that iterative decoding of the LDPC code can be performed.

Here, the second calculation result according to the equation (9) is described as a decoding intermediate result u _j, and this decoding intermediate result u _j is equal to the check node calculation result u _j of the equation (7).

  The decoding device 630 in FIG. 30 includes the calculation unit 641 instead of the node calculation unit 581 in FIG. 28, and the branch memory 610 is replaced with the memory 640 and the control unit 611 is replaced with the control unit 642.

  That is, the decoding device 630 includes a reception data memory 544, a cyclic shift circuit 551, a memory 640, a calculation unit 641, and a control unit 642.

  28, ie, the received data memory 544 and the cyclic shift circuit 551 of the decoding device 630 of FIG. 30 are the same as those of the decoding device 600 of FIG. The description will be omitted because it is repeated.

  The memory 640 is supplied from the cyclic shift circuit 551 with five decoding intermediate results D640 obtained by cyclically shifting the five decoding intermediate results D642, which are the operation results of the calculation unit 641, and the memory 640 includes the cyclic shift circuit. Five decoding intermediate results D640 supplied from 551 are simultaneously stored (stored) in the same address, and five already stored decoding intermediate results D640 are simultaneously used as five messages D641 as a calculation unit. 641. Note that, when the memory 650 stores the decoding intermediate result D630 obtained as a result of the last second calculation by the calculation unit 641, the decoding intermediate result D630 is calculated using the above-described equation (5). Supply to the block.

  That is, the memory 640 reads out five decoding intermediate results D640 supplied from the cyclic shift circuit 551 and stored at the same address at the same time, and supplies them to the calculation unit 641 as the decoding intermediate results D641 simultaneously. Five decoding intermediate results D640 output from the shift circuit 551 are received, and five of them are written simultaneously to the address where the decoding intermediate results (decoding intermediate results D640) already read out of the memory 640 are stored. That is, the memory 640 simultaneously reads five decoding intermediate results D640 supplied to the calculation unit 641 and simultaneously writes five decoding intermediate results D640 supplied from the calculation unit 641.

  The memory 640 stores the result of cyclic shift of the decoding intermediate result calculated by the first calculation or the second calculation of the calculation unit 641, so that the amount of data stored in the memory 640, That is, the storage capacity required for the branch memory 640 is a product of the number of quantization bits of the message and the number of “1” in the check matrix H of FIG.

  In addition, the memory 640 can be configured by, for example, a dual port RAM capable of reading and writing simultaneously.

The calculation unit 641 includes five calculators 641 _{1 to} 641 ₅ . The calculation unit 641, D641 from the memory 640 five decoding intermediate results is supplied, the message D641 is supplied one by one to each of the calculators 641 ₁ to 641 _5. Further, the calculation unit 641, five received data D544 from the reception data memory 544 are supplied, the reception data D544 is supplied one by one to each of the calculators 641 ₁ to 641 _5. Further, a control signal D583 is supplied to the calculation unit 641 from the control unit 642, and a selection signal D643 representing one of the first calculation or the second calculation as the calculation performed by the calculation unit 641 is received. is supplied, the select signal D643 and the control signal D583 is supplied to the calculator 641 ₁ to 641 _5.

The calculators 641 _{1 to} 641 ₅ select one of the first calculation and the second calculation based on the selection signal D643 and perform the selected calculation. That is, the calculators 641 _{1 to} 641 ₅ use the decoding intermediate result D641 supplied from the memory 640 and the received data D544 supplied from the receiving memory 544 based on the control signal D643, and the expressions (1) and (8) ) To perform the first operation for decoding the LDPC code, respectively, or use the message D641 supplied from the memory 640 and respectively to decode the LDPC code according to equation (9). A second calculation is performed.

Then, the calculators 641 _{1 to} 641 ₅ supply five decoding intermediate results obtained as a result of the first calculation or the second calculation to the cyclic shift circuit 551 as decoding intermediate results D642.

  The control unit 642 controls the control signal D559 or the control signal D583 and the selection signal D643 by supplying them to the cyclic shift circuit 551 or the calculation unit 641, respectively.

Figure 31 is a block diagram showing a configuration example of a calculator 641 ₁ in FIG. 30.

Calculator 641 ₁ of Figure 31 performs the first operation or the second operation.

In FIG. 31, the configuration of the calculator 641 ₁ will be described. The calculators 641 _{2 to} 641 ₄ in FIG. 30 are also configured in the same manner as the calculator 641 _{1 in} FIG.

Further, in FIG. 31, as the decoding intermediate result is quantized into a total of 6 bits (bit) to match the sign bit represents a calculator 641 _1. Further, the calculator 641 ₁ of FIG. 31, the clock ck is supplied, the clock ck is to be supplied to the necessary blocks. Each block performs processing in synchronization with the clock ck.

Calculator 641 ₁ in FIG. 31, a selector 661, integrating unit 701, an adder 666, a selector 667, FIFO memory 669, a selector 670, a subtracter 671, LUT672, multiplication unit 702, FIFO memory 678, EXOR circuit 679, a selector 680 Consists of The accumulating unit 701 includes an adder 662, a register 663, a selector 664, and a register 665. The multiplying unit 702 includes an EXOR circuit 673, a register 674, a selector 675, and a register 676.

Calculator 641 ₁ of FIG. 31 is supplied from the control unit 642, for example, based on 1-bit control signal D583 and 1-bit selection signal D643, by using the decoding intermediate results D641 read out from the memory 640 one by one The second calculation is performed according to the equation (9), or the first calculation is performed according to the equations (1) and (8) using the decoding intermediate result D641 and the reception data D544 supplied from the reception data memory 544. Perform the operation.

That is, the calculator 6411 ₁ generates a 6-bit decoding intermediate result (V _i ) corresponding to 1 of each column of the parity check matrix or a 6-bit decoding intermediate result (u _j ) corresponding to 1 of each row of the parity check matrix. When the decoding result D641 is read one by one, the lower 5 bits of the absolute value D662 is supplied to the FIFO memory 669, and in the absolute value D662, the 1-bit value “0” is the most significant bit. To the bit extension, and a 6-bit value D663 as a result of the bit extension is supplied to the selector 661. Also, the sign bit D661 which is the most significant bit of the decoding intermediate result D641 is supplied to the EXOR circuit 673 and the FIFO memory 678, respectively. Further, the calculator 641 _1, one by one imported 6-bit decoding intermediate results D641 are supplied to the selector 661.

Further, the control signal D583 is supplied from the control unit 642 to the calculator 6411 ₁ , and the control signal D583 is supplied to the selector 664 and the selector 675. Further, the calculator 641 _1, the control unit 642, a selection signal D643 representative of the one of the selection of the first operation or the second operation is supplied, the selection signal D643 is a selector 661, a selector 667, and the selector 670. Further, the reception data D544 is supplied from the reception data memory 544 to the calculator 6411 ₁ , and the reception data D544 is supplied to the adder 666.

First, the decoding intermediate result u _j of 6 bits corresponding to one row of the parity check matrix will be described calculator 641 _first processing when read in one by one as the decoding intermediate results D641. At this time, the control unit 642 selects the first calculation of the first calculation or the second calculation as the calculation to be performed by the calculator 6411 ₁ , and selects the selection signal D583 indicating the selection as the calculator. 641 and supplies to _1, the value of the control signal D583 for controlling the operation calculator 641 ₁ (second calculation result corresponding to one of the columns of the check matrix H) decoding intermediate results across one row Is changed from “0” to “1”.

Thus, the control unit 642, now as operation performed by the calculator 641 _1, when the first operation is selected, the calculator 641 _1, supplied from the control unit 642, for example, 1-bit control Based on the signal D583, the calculation is performed according to the equations (1) and (8) using the decoding intermediate result D641 read from the memory 640 one by one.

The calculator 641 _1, the decoding intermediate results of 6 bits corresponding to one row of the check matrix D641 (decoding intermediate results u _j) are read in one by one, the absolute value is the lower 5 bits D662 (| u _j | ) Is supplied to the FIFO memory 669, and in the absolute value D662, 1-bit value “0” is added to the most significant bit, so that bit expansion is performed, and this is the result of the bit expansion. A 6-bit value D663 is supplied to the selector 661. Also, the sign bit D661 (sign (u _j )) which is the most significant bit of the decoding intermediate result D641 is supplied to the EXOR circuit 673 and the FIFO memory 678, respectively. Further, the calculator 641 _1, one by one imported 6-bit decoding intermediate results D641 are supplied to the selector 661.

The selector 661 is supplied with a 6-bit decoding intermediate result D641 (decoding intermediate result u _j ) and a 6-bit value D663. The selector 661 is supplied with a selection signal D643 indicating selection of one of the first calculation and the second calculation. The selector 661 selects one of the decoding intermediate result D641 and the value D663 based on the selection signal D643, and supplies the selected one to the adder 662 as a value D664. Here, since the selection signal D643 indicates the selection of the first calculation, the selector 661 supplies the value D641 (u _j ) to the adder 662 as the value D664.

The adder 662 of the integrating unit 701 adds the value D641 (u _j ) and the 9-bit value D665 stored in the register 663 to integrate the value D641, and the 9-bit integrated value obtained as a result. Is stored again in the register 663. When the decoding intermediate result D641 corresponding to 1 over one column of the check matrix is accumulated, the register 663 is reset.

Decoding intermediate result D641 (all decoding intermediate results D641 corresponding to 1 in each row of the check matrix) is read one by one and the integrated value obtained by accumulating the value D641 for one column in the register 663 When (Σu _j from j = 1 to j = d _v ) is stored, the control signal D583 supplied from the control unit 642 changes from 0 to 1. For example, when the column weight is “5”, the control signal D583 is “0” from the first to the fourth clock, and “1” at the fifth clock.

When the control signal D583 is “1”, the selector 664 accumulates the value stored in the register 663, that is, the decoding intermediate result D641 (decoding intermediate result u _j ) corresponding to 1 over one column of the check matrix. was selected 9-bit value D665 (? uj _j from j = 1 to j = d _v), as a value D666, and stores and outputs to the register 665. The register 665 supplies the stored value D666 to the selector 664, the adder 666, and the selector 667 as a 9-bit value D667.

When the control signal D583 is “0”, the selector 661 selects the value D667 supplied from the register 665, outputs it to the register 665, and stores it again. That is, until the decoding intermediate result D641 (decoding intermediate result u _j ) corresponding to 1 over one column of the parity check matrix is integrated, the register 665 converts the previous integrated u _j into the selector 664, the adder 666, and This is supplied to the selector 667.

In the adder 666, the value D667 is supplied from the register 665, and the reception data D544 (LDPC code) is supplied from the reception data memory 544. The adder 666 adds the reception data D544 (reception value u _0i ) supplied from the reception data memory 544 to the value D667, and supplies the value D668 obtained as a result to the selector 667.

  The selector 667 is supplied with the value D668 from the adder 666 and the value D667 from the register 665. Further, the selector 667 is supplied with a selection signal D643 indicating selection of one of the first calculation and the second calculation from the control unit 642. The selector 667 selects one of the value D668 and the value D667 based on the selection signal D643, and supplies the selected value to the subtracter 671 as the value D669. Here, since the selection signal D643 represents selection of the first calculation, the selector 667 selects the value D668 and supplies it to the subtractor 671 as the value D669.

On the other hand, FIFO memories 669, (from j = 1 j = d _v up to? Uj _j) a new value D667 from the register 665 until it is output, 5 bits supplied from the memory 640 decoding intermediate results of D641 The absolute value (| u _j |) is delayed and output as a 5-bit value D670. In the value D670, “0”, which is a 1-bit value, is added to the most significant bit to perform bit extension, and a 6-bit value D671 resulting from the bit extension is supplied to the selector 670. The

  In parallel with the above processing, the EXOR circuit 673 of the multiplying unit 702 multiplies the sign bits by calculating the exclusive OR of the 1-bit value D673 stored in the register 674 and the sign bit D661. The 1-bit multiplication result D672 is re-stored in the register 674. In addition, when the sign bit D661 of the decoding intermediate result D641 corresponding to 1 over one column of the check matrix is multiplied, the register 674 is reset.

  When the multiplication result D672 obtained by multiplying the code bit D661 of the decoding intermediate result D641 corresponding to 1 over one column of the check matrix is stored in the register 674, the control signal D583 supplied from the control unit 642 is “0”. Changes to "1".

  When the control signal D583 is “1”, the selector 675 multiplies the value stored in the register 674, that is, the value D673 obtained by multiplying the sign bit D661 of the decoding intermediate result D641 corresponding to 1 over one column of the check matrix. Is output to the register 676 and stored as a 1-bit value D674. The register 676 supplies the stored value D674 to the selector 675 and the EXOR circuit 679 as a 1-bit value D675.

  When the control signal D583 is “0”, the selector 675 selects the value D675 supplied from the register 674, outputs it to the register 676, and stores it again. In other words, the register 676 supplies the previously stored value to the selector 675 and the EXOR circuit 679 until the sign bit D661 of the decoding intermediate result D641 corresponding to 1 over one column of the check matrix is multiplied.

On the other hand, the FIFO memory 678 delays the sign bit D661 (sign (u _j )) until a new value D675 is supplied from the register 676 to the EXOR circuit 679, and outputs it as a 1-bit value D676. The 1-bit value D676 (sign (u _j )) output from the FIFO memory 678 is set as the most significant bit, and the 5-bit value D670 (| u _j |) output from the FIFO memory 669 is set as the lower 5 bits. The total 6-bit value D678 (u _j ) thus supplied is supplied to the selector 670. The 1-bit value D676 is supplied to the EXOR circuit 679.

The selector 670 is supplied with a 6-bit value D671 from the FIFO memory 669 and a 6-bit value D678 (u _j ). The selector 670 is supplied with a selection signal D643 from the control unit 642. The selector 670 selects one of the value D671 and the value D678 based on the selection signal D643 indicating selection of one of the first calculation and the second calculation, and uses the selected value as the value D679 as a subtracter 671. To supply. Here, since the selection signal D643 represents the selection of the first calculation, the value D678 (u _j ) is output to the subtracter 671 as the value D679.

The subtractor 671 subtracts the 6-bit value D679 supplied from the selector 670 from the 9-bit value D669 supplied from the selector 667, and outputs the subtraction result as a 6-bit subtraction value D680. That is, the subtractor 671 determines the parity check matrix from the sum of the integration value of the decoding intermediate result D641 (decoding intermediate result u _j ) corresponding to 1 over one column of the parity check matrix and the reception data D643 (reception value u _0i ). The subtraction result D641 (u _j ) corresponding to the predetermined 1 is subtracted, and the subtraction value (the sum of Σu _j from j = 1 to j = d _v −1 and the received value u _0i , that is, v _i ) is output as a 6-bit subtraction value D680. That is, in the subtracter 671, among the decoding results corresponding to 1 of each column of the parity check matrix, a value obtained by adding all of the decoding results other than the decoding result corresponding to the predetermined 1 of the parity check matrix and the value obtained by adding the reception data D544 are obtained. Output as subtraction value D680. The output subtraction value D680 is supplied to the LUT 672 with the lower 5 bits as the value D681 (| v _i |), and is supplied to the selector 680 with the upper 1 bit as the sign bit D683 (sign (v _i )). . The decoding result corresponding to “predetermined 1” here is u _j corresponding to the message from the branch for which the decoding intermediate result v _i ′ is to be obtained by the operations of equations (1) and (8).

The LUT 672 outputs a 5-bit calculation result D682 (φ (| v _i |)) obtained by calculating φ for the value D681 (| v _i |). In other words, a value obtained by converting the value D681 by using the function of φ is read and output as the calculation result D682.

  On the other hand, the EXOR circuit 679 calculates the exclusive DOR of the 1-bit value D675 supplied from the register 676 and the 1-bit value D676 supplied from the FIFO memory 678 to obtain the value D675 as the value D676. The 1-bit division result is supplied to the selector 680 as a division value D684.

The selector 680 is supplied with the 1-bit sign bit D683 (sign (v _i )) supplied from the subtractor 671 and the EXOR circuit 679 with the 1-bit division value D684. The selector 680 is supplied with a selection signal D643 from the control unit 642. The selector 680 selects one of the sign bit D683 and the division value D684 based on the selection signal D643 indicating selection of either the first operation or the second operation, and sets the selected 1-bit value to D685. As output. Here, since the selection signal represents the selection of the first calculation, the value D683 (sign (v _i )) is output as the value D685.

The 5-bit operation result D682 (φ (| v _i |) output from the LUT 672 is set to the lower 5 bits, and the 1-bit value D685 (sign (v _i )) output from the selector 680 is set to the most significant bit. A decoding intermediate result D642 (decoding intermediate result v _i ′) of 6 bits in total is output, that is, the operation result D682 and the value D685 are multiplied to be the first operation result corresponding to the predetermined 1 of the parity check matrix. Decryption intermediate result D642 is output.

As described above, the control unit 642, a calculation performed in the calculator 641 _1, when the first operation is selected, the calculator 641 _1, the operation of equation (1) and equation (8) is performed, A decryption result v _i 'is obtained.

Next, the way the corresponding 6-bit decoding one of each column of the check matrix results v _i 'is explained calculator 641 _first processing when read in one by one as the decoding intermediate results D641. At this time, the control unit 642 selects the second calculation of the first calculation or the second calculation as the calculation to be performed by the calculator 6411 ₁ and selects the selection signal D583 indicating the selection as the calculator. 641 _1, and the value of the control signal D583 for controlling the calculation is calculated by the calculator 641 ₁ during decoding (the result of the first calculation corresponding to 1 in each row of the check matrix H). Is changed from “0” to “1”.

In the calculator 641 ₁ , even when the control unit 642 selects the second calculation as the calculation performed by the calculator 6411 ₁ , the calculation is performed in the same manner as when the first calculation is selected. Since D643 represents the selection of the second operation, in selector 661, selector 667, selector 670, and selector 680, the other value different from the case where the selection signal D643 described above represents the selection of the first operation. Is selected.

That is, the control unit 642, now as operation performed by the calculator 641 _1, when the second operation is selected, the calculator 641 _1, supplied from the control unit 642, for example, 1-bit control signal D583 Based on the above, the calculation is performed according to the equation (9) using the intermediate decoding result D641 read from the memory 640 one by one.

The calculator 641 _1, 6-bit decoding intermediate results corresponding to 1 in each column of the check matrix D641 (decoding intermediate results v _i ') are read in one by one, the absolute value is the lower bit D662 (| v _i '|) Is supplied to the FIFO memory 669, and in the absolute value D662, 1-bit value “0” is added to the most significant bit to perform bit expansion, and the result of the bit expansion A 6-bit value D663 is supplied to the selector 661. Also, the sign bit D661 (sign (v _i ′)) which is the most significant bit of the decoding intermediate result D641 is supplied to the EXOR circuit 673 and the FIFO memory 678, respectively. Further, the calculator 641 _1, one by one imported 6-bit decoding intermediate results D641 are supplied to the selector 661.

The selector 661 is supplied with a 6-bit decoding intermediate result D641 and a 6-bit value D663 (| v _i '|). The selector 661 is supplied with a selection signal D643 indicating selection of one of the first calculation and the second calculation. The selector 661 selects one of the decoding intermediate result D641 and the value D663 based on the selection signal D643, and supplies one of them as a value D664 to the adder 662. Here, since the selection signal D643 indicates selection of the second calculation, the selector 661 supplies the value D663 (| v _i '|) to the adder 662 as the value D664.

The adder 662 of the accumulating unit 701 adds the value D664 (| v _i '|) and the 9-bit value D665 stored in the register 663, thereby accumulating the value D664, and the 9-bit obtained as a result. Is stored again in the register 663. Note that the register 663 is reset when the value D664 for the absolute value D662 (| v _i |) of the decoding intermediate result D641 corresponding to 1 over one row of the parity check matrix is accumulated.

  The decoding intermediate result D641 (all decoding intermediate results D641 of each column of the check matrix) for one row of the check matrix is read one by one, and the integrated value obtained by integrating the value D664 for one row is stored in the register 663. In this case, the control signal D583 supplied from the control unit 642 changes from 0 to 1. For example, when the row weight is “9”, the control signal D583 is “0” from the first to the eighth clock, and “1” at the ninth clock.

When the control signal D583 is “1”, the selector 664 selects the value stored in the register 663, that is, the absolute value (| v _i '|) of the decoding intermediate result D641 corresponding to 1 over one row of the check matrix. There accumulated a 9-bit value D665 (from i = 1 to _{i = d c Σ | v i} '|) is selected, as a value D666, and stores and outputs to the register 665. The register 665 supplies the stored value D666 to the selector 664, the adder 666, and the selector 667 as a 9-bit value D667.

When the control signal D583 is “0”, the selector 664 selects the value D667 supplied from the register 665, outputs it to the register 665, and stores it again. That is, until the absolute value D664 (| v _i '|) of the decoding intermediate result D641 corresponding to 1 over one row of the check matrix is accumulated, the register 665 selects | v _i ' | 664, an adder 666, and a selector 667.

  In the adder 666, the value D667 is supplied from the register 665, and the reception data D544 is supplied from the reception data memory 544. The adder 666 adds the reception data D544 supplied from the reception data memory 544 to the value D667, and supplies the resulting value D668 to the selector 667.

  The selector 667 is supplied with the value D668 from the adder 666 and the value D667 from the register 665. Further, the selector 667 is supplied with a selection signal D643 indicating selection of one of the first calculation and the second calculation from the control unit 642. The selector 667 selects one of the value D668 and the value D667 based on the selection signal D643, and supplies the selected value to the subtracter 671 as the value D669. Here, since the selection signal D643 indicates selection of the first calculation, the selector 667 selects the value D667 and supplies it to the subtractor 671 as the value D669.

On the other hand, the FIFO memory 669 decodes the 5-bit supplied from the memory 640 until a new value D667 (Σ | v _i '| from i = 1 to i = d _C ) is output from the register 665. The absolute value D662 (| v _i '|) of the midway result D641 is delayed and output as a 5-bit value D670. In the value D670, 1-bit value “0” is added to the most significant bit to perform bit expansion, and the 6-bit value D671 (| v _i '|) as a result of the bit expansion. Is supplied to the selector 670.

In parallel with the above processing, the EXOR circuit 673 of the multiplication unit 702 calculates the exclusive OR of the 1-bit value D673 stored in the register 674 and the sign bit D661 (sign (v _i ′)). Thus, the sign bits are multiplied and the 1-bit multiplication result D672 is stored again in the register 674. Note that when the decoding bit D661 of the decoding intermediate result D641 corresponding to 1 over one row of the check matrix is multiplied, the register 674 is reset.

  When the multiplication result D672 obtained by multiplying the sign bit D661 of the decoding intermediate result D641 corresponding to 1 over one row of the check matrix is stored in the register 674, the control signal D583 supplied from the control unit 642 is “0”. Changes to "1".

When the control signal D583 is “1”, the selector 675 has the value D673 obtained by multiplying the value stored in the register 674, that is, the code bit D661 of the decoding intermediate result D641 corresponding to 1 over one row of the check matrix. (i = 1 from up to _{i = d c Πsign (v i} ')) is selected, to store output as 1-bit value D674 to the register 676. The register 676 supplies the stored value D674 to the selector 675 and the EXOR circuit 679 as a 1-bit value D675.

  When the control signal D583 is “0”, the selector 675 selects the value D675 supplied from the register 676, outputs it to the register 676, and stores it again. In other words, the register 676 supplies the previously stored value to the selector 675 and the EXOR circuit 679 until the sign bit D661 of the decoding intermediate result D641 corresponding to 1 over one row of the parity check matrix is multiplied.

  On the other hand, the FIFO memory 678 delays the sign bit D661 until a new value D675 is supplied from the register 676 to the EXOR circuit 679, and outputs it as a 1-bit value D676. A 1-bit value D676 output from the FIFO memory 678 is set as the most significant bit, and a total 6-bit value D678 including the 5-bit value D670 output from the FIFO memory 669 as the lower 5 bits is supplied to the selector 670. Is done. The 1-bit value D676 is supplied to the EXOR circuit 679.

The selector 670 is supplied with a 6-bit value D671 (| v _i '|) from the FIFO memory 669 and a 6-bit value D678. The selector 670 is supplied with a selection signal D643 from the control unit 642. The selector 670 selects one of the value D671 and the value D678 based on the selection signal D643 indicating selection of one of the first calculation and the second calculation, and uses the selected value as the value D679 as a subtracter 671. To supply. Here, since the selection signal D643 represents the selection of the second calculation, the value D671 (| v _i '|) is output to the subtractor 671 as the value D679.

The subtractor 671 subtracts the 6-bit value D679 supplied from the selector 670 from the 9-bit value D669 supplied from the selector 667, and outputs the subtraction result as a 6-bit subtraction value D680. That is, the subtractor 671 calculates the decoding intermediate result corresponding to a predetermined 1 of the parity check matrix from the integrated value of the absolute value D662 (| v _i '|) of the decoding intermediate result D641 corresponding to 1 over one row of the parity check matrix. The absolute value (| v _i '|) of D641 is subtracted, and the subtraction value (Σ | v _i ' | from i = 1 to i = d _c -1) is output as a 6-bit subtraction value D680. That is, in the subtracter 671, a value obtained by integrating all of the absolute values D662 of the decoding intermediate result D641 corresponding to 1 over one row of the parity check matrix except for the decoding intermediate result D641 corresponding to the predetermined 1 of the parity check matrix. Is output as the subtraction value D681. The output subtraction value D680 is supplied to the LUT 672 as its lower 5 bits as a value D681 and supplied to the selector 680 as its most significant bit as a sign bit D683. The decoding result corresponding to “predetermined 1” here is v _i ′ corresponding to the message from the branch for which the message u _{j is} to be obtained by the calculation of Expression (9).

The LUT 672 calculates a 5-bit calculation result D682 (φ ⁻¹ (Σ (v (v) ′)) by performing φ ⁻¹ calculation on the value D681 (Σ (v _i ′) from i = 1 to i = d _c −1) _i '))) is output. That is, in the LUT 672, a value obtained by converting the value D681 using a function of φ ⁻¹ that is an inverse function of φ is read and output as a calculation result D682.

That is, since φ is a function such that φ = φ ⁻¹ , the LUT of φ can be used as the LUT of φ ⁻¹ . That is, the LUT with φ = φ ⁻¹ can be shared.

On the other hand, the EXOR circuit 679 calculates the exclusive DOR of the 1-bit value D675 supplied from the register 676 and the 1-bit value D676 supplied from the FIFO memory 678 to obtain the value D675 as the value D676. The 1-bit division result is supplied to the selector 680 as a division value D684. That, EXOR circuit 679, the multiplication value of the sign bit D661 of the decoding intermediate result D641 corresponding to one across one line of the parity check matrix (Paisign of i = 1 to _{i = d c (v i '} )), inspection Dividing by the sign bit D661 of the decoding intermediate result D641 corresponding to the predetermined 1 of the matrix, and the division value as a division value D684 (684sign (v _i ′) from i = 1 to i = d _c −1), This is supplied to the selector 680. That is, in the EXOR circuit 679, a value obtained by multiplying all the sign bits D661 of the decoding intermediate result D641 corresponding to 1 over one row of the check matrix except the sign bit D661 corresponding to the predetermined 1 of the check matrix is obtained. , And output as a division value D684. The decoding intermediate result D641 corresponding to “predetermined 1” here is v _i ′ corresponding to the message from the branch for which the message u _{j is} to be obtained by the operation of Equation (9) (second operation).

The selector 680 is supplied with the 1-bit sign bit D683 supplied from the subtractor 671 and the EXOR circuit 679 with the 1-bit division value D684. The selector 680 is supplied with a selection signal D643 from the control unit 642. The selector 680 selects one of the sign bit D683 and the division value D684 based on the selection signal D643 indicating selection of either the first operation or the second operation, and sets the selected 1-bit value to D685. As output. Here, since the selection signal indicates selection of the second calculation, the division value D684 (Πsign (v _i ′) from i = 1 to i = d _c −1) is output as the value D685.

The 5-bit operation result D682 output from the LUT 672 is set to the lower 5 bits, and a total 6-bit decoding result D642 (u _j ) is output using the 1-bit value D685 output from the selector 680 as the most significant bit. Is done. That is, the operation result D682 and the value D685 are multiplied, and a 6-bit decoding result D642 (u _j ) that is a second operation result corresponding to a predetermined 1 of the parity check matrix is output.

As described above, the control unit 642, a calculation performed in the calculator 641 _1, when the second operation is selected, the calculator 641 _1, the calculation of the equation (9) is performed, the decoding intermediate result u _j Is required.

As described above, the calculator 6411 ₁ outputs the decoding intermediate result v _i ′ that is the result of the first calculation and the decoding intermediate result u _j that is the result of the second calculation, and stores them in the memory 640. Thus, the LUT can be shared, and the circuit scale of the calculator 6411 ₁ can be reduced as compared with the node calculator 581 _k (K = 1, 2,... 5). Further, the calculator 641 _1, it is possible to share a single LUT672 the LUT of phi and phi ^-1, it can be performed as compared with the node calculator 581 _k in FIG. 28, the efficient operation.

In calculator 6411 ₁ , when the second calculation is performed, the delay amount in FIFO memory 669 and FIFO memory 678 is reduced to the value of the weight of the row based on the row weight of each row of the check matrix. When the first calculation is performed, the delay amount in the FIFO memory 669 and the FIFO memory 678 is reduced to the weight value of the column based on the column weight of each column of the parity check matrix.

Further, the calculator 641 ₁ of FIG. 31, LUT672 is provided on the output side, the input side, i.e., may be provided before the selector 661.

  FIG. 32 is a flowchart for explaining the decoding process of the decoding device 630 in FIG. This process is started, for example, when reception data to be decoded is stored in the reception data memory 544.

  In step S141, the control unit 642 selects the first calculation as the calculation to be performed among the first calculation and the second calculation, and sends the selection signal D643 indicating the selection to the calculation unit 641. Supply.

  After the processing in step S141, the process proceeds to step S142, and the calculation unit 641 now calculates the calculation unit 641 out of the first calculation and the second calculation based on the selection signal D643 supplied from the control unit 642 in step S141. As the calculation performed in step 1, the first calculation is selected and the first calculation is performed.

Specifically, the calculation unit 641 is supplied with five decoding intermediate results D640 (decoding intermediate result u _j ) stored in step S149 described later from the memory 640, and five from the reception data memory 544. receive data D544 (reception values u _0i) is supplied, the decoding intermediate results D640 and the received data D544, supplied one for each calculator 641 ₁ to 641 ₅ calculator 641. The calculation unit 641 is supplied with a control signal D583 and a selection signal D643 from the control unit 642.

If the second calculation has not yet been performed on the reception data D544 supplied from the reception memory 544 and the decoding intermediate result D640 (D641) is not stored in the memory 640, the memory 640 The decoding intermediate result D640 is not supplied to the calculating unit 641, and the calculating unit 641 sets the decoding intermediate result u _j to an initial value.

The calculators 641 _{1 to} 641 ₅ select an operation to be performed based on the selection signal D643. That is, here, the selection signal D643 supplied from the control unit 642, since it represents the selection of the first operation calculators 641 ₁ to 641 ₅ performs the first operation. That is, the calculators 641 _{1 to} 641 ₅ use the decoding intermediate result D640 and the received data D544, respectively, based on the control signal D583, according to the equation (9), and perform decoding that is the result of the calculation. An intermediate result D642 (v _i ) is obtained.

As described above with reference to FIG. 31, the calculators 641 _{1 to} 641 ₅ select an operation to be performed based on the selection signal D643 and read out the necessary decoding intermediate results D640 one by one from the memory 640. The necessary reception data D544 is read one by one from the reception data memory 544, the first calculation is performed, and a decoding intermediate result D642, which is the result of the calculation, is obtained.

  After the process of step S142, the process proceeds to step S143, and the calculation unit 641 supplies the five intermediate decoding results D642 obtained as a result of the first calculation to the cyclic shift circuit 551, and the process proceeds to step S144.

  In step S144, the cyclic shift circuit 551 cyclically shifts the five decoding intermediate results D642 supplied from the calculation unit 641, and the five decoding intermediate results D640, which are the results, have already been read from the memory 640. Stored in the address of the decoding result (D641). Note that the five intermediate decoding results D640 are stored at the same address.

  After the processing in step S144, the process proceeds to step S145, and the control unit 642 decodes all the decoding intermediate results by the calculation unit 641, that is, decoding for the number of “1” s in the check matrix H in FIG. It is determined whether or not intermediate results have been calculated. If it is determined that not all decoding intermediate results have been calculated, the process returns to step S142 and the above-described processing is repeated.

  On the other hand, in step S145, when the control unit 642 determines that all the decoding intermediate results have been calculated by the calculation unit 641, the control unit 642 proceeds to step S146, and the control unit 642 now determines the second calculation as the calculation to be performed. The calculation is selected, and the selection signal D643 representing the selection of the first calculation generated in step S141 is changed to the selection signal D643 representing the selection of the second calculation.

  After the process of step S146, the process proceeds to step S147, and the calculation unit 641 performs the second calculation as the present calculation to be performed among the first calculation and the second calculation based on the selection signal D643 changed in step S146. An operation is selected and a second operation is performed.

Specifically, the decoding unit 641 is supplied with the five decoding intermediate results D640 stored in step S144 from the memory 640 as decoding intermediate results D641, and the decoding intermediate result D641 is a calculator 641 of the calculator 641. one for each ₁ to 641 ₅ is supplied.

The calculators 641 _{1 to} 641 ₅ select the operation to be performed based on the selection signal D643 changed in step S146. That is, here, the selection signal D643 is because it represents the selection of the second operation, calculators 641 ₁ to 641 _5, a second operation. That is, the calculators 641 _{1 to} 641 ₅ perform computations according to the equations (1) and (8) based on the control signal D583 using the decoding intermediate result D641, respectively, and the decoding that is the result of the computation An intermediate result D642 (u _j ) is obtained.

As described above with reference to FIG. 31, the calculators 641 _{1 to} 641 ₅ select an operation to be performed based on the selection signal D643 and read out the decoding intermediate results D641 required by the memory 640 one by one. The second calculation is performed, and a decoding intermediate result D642 which is the result of the calculation is obtained.

  After the process of step S147, the process proceeds to step S148, and the calculation unit 641 supplies the five intermediate decoding results D642 obtained as a result of the second calculation to the cyclic shift circuit 551, and the process proceeds to step S149.

  In step S149, the cyclic shift circuit 551 cyclically shifts the five decoding intermediate results D642 supplied from the calculation unit 641, and the results are already read from the memory 640 as the five decoding intermediate results D640. Stored in the address of the decoding result (D641). Note that the five intermediate decoding results D640 are stored at the same address.

  After the processing of step S149, the process proceeds to step S150, and the control unit 642 determines whether all the decoding intermediate results have been calculated by the calculation unit 641, and determines that all the decoding intermediate results have not been calculated. Returning to step S147, the above-described processing is repeated.

  On the other hand, in step S150, when the control unit 642 determines that all the decoding intermediate results have been calculated by the calculation unit 641, the control unit 642 ends the process.

Note that the decoding device 630 repeatedly performs the decoding process of FIG. 32 as many times as the number of decoding, and when the decoding intermediate result D642 (u _j ) obtained as a result of the last first calculation is stored in the memory 640, the decoding is in progress The result D642 (u _j ) is supplied to a block (not shown) that performs the calculation of the above equation (5). Reception data D544 is further supplied from the reception data memory 544 to the block not shown. The block (not shown) performs the calculation of Expression (5) using the decoding intermediate result D642 and the reception data D544. The result is output as the final decoding result.

Figure 33 is a flowchart illustrating a first operation processing calculator 641 ₁ in FIG. 31. Note that the flowchart in FIG. 33 is a flowchart for explaining in detail the processing of the first calculation in step S142 in FIG.

In Figure 33, will be described calculator 641 ₁ of the processing of FIG. 31, the same processing even calculators 641 ₂ to calculator 641 ₅ of data is performed.

In step S161, the accumulation unit 701 accumulates the decoding intermediate result D641 (u _j ).

Specifically, the adder 662 of the accumulating unit 701 adds the 6-bit value D641 (u _j ) supplied from the memory 640 and the 9-bit value D665 stored in the register 663, thereby The value D641 is integrated, and the 9-bit integrated value (first integrated value) obtained as a result is stored in the register 663 again.

Decoding intermediate result D641 (all decoding intermediate results D641 corresponding to 1 in each row of the check matrix) is read one by one and the integrated value obtained by accumulating the value D641 for one column in the register 663 When (Σu _j from j = 1 to j = d _v ) is stored, the control signal D583 supplied from the control unit 642 changes from 0 to 1.

When the control signal D583 is “1”, the selector 664 accumulates the value stored in the register 663, that is, the decoding intermediate result D641 (decoding intermediate result u _j ) corresponding to 1 over one column of the check matrix. was selected 9-bit value D665 (? uj _j from j = 1 to j = d _v), as a value D666, and stores and outputs to the register 665. The register 665 supplies the stored value D666 to the selector 664 and the adder 666 as a 9-bit value D667.

When the control signal D583 is “0”, the selector 661 selects the value D667 supplied from the register 665, outputs it to the register 665, and stores it again. That is, until the decoding intermediate result D641 (decoding intermediate result u _j ) corresponding to 1 over one column of the parity check matrix is integrated, the register 665 supplies u _j previously integrated to the selector 664 and the adder 666. To do.

  After the process of step S161, the process proceeds to step S162, where the adder 666 adds the value D667 that is the integrated value obtained in step S161 and the reception data D544 (LDPC code) supplied from the reception data memory 544. Then, a value D666 (added value) is obtained and supplied to the subtracter 671 via the selector 667.

After the processing of step S162, the process proceeds to step S163, and the subtractor 671 calculates the decoding intermediate result D641 (u _j ) corresponding to the predetermined 1 of the parity check matrix from the value D669 (value D667) supplied from the adder 666. The subtraction value (the sum of Σu _j from j = 1 to j = d _v −1 and the reception value u _0i , that is, v _i ) is subtracted 6-bit subtraction value D680 (first subtraction value) Output as.

Specifically, FIFO memories 669, between (from j = 1? Uj _j to j = d _v) a new value D667 from the register 665 until the output, 5 bits of the decoded middle supplied from the memory 640 The absolute value (| u _j |) of the result D641 is delayed and output as a 5-bit value D670.

On the other hand, the FIFO memory 678 delays the sign bit D661 (sign (u _j )) of the decoding intermediate result D641 supplied from the memory 640 until the new value D675 is supplied from the register 676 to the EXOR circuit 679. Output as 1-bit value D676.

The 1-bit value D676 (sign (u _j )) output from the FIFO memory 678 is set as the most significant bit, and the 5-bit value D670 (| u _j |) output from the FIFO memory 669 is set as the lower 5 bits. The total 6-bit value D678 (u _j ) is supplied to the subtracter 671 via the selector 670.

The subtractor 671 subtracts the 6-bit value D679 supplied via the selector 670 from the 9-bit value D669 supplied from the register 665 via the selector 667 and subtracts the subtraction result to 6-bit subtraction. Output as the value D680. That is, the subtractor 671 determines the parity check matrix from the sum of the integration value of the decoding intermediate result D641 (decoding intermediate result u _j ) corresponding to 1 over one column of the parity check matrix and the reception data D643 (reception value u _0i ). The subtraction result D641 (u _j ) corresponding to the predetermined 1 is subtracted, and the subtraction value (the sum of Σu _j from j = 1 to j = d _v −1 and the received value u _0i , that is, v _i ) is output as a 6-bit subtraction value D680. That is, in the subtracter 671, among the decoding results corresponding to 1 of each column of the parity check matrix, a value obtained by adding all of the decoding results other than the decoding result corresponding to the predetermined 1 of the parity check matrix and the value obtained by adding the reception data D544 are obtained. Output as subtraction value D680. The decoding result corresponding to “predetermined 1” here is u _j corresponding to the message from the branch for which the message v _i ′ is to be obtained by the calculation of Expression (1) and Expression (8).

The output subtraction value D680 is supplied to the LUT 672 with the lower 5 bits as the value D681 (| v _i |), and the higher 1 bit as the sign bit D683 (sign (v _i )) via the selector 680. Is output.

After the process of step S163, the process proceeds to step S164, and the LUT 672 performs a function of φ on the value D681 (| v _i |) which is the lower 5 bits (absolute value) of the subtraction value D680 supplied from the subtractor 671. The conversion value (first conversion value) converted using is read and output. That is, the LUT 672 outputs a 5-bit calculation result D682 (φ (| v _i |)) obtained by performing φ calculation on the value D681.

After the processing in step S164, the process proceeds to step S165, and the calculator 6411 ₁ outputs the 5-bit calculation result D682 (φ (| v _i |) output from the LUT 672 and the 1-bit value D685 output from the selector 680. (Sign (v _i )) is multiplied and output as a decoding intermediate result D642 which is a first operation result corresponding to a predetermined 1 of the parity check matrix, that is, the calculator 6411 ₁ has a 5-bit operation result D682. (6 (total decoding result v _i ′) of 6 bits in total, with φ (| v _i |) as the lower 5 bits and a 1-bit value D685 (sign (v _i )) as the most significant bit (second multiplier) is output. the calculator 641 ₁ ends the process.

As described above, the calculator 641 _1, operation of equation (1) and equation (8) is performed, the decoding intermediate results v _i 'is obtained.

Figure 34 is a flow chart for explaining a second operation processing calculator 641 ₁ in FIG. 30. Note that the flowchart in FIG. 33 is a flowchart for explaining in detail the processing of the second calculation in step S147 in FIG.

In Figure 33, it will be described calculator 641 ₁ of the processing of FIG. 31, the other calculators 641 ₂ to calculator 641 ₅ even similar processing is performed.

In step S181, the integrating unit 701 integrates the absolute values | v _i | of the decoding intermediate results v _i supplied from the memory 640.

Specifically, the calculator 641 in _1, 6-bit decoding intermediate results corresponding to 1 in each column of the check matrix D641 (decoding intermediate results v _i ') are read in one by one, the absolute value is the lower bits D662 (| v _i '|) is supplied to the FIFO memory 669, and in the absolute value D662, 1-bit value “0” is added to the most significant bit, thereby performing bit expansion. A 6-bit value D663 as a result of the bit expansion is supplied to the adder 662 of the accumulating unit 701 via the selector 661.

The adder 662 of the accumulating unit 701 adds the value D664 (D663 (| v _i '|)) and the 9-bit value D665 stored in the register 663, thereby accumulating the value D664. The 9-bit integrated value (second integrated value) is stored in the register 663 again.

  The decoding intermediate result D641 (all decoding intermediate results D641 of each column of the check matrix) for one row of the check matrix is read one by one, and the integrated value obtained by integrating the value D664 for one row is stored in the register 663. In this case, the control signal D583 supplied from the control unit 642 changes from 0 to 1.

When the control signal D583 is “1”, the selector 664 selects the value stored in the register 663, that is, the absolute value (| v _i '|) of the decoding intermediate result D641 corresponding to 1 over one row of the check matrix. There accumulated a 9-bit value D665 (from i = 1 to _{i = d c Σ | v i} '|) is selected, as a value D666, and stores and outputs to the register 665. The register 665 supplies the stored value D666 as a 9-bit value D667 to the selector 664 and also supplies it to the subtracter 671 via the selector 667.

When the control signal D583 is “0”, the selector 664 selects the value D667 supplied from the register 665, outputs it to the register 665, and stores it again. That is, until the absolute value D664 (| v _i '|) of the decoding intermediate result D641 corresponding to 1 over one row of the check matrix is accumulated, the register 665 selects | v _i ' | In addition, the signal is supplied to the subtracter 671 via the selector 667.

After the process of step S181, the process proceeds to step S182, where the subtractor 671 determines the absolute value | v _{i of the} predetermined decoding intermediate result v _i ′ from the 9-bit value D669 supplied from the register 665 via the selector 667. '| Is subtracted, and the subtraction result is output as a 6-bit subtraction value D680 (second subtraction value).

Specifically, the FIFO memory 669 is supplied from the memory 640 until the new value D667 (Σ | v _i ′ from i = 1 to i = d _C ) is output from the register 665. The absolute value D662 (| v _i '|) of the bit decoding result D641 is delayed and output as a 5-bit value D670. In the value D670, 1-bit value “0” is added to the most significant bit to perform bit expansion, and the 6-bit value D671 (| v _i '|) as a result of the bit expansion. Is supplied to the subtractor 671 via the selector 670.

The subtracter 671 uses the integrated value of the absolute value D662 (| v _i '|) of the decoding intermediate result D641 corresponding to 1 over one row of the check matrix supplied from the register 665, and the check supplied from the FIFO memory 669. The absolute value (| v _i '|) of the decoding intermediate result D641 corresponding to the predetermined 1 of the matrix is subtracted, and the subtraction value (Σ | v _i ' | from i = 1 to i = d _c −1). Is output as a 6-bit subtraction value D680. That is, in the subtracter 671, a value obtained by integrating all of the absolute values D662 of the decoding intermediate result D641 corresponding to 1 over one row of the parity check matrix except for the decoding intermediate result D641 corresponding to the predetermined 1 of the parity check matrix. Is output as the subtraction value D681. The decoding result corresponding to “predetermined 1” here is v _i ′ corresponding to the message from the branch for which the message u _{j is} to be obtained by the calculation of Expression (9).

  Then, the output subtraction value D680 is supplied to the LUT 672 as the absolute value of the lower 5 bits as the value D681.

After the process of step S182, the process proceeds to step S183, and the LUT 672 causes the value D681 (i = 1 to i = d _c −1 from Σ (v _i ′) which is the absolute value of the subtraction value D680 supplied from the subtractor 671. )), A value (second converted value) converted by using a function of φ ⁻¹ which is an inverse function of φ is read, and a 5-bit operation result D682 obtained by performing an operation of φ ⁻¹ (Φ ^-1 (Σ (v _i '))) is output. That is, the LUT 672 calculates a 5-bit calculation result D682 (φ ⁻¹ (Σ) obtained by performing a calculation of φ ^{−1 on} the value D681 (Σ (v _i ′) from i = 1 to i = d _c −1). (V _i '))) is output.

After the process of step S183, the process proceeds to step S184, where the multiplier 702 multiplies the sign bit of the decoding intermediate result v _i ′.

Specifically, the calculator 641 _1, the sign bit D661 which is the most significant bit of the decoding intermediate result _{D641 (sign (v i ')} ) are supplied to the EXOR circuit 673 and FIFO memory 678. Then, the EXOR circuit 673 of the multiplication unit 702 calculates the exclusive OR of the 1-bit value D673 stored in the register 674 and the sign bit D661 (sign (v _i ′)), thereby obtaining sign bits. The 1-bit multiplication result D672 is stored again in the register 674.

  When the multiplication result D672 obtained by multiplying the sign bit D661 of the decoding intermediate result D641 corresponding to 1 over one row of the check matrix is stored in the register 674, the control signal D583 supplied from the control unit 642 is “0”. Changes to "1".

When the control signal D583 is “1”, the selector 675 has the value D673 obtained by multiplying the value stored in the register 674, that is, the code bit D661 of the decoding intermediate result D641 corresponding to 1 over one row of the check matrix. (i = 1 from up to _{i = d c Πsign (v i} ')) is selected, to store output as 1-bit value D674 to the register 676. The register 676 supplies the stored value D674 to the selector 675 and the EXOR circuit 679 as a 1-bit value D675.

  When the control signal D583 is “0”, the selector 675 selects the value D675 supplied from the register 676, outputs it to the register 676, and stores it again. In other words, the register 676 supplies the previously stored value to the selector 675 and the EXOR circuit 679 until the sign bit D661 of the decoding intermediate result D641 corresponding to 1 over one row of the parity check matrix is multiplied.

After the process of step S184, the process proceeds to step S185, and the EXOR circuit 679 divides the 1-bit value D675 supplied from the register 676 and the sign bit sign (v _i ') of the predetermined decoding intermediate result v _i ', The division result is output as a 1-bit division value D684 (sign multiplication value) via the selector 680.

  That is, the FIFO memory 678 delays the sign bit D661 until the new value D675 is supplied from the register 676 to the EXOR circuit 679, and supplies the delayed sign bit D661 to the EXOR circuit 679.

The EXOR circuit 679 calculates the exclusive OR of the 1-bit value D675 supplied from the register 676 and the 1-bit value D676 supplied from the FIFO memory 678, thereby dividing the value D675 by the value D676. The 1-bit division result is supplied to the selector 680 as a division value D684. That, EXOR circuit 679, the multiplication value of the sign bit D661 of the decoding intermediate result D641 corresponding to one across one line of the parity check matrix (Paisign of i = 1 to _{i = d c (v i '} )), inspection Dividing by the sign bit D661 of the decoding intermediate result D641 corresponding to the predetermined 1 of the matrix, and the division value as a division value D684 (684sign (v _i ′) from i = 1 to i = d _c −1), This is supplied to the selector 680. That is, in the EXOR circuit 679, a value obtained by multiplying all the sign bits D661 of the decoding intermediate result D641 corresponding to 1 over one row of the check matrix except the sign bit D661 corresponding to the predetermined 1 of the check matrix is obtained. The divided value D684 is output via the selector 680. The decoding result corresponding to “predetermined 1” here is v _i ′ corresponding to the message from the branch for which the message u _{j is} to be obtained by the calculation of Expression (9).

After the processing in step S185, the process proceeds to step S186, where the calculator 6411 ₁ , that is, the 5-bit calculation result D682 output from the LUT 672 and the 1-bit value D685 output from the EXOR circuit 679 via the selector 680 are obtained. Are multiplied and output as a 6-bit decoded result D642 (u _j ) which is a second calculation result corresponding to a predetermined 1 of the parity check matrix. That is, a 5-bit decoding result D642 (u _j ) (first multiplication value) is output with the 5-bit operation result D682 as the lower 5 bits and the 1-bit value D685 as the most significant bit. . The calculator 641 ₁ ends the process.

As described above, the calculator 641 _1, performs the operation of equation (9), the decoding intermediate results u _j is obtained.

  If a barrel shifter is used for the above-described cyclic shift circuit, a desired operation can be realized while reducing the circuit scale.

  When the physical bit width of the FIFO or RAM is insufficient, it can be logically regarded as one RAM by giving the same control signal using a plurality of RAMs.

  Further, in the above case, for the sake of simplicity of explanation, the case where P is 5, that is, the case where the number of rows and the number of columns of the constituent matrix constituting the parity check matrix is five is taken as an example. The number of rows and the number of columns P need not necessarily be 5, and may take different values depending on the parity check matrix. For example, P may be 360 or 392.

  In this embodiment, an LDPC code having a code length of 90 and a coding rate of 2/3 is used. However, the LDPC code may have any number of code lengths and coding rates. For example, when the number of rows and the number of columns P of the configuration matrix is 5, and the total number of branches is 5 or less, the LDPC code of any code length and coding rate can be used to perform the decoding of FIG. Decoding is possible using the apparatus 530, the decoding apparatus 570 in FIG. 26, the decoding apparatus 600 in FIG. 28, and the decoding apparatus 630 in FIG.

  Further, a certain LDPC code decoding apparatus that satisfies the condition that the number of rows and the number of columns P of the configuration matrix are predetermined values and the total number of branches is equal to or less than a certain value, an arbitrary code length that satisfies the conditions, and an arbitrary code length An LDPC code with a coding rate can be decoded.

  When the parity check matrix is not a multiple of the number of rows and the number of columns P of the constituent matrix, it may be applied by adding all 0 (all 0) components outside the fraction of the parity check matrix and considering it as a multiple of P.

  Further, in the present embodiment, the parity check matrix is configured from a configuration matrix, but the parity check matrix may not be configured from a configuration matrix.

  Next, the series of processes described above can be performed by hardware or software. When a series of processing is performed by software, a program constituting the software is installed in a general-purpose computer or the like.

  Therefore, FIG. 34 shows a configuration example of an embodiment of a computer in which a program for executing the above-described series of processing is installed.

  The program can be recorded in advance in a hard disk 905 or a ROM 903 as a recording medium built in the computer.

  Alternatively, the program is stored temporarily on a removable recording medium 911 such as a flexible disk, a CD-ROM (Compact Disc Read Only Memory), an MO (Magneto Optical) disk, a DVD (Digital Versatile Disc), a magnetic disk, or a semiconductor memory. It can be stored permanently (recorded). Such a removable recording medium 911 can be provided as so-called package software.

  The program is installed in the computer from the removable recording medium 911 as described above, or transferred from the download site to the computer wirelessly via a digital satellite broadcasting artificial satellite, LAN (Local Area Network), The program can be transferred to a computer via a network such as the Internet. The computer can receive the program transferred in this way by the communication unit 908 and install it in the built-in hard disk 905.

  The computer includes a CPU (Central Processing Unit) 902. An input / output interface 910 is connected to the CPU 902 via a bus 901, and the CPU 902 operates an input unit 907 including a keyboard, a mouse, a microphone, and the like by the user via the input / output interface 910. When a command is input as a result, the program stored in a ROM (Read Only Memory) 903 is executed accordingly. Alternatively, the CPU 902 may be a program stored in the hard disk 905, a program transferred from a satellite or a network, received by the communication unit 908 and installed in the hard disk 905, or a removable recording medium 911 attached to the drive 909. The program read and installed in the hard disk 905 is loaded into a RAM (Random Access Memory) 904 and executed. Thereby, the CPU 902 performs processing according to the above-described flowchart or processing performed by the configuration of the above-described block diagram. Then, the CPU 902 outputs the processing result from the output unit 906 configured with an LCD (Liquid Crystal Display), a speaker, or the like via the input / output interface 910, or from the communication unit 908 as necessary. Transmission, and further recording on the hard disk 905 is performed.

  Here, in this specification, the processing steps for describing a program for causing a computer to perform various types of processing do not necessarily have to be processed in time series according to the order described in the flowchart, but in parallel or individually. This includes processing to be executed (for example, parallel processing or processing by an object).

  Further, the program may be processed by a single computer, or may be processed in a distributed manner by a plurality of computers. Furthermore, the program may be transferred to a remote computer and executed.

It is a figure explaining the check matrix H of an LDPC code. It is a flowchart explaining the decoding procedure of an LDPC code. It is a figure explaining the flow of a message. It is a figure which shows the example of the check matrix of a LDPC code. It is a figure which shows the Tanner graph of a check matrix. It is a figure which shows a variable node. It is a figure which shows a check node. It is a figure which shows the example of the check matrix of a LDPC code. It is a block diagram which shows the structural example of the decoding apparatus of the LDPC code which performs node calculation one by one. It is a block diagram which shows the structural example of the check node calculator which calculates a message one by one. It is a block diagram which shows the structural example of the variable node calculator which calculates a message one by one. It is a block diagram which shows the structural example of the decoding apparatus of the LDPC code which performs all node calculations simultaneously. It is a block diagram which shows the structural example of the check node calculator which calculates a message simultaneously. It is a block diagram which shows the structural example of the variable node calculator which calculates a message simultaneously. It is a block diagram which shows the structural example of one Embodiment of the decoding apparatus to which this invention is applied. It is a flowchart explaining the decoding process of the decoding apparatus of FIG. It is a block diagram which shows the structural example of other one Embodiment of the decoding apparatus to which this invention is applied. It is a block diagram which shows the detailed structural example of the node calculator of the decoding apparatus of FIG. It is a flowchart explaining the decoding process of the decoding apparatus of FIG. It is a block diagram which shows the structural example of other one Embodiment of the decoding apparatus to which this invention is applied. It is a flowchart explaining the decoding process of the decoding apparatus of FIG. It is a figure which shows the example of the check matrix of a LDPC code. It is a block diagram which shows the structural example of a decoding apparatus. It is a block diagram which shows the structural example of other one Embodiment of the decoding apparatus to which this invention is applied. It is a flowchart explaining the decoding process of the decoding apparatus of FIG. It is a block diagram which shows the structural example of other one Embodiment of the decoding apparatus to which this invention is applied. It is a flowchart explaining the decoding process of the decoding apparatus of FIG. It is a block diagram which shows the structural example of other one Embodiment of the decoding apparatus to which this invention is applied. It is a flowchart explaining the decoding process of the decoding apparatus of FIG. It is a block diagram which shows the structural example of other one Embodiment of the decoding apparatus to which this invention is applied. It is a block diagram which shows the detailed structural example of the calculator of FIG. It is a flowchart explaining the decoding process of the decoding apparatus of FIG. It is a flowchart explaining the 1st arithmetic processing of the calculator of FIG. It is a flowchart explaining the 2nd arithmetic processing of the calculator of FIG. It is a block diagram which shows the structural example of one Embodiment of the computer to which this invention is applied.

Explanation of symbols

  300 Decoder, 310 Branch Memory, 311 Switch, 312 Variable Node Calculator, 313 Check Node Calculator, 314 Selector, 315 Receiving Memory, 316 Control Unit, 340 Decoder, 350 Switch, 351 Branch Memory, 352 Branch Memory, 353 selector, 354 node calculator, 355 reception memory, 356 control unit, 430 decoding device, 440 branch memory, 441 node calculator, 442 reception memory, 443 control unit, 530 decoding device, 540 switch, 541 switch, 542 branch data storage memory, 543 selector, 544 received data memory, 545 variable node calculation unit, 546 switch, 547 branch data storage memory, 548 selector 549 check node calculation unit, 550 selector, 551 cyclic shift circuit, 552 control unit, 570 decoding device, 580 selector, 581 node calculation unit, 582 control unit, 600 decoding device, 610 branch memory, 611 control unit, 630 decoding Device, 640 memory, 641 calculation unit, 642 control unit, 901 bus, 902 CPU, 903 ROM, 904 RAM, 905 hard disk, 906 output unit, 907 input unit, 908 communication unit, 909 drive, 910 input / output interface, 911 removable recoding media

Claims (10)

A decoding device for decoding LDPC (Low Density Parity Check) code,
Check node calculation means for performing a check node operation for decoding the LDPC code using a necessary message;
Variable node calculation means for performing a variable node operation for decoding the LDPC code using a necessary message;
Storage means for storing a message obtained as a result of the operation of the check node or the operation of the variable node;
A decoding device comprising: a supply unit that selectively supplies one of the check node calculation unit and the variable node calculation unit to the message stored in the storage unit. The decoding device according to claim 1,
The decoding device, wherein the storage means is a dual port RAM (Random Access Memory) or a single port RAM (Random Access Memory). A decoding method of a decoding device for decoding LDPC (Low Density Parity Check) code,
A check node calculation step for performing a check node operation for decoding the LDPC code by a check node calculation means using a necessary message;
A variable node calculation step for performing a variable node calculation for decoding the LDPC code by a variable node calculation means using a necessary message;
A storage step of storing in a storage means a message obtained as a result of the operation of the check node or the operation of the variable node;
And a supply step of supplying the message stored in the storage means to one of the check node calculation means and the variable node calculation means. A program that causes a computer to decode LDPC (Low Density Parity Check) code,
A check node calculation step of performing a check node operation for decoding the LDPC code by a check node calculation means using a necessary message;
A variable node calculation step for performing a variable node calculation for decoding the LDPC code by a variable node calculation means using a necessary message;
A storage step of storing in a storage means a message obtained as a result of the operation of the check node or the operation of the variable node;
A supply step of supplying the message stored in the storage means to one of the check node calculation means or the variable node calculation means. A decoding device for decoding LDPC (Low Density Parity Check) code,
A selection means for selecting one of a check node operation for decoding the LDPC code or a variable node operation;
Node calculation means for performing the calculation of the check node selected by the selection means or the calculation of the variable node using a necessary message;
Storage means for storing a message obtained as a result of the computation of the check node by the node computation means or the computation of the variable node;
A decoding device comprising: a supply unit configured to supply the message stored in the storage unit to the node calculation unit. The decoding device according to claim 5,
The decoding device, wherein the storage means is a dual port RAM (Random Access Memory) or a single port RAM (Random Access Memory). A decoding method of a decoding device for decoding LDPC (Low Density Parity Check) code,
A selection step of selecting one of a check node operation for decoding the LDPC code or a variable node operation;
A node calculation step for causing the node calculation means to perform an operation of the check node selected by the processing of the selection step or an operation of the variable node using a necessary message;
A storage step of storing in the storage means a message obtained as a result of the calculation of the check node by the node calculation means or the calculation of the variable node;
And a supply step of supplying the message stored by the processing of the storage step to the node calculation means. A program that causes a computer to decode LDPC (Low Density Parity Check) code,
A selection step of selecting one of a check node operation for decoding the LDPC code or a variable node operation;
A node calculation step for causing the node calculation means to perform an operation of the check node selected by the processing of the selection step or an operation of the variable node using a necessary message;
A storage step of storing in the storage means a message obtained as a result of the calculation of the check node by the node calculation means or the calculation of the variable node;
And a supplying step of supplying the message stored by the processing of the storing step to the node calculating means. Check node calculation means for performing a check node operation for decoding the LDPC code using a necessary message;
Variable node calculation means for performing a variable node operation for decoding the LDPC code using a necessary message;
First storage means for storing a message obtained as a result of the check node calculation;
Second storage means for storing a message obtained as a result of the variable node calculation,
The decoding apparatus, wherein the first storage unit and the second storage unit are shared by one storage unit. The decoding device according to claim 9, wherein
Furthermore, the check node calculation unit and the variable node calculation unit are shared by a single node calculation unit.

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