JP2005064717A - State holding device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a state holding device wherein malfunction due to a wrong output of software sporadically caused or noise hardly takes place. <P>SOLUTION: A charge/discharge capacitor C52 in trigger signal generating circuits 11, 13 is charged up at a leading edge of a pulse signal from a microcomputer 5, and the charging electric charges are gradually discharged via resistors R11, R12 and a transistor TR 1 (in the case of the trigger signal generating circuit 11) or via resistors R31, R32 and a transistor TR 2 (in the case of the trigger signal generating circuit 13). The capacitance of the charge/discharge capacitor C52 is selected so as to provide a charging voltage (i.e., a signal level of trigger signals T1, T2) to be an ON voltage or over at which the transistors Tr1, Tr3 are turned on (i.e., activation of a drive current supply circuit 15 and a cancel circuit 19) at the input of the specified number of pulses or over within a specified period. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a state holding device including a hold circuit in which a held signal level is switched by input of a trigger signal.

  Conventionally, when a trigger signal is input, as represented by an RS flip-flop circuit, various self-holding circuits used for automatic control, etc., the output level is switched to a predetermined output level. A hold circuit that keeps the output level is known.

  This type of hold circuit has only one input terminal, and the output level changes each time a trigger signal is input, or a plurality of input terminals (for example, set / reset), and the trigger signal is input. The output level held at the time of being input varies depending on the input terminal.

  Note that such a hold circuit and a state holding device that holds a predetermined state using the hold circuit are related to a publicly known and publicly used technique, and thus no literature is disclosed.

  In such a hold circuit, if noise or software error output is input to the input terminal of the trigger signal, the output level is easily switched to something different from the one intended by the user. There was a problem that it was kept in the switched state.

  For example, when this hold circuit is applied to a device that controls power supply to a drive system of a vehicle, when noise that satisfies a condition as a trigger signal is input to the hold circuit during vehicle travel, It is conceivable that the power supply to the drive system is unexpectedly stopped even though it is in the middle and cannot be controlled.

  Therefore, when such a hold circuit is applied to a device that requires high reliability and safety, such as an in-vehicle device, a circuit for ensuring reliability and safety must be provided separately. There is also a problem that the scale of the apparatus becomes large.

  In order to solve the above-described problems, an object of the present invention is to provide a state holding device that is unlikely to cause a malfunction caused by a single software error or noise.

  In the state holding device of the present invention made to achieve the above object, the trigger signal generation circuit receives a trigger signal when a predetermined number of pulse signals set in advance within a predetermined period set in advance. The hold circuit switches the signal level held by the input of the trigger signal generated by the trigger signal generation circuit.

That is, the trigger signal generation circuit does not generate a trigger signal due to a single erroneous software output or noise (hereinafter simply referred to as “noise etc.”).
Therefore, according to the state holding device of the present invention, the malfunction of the hold circuit due to noise or the like can be prevented, and even if the device is applied to a device used in a noisy environment, the reliability and safety of the device Can be secured sufficiently.

  When the hold circuit includes a plurality of input terminals (for example, set / reset) and is configured to have different signal levels when a trigger signal is input for each input terminal, the trigger signal generation circuit Is preferably provided for each input terminal.

  In addition, the specified period and the specified number of settings in the trigger signal generation circuit take into account the characteristics of noise generated at the place where the device is used (for example, if burst noise occurs, the specified number is set sufficiently large). Etc.).

  By the way, as the trigger signal generation circuit, for example, a frequency / voltage conversion circuit that generates an output signal having a signal level corresponding to the pulse interval (pulse frequency) of the pulse signal can be used. The output signal may be used as a trigger signal as it is.

  Specifically, the frequency / voltage conversion circuit uses, for example, a capacitor charged by a pulse signal and a discharge circuit that discharges the capacitor at a constant rate, and has an output having a signal level corresponding to the charging voltage of the capacitor. It can be configured to generate a signal (ie, a trigger signal).

  In this case, the setting relating to the pulse signal (specified period, specified number) is such that the next pulse signal is input before the capacitor charged by the pulse signal is completely discharged by the discharge circuit, and the trigger signal is What is necessary is just to determine suitably so that the signal level which satisfy | fills conditions may be obtained.

  In addition, the trigger signal generation circuit, for example, counts the input pulse signal, and when the count value reaches a preset threshold value, a counter that generates a trigger signal, and a preset period, You may comprise by the free run timer which produces | generates the signal which resets a counter. In this case, since the trigger signal generation circuit can be configured by a logic circuit, it can also be configured as a semiconductor integrated circuit, which is suitable when downsizing of the device is required. In this case, if the hold circuit is also configured using a logic circuit such as an RS flip-flop circuit, the apparatus can be further downsized.

  The state holding device of the present invention can be used by being incorporated in, for example, an in-vehicle device used in a noisy environment. In particular, when the output of the hold circuit is used as a control signal for controlling the energization state of the power supply line provided in the vehicle, the power supply is unexpectedly stopped due to noise or the like while the vehicle is running. Can be prevented, and the safety and reliability of the vehicle can be sufficiently secured.

Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a configuration diagram of a power supply system to which the state holding device of the present invention is applied.
In addition, the power supply system of this embodiment controls the energization state of the electric power feeding line provided in order to supply electric power to the various vehicle-mounted apparatuses mounted in a vehicle.

  As shown in FIG. 1, the power supply system 1 of this embodiment includes a push button switch 3 for inputting a command for instructing start and stop of power feeding, and a port for outputting a hold pulse signal P1 composed of a plurality of pulse trains. And a microcomputer that outputs a cancel pulse signal P2 composed of a plurality of pulse trains, and operates so as to alternately output one of the signals P1 and P2 each time the pushbutton switch 3 is pressed. (Hereinafter referred to as “microcomputer”) 5, and the supply state of the drive current Id to the drive coil of the relay RLY connected in series to the power supply line L is switched according to the hold pulse signal P 1 and the cancel pulse signal P 2 from the microcomputer 5. And a state holding device 7.

In this configuration, the drive current Id can continue to flow even if both the hold pulse signal P1 and the cancel pulse signal P2 are output.
The state holding device 7 cancels the first trigger signal generation circuit 11 that generates the hold trigger signal T1 when the hold pulse signal P1 is input from the microcomputer 5 and the cancel pulse signal P2 that is input from the microcomputer 5. The second trigger signal generation circuit 13 that generates the trigger signal T2, the drive current supply circuit 15 that starts the supply of the drive current Id when the hold trigger signal T1 is input (at the active level), and the hold trigger signal When the cancellation trigger signal T2 and the holding current supply circuit 17 for supplying a holding current for continuing the supply of the driving current Id to the driving current supply circuit 15 after the disappearance of T1 (returning to the inactive level) are input. The cancel circuit 1 interrupts the holding current and stops the drive current supply circuit 15 from supplying the drive current Id. It is equipped with a door.

  The drive current supply circuit 15, the holding current supply circuit 17, and the cancel circuit 19 correspond to the hold circuit in the present invention, and the first and second trigger signal generation circuits correspond to the trigger signal generation circuit in the present invention.

  Among them, the drive current supply circuit 15 includes an NPN transistor Tr1 whose emitter is grounded and the hold trigger signal T1 from the first trigger signal generation circuit 11 is applied to the base via the resistor R12, and the emitter is a power source. A current supply line Ld for supplying a drive current Id to the drive coil of the relay RLY, and a PNP transistor Tr2 whose base is connected to the collector of the transistor Tr1 via a resistor R22. The hold trigger signal T1 When the transistor Tr1 is turned on, the transistor Tr2 is also turned on so that the drive current Id flows through the current supply line Ld.

  Further, in the drive current supply circuit 15, a resistor and a capacitor constituting a filter for removing noise applied to the gates between the gates and the emitters of the transistors Tr1 and Tr2 (R12, C11 and transistor Tr2 in the transistor Tr1). Then, resistors R11 and R21 for stabilizing the gate potentials of R22, C21) and Tr1, Tr2 are connected, and further, an excessive voltage is applied to the transistor Tr2 between the emitter and collector of the transistor Tr2. A diode D22 for preventing the backflow of the drive current Id is connected to the Zener diode D21 to be prevented and the current supply line Ld.

  Next, the holding current supply circuit 17 is configured by connecting a pair of resistors R41 and R42 and a diode D41 in series, one end being the collector of the transistor Tr2 (current supply line Ld) and the other end being the base of the transistor Tr1. It is connected. However, the diode D41 is connected so that a current flows from the current supply line Ld toward the base of the transistor Tr1.

  That is, when the drive current Id is not supplied by the drive current supply circuit 15 (that is, the transistors Tr1 and Tr2 are off), the diode D41 is also turned off, so that the transistor Tr1 operates according to the hold trigger signal T1. On the other hand, when the driving current Id is supplied by the driving current supply circuit 15 (that is, the transistors Tr1 and Tr2 are on), the holding current is supplied from the current supply line Ld to the base of the transistor Tr1 via the holding current supply circuit 17. Therefore, even if the hold trigger signal T1 disappears, the on state of the transistor Tr1 is maintained and the supply of the drive current Id is continued.

  Next, the cancel circuit 19 includes an NPN transistor Tr3 whose emitter is grounded and the cancel trigger signal T2 from the second trigger signal generation circuit 13 is applied to the base via the resistor R32, and the collector of the transistor Tr3. Is connected to a common connection point of a pair of resistors R41 and R42 constituting the holding current supply circuit 17 via a resistor R33.

  In the cancel circuit 19, a capacitor C31 constituting a filter for removing noise applied to the gate and a resistor R31 for stabilizing the gate potential are connected in parallel between the gate and emitter of the transistor Tr3. .

  That is, when the transistor Tr3 is turned on by the cancel trigger signal T2, the potential on the anode side of the diode D41 is lowered and the diode D41 is turned off. At this time, if the signal level of the hold trigger signal T1 is not large enough to turn on the transistor Tr1, the transistor Tr1 is turned off. As a result, the transistor Tr2 is also turned off, and the supply of the drive current Id is stopped.

  Next, the first trigger signal generation circuit 11 includes an AC coupling capacitor C51 having one end connected to the port of the microcomputer 5 that outputs the hold pulse signal P1 via the resistor R51, and the AC coupling capacitor C51. And a charge / discharge capacitor C52 charged by a pulse signal supplied via the diode, and diodes D51 and D52 forming a charge supply path such that the charge / discharge capacitor C52 is charged only at the rising edge of the pulse signal. . The first trigger signal generation circuit 11 is connected so as to supply a hold trigger signal T1 whose signal level is the charging voltage of the charge / discharge capacitor C52 to the transistor Tr1 of the drive current supply circuit 15.

  The second trigger signal generation circuit 13 is configured in exactly the same way as the first trigger signal generation circuit 11, and the cancel trigger signal T 2 having the charge voltage of the charge / discharge capacitor C 52 as the signal level is supplied to the cancel circuit 19. The transistors Tr3 are connected so as to be supplied.

  In the trigger signal generation circuits 11 and 13 configured as described above, the charging / discharging capacitor C52 is charged at the rising edge of the pulse signal from the microcomputer 5, and the charged charges are the resistances R11 and R12 and the transistor Tr1 (trigger signal In the case of the generation circuit 11), or is gradually discharged via the resistors R31 and R32 and the transistor Tr2 (in the case of the trigger signal generation circuit 13). Accordingly, when the next pulse is input before the charge of the charge / discharge capacitor C52 is completely discharged, the charge voltage of the charge / discharge capacitor C52 depends on the pulse period (pulse frequency) of the input pulse signal. It becomes the size.

  That is, the trigger signal generation circuits 11 and 13 operate as so-called frequency / voltage (F / V) conversion circuits, and the resistors R11 and R12, the transistor Tr1, the resistors R31 and 32, and the transistor Tr2 are the discharge circuit in the present invention. Equivalent to.

  However, the capacity of the charge / discharge capacitor C52 is based on a charge amount determined by one pulse signal and a discharge amount determined by the resistance values of the resistors R11, R12 and R31, 32 as shown in FIG. When a predetermined number N of pulses (N = 3 in the figure) are input at the interval W, the charging voltage is set to be equal to or higher than the ON voltage for turning on the transistors Tr1 and Tr3.

  In other words, the trigger signals T1 and T2 generated by the trigger signal generation circuits 11 and 13 are set to the ON voltage of the transistors Tr1 and Tr3 when N or more pulses are input within a specified period (W × N). To be reached. Further, based on this, the microcomputer 5 is configured to output a hold pulse signal P1 and a cancel pulse signal P2 composed of N or more pulses continuous at intervals of W or less.

  Therefore, when the port of the microcomputer 5 is fixed to the active level (here, high level) due to failure or erroneous output (period X in FIG. 2), the charging / discharging capacitor C52 is charged at the first rising edge. However, since there is no next next pulse input, it is discharged unilaterally and does not reach the on-voltage. The same applies to a case where a single pulse that does not reach the specified number N is input during the specified period (W × N).

  On the other hand, when the pulse signals P1 and P2 are supplied from the microcomputer 5 (period Y in FIG. 2), the charging / discharging capacitor C52 is recharged one after another by successive pulses, so that a predetermined number N of pulses are input. At this point, the ON voltage is reached, and the transistors Tr1 and Tr3 can be turned on.

  As described above, in the power supply system 1 according to the present embodiment, a predetermined number N or more pulses are not input to the first or second trigger signal generation circuits 11 and 13 within a specified period (W × N). The hold trigger signal T1 and the cancel trigger signal T2 that change the supply state of the drive current Id are not generated.

  Therefore, according to the power supply system 1 of the present embodiment, when the output port of the microcomputer 5 is fixed at any level due to a failure or the like, it is a single occurrence (specified within a specified period) due to noise or the like. Even when pulses that do not reach the number are input, the state held by the state holding device 7 (here, the supply state of the drive current Id) does not change.

  That is, the state held by the state holding device 7 is switched only when the user operates the push button switch 3, and it is not switched unintentionally by the user due to other factors. The reliability and safety of the device whose power supply state is controlled by the system 1 can be ensured.

In this embodiment,
[Second Embodiment]
Next, a second embodiment will be described.

The power supply system 1a of the present embodiment is different from the power supply system 1 of the first embodiment only in a part of the configuration of the state holding device.
As shown in FIG. 3, in the power supply system 1 a of this embodiment, the state holding device 7 a includes a drive current supply circuit 15 configured similarly to that of the first embodiment, and a hold pulse signal output from the microcomputer 5. The number of pulses of P1 is counted, and when the count value reaches a preset specified value, the first counter 21 that outputs the hold trigger signal T1 and the number of pulses of the cancel pulse signal P2 that is output from the microcomputer 5 are counted. When the count value reaches a preset specified value, the second counter 23 that outputs a cancel trigger signal T2 and the system clock CLK are operated. A free-run counter 25 for generating a reset signal RST for resetting the count value, and a hold trigger signal When 1 is input, an active level at which the transistor Tr1 is turned on, and when a cancel trigger signal T2 is input, a drive signal at an inactive level at which the transistor Tr2 is turned off is supplied to the transistor Tr1 of the drive current supply circuit 15. RS flip-flop circuit 27.

  In the present embodiment, the drive current supply circuit 15 and the RS flip-flop circuit 27 correspond to the hold circuit in the present invention, and the counters 21 and 23 and the free-run timer 25 correspond to the trigger signal generation circuit in the present invention.

  That is, in the state holding device 7a, the supply state of the drive current Id changes according to the signal level of the drive signal output from the RS flip-flop circuit 27, and the trigger signals T1 and T2 whose signal level of the drive signal is changed are It is generated only when a pulse exceeding the specified value is input within the certain period (the reset period of the counters 21 and 23).

The microcomputer 5 is configured to output a hold pulse signal P1 and a cancel pulse signal P2 that satisfy the generation conditions of the trigger signals T1 and T2.
According to the power supply system 1a of the present embodiment configured as described above, not only the operation and effect similar to those of the power supply system 1 of the first embodiment are obtained, but also the drive current supply circuit 15 of the state holding device 7a is excluded. Since all the parts are composed of logic circuits, the logic circuit parts can be realized by a semiconductor integrated circuit, and the system can be miniaturized.

  In the present embodiment, the counters 21 and 23 are directly connected to the ports of the microcomputer 5, but may be configured to be connected via a filter circuit or a gate circuit for removing noise.

  The filter circuits (C11, C21, C31), the protection circuits (D21, D22), and the resistors (R11, R31) for stabilizing the gate potential may be omitted because they are used as necessary.

It is a block diagram of the power supply system of 1st Embodiment. It is a timing diagram for explaining the operation of the trigger signal generation circuit. It is a block diagram of the power supply system of 2nd Embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1,1a ... Power supply system, 3 ... Push button switch, 5 ... Microcomputer (microcomputer), 7, 7a ... State holding device, 11, 13 ... Trigger signal generation circuit, 15 ... Drive current supply circuit, 17 ... Holding current supply Circuit, 19 ... Cancel circuit, 21, 23 ... Counter, 25 ... Free-run counter, 27 ... RS flip-flop circuit, C51 ... AC coupling capacitor, C52 ... Charge / discharge capacitor, L ... Feed line, Ld ... Current supply Line, RLY ... relay, Tr1-Tr3 ... transistor.

Claims (7)

A hold circuit in which the signal level to be held is switched by the input of a trigger signal; and
A trigger signal generation circuit for generating the trigger signal when a predetermined number of pulse signals or more set in advance within a predetermined period set in advance;
A state holding device comprising: The hold circuit includes a plurality of input terminals, and the signal level held when the trigger signal is input is different for each input terminal,
The state holding device according to claim 1, wherein the trigger signal generation circuit is provided for each of the input terminals. The trigger signal generation circuit includes:
A frequency / voltage conversion circuit that generates an output signal having a signal level corresponding to the pulse interval of the pulse signal;
3. The state holding device according to claim 1, wherein an output signal of the frequency / voltage conversion circuit is used as the trigger signal. The frequency / voltage conversion circuit includes:
A capacitor charged by the pulse signal;
A discharge circuit for discharging the capacitor at a constant rate;
The state holding device according to claim 3, further comprising: an output signal having a signal level corresponding to a charging voltage of the capacitor. The trigger signal generation circuit includes:
A counter that counts the input pulse signal and generates the trigger signal when the count value reaches a preset threshold;
A free-run timer that generates a signal for resetting the counter for each preset period;
The state holding device according to claim 1 or 2, further comprising:   The state holding device according to claim 1, wherein the state holding device is incorporated in an in-vehicle device. The state holding device according to claim 6, wherein the output of the hold circuit is used as a control signal for controlling an energization state of a power supply line provided in the vehicle.

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