JP2005062382A - Display driving circuit and display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display driving circuit and a display device that effectively reduce luminance unevenness of a display panel due to a voltage drop caused by wiring resistance of a data line without lowering the total luminance of the display panel. <P>SOLUTION: Provided is the display driving circuit which drives with currents a plurality of light emitting elements connected to respective intersections of data lines and scan lines arranged in matrix, and performs control so that the product of the pulse width and current peak value of a current pulse driving each light emitting element becomes constant and a current application time allocated to each scan line in one frame period is sequentially varied while related to the wiring resistance of the data line. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a display driving circuit and a display device using a light emitting element such as an organic EL (electro-luminescence) element.

  A configuration of a conventional passive matrix display device is shown in FIG.

  The display device of FIG. 1 includes a data drive circuit 2, a scan circuit 4, and a passive matrix organic EL display 6. In the display 6, a plurality of organic EL elements are arranged in a matrix as light emitting elements, and each light emitting element (pixel) is at each intersection of a data line from the data drive circuit 2 and a scan line from the scan circuit 4. It is connected. At each intersection, the light emitting layer of the organic EL element is sandwiched between the data line (anode) and the scan line (cathode).

  FIG. 2 is a waveform diagram for explaining a conventional passive matrix driving method applied to the display device of FIG.

  As shown in FIG. 2, in the conventional passive matrix driving method, one frame period is time-divided at equal intervals by the number of scan lines to drive the display elements. Here, a transparent electrode such as ITO (indium tin oxide) is used for the data line (anode) connected to the data driving circuit. An aluminum electrode or the like is used for a scan line (cathode) connected to the scan circuit.

  The light emission luminance of the organic EL element is proportional to the current, and its temperature dependency is low, so that control with the current is easy. For this reason, in general, current pulse driving is often used in an organic EL display.

  To achieve the same brightness when changing the number of scan lines with the same element configuration and the same aperture ratio, the brightness is the area of the current pulse, that is, (current peak value) x (application time (pulse width)). Therefore, for example, when the number of scan lines is doubled (duty ratio is ½), the application time may be halved. In this case, if one frame period is constant (for example, 60 Hz), the number of scan lines in the period and the duty ratio of the pulse are inversely proportional.

  FIG. 3 is a diagram for explaining the dependence of the voltage / current characteristics of the organic EL element on the current pulse / duty ratio.

  As shown in FIG. 3, the inter-terminal voltage V of the organic EL element greatly depends on the current pulse / duty ratio, and the inter-terminal voltage V tends to increase as the current pulse / duty ratio decreases.

  From the above, in the passive matrix driving method, the required current peak value and driving voltage of the organic EL element vary greatly depending on the number of scanning lines, and the increase in the number of scanning lines causes an increase in current peak value and driving voltage. However, the withstand voltage of the drive circuit is limited, and no voltage can be applied beyond this value.

  On the other hand, high definition and large size of the display panel increase the wiring resistance of transparent electrodes such as ITO. FIG. 4 is a diagram for explaining a voltage drop caused by the wiring resistance of a transparent electrode such as ITO on the data line connected to the data driving circuit 2.

  As shown in FIG. 4, the voltage drop at the anode (data line) increases as the light emitting element (organic EL element) arranged farther from the output terminal of the data driving circuit 2. The voltage drop at the farthest end is the maximum, that is, the voltage between the terminals that can be applied to the light emitting element disposed at the farthest position is the minimum. In the display device described above, since the power supply voltage of the data driving circuit has an upper limit, the current peak value that can be passed is also minimum in the light-emitting element at the farthest end.

  FIG. 5 is a diagram for explaining voltage / current characteristics of the organic EL element and current limitation due to a voltage drop in the data line.

As shown in FIG. 5, when the voltage of the data driving circuit is set to V _H , the terminal voltage V ₀ of the data driving circuit is 0 to several hundred mV lower than V _H (indicated by a broken line in FIG. 5). . When the voltage-current (V-I) characteristic curve of the light-emitting elements such as organic EL devices are shown in curve upward-sloping 5, resistors R ₀ to R _N is small voltage drop of the transparent electrode such as ITO is negligible In this case, a current designated by the data driving circuit (current source) can be passed. On the other hand, if the resistance R ₀ to R _N is large voltage drop can not be ignored, the load curve of downward-sloping through (V _{0, 0)} in FIG. 5 current is limited, the current I flowing through the light emitting element thereof The inter-terminal voltage V is determined as the intersection of the load curve and the voltage / current characteristic curve.

  FIG. 17 shows the configuration of a conventional passive matrix display device. The display device of FIG. 17 includes a data drive circuit 2, a scan circuit 4, a passive matrix type organic EL display 6, a data side shift register 7, a scan side shift register 8, and a modulation circuit 9. As in the configuration of FIG. 1, a transparent electrode such as ITO is used for the data line connected to the data driving circuit 2, and an aluminum electrode or the like is used for the scan line connected to the scan circuit 4.

  In the passive matrix driving method of FIG. 17, as in the waveform diagram of FIG. 2, one frame period is time-divided by the number N of scan lines (scan lines), and the scan lines (scans) to be displayed for each N-divided period. The voltage between the terminals of the light emitting elements is selected so that the light emitting elements on the other (N-1) non-selected scanning lines do not emit light at the same time. A bias voltage as follows is given. Each light emitting element is driven by applying a current pulse to the data line in synchronization with the selection operation of the scanning line.

  FIG. 18 shows voltage / current density characteristics of the organic EL element. As shown in FIG. 18, the voltage between terminals of the organic EL element greatly depends on the pulse duty ratio. When driving an organic EL element with the same current pulse peak value, the voltage between terminals of the organic EL element increases as the pulse duty ratio decreases. In a light emitting device having a general device configuration (hole transport layer: α-NPD, electron transport layer: Alq3), when the duty ratio is 1/120 (= 0.83%), it is at the time of DC (direct current) driving. In comparison, it is known that the voltage between the terminals of the light emitting element is increased by about 5V.

As a prior art of the present invention, Japanese Patent Laid-Open No. 2001-013923 discloses a display driving method for stably driving an organic EL element using constant voltage driving without using constant current driving. Yes.
JP 2001-013923 A

  When the current value set in the conventional display driving method is a predetermined value, the current that can flow through the light emitting element farther from the data driving circuit output terminal becomes smaller, so the light emitting element that is farther from the data driving circuit output terminal It gets lower. There is a problem that such luminance unevenness causes a decrease in image quality.

  In the conventional display driving method, this uneven brightness can be suppressed by aligning the set current value at this time with the lowest current value. However, this method has a problem of sacrificing the overall luminance of the display panel.

  In the passive matrix driving method, the required current peak value and driving voltage of the organic EL element vary greatly depending on the number of scan lines. In particular, the increase in the number of scan lines associated with the higher definition of the display panel leads to an increase in the current pulse peak value and the driving voltage. Therefore, when trying to achieve the same brightness as the low definition panel, the energy conversion efficiency (luminous efficiency) ) Was a problem.

  Further, the damage of the light emitting element due to the application of the current pulse to the organic EL element is larger when the current pulse peak value is high under the condition that the product of the current pulse peak value and the application time, that is, the luminance is constant. This is because a high-density current is instantaneously applied to the light-emitting element. As the duty ratio decreases as the number of scan lines increases, the damage to the light-emitting elements increases and the progress of dark spot expansion and current / brightness characteristics deterioration is promoted. The display panel has a problem that its life is shortened.

  The present invention has been made in view of the above-described problems, and effectively reduces display panel luminance unevenness caused by a voltage drop due to wiring resistance of data lines without reducing the overall display panel brightness. An object is to provide a display driving circuit and a display device.

  The present invention provides a display driving circuit and a display device that reduce the power consumption of a passive matrix display to increase energy conversion efficiency (light emission efficiency) and are effective in extending the life of a high-definition display panel. For other purposes.

  In order to solve the above problems, a display driving circuit according to the present invention is a display driving circuit that current-drives a plurality of light emitting elements connected to intersections of data lines and scan lines arranged in a matrix, and each light emitting element. The product of the pulse width and current peak value of the current pulse that drives the current is constant, and the current application time assigned to each scan line within one frame period is controlled so as to sequentially change in association with the wiring resistance of the data line The data drive circuit is provided.

  In order to solve the above problems, the display device of the present invention includes a display having a plurality of light emitting elements connected to intersections of data lines and scan lines arranged in a matrix, the number of scan lines, and the number of scan lines. A ROM for storing a table of duty ratio and maximum current peak value, and a scan circuit connected to each scan line, and referring to the table of the ROM, from the scan line number information and the duty ratio information of each scan line, A scan circuit for controlling a pulse width and generation timing generated when a scan line is selected, and a data driving circuit connected to each data line, wherein the duty ratio information of each scan line is referred to the ROM table. Therefore, the clock frequency and generation timing of the pulse width modulation clock generated when each scan line is selected, A data drive circuit for controlling the output timing of the data, wherein the data drive circuit has a constant product of the pulse width of the current pulse for driving each light emitting element and the current peak value, and each scan line within one frame period. The current application time allotted to is controlled so as to change sequentially in association with the wiring resistance of the data line.

  In order to solve the above problems, a display driving circuit according to the present invention is a display driving circuit that current-drives a plurality of light-emitting elements connected to intersections of data lines and scan lines arranged in a matrix. A data drive circuit connected to the data line; a scan circuit connected to each scan line to simultaneously select a plurality of adjacent scan lines; and when the plurality of scan lines are selected, the data drive circuit selects the scan line Line averaging for controlling a plurality of data to be displayed on a plurality of light emitting elements located at the intersections of the data lines and outputting them to the data driving circuit and simultaneously driving the plurality of light emitting elements A processing circuit is provided. The drive current pulse peak value applied to each light-emitting element is reduced to a selected number, thereby reducing the current density of the light-emitting element.

  Furthermore, in order to solve the above problems, a display device of the present invention includes a display having a plurality of light emitting elements connected to intersections of data lines and scan lines arranged in a matrix, and data driving connected to each data line. The circuit, the scan circuit connected to each scan line, and (M-1) lines of RGB data signals are stored in memory, and the Nth to (N + M-1) th total M scan lines and data lines are crossed. A line averaging processing circuit for adding and averaging data to be displayed on each of M light emitting elements, a data side shift register for inputting the averaged data, a data shift clock and a data latch signal, and the shift A data modulation circuit that inputs a signal latched from a register and modulates it into a current pulse signal, and a scan that inputs a scan pulse and a scan clock And a shift register, the scan circuit and the data driving circuit is characterized in that it simultaneously selectively driving the M light emitting elements of the scan line adjacent the M.

  According to the display driving circuit and the display device of the present invention, it is possible to reduce the luminance unevenness caused by the voltage drop caused by the wiring resistance of the data line of the display panel at a low cost without reducing the overall luminance of the display panel. Is possible. In addition, according to the display driving circuit and the display device of the present invention, it is possible to suppress an increase in power consumption and a decrease in light emission efficiency due to high definition of a passive matrix display, and a long life of a high definition display panel. It is effective for conversion. Therefore, it greatly contributes to equipment equipped with a passive matrix display device.

  FIG. 6 shows a display device including a display driving circuit according to an embodiment of the present invention.

  6 includes a passive matrix organic EL display 16, a data driving circuit 12 connected to a plurality of data lines from the display 16, a scan circuit 14 connected to a plurality of scan lines from the display 16, and a scan. A ROM (read-only memory) 13 that stores a table of the number of lines, the duty ratio (pulse width) of each scan line, and the maximum current peak value.

  The scan circuit 14 refers to the table stored in the ROM 13, and based on the scan line number information and the pulse width information of each scan line, the pulse width (current application time) generated when each scan line is selected. And the generation timing is controlled. The data driving circuit 12 refers to the table stored in the ROM 13, and based on the pulse width information of each scan line, the clock frequency and generation timing of the pulse width modulation clock generated when each scan line is selected, Control data output timing.

  The maximum current peak value stored in the ROM 13 and passed through each scan line is determined as follows. In other words, the voltage / current (VI) characteristics of the organic EL element tend to increase as the duty ratio decreases, but when the duty ratio decreases to some extent as shown in FIG. I know it will converge.

  For example, when the number of scan lines is 120 in a passive matrix display, the duty ratio is 1/120 (= 0.83%) if the scan time is uniform. In a region where the duty ratio is as small as this, the voltage / current characteristics are hardly dependent on the duty ratio, and may be considered constant.

  On the other hand, since the luminance of each light emitting element of the display depends on the area of (current peak value) × (pulse width (current application time)), as shown in FIG. It can be considered that it is proportional to.

Here, since the voltage / current characteristics of the organic EL element can be calculated by performing a high-order polynomial or exponential approximation, as shown in FIG. 5, the intersection with the load curve on the data line side (straight-downward straight line). Can be calculated for each scan line. From the coordinates of these intersections, the maximum current peak value I _i (i = 1 to N) of each scan line can be determined. Therefore, in order to obtain the duty ratio D _i of the i-th scan line, it may be calculated as follows.

図５に示した有機ＥＬ素子の電圧・電流特性曲線と１２０本分のスキャン線に対する負荷曲線との交点を求めると、その間隔がほぼ一定になるように近似できるので、簡略化のため次のように計算することができる。

When the intersection between the voltage / current characteristic curve of the organic EL element shown in FIG. 5 and the load curve for 120 scan lines is obtained, the interval can be approximated to be substantially constant. Can be calculated as follows.

  First, the maximum currents in the first scan line with the smallest voltage drop and the Nth scan line with the largest voltage drop are respectively obtained, and the ratio thereof is calculated. Next, the maximum current of each of the 2nd to (N−1) th scan lines can be approximately calculated by equally dividing the difference between the first and Nth maximum currents obtained above.

The number of scan lines is N, the ratio (Imax / Imin) of the current value Imax at the scan line with the maximum drive current to the current value Imin at the scan line with the minimum drive current is M, and the Nth scan line Is set to I _N , the current peak value I ₁ in the _first scan line is expressed by the following equation.

ｉ番目のスキャン線での電流波高値Ｉ_ｉは、次式で表される。

The current peak value I _i in the i-th scan line is expressed by the following equation.

ここで、Ｉ_ｉの総和は、次式のようになる。

Here, the total sum of I _i is expressed by the following equation.

図８は、本実施例で用いられる、１番目〜Ｎ番目の各スキャン線に割当てられる電流波高値の配分を説明するための図である。

FIG. 8 is a diagram for explaining the distribution of current peak values assigned to the first to Nth scan lines used in this embodiment.

The duty ratio of the i-th scan line in one frame period is set in inverse proportion to the current peak value in each scan line, but the current peak value I _i in each scan line is smaller than the number N of scan lines. Therefore, it can be considered that the duty ratio D _i of each scan line is proportional to the number of scan lines (N−i + 1). Therefore, the duty ratio D _i of the i-th scan line is expressed by the following equation.

上式にしたがい、例えば、Ｍ＝２、Ｎ＝１２０のとき、１番目のスキャン線のデューティ比は１／１８０、１２０番目のスキャン線のデューティ比は１／９０と計算できる。Ｍ＝３、Ｎ＝１２０のとき、１番目のスキャン線のデューティ比は１／２４０、１２０番目のスキャン線のデューティ比は１／８０と計算できる。

According to the above formula, for example, when M = 2 and N = 120, the duty ratio of the first scan line can be calculated as 1/180, and the duty ratio of the 120th scan line can be calculated as 1/90. When M = 3 and N = 120, the duty ratio of the first scan line can be calculated as 1/240, and the duty ratio of the 120th scan line can be calculated as 1/80.

  In the passive matrix driving method using the display driving circuit of this embodiment, scanning is performed according to the duty ratio thus obtained, and driving is performed so that the product of the duty ratio and the current peak value is constant. FIG. 9 shows drive waveforms used in the display drive circuit of this embodiment.

  FIG. 12 shows an example of a scan circuit according to the display drive circuit of the present invention. FIG. 11 is a diagram for explaining a table held in the ROM according to the scan circuit of FIG. FIG. 13 is a waveform diagram for explaining the operation of the scan circuit of FIG.

  The scan circuit 140 in FIG. 12 includes a ROM 141, a counter 142, and a scan line driving unit. The ROM 141 may be the same memory as the ROM 13 in the configuration of FIG. 6 and can be provided inside the scan circuit 140 or outside the scan circuit 140.

As shown in FIG. 11, the table held in the ROM 141 includes the duty ratio (pulse width) of each scan line, the maximum current peak value, and the corresponding duty ratio calculated as described above. The count start value and end value calculated accordingly are included. The count start value and end value of the first scan line are 1 and C ₁ , and the count start value and end value of the _nth scan line farthest from the output terminal of the data driving circuit 12 are C _n−1 and C _n. It is.

  12 includes a plurality of pairs of comparators 143-1S, 143-1E,..., 143-nS, 143-nE, and NAND circuits 144-1 connected to each pair of comparators. , 144-n and voltage drivers 145-1,..., 145-n connected to the outputs of the NAND circuits. A power supply voltage is supplied to each voltage driver, and the potential of each scan line connected to the display 16 is set to the power supply voltage (non-selected) or the ground voltage (selected) according to the output of the corresponding NAND circuit. To do.

  In the scan circuit 140 of FIG. 12, a clock signal and a frame signal defining the start and end of one frame period are supplied to the input of the counter 142. In synchronization with the falling edge of the frame signal, the counter 142 starts a count operation and outputs a count signal (Q) indicating the result of counting the clock signal. The count signal (Q) from the counter 142 is output to one input terminal (a) of each comparator 143. The counter 142 is reset in synchronization with the next falling edge of the frame signal, and ends the counting operation.

  In the scan circuit 140 of FIG. 12, the count start value and the end value from the ROM 141 are output to the other input terminal (b) of the comparator pair of the corresponding scan line. For example, the count start value from the ROM 141 is supplied to the input terminal (b) of the comparator 143-1S, and the count end value from the ROM 141 is supplied to the input terminal (b) of the comparator 143-1E. The output of the comparator 143-1S transits to a HIGH level only when the signal at the input terminal is a ≧ b, and otherwise maintains the LOW level. On the other hand, the output of the comparator 143-1E transitions to the HIGH level only when the signal at the input terminal is a ≦ b, and otherwise maintains the LOW level.

  Therefore, as shown in FIG. 13, the scan circuit 140 of FIG. 12 changes the output of each comparator 143 in accordance with the count signal (Q), so that the potential of each scan line is changed within one frame period. The ground voltage (selection) is sequentially set for the current application time assigned to the scan line.

  FIG. 15 shows an example of a data driving circuit according to the display driving circuit of the present invention. FIG. 14 is a diagram for explaining a table held in the ROM according to the data driving circuit of FIG. FIG. 16 is a waveform diagram for explaining the driving operation of the data driving circuit of FIG.

  The data driving circuit 120 in FIG. 15 includes a ROM 121, a counter 122, and a data line driving unit. The ROM 121 may be the same memory as the ROM 13 in the configuration of FIG. 6, and can be provided inside the data driving circuit 120 or outside the data driving circuit 120.

As shown in FIG. 14, in the table held in the ROM 121, the duty ratio (pulse width) of each scan line, the maximum current peak value, and the corresponding duty ratio calculated as described above are shown. The count start value and end value calculated in response to this, and the DA value calculated in accordance with the corresponding maximum current peak value are included. The count start value and end value of the first scan line are 1 and C ₁ , and the count start value and end value of the _nth scan line farthest from the output terminal of the data driving circuit 12 are C _n−1 and C _n. It is. The DA value of the _first scan line is DA ₁ and the DA value of the farthest nth scan line is DA _n .

  15 includes a plurality of pairs of comparators 123-1S, 123-1E,..., 123-nS, 123-nE, and a NAND circuit 124-1 connected to each comparator pair. ,..., 124-n, DA converters (DACs) 125-1,..., 125-n connected to the outputs of the NAND circuits, and current drivers 126-1 connected to the outputs of the DA converters,. 126-n.

  The DA value for each scan line from the ROM 121 is output to the input of each DA converter 125, and the signal after the DA conversion of the light emitting element driving current is sent to each current driver 126 according to the output of the corresponding NAND circuit. Output. Each current driver 126 amplifies the output signal of the DA converter according to the output of the corresponding NAND circuit, and sets the drive current pulse of each data line connected to the display 16.

  In the data driving circuit 120 of FIG. 15, a clock signal and a frame signal that defines the start and end of one frame period are supplied to the input of the counter 122. In synchronization with the falling edge of the frame signal, the counter 122 starts a count operation and outputs a count signal (Q) indicating the result of counting the clock signal. The count signal (Q) from the counter 122 is output to one input terminal (a) of each comparator 123. The counter 122 is reset in synchronization with the next falling edge of the frame signal, and ends the counting operation.

  In the data drive circuit 120 of FIG. 15, the count start value and end value from the ROM 121 are output to the other input terminal (b) of the comparator pair of the corresponding scan line. For example, the count start value from the ROM 121 is supplied to the input terminal (b) of the comparator 123-1S, and the count end value from the ROM 121 is supplied to the input terminal (b) of the comparator 123-1E. The output of the comparator 123-1S transitions to the HIGH level (H) only when the signal at the input terminal is a ≧ b, and otherwise maintains the LOW level (L). On the other hand, the output of the comparator 123-1E transitions to the HIGH level (H) only when the signal at the input terminal is a ≦ b, and otherwise maintains the LOW level (L).

  Therefore, as shown in FIG. 16, the data driving circuit 120 of FIG. 15 changes the output of each comparator 123 according to the count signal (Q), so that the pulse width and current of the driving current pulse of each data line are changed. The product of the crest values is constant, and the current application time assigned to each scan line within one frame period is controlled so as to sequentially change in association with the wiring resistance of the data line.

  FIG. 10 shows a display device including a display driving circuit according to another embodiment of the present invention.

  10 includes a passive matrix organic EL display 16, a data driving circuit 12 connected to a plurality of data lines from the display 16, a scan circuit 14 connected to a plurality of scan lines from the display 16, and a scan. A table of the number of lines, duty ratio (pulse width) and maximum current peak value of each scan line is stored, and a table having an optimum duty ratio (pulse width) and maximum current peak value for each power supply voltage of the data drive circuit 12 is stored. A plurality of ROMs 13 (ROM # 1, ROM # 2,..., ROM #n) and a power supply voltage monitor circuit 15 are included.

  The scan circuit 14 refers to a table stored in the ROM 13 of the power supply voltage closest to the output value of the power supply voltage monitor circuit 15 and selects each scan line based on the number of scan lines information and the pulse width information of each scan line. Controls the pulse width (current application time) and generation timing generated when the pulse is generated.

  Similarly, the data drive circuit 12 refers to the table stored in the ROM 13 of the power supply voltage closest to the output value of the power supply voltage monitor circuit 15 and selects each scan line based on the pulse width information of each scan line. The clock frequency, generation timing, and data output timing of the pulse width modulation clock generated at the time are controlled.

  According to the display drive circuit of the embodiment of FIG. 10, even when the power supply voltage of the data drive circuit 12 changes, the ROM 13 storing the table having the optimum duty ratio (pulse width) and the maximum current peak value is selected. As a result, the luminance unevenness of the display 16 can be effectively reduced.

  FIG. 19 shows a display device including a display driving circuit according to another embodiment of the present invention.

  The embodiment of FIG. 19 is a display driving circuit for current-driving a plurality of light emitting elements connected to the intersections of data lines and scan lines arranged in a matrix, and the data driving circuit connected to each data line; A scan circuit connected to each scan line and selecting a plurality of adjacent scan lines at the same time, and a plurality of data driving circuits located at the intersections of the scan lines and data lines when the plurality of scan lines are selected A plurality of data to be displayed on each light emitting element is averaged and output to the data driving circuit, and a line averaging processing circuit for controlling to drive the plurality of light emitting elements at the same time is provided. When a plurality of scan lines are selected by the line averaging processing circuit, the data driving circuit simultaneously drives the plurality of light emitting elements, and the current peak value of the driving current pulse applied to each light emitting element is reduced to the selected number. Thus, the current density of the light emitting element is reduced.

  The display device shown in FIG. 19 includes a passive matrix light emitting element display 16A, a data driving circuit 12 connected to a data line, a scan circuit 14 connected to a scan line, and RGB data signals for (M-1) lines. A line averaging process that holds and adds the data to be displayed on each of the M light emitting elements at the intersections of the Nth to (N + M-1) th total M scan lines and data lines, and performs an averaging process. A circuit 20, a data-side shift register 17 for inputting the averaged data, a data shift clock, and a data latch signal, a data modulation circuit 19 for inputting a signal latched from the shift register and modulating the signal into a current pulse signal, And a scan side shift register 18 for inputting a scan pulse and a scan clock.

  The line averaging processing circuit 20 of this embodiment includes line memories 21-1,..., 21- (M−1) for holding RGB data signals for (M−1) lines, and Nth (N + M−). 1) An averaging processing unit 22 that performs an averaging process by adding data to be displayed on M light emitting elements at the intersections of the first M total scan lines and data lines.

  The display device of FIG. 19 is characterized in that M adjacent scan lines are simultaneously selected and driven. According to this embodiment, it is possible to suppress an increase in power consumption and a decrease in light emission efficiency due to high definition of a passive matrix display, which is effective for extending the life of a high definition display panel.

  FIG. 20 shows a display device including a display driving circuit according to still another embodiment of the present invention.

  The display device of FIG. 20 holds a passive matrix type organic EL display 16, a data drive circuit 12 connected to the data lines, a scan circuit 14 connected to the scan lines, and RGB data signals for (M-1) lines. A line averaging processing circuit for adding and averaging data to be respectively displayed on M organic EL elements at intersections of the Nth to (N + M−1) th M scanning lines and data lines 20, a data-side shift register 17 that receives the averaged data, the data shift clock, and the data latch signal, a data modulation circuit 19 that receives the signal latched from the shift register 17 and modulates it into a current pulse signal, and scanning And a scan side shift register 18 for inputting a pulse and a scan clock.

  The line averaging processing circuit 20 of this embodiment includes line memories 21-1,..., 21- (M−1) for holding RGB data signals for (M−1) lines, and Nth (N + M−). 1) An averaging processing unit 22 that performs an averaging process by adding data to be displayed on M light emitting elements at the intersections of the first M total scan lines and data lines.

  The display device of FIG. 20 is characterized in that M adjacent scan lines are simultaneously selected and driven. According to this embodiment, it is possible to suppress an increase in power consumption and a decrease in light emission efficiency due to high definition of a passive matrix organic EL display, which is effective for extending the life of a high definition display panel.

  FIG. 21 shows a display device including a display driving circuit according to still another embodiment of the present invention.

  The display device shown in FIG. 21 holds a passive matrix organic EL display 16, a data drive circuit 12 connected to a data line, a scan circuit 14 connected to a scan line, and one RGB data signal for two adjacent lines. A line averaging processing circuit 20A for adding and averaging data to be displayed on the two organic EL elements at the intersections of the scan lines and the data lines, the averaged data, the data shift clock, and the data latch A data side shift register 17 for inputting a signal, a data modulation circuit 19 for inputting a signal latched from the shift register 17 and modulating it to a current pulse signal, and a scan side shift register 18 for inputting a scan pulse and a scan clock. Including.

  The line averaging processing circuit 20A of the present embodiment adds a line memory 23 (such as a RAM) that holds RGB data signals for one line, and adds N-th and (N + 1) -th two points of data on the same column. And a half-value processing unit 25 for averaging the output values of the adder 24.

  The display device of FIG. 21 is characterized in that two adjacent scan lines are selected and driven simultaneously. According to this embodiment, it is possible to suppress an increase in power consumption and a decrease in light emission efficiency due to high definition of a passive matrix organic EL display, which is effective for extending the life of a high definition display panel.

  FIG. 22 is a waveform diagram for explaining the operation of the display drive circuit of FIG.

  FIG. 22 schematically shows drive waveforms when the number of scanning lines (number of scanning lines) is N. The scanning pulse to be input is a pulse that becomes LOW only for a period of two lines, and the scanning clock is a clock having a period of one line period. With these signals, the shift register output has a waveform similar to the scan circuit output of FIG. As a result, two adjacent scanning lines are always selected (that is, become LOW level).

  For example, when the scanning line # 1 and the scanning line # 2 are simultaneously selected, the data driving circuit 12 averages the data displayed on the scanning line # 1 and the data displayed on the scanning line # 2. This data is output, and this data is simultaneously displayed on the pixels of the scanning line # 1 and the scanning line # 2.

  Next, when scanning line # 2 and scanning line # 3 are selected simultaneously, the data driving circuit averages the data displayed on scanning line # 2 and the data displayed on scanning line # 3. This data is output, and this data is simultaneously displayed on the pixels of the scanning line # 2 and the scanning line # 3.

  On the other hand, the data displayed on the scanning line # 1 and the last scanning line #N are output without being subjected to the averaging process.

  In the passive matrix organic EL display 16, when the number of scanning lines N is 240, the duty ratio is 1/240 (= 0.41%).

  The luminance of each light emitting element of the display 16 depends on the area of (current peak value) × (pulse width (current application time)). When two scanning lines are simultaneously selected as in this embodiment, the drive current pulse is equally divided into the two selected pixels, so that the current density applied to the light emitting element is effectively halved and the terminal of the light emitting element The voltage between them will decrease. Therefore, power consumption is reduced and energy conversion efficiency (light emission efficiency) is improved. Furthermore, the deterioration rate of the current / luminance characteristics of the light emitting element is weakened, and a longer life can be expected compared to the conventional one.

  FIG. 23 shows a display device including a display driving circuit according to still another embodiment of the present invention.

  The display device in FIG. 23 holds a passive matrix organic EL display 16, a data drive circuit 12 connected to the data lines, a scan circuit 14 connected to the scan lines, and RGB data signals for two lines. , The (N + 1) th and (N + 2) th data on the same column are added together to perform the averaging process, the line averaging processing circuit 20B, and the shift for inputting the averaged data, the data shift clock and the data latch signal. The register 17 includes a data modulation circuit 19 that inputs a signal latched from the shift register 17 and modulates the signal into an analog signal, and a shift register 18 that receives a scan pulse and a scan clock.

  The line averaging processing circuit 20B of this embodiment is the same as the Nth, (N + 1) th, and (N + 2) th line memories 26-1 and 26-2 (such as RAM) that hold RGB data signals for two lines. And an averaging processing unit 27 that performs an averaging process by adding the data on the columns.

  The display device of FIG. 23 is characterized in that three adjacent scan lines are selected and driven simultaneously. According to this embodiment, it is possible to suppress an increase in power consumption and a decrease in light emission efficiency due to high definition of a passive matrix organic EL display, which is effective for extending the life of a high definition display panel.

  FIG. 24 is a waveform diagram for explaining the operation of the display drive circuit of FIG.

  FIG. 24 schematically shows drive waveforms when the number of scanning lines is N. The scanning pulse to be input is a pulse that is LOW only for a period of three lines, and the scanning clock is a clock having a period of one line period. With these signals, the shift register output has a waveform similar to the scan circuit output of FIG. As a result, three adjacent scanning lines are always selected (that is, become LOW level).

  For example, when the scanning line # 1, the scanning line # 2, and the scanning line # 3 are selected at the same time, the data displayed on the scanning line # 1 and the data displayed on the scanning line # 2 from the data driving circuit. Then, data obtained by averaging the data displayed on the scanning line # 3 is output, and this data is simultaneously displayed on the pixels of the scanning line # 1, the scanning line # 2, and the scanning line # 3.

  Next, scanning line # 2, scanning line # 3, and scanning line # 4 are selected at the same time, and similarly, data displayed on scanning line # 2, data displayed on scanning line # 3, and scanning line # The data obtained by averaging the data displayed in 4 is output, and this data is simultaneously displayed on the pixels of the scanning line # 2, the scanning line # 3, and the scanning line # 4.

  In a passive matrix organic EL display, the luminance of each light emitting element of the display depends on the area of (current peak value) × (pulse width (current application time)). When three scanning lines are selected simultaneously as in this embodiment, the drive current pulse is equally divided into the three selected pixels, so that the current density applied to the light emitting element is effectively 1/3, and the light emitting element As a result, the inter-terminal voltage decreases. Therefore, power consumption is reduced and energy conversion efficiency (light emission efficiency) is improved. Furthermore, the deterioration rate of the current / luminance characteristics of the light emitting element is weakened, and a longer life can be expected compared to the conventional one.

  (Supplementary note 1) A display driving circuit for driving a plurality of light emitting elements connected to the intersections of data lines and scan lines arranged in a matrix, the pulse width and current wave of a current pulse driving each light emitting element A high-value product is constant, and a data driving circuit is provided for controlling the current application time allocated to each scan line within one frame period so as to sequentially change in association with the wiring resistance of the data line. Display drive circuit.

  (Supplementary Note 2) The data driving circuit is a product of the wiring resistance of the data line from the output terminal to the light emitting element of each scan line, the power supply voltage, and the maximum current value determined by the voltage / current characteristics of the light emitting element. The display drive circuit according to appendix 1, wherein the current application time of each scan line is set so as to be constant.

  (Supplementary Note 3) Based on the wiring resistance of the data line from the output terminal of the data driving circuit to the light emitting element of each of the first and Nth scan lines, the power supply voltage, and the voltage / current characteristics of the light emitting element, 1 The maximum current values Imax and Imin of the nth and Nth scan lines are calculated, and the maximum current values of the 2nd to (N-1) th scan lines equally divide the difference between the maximum current values Imax and Imin. The display driving circuit according to claim 1, wherein the data driving circuit sets the current application time of each scan line so that the product with the current value is constant.

  (Supplementary Note 4) Based on the wiring resistance of the data line from the output terminal of the data driving circuit to the light emitting element of each of the first and Nth scan lines, the power supply voltage, and the voltage / current characteristics of the light emitting element, 1 The maximum current values Imax and Imin of the nth and Nth scan lines are calculated, and the maximum current values of the 2nd to (N-1) th scan lines equally divide the difference between the maximum current values Imax and Imin. And the data driving circuit sets the current application time allocated to the i-th (i = 1 to N) scan line in proportion to the maximum current value of the (N−i + 1) -th scan line. The display driving circuit according to appendix 1, wherein:

  (Supplementary Note 5) A display having a plurality of light emitting elements connected to intersections of data lines and scan lines arranged in a matrix, and a table of the number of scan lines, the duty ratio of each scan line, and the maximum current peak value are stored. ROM and a scan circuit connected to each scan line, the pulse width generated when each scan line is selected from the scan line number information and the duty ratio information of each scan line by referring to the ROM table And a scan circuit for controlling the generation timing and a data drive circuit connected to each data line, which are generated when each scan line is selected from the duty ratio information of each scan line by referring to the ROM table. Data drive circuit that controls the clock frequency, generation timing, and data output timing of the pulse width modulation clock The data driving circuit has a constant product of a pulse width and a current peak value of a current pulse for driving each light emitting element, and a current application time allocated to each scan line within one frame period A display device that is controlled so as to sequentially change in association with a wiring resistance of a line.

  (Supplementary Note 6) A display having a plurality of light emitting elements connected to each intersection of data lines and scan lines arranged in a matrix, and a table of the number of scan lines, the duty ratio of each scan line, and the maximum current peak value are different power sources A plurality of ROMs for each voltage, a power supply voltage monitor circuit, and a scan circuit connected to each scan line, and scans by referring to the ROM table of the power supply voltage closest to the output value of the power supply voltage monitor circuit A scan circuit for controlling the pulse width and generation timing generated when each scan line is selected from the line number information and the duty ratio information of each scan line, and a data drive circuit connected to each data line, Refer to the ROM table of the power supply voltage closest to the output value of the power supply voltage monitor circuit, and from the duty ratio information of each scan line, And a data drive circuit for controlling the clock frequency and generation timing of the pulse width modulation clock to be generated when the scan line is selected, and the data output timing, and the data drive circuit generates a current pulse for driving each light emitting element. The product of the pulse width and the current peak value is constant, and the current application time assigned to each scan line within one frame period is controlled so as to sequentially change in association with the wiring resistance of the data line. Display device.

  (Supplementary note 7) A display driving circuit for current-driving a plurality of light emitting elements connected to intersections of data lines and scan lines arranged in a matrix, the data driving circuit connected to each data line, and each scan line And a plurality of light emitting elements in which the data driving circuit is located at an intersection of the scan line and the data line when the plurality of scan lines are selected. A display driving circuit comprising: a line averaging processing circuit that controls to average a plurality of data to be displayed and output the data to the data driving circuit and simultaneously drive a plurality of light emitting elements.

(Supplementary note 8) A display having a plurality of light emitting elements connected to intersections of data lines and scan lines arranged in a matrix, a data driving circuit connected to each data line,
A scan circuit connected to each scan line and (M-1) lines of RGB data signals are stored in memory, and M at the intersection of the Nth to (N + M-1) th total M scan lines and data lines. A line averaging processing circuit for adding and averaging data to be displayed on each light emitting element, a data side shift register for inputting the averaged data, a data shift clock and a data latch signal, and latching from the shift register A data modulation circuit that inputs the received signal and modulates it into a current pulse signal, and a scan-side shift register that inputs a scan pulse and a scan clock, and the scan circuit and the data drive circuit are on M adjacent scan lines. A display device characterized in that the M light emitting elements are selectively driven at the same time.

  (Supplementary note 9) The display device according to supplementary note 8, wherein the display is a passive matrix type organic EL display composed of a plurality of organic EL elements.

(Supplementary Note 10) A display having a plurality of light emitting elements connected to intersections of data lines and scan lines arranged in a matrix, a data driving circuit connected to each data line,
A scan circuit connected to each scan line and one line of RGB data signal are stored in memory, and the data to be displayed on the two light emitting elements at the intersection of two adjacent scan lines and the data line are added and averaged. A line averaging processing circuit that performs processing, a data-side shift register that inputs the averaged data, a data shift clock, and a data latch signal, and data that receives a signal latched from the shift register and modulates it into a current pulse signal A modulation circuit;
A display device comprising: a scan-side shift register for inputting a scan pulse and a scan clock, wherein the scan circuit and the data driving circuit simultaneously select and drive a plurality of light emitting elements on two adjacent scan lines.

It is a figure which shows the structure of the conventional passive matrix type display apparatus. It is a wave form diagram for demonstrating the conventional passive matrix drive system. It is a figure for demonstrating the electric current pulse and duty ratio dependence of the voltage and electric current characteristic of an organic EL element. It is a figure for demonstrating the voltage drop in the data line connected to a data drive circuit. It is a figure for demonstrating the current limitation by the voltage and current characteristic of an organic EL element, and the voltage drop in a data line. It is a figure which shows the structure of the display drive circuit in one Example of this invention. It is a figure for demonstrating the electric current pulse-duty ratio dependence of the electric current and luminance characteristic of an organic EL element. It is a figure for demonstrating the current distribution by the display drive circuit of this invention. It is a wave form diagram for demonstrating the passive matrix drive system by the display drive circuit of this invention. It is a figure which shows the structure of the display drive circuit in the other Example of this invention. It is a figure for demonstrating the table hold | maintained in ROM of a scanning circuit. It is a block diagram which shows an example of the scanning circuit which concerns on the display drive circuit of this invention. FIG. 13 is a waveform diagram for explaining the operation of the scan circuit of FIG. 12. It is a figure for demonstrating the table hold | maintained in ROM of a data drive circuit. It is a block diagram which shows an example of the data drive circuit which concerns on the display drive circuit of this invention. FIG. 15 is a waveform diagram for explaining a driving operation of the data driving circuit of FIG. 14. It is a figure which shows the structure of the conventional passive matrix type display apparatus. It is a figure for demonstrating the electric current pulse and duty ratio dependence of the voltage and electric current characteristic of an organic EL element. It is a figure which shows the structure of the display drive circuit in the other Example of this invention. It is a figure which shows the structure of the display drive circuit in the other Example of this invention. It is a figure which shows the structure of the display drive circuit in the other Example of this invention. FIG. 22 is a waveform diagram for explaining the operation of the data drive circuit of FIG. 21. It is a figure which shows the structure of the display drive circuit in the other Example of this invention. FIG. 24 is a waveform diagram for explaining the operation of the data driving circuit of FIG. 23.

Explanation of symbols

2 Data Drive Circuit 4 Scan Circuit 6 Display 7 Data Side Shift Register 8 Scan Side Shift Register 9 Modulation Circuit 12 Data Drive Circuit 13 ROM
14 Scan circuit 15 Power supply voltage monitor circuit 16 Display 17 Data side shift register 18 Scan side shift register 19 Modulation circuit 20 Line averaging processing circuit

Claims (6)

  A display driving circuit for driving a plurality of light emitting elements connected to intersections of data lines and scan lines arranged in a matrix, wherein the product of the pulse width of the current pulse driving each light emitting element and the current peak value is A display driving circuit comprising a data driving circuit that is constant and controls the current application time allocated to each scan line within one frame period so as to sequentially change in association with the wiring resistance of the data line. A display having a plurality of light emitting elements connected to intersections of data lines and scan lines arranged in a matrix;
ROM storing a table of the number of scan lines, the duty ratio of each scan line and the maximum current peak value;
A scan circuit connected to each scan line, referring to the table in the ROM, and a pulse width and generation timing generated when each scan line is selected from the scan line number information and the duty ratio information of each scan line A scanning circuit for controlling
A data driving circuit connected to each data line, wherein the clock frequency of the pulse width modulation clock generated when each scan line is selected from the duty ratio information of each scan line by referring to the table of the ROM, and A data driving circuit for controlling the generation timing and the data output timing, wherein the data driving circuit has a constant product of a pulse width and a current peak value of a current pulse for driving each light emitting element, and within one frame period. A display device characterized by controlling a current application time allocated to each scan line so as to sequentially change in association with a wiring resistance of a data line. A display having a plurality of light emitting elements connected to intersections of data lines and scan lines arranged in a matrix;
A plurality of ROMs storing a table of the number of scan lines, the duty ratio of each scan line and the maximum current peak value for each different power supply voltage;
A power supply voltage monitor circuit;
A scan circuit connected to each scan line, wherein a reference is made to the ROM table of the power supply voltage closest to the output value of the power supply voltage monitor circuit, and each scan line is determined from the scan line number information and the duty ratio information of each scan line. A scan circuit for controlling a pulse width and a generation timing generated when is selected,
A data driving circuit connected to each data line, wherein the scan line is selected from the duty ratio information of each scan line with reference to the ROM table of the power supply voltage closest to the output value of the power supply voltage monitor circuit A data drive circuit that controls the clock frequency and generation timing of the pulse width modulation clock that is sometimes generated, and the data output timing, and the data drive circuit includes a pulse width and a current peak value of a current pulse that drives each light emitting element. And a current application time assigned to each scan line within one frame period is controlled so as to sequentially change in association with the wiring resistance of the data line.   A display driving circuit for current-driving a plurality of light emitting elements connected to intersections of data lines and scan lines arranged in a matrix, the data driving circuit connected to each data line, and each scanning line, A scan circuit that simultaneously selects a plurality of adjacent scan lines, and when the plurality of scan lines are selected, the data driving circuit displays each on a plurality of light emitting elements located at intersections of the scan lines and the data lines. A display driving circuit comprising: a line averaging processing circuit that controls a plurality of data to be averaged and output to the data driving circuit to simultaneously drive a plurality of light emitting elements. A display having a plurality of light emitting elements connected to intersections of data lines and scan lines arranged in a matrix;
A data driving circuit connected to each data line;
A scan circuit connected to each scan line;
The RGB data signals are stored for (M−1) lines, and the data to be displayed on each of the M light emitting elements at the intersections of the Nth to (N + M−1) th total M scan lines and data lines is added. A line averaging processing circuit that performs averaging processing together,
A data side shift register for inputting the averaged data, data shift clock and data latch signal;
A data modulation circuit that receives a latched signal from the shift register and modulates the signal into a current pulse signal;
And a scanning side shift register for inputting a scanning pulse and a scanning clock, wherein the scanning circuit and the data driving circuit simultaneously select and drive M light emitting elements on M adjacent scanning lines. . A display having a plurality of light emitting elements connected to intersections of data lines and scan lines arranged in a matrix;
A data driving circuit connected to each data line;
A scan circuit connected to each scan line;
A line averaging processing circuit for storing RGB data signals for one line and adding the data to be displayed on each of the two light emitting elements at the intersections of two adjacent scan lines and data lines to perform averaging processing;
A data side shift register for inputting the averaged data, data shift clock and data latch signal;
A data modulation circuit that receives a latched signal from the shift register and modulates the signal into a current pulse signal;
A display device comprising: a scan-side shift register for inputting a scan pulse and a scan clock, wherein the scan circuit and the data driving circuit simultaneously select and drive a plurality of light emitting elements on two adjacent scan lines.

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