JP2005057909A - Voltage variation compensator - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a voltage variation compensator for compensating a voltage variation when a system voltage is interrupted instantaneously by outputting the voltage of a capacitor provided for each phase from a voltage compensation circuit for each phase connected in series with each phase of a power system in which voltage compensation is performed efficiently by utilizing the energy of the capacitor for each phase uniformly. <P>SOLUTION: The voltage variation is compensated by outputting the compensation voltage of each phase generated by superposing the same superposition voltage vector on the error voltage of each phase for compensating the system voltage of each phase to obtain a normal voltage from the voltage compensation circuit of each phase. The superposition voltage is operated repeatedly every specified unit time such that deviation in the voltage drop of the capacitor for each phase is eliminated during the periodic time of the system voltage. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a voltage fluctuation compensator that detects and compensates for voltage fluctuation when the voltage of a power system supplied to a load fluctuates instantaneously.

The voltage of the electric power system is instantaneously reduced by lightning, etc., and a precision device such as a factory malfunctions or is temporarily stopped, which may cause a great damage on the production line. In order to prevent such damage, a voltage fluctuation compensator that monitors voltage fluctuations such as an instantaneous voltage drop (hereinafter referred to as a momentary voltage drop) of the power system and compensates for the voltage drop is used.
A conventional voltage fluctuation compensator is configured by a plurality of voltage compensation circuits that are connected in series to a power system and output a compensation voltage with either positive or negative polarity. Each voltage compensation circuit is provided with a full bridge inverter composed of four semiconductor switching elements with diodes connected in antiparallel, and a charging capacitor, which converts the DC voltage of the charging capacitor into AC and outputs it. In addition, a high-speed mechanical steady short-circuit switch is provided in parallel at the output terminal of each voltage compensation circuit. The charging capacitors in each voltage compensation circuit are charged with different voltages by the charging diode and the charging transformer, and the voltage ratio is set to a power ratio of about 2.
Constantly, current flows through a steady short circuit switch. Further, when the power system is instantaneously reduced, a desired combination is selected from a plurality of voltage compensation circuits according to the error voltage, and the voltage drop of the power system is compensated by the sum of the output voltages (see, for example, Patent Document 1).

JP 2002-359929 A (page 1, page 6, page 8, FIG. 1, FIG. 6)

The conventional voltage fluctuation compensator compensates each phase of the system voltage independently. When the system voltage fluctuation is detected, the compensation voltage required for each phase is calculated and can be output for each phase. Since the compensation voltage is output to each phase when the voltage is equal to or lower than the voltage of the capacitor, if there is a phase in which the required compensation voltage exceeds the voltage of the capacitor, compensation for the voltage variation becomes impossible.
In this way, if the compensation voltage that can be output by the voltage fluctuation compensator is less than the required compensation voltage, even if one phase is not compensated, compensation time is determined for the phase with the largest voltage drop of the capacitor. However, there is a problem that the energy of other phases cannot be effectively used and it is easy to fall out of compensation.

  The present invention has been made to solve the above problems, and in a voltage fluctuation compensator that compensates for voltage fluctuations in each phase of the voltage system, the energy of the energy storage means in each phase is totally reduced. As a result, the voltage can be continuously compensated even if there is a phase whose compensation voltage that can be output is less than the required compensation voltage.

  A voltage fluctuation compensator according to the present invention includes a control unit that monitors voltage fluctuation in a power system and performs power feeding control based on the voltage fluctuation, and is connected in series to each phase of the power system, and has a capacitor independently for each phase. In addition, each phase voltage compensation circuit that converts the DC voltage of each phase capacitor into AC and outputs it is used to suppress fluctuations in the voltage supplied to the load. Also, each phase compensation voltage is calculated by superimposing the same output voltage (hereinafter referred to as superimposed voltage) on each phase error voltage to compensate the system voltage of each phase to normal voltage when the voltage of the power system changes. A compensation voltage calculation unit for calculating the superimposed voltage and a superimposed voltage calculation unit for calculating the superimposed voltage. The superposed voltage calculation unit detects the voltage drop state of each phase capacitor every predetermined unit time, and eliminates the deviation between the phases for a predetermined time sufficiently longer than the predetermined unit time. , Repeatedly calculating the superimposed voltage constituted by combining the voltage components of each phase, and outputting each phase compensation voltage calculated by the compensation voltage calculation unit using the superimposed voltage from each phase voltage compensation circuit Thus, the voltage fluctuation of the line voltage in the power system is suppressed.

  The voltage fluctuation compensator according to the present invention superimposes the same output voltage (hereinafter referred to as a superimposed voltage) on each phase error voltage for compensating the system voltage of each phase to a normal voltage when the voltage of the power system fluctuates. A compensation voltage calculation unit that calculates each phase compensation voltage and a superimposed voltage calculation unit that calculates the superimposed voltage in the control unit, and outputs the phase compensation voltage from the phase voltage compensation circuit to output the phase compensation voltage. Suppresses voltage fluctuations in the line voltage in the power system. Then, the superimposed voltage calculation unit outputs the phase compensation voltage from the phase voltage compensation circuit as the phase where cos θ due to the phase angle shift θ between the phase compensation voltage and the phase system current is closer to 1 is obtained. The superimposed voltage is calculated so as to increase the energy.

  In such a voltage fluctuation compensator, it is possible to substantially uniformly reduce the capacitor voltage of each phase while maintaining the reliability of power supply to the load by compensating for the voltage fluctuation of the line voltage. For this reason, the energy of the capacitor of the entire voltage fluctuation compensation device can be effectively used, and as a result, the voltage fluctuation compensation possible time can be extended.

  In addition, in such a voltage fluctuation compensator, when the power factor is small, it is possible to suppress an increase in the compensation voltage of each phase, and it is possible to prevent the compensation voltage from being output even though the capacitor voltage is relatively high. it can. For this reason, the energy of the capacitor of the entire voltage fluctuation compensation device can be effectively used, and as a result, the voltage fluctuation compensation possible time can be extended.

Embodiment 1 FIG.
Embodiment 1 of the present invention will be described below. FIG. 1 is a schematic configuration diagram of a voltage fluctuation compensating apparatus 200 according to Embodiment 1 of the present invention.
As shown to Fig.1 (a), the electric power from the transmission line 1 is stepped down by the transformer 2, is connected to the consumer 3 (load) via the voltage fluctuation compensation apparatus 200, and electric power is supplied. As shown in FIG. 1B, the voltage fluctuation compensator 200 includes a phase voltage compensation circuit 110a including capacitors 10a, 10b, and 10c for each of three phases of alternating current (a phase, b phase, and c phase). , 110b, 110c are connected in series, and a control circuit 30 that is common to all phases is provided as a control unit, and a compensation voltage is supplied from each phase voltage compensation circuit 110a, 110b, 110c to each phase according to a command from the control circuit 30. To compensate for voltage fluctuations due to instantaneous voltage drop.

The detailed configuration of each phase voltage compensation circuit 110a, 110b, 110c will be described below with reference to FIG.
As shown in FIG. 2, each phase voltage compensation circuit 110a, 110b, 110c is composed of a plurality of (in this case, three) voltage compensation units 15 and outputs a compensation voltage with either positive or negative polarity. PN1, PN2, and PN3 are connected in series to the power system. Each voltage compensation unit 15 is composed of four IGBTs 9sw11 to 9sw14, 9sw21 to 9sw24, 9sw31 to 9sw34 having diodes connected in antiparallel, and charging capacitors 10pn1 to 10pn3 as sub capacitors. Each voltage compensation subcircuit PN (PN1, PN2, PN3), a charging diode 11 for charging the charging capacitor 10 (10pn1 to 10pn3), and a secondary winding 13 of the charging transformer 14 are provided. The charging voltages V1 to V3 of the charging capacitor 10 are connected to the power system with either positive or negative polarity by on / off control of the IGBT 9 (9sw11 to 9sw14, 9sw21 to 9sw24, 9sw31 to 9sw34). Further, the capacitors 10a, 10b, and 10c (see FIG. 1) included in the phase voltage compensation circuits 110a, 110b, and 110c are configured by the plurality of charging capacitors 10 (10pn1 to 10pn3), respectively.

Further, a high-speed mechanical steady short-circuit switch 8 is provided in parallel at the output terminals of the phase voltage compensation circuits 110a, 110b, and 110c. Note that a plurality of the steady short-circuit switches 8 may be provided in parallel with each voltage compensation subcircuit PN, and may be provided for each output terminal of one or a plurality of voltage compensation subcircuits PN connected in series. . Further, the full bridge inverter may be formed of a self-extinguishing semiconductor switching element other than the IGBT 9.
The charging capacitor 10 is charged with different voltages by the charging diode 11 and the secondary winding 13 of the charging transformer 14, and the charging transformer primary winding 12 is connected to the power system. The ratio of the voltages charged in the charging capacitors 10 in the voltage compensation subcircuits PN1, PN2, and PN3 is set to a power ratio of about 2. That is, the following relationship is satisfied.
V3 = 2 × V2 = 2 × 2 × V1

The steady short-circuit switch 8 and each semiconductor switching element 9 of each phase voltage compensation circuit 110a, 110b, 110c are connected to the control circuit 30, and by command signals z, g11-g14, g21g-24, g31-g34 from the control circuit 30. Operate. The configuration and operation of the control circuit 30 will be described below with reference to FIG.
As shown in FIG. 3, the system voltage Vx and the system current Ix observed by monitoring the voltage and current of each phase of the power system are respectively input to the control circuit 30. In addition, values Va1 to Va3, Vb1 to Vb3, and Vc1 to Vc3 obtained by monitoring the voltages of the capacitors 10pn1 to 10pn3 in the phase voltage compensation circuits 110a, 110b, and 110c are also input to the control circuit 30, respectively. The input capacitor voltages Va1 to Va3, Vb1 to Vb3, and Vc1 to Vc3 are calculated by the voltage adder 40 as the capacitor total voltage Vca, Vcb, Vcc as a capacitor voltage detection value for each phase. With respect to the total capacitor voltages Vca, Vcb, and Vcc of each phase, the average value calculation unit 41 calculates the capacitor average voltage Vcave for all phases.
The comparison operation unit 44 calculates differences Vca−Vcave, Vcb−Vcave, and Vcc−Vcave between the capacitor total voltages Vca, Vcb, and Vcc for each phase and the capacitor average voltage Vcave for all phases, respectively.

  In the compensation voltage calculation unit 33, the system voltage Vx of each phase, the system current Ix, the set voltage 31 of each phase which is the system voltage at normal time, the total capacitor voltage Vca, Vcb, Vcc of each phase, and the average voltage of the capacitors of all phases When Vcave and the output from the comparison calculation unit 44 are input and the system voltage Vx of each phase is lower than the set voltage 31 of each phase, which is the system voltage at normal time, the voltage fluctuation of each line voltage is Compensation voltages Via, Vib, and Vic for each phase are calculated so as to compensate. The calculation of the compensation voltages Via, Vib, and Vic for each phase is performed by superimposing a common superimposed voltage vector V0 on all phases calculated by the superimposed voltage calculation unit 34 in the compensation voltage calculation unit 33. It will be described in detail.

FIG. 4 is a vector diagram showing the voltage and current of each phase of the power system. FIG. 4A shows voltage vectors Vna, Vnb, and Vnc (hereinafter referred to as normal voltage vectors) of each phase in the normal state. ), Current vectors Ina, Inb, and Inc (hereinafter referred to as normal current vectors), and voltage vectors Vsa, Vsb, and Vsc (hereinafter referred to as instantaneous voltage drop vectors) of the respective phases at the time of voltage fluctuation due to an instantaneous drop. Note that θsa, θsb, and θsc represent phase differences between the instantaneous low voltage vector and the normal current vector when the voltage fluctuates. As shown in FIG. 4B, the phase error voltages Vna−Vsa, Vnb−Vsb, and Vnc− for compensating for the instantaneous voltage vectors Vsa, Vsb, and Vsc of the respective phases to the normal voltage vectors Vna, Vnb, and Vnc. A superimposed voltage vector V0, which is the same output voltage vector, is superimposed (added) on Vsc (hereinafter referred to as Vta, Vtb, and Vtc) to obtain a compensation voltage for each phase as shown in FIG. Each phase compensation voltage vector Via, Vib, Vic is calculated.
At this time, the superimposed voltage V0 is repeatedly calculated every predetermined unit time Δt, and at each calculation, the bias of the voltage drop of each phase capacitor at that time is eliminated by the time T of one cycle of the system voltage, that is, Calculation is performed so that the voltage detection values (capacitor total voltage) of the capacitors of each phase are substantially equal. Note that the time interval Δt of the above calculation is sufficiently shorter than the period T of the system voltage. Details of the method of calculating the superimposed voltage V0 will be described later.
In this way, the compensation voltages Via, Vib, and Vic for each phase are calculated by superimposing the superimposed voltage V0 so as to compensate for the line voltage that has fluctuated due to the voltage fluctuation of each phase.

When the system voltage is normal, the steady short-circuit switch 8 is on, and the current flows through the steady short-circuit switch 8. When a voltage sag occurs, the voltage sag detector 37 detects the voltage sag and turns off the steady short-circuit switch 8 of each phase voltage compensation circuit 110a, 110b, 110c by a signal z (za, zb, zc) (= 0). To do. At this time, the superimposed voltage calculation unit 34 repeatedly calculates the superimposed voltage V0 every predetermined unit time Δt, and the compensation voltage calculation unit 33 calculates the compensation voltages Via, Vib, and Vic for each phase.
When the compensation voltages Via, Vib, and Vic for each phase are calculated, as shown in FIG. 3, after being amplified by an amplifier circuit 35 and further subjected to absolute value conversion, each phase is corrected by an A / D converter 36. Are converted into 3-bit digital signals (D1 to D3). When the compensation voltages Via, Vib, Vic of each phase are equal to the charging voltage V1 of the charging capacitor 10pn1, only the least significant bit D1 in the output signal from the A / D converter 36 is 1, that is, “001”. Similarly, in the case of “010” to “111”, the gain of the amplifier circuit 35 is adjusted in advance so as to be equal to the combination of the charging voltages of the charging capacitor 10.

  On the other hand, the calculated compensation voltages Via, Vib, and Vic for each phase are also input to the polarity determination circuit 38 to determine the polarity. 39a, 39b, 39c are drive signal generators that generate drive signals ga, gb, gc for the phase voltage compensation circuits 110a, 110b, 110c. The drive signals ga, gb, gc for each phase are Each phase voltage compensation circuit 110a, 110b, 110c is composed of 12 types of drive signals g11-g14, g21-g24, g31-g34 of inverters of a plurality of voltage compensation subcircuits PN. The drive signal generators 39a, 39b, and 39c select the signals that become active in the digital signals D1 to D3 according to the cases where the polarities of the compensation voltages Via, Vib, and Vic of each phase are positive and negative, Drive signals ga, gb, and gc are generated for the phase voltage compensation circuits 110a, 110b, and 110c.

For example, in the voltage compensation subcircuit PN1 in each phase voltage compensation circuit 110a, 110b, 110c shown in FIG. 2, when the least significant bit D1 = 1 and the polarity of the system voltage is positive, the switching elements 9sw11, 9sw14 Is turned on, and the switching elements 9sw12 and 9sw13 are turned off, so that the charging voltage V1 is output in a positive polarity. When the polarity of the system voltage is negative, the switching elements 9sw12 and 9sw13 are turned on and the switching elements 9sw11 and 9sw14 are turned off to output the charging voltage V1 with a negative polarity. When D1 = 0, one of the upper arm side 9sw12 and 9sw14 or the lower arm side 9sw11 and 9sw13 among the switching elements 9sw11 to 9sw14 is turned on and the other is turned off, and the output terminal is short-circuited. The output from the circuit PN1 is almost zero.
The outputs from the other voltage compensation sub-circuits PN2 and PN3 are similarly performed according to the digital signals D2 and D3 of the corresponding bits, that is, in each phase voltage compensation circuit 110a, 110b, and 110c, the digital signals D1 to D1. A compensation voltage is output from each compensation subcircuit PN1, PN2, PN3 selected by D3. These outputs are combined in the system, and voltage output of 8 gradations of “000” to “111” can be generated in each phase, and the maximum compensation voltage is 7 × V1.

Next, details of a method for calculating the superimposed voltage V0 will be described.
At the time of voltage fluctuation compensation, in each phase voltage compensation circuit, the capacitor voltage Vc decreases with time due to the output of the compensation voltage (Vt + V0) in which the superimposed voltage V0 is superimposed on the error voltage Vt. If the capacitor voltage at time t is Vc (t), the following equation is established.

ここで、Ｃはコンデンサ静電容量を、Ｐは皮相電力を、pfは負荷力率を、Ｔは系統電圧の周期を、Ｖｎは正常時の系統電圧を表している。
重畳電圧Ｖ0を（Ｖ0＋ΔＶ0）に変化させたときの、Ｖｃ（ｔ）の変化量をΔＶｃとすると、（１）式より次の関係式が得られる。

Here, C represents the capacitor capacitance, P represents the apparent power, pf represents the load power factor, T represents the system voltage period, and Vn represents the normal system voltage.
When the amount of change in Vc (t) when the superposed voltage V0 is changed to (V0 + ΔV0) is ΔVc, the following relational expression is obtained from the expression (1).

Ｖｃ（ｔ）をＶｎ・Ｖｃpuとおいて（２）式を変形すると、次式が得られる。

When Vc (t) is set to Vn · Vcpu and the equation (2) is modified, the following equation is obtained.

As shown in the above equation (3), the superimposed voltage change amount ΔV0 for each time is determined based on the change amount ΔVc of the capacitor voltage.
This superimposed voltage V0 is repeatedly calculated every predetermined unit time Δt, and at each calculation, the capacitor total voltage of each phase is detected and calculated by the superimposed voltage calculation unit 34 so that they are substantially equal. When the normal voltage vector of each phase is Vnj (j = a, b, c), it is expressed by the following equation.

即ち、重畳電圧演算部３４は、所定の単位時間Δｔ毎に、Ｖnjの係数であるＳjを演算して重畳電圧Ｖ0を決定する。Ｓjの演算は、以下の式により行う。

That is, the superimposed voltage calculation unit 34 calculates the superimposed voltage V0 by calculating Sj that is a coefficient of Vnj every predetermined unit time Δt. The calculation of Sj is performed by the following equation.

但し、Ｋ，ｍは定数

K and m are constants

In this way, Sj (t _n ) at each calculation time t _n is determined. This operation is the difference between the phase of the capacitor sum voltage Vcj and all phases capacitor average voltage Vcave at that time t _n, in which computing the Sj (t _n) so as to eliminate during the period time T of the system voltage is there. That is, the calculation is performed so that the voltage drop bias of each phase capacitor at that time is eliminated by the time T of one cycle of the system voltage.
Further, Sj _{(t n)} is the previous calculation time _{t n-1} value Sj _{(t n-1),} and that time based on the capacitor variation ΔVcj of (Delta] t between the from the previous operation) is calculated The That is, the superposed voltage change amount ΔV0 for each time is calculated based on the change amount ΔVc of the capacitor voltage. Further, although Sj (t _n ) calculated in this way may temporarily increase, it shows a tendency to decrease over time during the continuous compensation time. As a result, when the compensation operation continues and the capacitor voltage decreases, the superimposed voltage V0 and the amount of change thereof are also reduced.

In this embodiment, the superposed voltage V0 is calculated so as to eliminate variations in the capacitor total voltages Vca, Vcb, Vcc of the respective phases of the phase voltage compensation circuits 110a, 110b, 110c, and the superposed voltage V0 is superposed to each other. Phase compensation voltages Via, Vib, Vic are calculated. For this reason, it is possible to reduce the capacitor total voltages Vca, Vcb, and Vcc of each phase substantially evenly while compensating for the voltage fluctuation of the line voltage and maintaining the reliability of power supply to the load 3. For this reason, the energy of the capacitor of the whole voltage fluctuation compensating apparatus 200 can be used effectively, and as a result, the voltage fluctuation compensation possible time can be extended.
Further, by using the above equations (4) and (5), the superimposed voltage V0 can be calculated reliably and reliably, and the above-described effects can be easily and reliably achieved.
Further, when the compensation operation is continued and the capacitor voltage is lowered, the superposed voltage V0 and the amount of change thereof are reduced, so that there is no problem that the control voltage diverges because the rate of change of the superposed voltage V0 increases with respect to the capacitor voltage. The stability of the compensation operation control is improved. In addition, since the superimposed voltage vector V0 can be determined according to the supplied power, the control reliability is improved.

Embodiment 2. FIG.
In the first embodiment, as the compensation operation continues, the capacitor voltage Vc decreases. When the calculated compensation voltage (Vt + V0) exceeds the capacitor voltage Vc, the compensation cannot be performed. Limit V0 by setting a limit value.
In order to keep each phase compensation voltage (Vnj-Vsj + V0) within each phase capacitor voltage Vcj, the following relationship is required.
│Vnj-Vsj + V0│≤Vcj (j = a, b, c) (6)
Since Vnj, Vsj, and V0 satisfy the above equation (6) and Vcj is positive at an arbitrary moment, equation (6) can be transformed as follows.
-Vcj≤Vnj-Vsj + V0≤Vcj (j = a, b, c) (7)
Therefore,
−Vcj−Vnj + Vsj ≦ V0 ≦ Vcj−Vnj + Vsj (j = a, b, c) (8)

For this reason, as shown in FIG. 5, the superimposed voltage V0 is obtained by limiting the voltage calculated using the above equations (4) and (5) using the limit value represented by the above equation (8). Each phase compensation voltage (Vnj-Vsj + V0) can be kept within each phase capacitor voltage Vcj.
As described above, the limit value is determined by the capacitor voltage detection value Vcj and the error voltage (Vnj−Vsj) of each phase at that time.
Further, since the change in the capacitor voltage detection value Vcj is small and the error voltage (Vnj−Vsj) fluctuates at the fundamental frequency of the system, the limit value of the superimposed voltage V0 does not change suddenly and stable control can be performed.

  In the one-phase or two-phase voltage compensation circuit 110, after the capacitor voltage of each phase becomes smaller than the calculated compensation voltage, it is impossible to control to reduce the capacitor voltage of each phase almost uniformly. It becomes. However, it retains the energy required for compensation. In this embodiment, the compensation is continued while limiting the superimposed voltage V0 so that the phase in which the output compensation voltage exceeds the capacitor voltage outputs a compensation voltage equal to the capacitor voltage. Thus, the compensation can be continued with easy control while keeping the three-phase line voltage normal.

  Not only the method of limiting each phase with the limit value, but after the capacitor voltage of each phase becomes smaller than the calculated compensation voltage, the calculated each phase compensation voltage is canceled and all the phases are canceled. Compensation can be continued in the same way by recalculating the superimposed voltage V0 so that each phase compensation voltage is equal to or lower than the capacitor voltage.

Embodiment 3 FIG.
In the third embodiment, control when the system voltage is normally restored during voltage fluctuation compensation in the first embodiment will be described.
When the system voltage becomes normal during voltage fluctuation compensation, the superimposed voltage calculation unit 34 that has calculated Sj and determined the superimposed voltage V0 every predetermined unit time Δt stops the calculation of the above equation (5). Thereafter, no new operation is performed. Then, the compensation operation is continued by the output of each phase compensation voltage on which the superimposed voltage V0 at the previous calculation is superimposed. When the instantaneous value of the superimposed voltage V0 becomes zero, the normal short-circuit switch 8 is closed to compensate the voltage fluctuation. Stop device output.
The neutral point voltage of the load changes suddenly due to the superposed voltage V0 being compensated. In this embodiment, since the superposed voltage V0, that is, the neutral point voltage is zero, power is supplied from the system side. There is no sudden change in the neutral voltage of the load and stable operation can be performed.

Embodiment 4 FIG.
In the third embodiment, when the system voltage becomes normal during the voltage fluctuation compensation, the calculation of the formula (5) is stopped, and the calculation of the new superimposed voltage V0 is not performed thereafter. In the fourth embodiment, the calculation of the superimposed voltage V0 is continued for a while even after the system voltage becomes normal.
In the superimposed voltage calculation unit 33, when the system voltage becomes normal during voltage fluctuation compensation, the equation (5) is used for each predetermined unit time Δt until the capacitor total voltages Vca, Vcb, Vcc of each phase become equal. Thus, the process of calculating Sj to determine the superimposed voltage V0 is continued, and the compensation operation is continued by outputting each phase compensation voltage on which the superimposed voltage V0 is superimposed. Then, when Vca = Vcb = Vcc, the steady short-circuit switch 8 is closed to stop the output of the voltage fluctuation compensator.

As a result, even when a repeated instantaneous drop occurs due to multiple lightning or the like, it is possible to compensate, and the reliability of the compensation operation is improved.
Here, during the time from when the system voltage becomes normal to when the steady short-circuit switch 8 is closed, energy is transferred from the voltage compensation circuit 110 having a higher voltage to the voltage compensation circuit 110 having a lower phase.

  The control of the third embodiment can be applied in combination. That is, in the fourth embodiment, when the total capacitor voltage Vca, Vcb, Vcc of each phase becomes equal, the calculation of the above equation (5) is stopped and the calculation of the new superimposed voltage V0 is not performed. The compensation operation may be continued with each phase compensation voltage using the superimposed voltage V0 at the time of calculation, and the compensation operation may be terminated when the instantaneous value of the superimposed voltage V0 becomes zero. This makes it possible to compensate even when repeated voltage drops occur due to multiple lightnings, etc., improving the reliability of the compensation operation and preventing sudden changes in the voltage at the neutral point of the load.

Embodiment 5 FIG.
Next, a voltage variation compensating apparatus according to Embodiment 5 of the present invention will be described below.
In each of the above embodiments, the superimposed voltage V0 is repeatedly calculated every predetermined unit time Δt so that the total capacitor voltage of each phase is substantially equal. However, as shown in the second and third embodiments, When it becomes impossible to output a voltage for keeping the total capacitor voltage of each phase uniform, the control is changed to continue the compensation.
In the fifth embodiment, the output energy of each phase compensation voltage from each phase voltage compensation circuit 110 increases as the cos θ due to the phase angle shift θ between each phase compensation voltage and each phase system current is closer to 1. The superimposed voltage V0 is calculated as follows. The calculation of the superposed voltage V0 may be performed only once at the start of compensation, and the superposed voltage V0 computed at that time is used from the start to the end of compensation.

A method for obtaining the superimposed voltage V0 and the compensation voltages Via, Vib, Vic will be described below.
FIG. 6 is a vector diagram showing the voltage, current, superimposed voltage, and compensation voltage of each phase of the power system according to the fifth embodiment. As shown in FIG. 5A, when the system voltages that are normal voltage vectors Vna, Vnb, and Vnc become instantaneous voltage vectors Vsa, Vsb, and Vsc due to an instantaneous voltage drop, the instantaneous voltage vectors Vsa, Vsa, A superimposed voltage vector V0, which is the same output voltage vector, is superimposed (added) on each phase error voltage Vna-Vsa, Vnb-Vsb, Vnc-Vsc for compensating Vsb, Vsc to normal voltage vectors Vna, Vnb, Vnc. Then, each phase compensation voltage vector Via, Vib, Vic is calculated. At this time, as shown in FIG. 5B, cos θ due to the phase angle deviation θ between each phase compensation voltage vector Via, Vib, Vic and normal current vectors Ina, Inb, Inc of each phase system current is close to 1. The energy of each phase compensation voltage vector Via, Vib, Vic is increased as the phase, that is, the power factor is closer to 1. Further, the superposed voltage vector V0 is determined so that the phase compensation voltage vectors Via, Vib, Vic and the normal current vectors Ina, Inb, Inc satisfy such a relationship.

  If the energy of each phase compensation voltage vector Via, Vib, Vic is determined to be equal as shown in FIG. 7, as shown in FIG. 7B, each phase compensation voltage vector Via, The phase compensation voltage vectors Via, Vib are reduced as the phase where the cos θ due to the phase angle deviation θ between Vib, Vic and the normal current vectors Ina, Inb, Inc of the respective phase system currents is away from 1, that is, the power factor is smaller. , The voltage of Vic increases. Therefore, in the phase voltage compensation circuit 110 that requires a high compensation voltage, it may be impossible to output the compensation voltage even when the capacitor voltage is relatively high.

In this embodiment, each phase compensation voltage vector becomes closer to a phase where cos θ due to a phase angle deviation θ between each phase compensation voltage vector Via, Vib, Vic and normal current vectors Ina, Inb, Inc of each phase system current is closer to 1. By increasing the energy of Via, Vib, and Vic, the compensation voltage output is not impossible when the capacitor voltage is relatively high, and the energy of the capacitor of the entire voltage fluctuation compensator 200 can be used effectively. As a result, the voltage fluctuation compensation possible time can be extended.
Ideally, when the compensation voltage output is impossible and the compensation is terminated, the total capacitor voltages Vca, Vcb, Vcc of each phase match the compensation voltages Via, Vib, Vic, respectively.
That is, the compensation ends when | Via | = Vca, | Vib | = Vcb, and | Vic | = Vcc are satisfied at the same time.

  In this case as well, the above-described third embodiment can be applied. When the system voltage becomes normal, the compensation operation is not immediately stopped, and when the instantaneous value of the superimposed voltage V0 becomes zero, the normal short-circuit switch 8 is closed to stop the output of the voltage fluctuation compensator. As a result, a sudden change in the voltage at the neutral point of the load can be prevented.

1 is a schematic configuration diagram of a voltage variation compensating apparatus according to Embodiment 1 of the present invention. It is a block diagram of each phase voltage compensation circuit by Embodiment 1 of this invention. It is a block diagram of the control circuit of the voltage fluctuation compensation apparatus by Embodiment 1 of this invention. It is a vector diagram of voltage and current for explaining the operation of the voltage fluctuation compensator according to Embodiment 1 of the present invention. It is explanatory drawing of the determination method of the superimposed voltage by Embodiment 2 of this invention. It is a vector diagram of the voltage and current explaining the operation | movement of the voltage fluctuation compensation apparatus by Embodiment 5 of this invention. It is a vector diagram of the voltage and current explaining the operation | movement by the comparative example of Embodiment 5 of this invention.

Explanation of symbols

3 load, 10, 10a, 10b, 10c capacitor,
30 Control circuit as control unit, 31 Set voltage as normal voltage,
33 Compensation voltage calculator, 34 Superposed voltage calculator, 37 Instantaneous voltage drop detector,
41 average value calculation unit, 44 voltage deviation detection unit, 110a to 110c voltage compensation circuit for each phase, 200 voltage fluctuation compensation device, PN1, PN2, PN3 voltage compensation subcircuit,
V0 superimposed voltage, Via, Vib, Vic Compensation voltage for each phase, Vsa, Vsb, Vsc Instantaneous low voltage,
Vca, Vcb, Vcc each phase capacitor detection voltage value (capacitor total voltage),
Vx grid voltage, Ix grid current.

Claims (11)

A control unit that monitors voltage fluctuations in the power system and performs power supply control based on the voltage fluctuation, and is connected in series to each phase of the power system, and has a capacitor independently for each phase, and the DC voltage of each phase capacitor A voltage fluctuation compensator that suppresses fluctuations in the voltage supplied to the load, and converts the system voltage of each phase to a normal voltage when the voltage of the power system fluctuates. A compensation voltage calculation unit for calculating each phase compensation voltage by superimposing the same output voltage (hereinafter referred to as a superimposed voltage) on each phase error voltage for compensation, and a superimposed voltage calculation unit for calculating the superimposed voltage; In the control unit, and the superimposed voltage calculation unit detects a voltage drop state of each phase capacitor every predetermined unit time, and the bias between the phases is a predetermined time sufficiently longer than the predetermined unit time. In time As described above, the superposed voltage constituted by combining the voltage components of the respective phases is repeatedly calculated, and the respective phase compensation voltages calculated by the compensation voltage calculating unit using the superposed voltage are converted into the respective phase voltage compensations. A voltage fluctuation compensator that outputs from a circuit and suppresses voltage fluctuation of a line voltage in the power system. 2. The voltage fluctuation compensator according to claim 1, wherein the sufficiently long predetermined time is a time determined based on a cycle of the power system. 3. The voltage fluctuation compensator according to claim 1, wherein the superimposed voltage is decreased with the passage of time. 4. The voltage fluctuation compensator according to claim 3, wherein each phase component of the superimposed voltage is determined according to a previous calculation value for each predetermined unit time and a voltage change amount of a capacitor of the phase. The superposed voltage calculation unit limits the superposed voltage to a limit value determined based on each phase error voltage at that time and a voltage detection value of each phase capacitor, and outputs the limited superposed voltage. Item 5. The voltage fluctuation compensation device according to any one of Items 1 to 4. When each phase compensation voltage exceeds the voltage detection value of the capacitor of the phase in an arbitrary phase, the calculated phase compensation voltage is canceled, and the superimposed voltage calculation unit performs the phase compensation for all phases. 2. The compensation operation of calculating the superposed voltage so that the voltage is equal to or lower than a voltage detection value of the capacitor of the phase and outputting the phase compensation voltage from the phase voltage compensation circuit is continued. The voltage fluctuation compensation apparatus in any one of 1-4. When the power system recovers from the voltage fluctuation to the normal voltage, the superimposed voltage calculation unit does not newly calculate the superimposed voltage based on the voltage of each phase capacitor, and is calculated using the superimposed voltage at the previous calculation. 7. The voltage variation according to claim 1, wherein the compensation operation for outputting each phase compensation voltage from each phase voltage compensation circuit is continued until the instantaneous value of the superimposed voltage becomes zero. Compensation device. When the power system recovers from the voltage fluctuation to the normal voltage, the superimposed voltage calculation unit repeatedly calculates the superimposed voltage until the voltage detection value of each phase capacitor becomes approximately equal, and from each phase voltage compensation circuit, 7. The voltage fluctuation compensating apparatus according to claim 1, wherein the compensation operation for outputting each phase compensation voltage is continued until the time point. A control unit that monitors voltage fluctuations in the power system and performs power supply control based on the voltage fluctuation, and is connected in series to each phase of the power system, and has a capacitor independently for each phase, and the DC voltage of each phase capacitor A voltage fluctuation compensator that suppresses fluctuations in the voltage supplied to the load, and converts the system voltage of each phase to a normal voltage when the voltage of the power system fluctuates. A compensation voltage calculation unit for calculating each phase compensation voltage by superimposing the same output voltage (hereinafter referred to as a superimposed voltage) on each phase error voltage for compensation, and a superimposed voltage calculation unit for calculating the superimposed voltage; In the control unit, the phase compensation voltage is output from the phase voltage compensation circuit to suppress voltage fluctuation of the line voltage in the power system, and the superimposed voltage calculation unit includes the phase compensation voltage and the phase compensation voltage. Each phase system The superimposed voltage is calculated so that the output energy of each phase compensation voltage from each phase voltage compensation circuit becomes larger in the phase where cos θ due to the phase angle deviation θ from the current is closer to 1. Fluctuation compensation device. When the power system recovers from the voltage fluctuation to the normal voltage, the compensation operation for outputting the phase compensation voltage from the phase compensation circuit using the superimposed voltage that has already been calculated is performed using the instantaneous value of the superimposed voltage. 10. The voltage fluctuation compensating apparatus according to claim 9, wherein the voltage fluctuation compensator is continued until zero. Each phase voltage compensation circuit connected in series to each phase of the power system includes a plurality of sub-capacitors, each of which is charged with a different voltage and constitutes the capacitor, and converts the voltage of the sub-capacitor into alternating current and outputs the plurality The voltage compensation subcircuits are connected in series, and when each phase compensation voltage is output, a desired combination is selected from the plurality of voltage compensation subcircuits in each phase, and the sum of the output voltages is used in the power system. The voltage fluctuation compensation apparatus according to claim 1, wherein voltage fluctuation of the line voltage is suppressed.

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